Wiring board and manufacturing method therefor

Abstract

According to the present disclosure, a wiring board comprises: an insulating layer including a first surface and a second surface positioned opposite to the first surface; a first wiring conductor positioned in a groove recessed from the first surface toward the second surface and including a narrow pattern having a width of 15 μm or less; and a second wiring conductor positioned on the first surface and including a wide pattern having a width of 150 μm or more. The first wiring conductor includes: a first base metal layer positioned on an inner wall surface of the groove; and a first electrolytic plating layer positioned on the first base metal layer and filled in the groove. The second wiring conductor includes: a second base metal layer positioned on the first surface; and a second electrolytic plating layer positioned on the second base metal layer.

Description

Wiring board and manufacturing method thereof

[0001] The present disclosure relates to a wiring board and a manufacturing method thereof.

[0002] Conventionally, the semi-additive method has been used as a method for forming wiring conductors in wiring boards. The semi-additive method forms wiring conductors using the following procedure. First, a thin base metal layer is formed on the exposed surface of an insulating layer by electroless plating, sputtering, or the like. Next, a plating resist layer having openings corresponding to the pattern of the wiring conductor is formed on this base metal layer. Next, an electrolytic plating layer is formed on the base metal layer exposed in the openings in the plating resist layer. Next, the plating resist layer is peeled off and removed, and finally, the base metal layer in the portions not covered by the electrolytic plating layer is removed by etching.

[0003] In recent years, wiring conductors in wiring boards have become increasingly finer. For example, there are cases where wiring boards are required in which the width of the wiring conductor is 15 μm or less and the spacing between adjacent wiring conductors is 15 μm or less. When the width of the wiring conductor is 15 μm or less, the bonding area between the insulating layer and the wiring conductor via the underlying metal layer becomes small. As a result, the wiring conductor is more likely to peel off from the insulating layer. Furthermore, the electrical insulation reliability between adjacent wiring conductors decreases.

[0004] Therefore, as described in Patent Document 1, a method for forming a wiring conductor consisting of a metal base layer and an electrolytic plating layer that remain in the groove has been proposed. First, grooves corresponding to the pattern of the wiring conductor are formed to a predetermined depth on the surface of an insulating layer by laser processing. Next, a thin metal base layer is formed on the surface of the insulating layer, including the inner walls of the grooves, by electroless plating or sputtering. Next, an electrolytic plating layer is formed on this metal base layer to a thickness that fills the grooves. Finally, the metal base layer and electrolytic plating layer on the insulating layer are polished and removed by chemical mechanical polishing.

[0005] Japanese Patent Application Laid-Open No. 2004-149926

[0006] A wiring board according to the present disclosure includes an insulating layer having a first surface and a second surface opposite the first surface, a first wiring conductor located in a groove recessed from the first surface toward the second surface and including a narrow pattern having a width of 15 μm or less, and a second wiring conductor located on the first surface and including a wide pattern having a width of 150 μm or more. The first wiring conductor includes a first base metal layer located on the inner wall surface of the groove and a first electrolytically plated layer located on the first base metal layer and filling the groove. The second wiring conductor includes a second base metal layer located on the first surface and a second electrolytically plated layer located on the second base metal layer.

[0007] A method for manufacturing a wiring board according to the present disclosure includes the steps of: forming a groove recessed from the first surface toward the second surface in an insulating layer having a first surface and a second surface opposite the first surface; forming a first base metal layer covering the first surface and the inner wall surface of the groove; forming a first electrolytically plated layer located on the first base metal layer and having a thickness sufficient to fill the groove; removing at least the first base metal layer and the first electrolytically plated layer located on the first surface to form a first wiring conductor including a narrow pattern having a width of 15 μm or less located in the groove; and forming a second wiring conductor on the first surface including a second base metal layer and a second electrolytically plated layer located on the second base metal layer, and including a wide pattern having a width of 150 μm or more.

[0008] 2A to 2L are explanatory views illustrating a main part of a wiring board according to an embodiment of the present disclosure, and are explanatory views illustrating a manufacturing process of a wiring board according to an embodiment of the present disclosure.

[0009] According to the method described in Patent Document 1, grooves for wiring conductors with relatively narrow widths (e.g., 15 μm or less) are successfully filled with an electrolytically plated layer. However, grooves for wiring conductors with relatively wide widths (e.g., 150 μm or more) are difficult to fill with an electrolytically plated layer. As a result, the upper surface of a wide wiring conductor is significantly recessed, resulting in poor flatness. If the thickness of the electrolytically plated layer is further increased to eliminate this recess, the stress generated during the formation of this electrolytically plated layer increases. As a result, the stress acts significantly between the inner wall of the groove for the wide wiring conductor via the base metal layer, making the wide wiring conductor more likely to peel off. Therefore, there is a need for a wiring board that is resistant to peeling of both narrow and wide wiring conductors.

[0010] The wiring board according to the present disclosure has the configuration described in the section on means for solving the above problems, and thus both narrow and wide wiring conductors are less likely to peel off. Furthermore, the method for manufacturing a wiring board according to the present disclosure has the configuration described in the section on means for solving the above problems, and thus can provide a wiring board in which both narrow and wide wiring conductors are less likely to peel off.

[0011] A wiring board according to the present disclosure will be described with reference to the drawings. FIG. 1 is an explanatory diagram illustrating a main portion of a wiring board 10 according to an embodiment of the present disclosure. The wiring board 10 according to the embodiment includes a core layer 1, a buildup layer 2 located on the surface of the core layer 1, and a solder resist 3 located on the surface of the buildup layer 2. In the wiring board 10, the buildup layer 2 is located on both surfaces (top and bottom surfaces) of the core layer 1. In FIG. 1, the buildup layer 2 located on the bottom surface of the core layer 1 is omitted.

[0012] The core layer 1 includes a core insulating layer 1a and a core conductor layer 11. The core insulating layer 1a is not particularly limited as long as it is made of an insulating material. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. These resins may be used alone or in combination of two or more. The thickness of the core insulating layer 1a is not particularly limited and may be, for example, 0.1 mm or more and 2.0 mm or less.

[0013] The core insulating layer 1a may contain a reinforcing material. Examples of reinforcing materials include insulating fabric materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Only one type of reinforcing material may be used, or two or more types may be used in combination. Furthermore, the core insulating layer 1a may contain dispersed therein an inorganic insulating filler such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide. Only one type of inorganic insulating filler may be used, or two or more types may be used in combination.

[0014] The core conductor layer 11 is located on the surface of the core insulating layer 1a. In FIG. 1, the core conductor layer 11 located on the underside of the core insulating layer 1a is omitted. The core conductor layer 11 is not particularly limited as long as it is made of a conductive material. Examples of conductive materials include metals such as copper. The thickness of the core conductor layer 11 is not particularly limited, and is, for example, 5 μm or more and 50 μm or less.

[0015] A through-hole conductor 12 is located in the core insulating layer 1a to electrically connect the upper and lower surfaces of the core insulating layer 1a. The through-hole conductor 12 is located in a through-hole 1T that penetrates the upper and lower surfaces of the core insulating layer 1a. The through-hole conductor 12 is formed of a metal such as copper. The through-hole conductor 12 may be formed only on the inner wall surface, or may fill the through-hole 1T. The through-hole conductor 12 is connected to the core conductor layer 11 on the surface of the core insulating layer 1a. The through-hole conductor 12 may be made of the same metal as the core conductor layer 11, or a different metal.

[0016] The buildup layer 2 includes an insulating layer 2a (hereinafter sometimes referred to as a "buildup insulating layer 2a"), a first wiring conductor 21, and a second wiring conductor 22. The buildup insulating layer 2a has a first surface 2a1 and a second surface 2a2. In this specification, the "first surface 2a1" refers to the surface of the buildup insulating layer 2a that is farther from the core insulating layer 1a. The "second surface 2a2" refers to the surface opposite the first surface 2a1, i.e., the surface closer to the core insulating layer 1a.

[0017] The build-up insulating layer 2a is not particularly limited as long as it is made of an insulating material. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. These resins may be used alone or in combination of two or more.

[0018] The build-up insulating layers 2a may be made of the same resin or different resins. The build-up insulating layers 2a and the core insulating layer 1a may be made of the same resin or different resins. The thickness of the build-up insulating layers 2a is not particularly limited and may be, for example, 10 μm or more and 50 μm or less. The build-up insulating layers 2a may have the same thickness or different thicknesses.

[0019] The build-up insulating layer 2a may contain a reinforcing material. Examples of reinforcing materials include insulating fabric materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Only one type of reinforcing material may be used, or two or more types may be used in combination. Furthermore, the build-up insulating layer 2a may have dispersed therein an inorganic insulating filler such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide. Only one type of inorganic insulating filler may be used, or two or more types may be used in combination.

[0020] The first wiring conductor 21 includes a narrow pattern having a width of 15 μm or less. As shown in FIG. 1 , the first wiring conductor 21 is located in a groove 2G recessed from the first surface 2a1 toward the second surface 2a2 of the build-up insulating layer 2a. The depth of the groove 2G is not limited and is set appropriately depending on the thickness of the build-up insulating layer 2a. The depth of the groove 2G may be, for example, 5 μm or more and 25 μm or less.

[0021] The first wiring conductor 21 mainly functions as a signal conductor. As shown in Fig. 1, the first wiring conductor 21 includes a first base metal layer 21a and a first electrolytic plated layer 21b. In Fig. 1, the first wiring conductor 21 appears to be wide, but the wide first wiring conductor 21 represents a cross section cut in the longitudinal direction.

[0022] The first base metal layer 21a is the base of the first wiring conductor 21 and is located on the inner wall surface of the groove 2G. The first base metal layer 21a is made of a metal such as copper. The first base metal layer 21a has a thickness of, for example, 0.1 μm or more and 0.5 μm or less. The first base metal layer 21a is formed to improve adhesion between the first electrolytic plating layer 21b and the build-up insulating layer 2a.

[0023] The first electrolytic plated layer 21b is a layer that forms the main body of the first wiring conductor 21 and fills the groove 2G in which the first base metal layer 21a is formed. Signals are transmitted to the first wiring conductor 21. The first electrolytic plated layer 21b is not limited to any particular material as long as it is formed by electrolytic plating, and may be made of a metal such as copper. The first electrolytic plated layer 21b is located in the groove 2G in the build-up insulating layer 2a via the first base metal layer 21a on both the side and bottom surfaces. This provides excellent adhesion and reduces peeling of the first electrolytic plated layer 21b.

[0024] The arithmetic mean roughness Ra of the region of the first wiring conductor 21 (first underlying metal layer 21a) that contacts the groove 2G is not limited and may be, for example, 50 nm or more and 100 nm or less. If the arithmetic mean roughness Ra of the region of the first wiring conductor 21 that contacts the groove 2G is 50 nm or more and 100 nm or less, the first underlying metal layer 21a is more firmly adhered to the inner wall surface of the groove 2G. Therefore, peeling of the first underlying metal layer 21a is further reduced.

[0025] The upper surfaces of the first wiring conductors 21, i.e., the surfaces on the first surface 2a1 side of the build-up insulating layer 2a, may be flush with the first surface 2a1, or may be located closer to the second surface 2a2 than the first surface 2a1 (i.e., may be recessed toward the second surface 2a2) as shown in FIG. 1 . When the upper surfaces of the first wiring conductors 21 are located closer to the second surface 2a2 than the first surface 2a1, the distance between adjacent first wiring conductors 21 increases. As a result, problems such as migration are reduced. The depth from the first surface 2a1 to the upper surfaces of the first wiring conductors 21 may be, for example, 0.5 μm or more and 5 μm or less.

[0026] The second wiring conductor 22 includes a wide pattern having a width of 150 μm or more. As shown in FIG. 1 , the second wiring conductor 22 is located on the first surface 2 a 1 of the build-up insulating layer 2 a. The second wiring conductor 22 mainly functions as a ground conductor and a power conductor. As shown in FIG. 1 , the second wiring conductor 22 includes a second base metal layer 22 a and a second electrolytic plated layer 22 b.

[0027] The second base metal layer 22a is a base for the second wiring conductor 22 and is located on the first surface 2a1 of the build-up insulating layer 2a. The second base metal layer 22a is formed of a metal such as copper. The second base metal layer 22a has a thickness of, for example, 0.1 μm or more and 0.5 μm or less. As shown in FIG. 1 , the second base metal layer 22a may be formed on the inner wall surface of the via hole 2V. The second base metal layer 22a is formed to improve the adhesion of the second electrolytic plating layer 22b.

[0028] The second electrolytically plated layer 22b is the layer that forms the main body of the second wiring conductor 22 and is located on the second base metal layer 22a. In the second wiring conductor 22, electric charge flows through the second electrolytically plated layer 22b. There are no particular restrictions on the second electrolytically plated layer 22b as long as it is a layer formed by electrolytic plating, and it may be formed of a metal such as copper. The second electrolytically plated layer 22b has a thickness of, for example, 5 μm or more and 25 μm or less.

[0029] Furthermore, the side surfaces of second electrolytic plated layer 22b are in contact with build-up insulating layer 2a. In other words, the absence of second base metal layer 22a on the side surfaces of second electrolytic plated layer 22b eliminates stress transmitted to build-up insulating layer 2a between the side surfaces of second electrolytic plated layer 22b and build-up insulating layer 2a. As a result, peeling of second electrolytic plated layer 22b is reduced.

[0030] The arithmetic mean roughness Ra of the side surface of second electrolytic plated layer 22b is not limited and may be, for example, 150 nm or more and 300 nm or less. If the arithmetic mean roughness Ra of the side surface of second electrolytic plated layer 22b is 150 nm or more and 300 nm or less, second electrolytic plated layer 22b is firmly adhered to build-up insulating layer 2a, and peeling of second electrolytic plated layer 22b is further reduced.

[0031] 1 , the wiring board 10 according to one embodiment may further include a via-hole conductor 23 that penetrates the build-up insulating layer 2a from the first surface 2a1 to the second surface 2a2. The via-hole conductor 23 is located in a via hole 2V formed in the build-up insulating layer 2a. The via-hole conductor 23 is made of a metal such as copper. The via-hole conductor 23 may be formed only on the inner wall surface, or may fill the via hole 2V. The via-hole conductor 23 may be made of the same metal as the first wiring conductor 21 and the second wiring conductor 22, or may be made of a different metal.

[0032] A portion of second electrolytic plated layer 22b is connected to via-hole conductor 23 via second base metal layer 22a. Specifically, a portion of via-hole conductor 23 electrically connects second wiring conductor 22 located on first surface 2a1 of build-up insulating layer 2a to second wiring conductor 22 located on first surface 2a1 of build-up insulating layer 2a located on the first core conductor layer 11 side. Via-hole conductor 23 included in build-up insulating layer 2a located on the surface of core insulating layer 1a electrically connects second wiring conductor 22 located on first surface 2a1 of build-up insulating layer 2a to core conductor layer 11 located on the surface of core insulating layer 1a.

[0033] In this specification, the first wiring conductor 21 is defined as including a narrow pattern having a width of 15 μm or less, and the second wiring conductor 22 is defined as including a wide pattern having a width of 150 μm or more. That is, the first wiring conductor 21 includes at least a narrow pattern but does not include a wide pattern. The second wiring conductor 22 includes at least a wide pattern but does not include a narrow pattern.

[0034] As shown in Fig. 1, a solder resist 3 may be located on the surface of the buildup layer 2. The solder resist 3 is formed, for example, from an acrylic-modified epoxy resin. The solder resist 3 has a function of repelling solder so that adjacent connection portions are not electrically short-circuited by molten solder when, for example, a semiconductor element is mounted or when connecting to a motherboard. Furthermore, the solder resist 3 has a function of protecting the first wiring conductor 21, the second wiring conductor 22, etc. from the heat of the molten solder.

[0035] The solder resist 3 has openings formed therein to expose parts of the first wiring conductors 21 and the second wiring conductors 22 located on the surface of the build-up layer 2. The parts of the first wiring conductors 21 and the second wiring conductors 22 exposed through these openings function as pads when mounting a semiconductor element or the like.

[0036] Next, a method for manufacturing a wiring board according to the present disclosure will be described. The method for manufacturing a wiring board 10 according to an embodiment of the present disclosure includes the following steps (a) to (e): (a) forming a groove recessed from the first surface toward the second surface in an insulating layer having a first surface and a second surface opposite the first surface; (b) forming a first underlying metal layer covering the first surface and the inner wall surface of the groove; (c) forming a first electrolytically plated layer located on the first underlying metal layer and having a thickness sufficient to fill the groove; (d) removing at least the first underlying metal layer and the first electrolytically plated layer located on the first surface to form a first wiring conductor located in the groove and including a narrow pattern having a width of 15 μm or less; and (e) forming a second wiring conductor including a wide pattern having a width of 150 μm or more on the first surface, including a second underlying metal layer and a second electrolytically plated layer located on the second underlying metal layer.

[0037] A method for manufacturing a wiring substrate according to the present disclosure will be described with reference to Figures 2A to 2L. Figures 2A to 2L are explanatory views for explaining the manufacturing process of a wiring substrate 10 according to an embodiment of the present disclosure.

[0038] First, a core layer 1 is prepared as shown in FIG. 2A. The core layer 1 includes a core insulating layer 1a and a core conductor layer 11 as described above. The core conductor layer 11 is located on the surface of the core insulating layer 1a. The core insulating layer 1a includes a through-hole 1T, and a through-hole conductor 12 is located in the through-hole 1T to electrically connect the upper and lower surfaces of the core insulating layer 1a. The core insulating layer 1a, the core conductor layer 11, and the through-hole conductor 12 are as described above, and detailed description thereof will be omitted.

[0039] 2B, an insulating layer 2a (build-up insulating layer 2a) is formed on the surface of the core layer 1. The build-up insulating layer 2a has a first surface 2a1 and a second surface 2a2 opposite to the first surface 2a1. The build-up insulating layer 2a is as described above, and a detailed description thereof will be omitted.

[0040] 2C, grooves 2G recessed from the first surface 2a1 to the second surface 2a2 are formed in the build-up insulating layer 2a (step (a)). The method for forming the grooves 2G is not limited. For example, the grooves 2G can be formed by excimer laser, CO ２ The grooves 2G are formed by laser processing using a laser, a UV-YAG laser, etc. The depth of the grooves 2G is as described above, and a detailed description thereof will be omitted.

[0041] 2C, via holes 2V may be formed in the build-up insulating layer 2a. The method for forming the via holes 2V is not limited. For example, the via holes 2V may be formed by excimer laser, CO ２ The groove 2G and the via hole 2V are formed by laser processing using a laser, a UV-YAG laser, etc. The groove 2G and the via hole 2V may be formed simultaneously or separately.

[0042] When forming the grooves 2G, the inner wall surfaces of the grooves 2G may be roughened so that the regions of the first wiring conductors 21 (first underlying metal layer 21a) in contact with the grooves 2G have an arithmetic mean roughness Ra of 50 nm to 100 nm. By performing the roughening treatment, the first underlying metal layer 21a is more firmly adhered to the inner wall surfaces of the grooves 2G. This further reduces peeling of the first underlying metal layer 21a.

[0043] Next, as shown in FIG. 2D , a first base metal layer 21a is formed to cover the first surface 2a1 of the build-up insulating layer 2a and the inner wall surfaces of the grooves 2G (step (b)). As shown in FIG. 2D , if the build-up insulating layer 2a has via holes 2V, the first base metal layer 21a is formed to also cover the inner wall surfaces of the via holes 2V. The first base metal layer 21a is formed of a metal such as copper by, for example, electroless plating. Palladium may be used as a catalyst when performing electroless plating. The thickness of the first base metal layer 21a is as described above, and a detailed description thereof will be omitted.

[0044] Next, as shown in Fig. 2E, a first electrolytic plated layer 21b is formed on the first base metal layer 21a to a thickness sufficient to fill the grooves 2G (step (c)). As shown in Fig. 2E, if the build-up insulating layer 2a has via holes 2V, the first electrolytic plated layer 21b is formed so as to also fill the via holes 2V. As described above, the first electrolytic plated layer 21b is formed of a metal such as copper.

[0045] 2F, at least the first undercoat metal layer 21a and the first electrolytically plated layer 21b located on the first surface 2a1 of the build-up insulating layer 2a are removed to form a first wiring conductor 21 including a narrow pattern having a width of 15 μm or less located in the groove 2G (step (d)). The method for removing the excess first undercoat metal layer 21a and the first electrolytically plated layer 21b is not limited, and examples thereof include chemical mechanical polishing. This also forms a via-hole conductor 23 filled in the via hole 2V.

[0046] When removing the excess first base metal layer 21a and first electrolytic plating layer 21b, the upper surface of the first wiring conductor 21 may be processed so as to be flush with the first surface 2a1, or may be processed so as to be positioned closer to the second surface 2a2 than the first surface 2a1 (i.e., recessed toward the second surface 2a2), as shown in Figure 2F.

[0047] Next, a second wiring conductor 22 including a wide pattern having a width of 150 μm or more is formed on the first surface 2a1 of the build-up insulating layer 2a, the wide pattern including a second base metal layer 22a and a second electrolytic plating layer 22b located on the second base metal layer 22a (step (e)).

[0048] First, as shown in FIG. 2G , a second base metal layer 22a is formed to cover the first surface 2a1 of the build-up insulating layer 2a. Specifically, the second base metal layer 22a is formed to cover the first surface 2a1 of the build-up insulating layer 2a, the upper surfaces of the first wiring conductors 21, and the upper surfaces of the via-hole conductors 23. The second base metal layer 22a is formed of a metal such as copper by electroless plating. Palladium may be used as a catalyst when performing the electroless plating. The thickness of the second base metal layer 22a is as described above, and a detailed description thereof will be omitted.

[0049] 2H, a resist 4 is formed on the surface of the second undercoat metal layer 22a. The resist 4 is formed on the area where the second electrolytic plated layer 22b is not to be deposited. Examples of the resist 4 include a dry film resist.

[0050] 2I, a second electrolytic plated layer 22b is formed on the surface of the second base metal layer 22a in the areas where the resist 4 is not formed. The second electrolytic plated layer 22b is made of a metal such as copper. The thickness of the second electrolytic plated layer 22b is as described above, and a detailed description thereof will be omitted.

[0051] Next, as shown in Fig. 2J, the resist 4 is peeled off, and as shown in Fig. 2K, the second underlying metal layer 22a is removed from the portion that was covered with the resist 4. The second underlying metal layer 22a is removed by, for example, etching. In this manner, the second wiring conductor 22 including a wide pattern having a width of 150 µm or more is formed on the first surface 2a1 of the build-up insulating layer 2a.

[0052] The side surfaces of second electrolytic plated layer 22b may be roughened so that the arithmetic mean roughness Ra of the side surfaces is, for example, 150 nm to 300 nm. By roughening the side surfaces, second electrolytic plated layer 22b is firmly adhered to build-up insulating layer 2a, further reducing peeling of second electrolytic plated layer 22b.

[0053] 2L, another build-up insulating layer 2a is formed so as to cover the first wiring conductor 21, the second wiring conductor 22, and the first surface 2a1. Thereafter, at least a part of the above-described steps (a) to (e) is repeated a desired number of times to form the build-up layer 2. In this manner, the wiring substrate 10 according to one embodiment is obtained.

[0054] The embodiments of the present disclosure have been described above. However, the invention according to the present disclosure is not limited to the above-described embodiments, and various modifications and improvements are possible within the scope of the present disclosure as shown in (1) to (7) below.

[0055] (1) A wiring board according to the present disclosure includes an insulating layer having a first surface and a second surface opposite the first surface, a first wiring conductor located in a groove recessed from the first surface toward the second surface and including a narrow pattern having a width of 15 μm or less, and a second wiring conductor located on the first surface and including a wide pattern having a width of 150 μm or more. The first wiring conductor includes a first base metal layer located on the inner wall surface of the groove and a first electroplated layer located on the first base metal layer and filling the groove. The second wiring conductor includes a second base metal layer located on the first surface and a second electroplated layer located on the second base metal layer. (2) In the wiring board described in (1) above, the top surface of the first wiring conductor is located closer to the second surface than the first surface. (3) In the wiring board described in (1) or (2) above, a via-hole conductor is further positioned, penetrating the insulating layer from the first surface to the second surface, and the second electrolytic plated layer is connected to the via-hole conductor via a second base metal layer. (4) In the wiring board described in any of (1) to (3) above, the arithmetic mean roughness Ra of the region of the first wiring conductor that contacts the groove is 50 nm or more and 100 nm or less. (5) In the wiring board described in any of (1) to (4) above, the arithmetic mean roughness Ra of the side surface of the second electrolytic plated layer is 150 nm or more and 300 nm or less. (6) A method for manufacturing a wiring board according to the present disclosure includes the steps of: forming a groove recessed from the first surface toward the second surface in an insulating layer having a first surface and a second surface opposite the first surface; forming a first base metal layer covering the first surface and an inner wall surface of the groove; forming a first electrolytically plated layer on the first base metal layer to a thickness sufficient to fill the groove; removing at least the first base metal layer and the first electrolytically plated layer on the first surface to form a first wiring conductor including a narrow pattern having a width of 15 μm or less located in the groove; and forming a second wiring conductor on the first surface including a second base metal layer and a second electrolytically plated layer on the second base metal layer, the second wiring conductor including a wide pattern having a width of 150 μm or more.

[0056] REFERENCE SIGNS LIST 1 Core layer 1a Core insulating layer 1T Through hole 11 Core conductor layer 12 Through hole conductor 2 Build-up layer 2a Insulating layer (build-up insulating layer) 2a1 First surface 2a2 Second surface 2G Groove 2V Via hole 21 First wiring conductor 21a First base metal layer 21b First electrolytic plated layer 22 Second wiring conductor 22a Second base metal layer 22b Second electrolytic plated layer 23 Via hole conductor 3 Solder resist 4 Resist

Claims

1. A wiring board comprising: an insulating layer having a first surface and a second surface located opposite the first surface; a first wiring conductor located in a groove recessed from the first surface toward the second surface, the first wiring conductor including a narrow pattern having a width of 15 μm or less; and a second wiring conductor located on the first surface, the second wiring conductor including a wide pattern having a width of 150 μm or more, wherein the first wiring conductor includes a first base metal layer located on an inner wall surface of the groove, and a first electrolytic plating layer located on the first base metal layer and filling the groove, and the second wiring conductor includes a second base metal layer located on the first surface, and a second electrolytic plating layer located on the second base metal layer.

2. The wiring board according to claim 1, wherein an upper surface of the first wiring conductor is located closer to the second surface than the first surface.

3. The wiring board described in claim 1 or 2, further comprising a via hole conductor penetrating the insulating layer from the first surface to the second surface, and the second electrolytic plating layer is connected to the via hole conductor via the second base metal layer.

4. The wiring board according to claim 1, wherein the arithmetic mean roughness Ra of the region of the first wiring conductor that contacts the groove is 50 nm or more and 100 nm or less.

5. The wiring board according to any one of claims 1 to 4, wherein the arithmetic mean roughness Ra of the side surface of the second electrolytic plating layer is 150 nm or more and 300 nm or less.

6. A method for manufacturing a wiring board, comprising the steps of: forming a groove recessed from a first surface to a second surface in an insulating layer having a first surface and a second surface opposite the first surface; forming a first base metal layer covering the first surface and an inner wall surface of the groove; forming a first electrolytically plated layer located on the first base metal layer and having a thickness sufficient to fill the groove; removing at least the first base metal layer and the first electrolytically plated layer located on the first surface to form a first wiring conductor including a narrow pattern having a width of 15 μm or less located in the groove; and forming a second wiring conductor including a wide pattern having a width of 150 μm or more on the first surface, the second base metal layer and a second electrolytically plated layer located on the second base metal layer.

7. The method for manufacturing a wiring board according to claim 6, wherein in the step of forming the first wiring conductor, a process is performed to form the upper surface of the first wiring conductor closer to the second surface than the first surface.

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