Semiconductor element and semiconductor device

Abstract

A semiconductor element according to the present invention comprises a body, an electrode, rewiring, a first protective film, and a first intermediate layer. The electrode is positioned on one side of the body in a first direction. The rewiring is positioned on the side opposite the body with respect to the electrode. The first protective film is positioned on the same side as the rewiring with respect to the electrode. When viewed in the first direction, the first protective film overlaps the rewiring. The first intermediate layer includes a first portion positioned between the rewiring and the first protective film. The first portion is in contact with the first protective film. The first intermediate layer is an insulator and contains an inorganic compound. The adhesive force of the first protective film with respect to the first intermediate layer is stronger than the adhesive force of the first protective film with respect to the rewiring.

Description

Semiconductor element and semiconductor device

[0001] The present disclosure relates to a semiconductor element and a semiconductor device on which the semiconductor element is mounted.

[0002] Patent Document 1 discloses an example of a semiconductor element (referred to as a semiconductor device in Patent Document 1). The semiconductor element includes a substrate having an element formation surface, pad terminals provided on the element formation surface, Cu rewiring extending from the pad terminals, an organic coating covering the Cu rewiring, and a resin film covering the organic coating. The surface of the Cu rewiring includes a roughened surface that has been roughened. The organic coating is in contact with the roughened surface. This configuration allows the organic coating to exhibit an anchoring effect with respect to the Cu rewiring. Furthermore, since the organic coating has a relatively high affinity with the resin film, the adhesive strength of the resin film to the organic coating is stronger. This makes it possible to suppress peeling of the resin film from the Cu rewiring layer.

[0003] The manufacturing of the semiconductor element disclosed in Patent Document 1 requires a roughening treatment of the surface of the Cu redistribution layer and the formation of an organic coating covering the surface. The roughening treatment is performed by immersing the surface of the Cu redistribution layer formed by electrolytic plating in an etching solution. During the roughening treatment, careful attention must be paid to manufacturing management, such as the immersion time in the etching solution, to prevent breakage of the Cu redistribution layer. Therefore, there is a problem in that the manufacturing of the semiconductor element requires more labor.

[0004] Japanese Patent Application Laid-Open No. 2014-165335

[0005] [Summary] An object of the present disclosure is to provide an improved semiconductor element compared to conventional semiconductor elements. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor element that can suppress peeling of a protective film due to rewiring with a simpler configuration.

[0006] A semiconductor device provided by a first aspect of the present disclosure includes a body including a semiconductor layer, an electrode conducting to the semiconductor layer, a redistribution line conducting to the electrode, a first protective film, and a first intermediate layer. The electrode is located on one side of the body in a first direction. The redistribution line is located on the opposite side of the body from the electrode. The first protective film is located on the same side as the redistribution line from the electrode. When viewed in the first direction, the first protective film overlaps the redistribution line. The first intermediate layer includes a first portion located between the redistribution line and the first protective film. The first portion is in contact with the first protective film. The first intermediate layer is an insulator and includes an inorganic compound. The adhesive strength of the first protective film to the first intermediate layer is stronger than the adhesive strength of the first protective film to the redistribution line.

[0007] A semiconductor device provided by a second aspect of the present disclosure includes the semiconductor element provided by the first aspect of the present disclosure and a substrate including a conductive portion. The semiconductor element further includes a terminal. The semiconductor element is mounted on the substrate. The terminal is conductively bonded to the conductive portion.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a cross-sectional view of a semiconductor element according to a first embodiment of the present disclosure. FIG. 2 is a partially enlarged view of FIG. 1 , illustrating the vicinity of an electrode. FIG. 3 is a partially enlarged view of FIG. 1 , illustrating the vicinity of a terminal. FIG. 4 is a cross-sectional view illustrating a first step in a manufacturing process of the semiconductor element shown in FIG. 1 . FIG. 5 is a cross-sectional view illustrating a second step in a manufacturing process of the semiconductor element shown in FIG. 1 . FIG. 6 is a cross-sectional view illustrating a third step in a manufacturing process of the semiconductor element shown in FIG. 1 . FIG. 7 is a cross-sectional view illustrating a fourth step in a manufacturing process of the semiconductor element shown in FIG. 1 . FIG. 8 is a cross-sectional view illustrating a fifth step in a manufacturing process of the semiconductor element shown in FIG. 1 . FIG. 9 is a cross-sectional view illustrating a sixth step in a manufacturing process of the semiconductor element shown in FIG. 1 . FIG. 10 is a cross-sectional view illustrating a seventh step in a manufacturing process of the semiconductor element shown in FIG. 1 . FIG. 11 is a cross-sectional view illustrating an eighth step in a manufacturing process of the semiconductor element shown in FIG. 1 . FIG. 12 is a cross-sectional view illustrating a ninth step in a manufacturing process of the semiconductor element shown in FIG. 1 . FIG. 13 is a cross-sectional view illustrating a tenth step in a manufacturing process of the semiconductor element shown in FIG. 1 . FIG. 14 is a cross-sectional view illustrating an eleventh step in the manufacturing process of the semiconductor element shown in FIG. 1 . FIG. 15 is a cross-sectional view illustrating a twelfth step in the manufacturing process of the semiconductor element shown in FIG. 1 . FIG. 16 is a cross-sectional view of a semiconductor device on which the semiconductor element shown in FIG. 1 is mounted. FIG. 17 is a cross-sectional view of a semiconductor element according to a second embodiment of the present disclosure. FIG. 18 is a partial enlarged view of FIG. 17 showing the vicinity of the electrodes. FIG. 19 is a partial enlarged view of FIG. 17 showing the vicinity of the terminals. FIG. 20 is a cross-sectional view illustrating a fifth step in the manufacturing process of the semiconductor element shown in FIG. 17 . FIG. 21 is a cross-sectional view illustrating a sixth step in the manufacturing process of the semiconductor element shown in FIG. 17 . FIG. 22 is a cross-sectional view of a semiconductor element according to a third embodiment of the present disclosure. FIG. 23 is a partial enlarged view of FIG. 22 . FIG. 24 is a cross-sectional view illustrating a step subsequent to the eighth step in the manufacturing process of the semiconductor element shown in FIG. 22 . FIG. 25 is a cross-sectional view illustrating a step subsequent to the step shown in FIG. 24 in the manufacturing process of the semiconductor element shown in FIG. 22 . FIG. 26 is a cross-sectional view of a semiconductor element according to a fourth embodiment of the present disclosure. FIG. 27 is a partially enlarged view of FIG.

[0010] DETAILED DESCRIPTION The present disclosure will be described in detail with reference to the accompanying drawings.

[0011] 1 to 3, a semiconductor element A10 according to a first embodiment of the present disclosure will be described. The semiconductor element A10 is an LSI (Large Scale Integration) known as a wafer level-chip size package (WL-CSP). The semiconductor element A10 includes a body 11, multiple electrodes 12, a passivation film 13, multiple rewirings 20, a first protective film 31, a second protective film 32, a third protective film 33, a first intermediate layer 41, multiple terminals 50, and multiple bonding layers 60.

[0012] In the description of the semiconductor element A10 and the semiconductor device B described later, for convenience, for example, the normal direction to the main surface 11A of the body 11 described later will be referred to as the "first direction z." Also, for example, the direction perpendicular to the first direction z will be referred to as the "second direction x." Figure 1 is a cross-sectional view in which the first direction z and the second direction x are in-plane directions.

[0013] As shown in FIG. 1 , the main body 11 includes a semiconductor substrate 111 and a semiconductor layer 112 located on one side of the semiconductor substrate 111 in the first direction z. The main body 11 has a main surface 11A and a back surface 11B facing opposite each other in the first direction z. The semiconductor substrate 111 includes the back surface 11B. The semiconductor layer 112 includes the main surface 11A. The semiconductor substrate 111 is obtained from, for example, a silicon wafer. Various semiconductor circuits such as transistors and diodes are configured on and near the main surface 11A of the semiconductor layer 112.

[0014] 1 , the plurality of electrodes 12 are located on one side of the main body 11 in the first direction z. The plurality of electrodes 12 are in contact with the main surface 11A of the main body 11. The plurality of electrodes 12 are electrically connected to various semiconductor circuits configured in the semiconductor layer 112.

[0015] The passivation film 13 covers the main surface 11A of the main body 11. The passivation film 13 is in contact with the plurality of electrodes 12. Each of the plurality of electrodes 12 is exposed from the passivation film 13. The passivation film 13 is a thin film containing silicon dioxide (SiO) or silicon nitride (SiN), or a laminate of these thin films.

[0016] As shown in FIG. 1 , the second protective film 32 is located between the main body 11 and the first protective film 31 in the first direction z. The second protective film 32 covers a portion of each of the plurality of electrodes 12 and the passivation film 13. The second protective film 32 is an insulator containing an organic compound. The second protective film 32 is made of a material containing polyimide. As shown in FIGS. 1 and 2 , the second protective film 32 has a plurality of second openings 321 that penetrate in the first direction z. A plurality of electrodes 12 are individually exposed from each of the plurality of second openings 321.

[0017] As shown in FIG. 1 , the multiple rewirings 20 are located on the opposite side of the main body 11 from the multiple electrodes 12 in the first direction z. Each of the multiple rewirings 20 is electrically connected to one of the multiple electrodes 12. As shown in FIGS. 2 and 3 , each of the multiple rewirings 20 includes an underlayer 20A and a conductive layer 20B. The underlayer 20A includes a barrier layer in contact with one of the multiple electrodes 12 and the second protective film 32, and a seed layer stacked on the barrier layer. The barrier layer includes titanium (Ti). The seed layer includes copper (Cu). The conductive layer 20B is stacked on the seed layer of the underlayer 20A. The conductive layer 20B includes copper. The dimension of the conductive layer 20B in the first direction z is larger than the dimension of the underlayer 20A in the first direction z.

[0018] 1 and 2 , each of the multiple rewirings 20 has a main portion 21 and a contact portion 22. The contact portion 22 is electrically connected to one of the multiple electrodes 12. The contact portion 22 is housed in one of the multiple second openings 321 in the second protective film 32 and is in contact with the second protective film 32. The main portion 21 is connected to the contact portion 22. The main portion 21 extends in the second direction x.

[0019] 2 and 3 , the main portion 21 has a first surface 211 and a second surface 212. The first surface 211 faces the side opposite to the side facing the main body 11 in the first direction z. That is, the first surface 211 faces the same side as the main surface 11A of the main body 11 in the first direction z. The normal direction of the second surface 212 intersects with the first direction z. The second surface 212 is inclined with respect to the first surface 211. When viewed in the first direction z, the second surface 212 overlaps the first surface 211.

[0020] 1 and 2, the main portion 21 is provided with a recess 23 recessed from the first surface 211. The recess 23 overlaps the contact portion 22 when viewed in the first direction z.

[0021] As shown in FIG. 1 , the first protective film 31 is located on the same side as the rewirings 20 in the first direction z with respect to the electrodes 12. As viewed in the first direction z, the first protective film 31 overlaps the rewirings 20 and the second protective film 32. The first protective film 31 is an insulator containing an organic compound. The first protective film 31 is made of a material containing polyimide. In the semiconductor element A10, the composition of the first protective film 31 is the same as the composition of the second protective film 32. The dimension of the first protective film 31 in the first direction z is larger than the dimension of the second protective film 32 in the first direction z. As shown in FIGS. 1 and 3 , the first protective film 31 has a plurality of first openings 311 penetrating in the first direction z. The first surface 211 of one of the rewirings 20 is exposed from each of the plurality of first openings 311.

[0022] As shown in FIG. 2, the first protective film 31 is recessed into the recesses 23 of each of the plurality of rewirings 20 .

[0023] As shown in FIGS. 1 to 3 , the first intermediate layer 41 includes a first portion 411 located between the multiple rewirings 20 and the first protective film 31, and a second portion 412 located between the first protective film 31 and the second protective film 32. The first intermediate layer 41 is an insulator containing an inorganic compound. The first intermediate layer 41 is a thin film containing silicon dioxide or silicon nitride, or a laminate of these thin films. Therefore, the composition of the first intermediate layer 41 includes silicon (Si). Alternatively, the first intermediate layer 41 may be a ceramic containing aluminum oxide (AlO) or aluminum nitride (AlN). The adhesive strength of the first protective film 31 to the first intermediate layer 41 is stronger than the adhesive strength of the first protective film 31 to each of the multiple rewirings 20.

[0024] 2 and 3 , the first portion 411 is in contact with the multiple rewirings 20 and the first protective film 31. The first portion 411 includes a first region 411A covering the first surface 211 of each of the multiple rewirings 20 and a second region 411B covering the second surface 212 of each of the multiple rewirings 20. The first region 411A also covers a region of the main portion 21 that defines the recess 23 of each of the multiple rewirings 20. The dimension of the second region 411B in a direction (second direction x) perpendicular to the first direction z is smaller than the dimension of the first region 411A in the first direction z.

[0025] 2 and 3 , the second portion 412 is in contact with the first protective film 31 and the second protective film 32. The second portion 412 is located on the opposite side of the first region 411A of the first portion 411 in the first direction z, with the second region 411B of the first portion 411 as the reference. In the semiconductor element A10, the first protective film 31 is spaced apart from the second protective film 32.

[0026] 1 , each of the multiple terminals 50 is located on the opposite side of the multiple electrodes 12 with respect to the multiple rewirings 20 in the first direction z. Each of the multiple terminals 50 is electrically connected to the main portion 21 of one of the multiple rewirings 20. The multiple terminals 50 are exposed from the first protective film 31.

[0027] As shown in FIG. 3 , each of the multiple terminals 50 includes an underlayer 50A and a conductive layer 50B. The underlayer 50A includes a barrier layer that contacts the main portion 21 of any of the multiple rewirings 20 and the first protective film 31, and a seed layer that is stacked on the barrier layer. The barrier layer includes titanium. The seed layer includes copper. The conductive layer 50B is stacked on the seed layer of the underlayer 50A. The conductive layer 50B includes copper. The dimension of the conductive layer 50B in the first direction z is larger than the dimension of the underlayer 50A in the first direction z.

[0028] 1 and 3 , each of the multiple terminals 50 has a base 51 and an extension 52. The base 51 is electrically connected to the main portion 21 of one of the multiple rewirings 20. A portion of the base 51 is housed in one of the multiple first openings 311 of the first protective film 31. The base 51 is in contact with the first protective film 31. A portion of the base 51 protrudes from the first protective film 31 in the first direction z. The extension 52 protrudes outward beyond one of the multiple first openings 311 when viewed in the first direction z. The extension 52 is in contact with the first protective film 31.

[0029] 1 , the base 51 has a recess 53 recessed in the first direction z toward the back surface 11B of the main body 11. As viewed in the first direction z, the recess 53 overlaps one of the plurality of first openings 311 of the first protective film 31.

[0030] As shown in FIG. 1 , the multiple bonding layers 60 are located on the opposite side of the multiple rewirings 20 relative to the multiple terminals 50 in the first direction z. The multiple bonding layers 60 are individually and electrically connected to the multiple terminals 50. The multiple bonding layers 60 are solder. Therefore, the composition of the multiple bonding layers 60 includes tin. The melting point of the multiple bonding layers 60 is lower than the melting point of the multiple terminals 50. Each of the multiple bonding layers 60 individually recesses into the recess 53 of each of the multiple terminals 50.

[0031] 1, the third protective film 33 is located on the opposite side of the second protective film 32 with respect to the main body 11 in the first direction z. The third protective film 33 covers the entire back surface 11B of the main body 11. The third protective film 33 is an insulator. The third protective film 33 contains, for example, an epoxy resin.

[0032] Next, an example of a method for manufacturing the semiconductor device A10 will be described with reference to Figures 4 to 15. Each of Figures 4 to 15 corresponds to Figure 1 showing the semiconductor device A10.

[0033] First, the first process P1 shown in Fig. 4 is performed. In the first process P1, a plurality of electrodes 12, a passivation film 13, and a third protective film 33 are formed on the main body 11 on which the semiconductor layer 112 has been formed. Here, the main body 11 corresponds to one element of a silicon wafer. The third protective film 33 is formed by applying a material containing epoxy resin to the rear surface 11B of the main body 11 and then curing the material.

[0034] Next, the second process P2 shown in FIG. 5 is performed. In the second process P2, a second protective film 32 is formed to cover the passivation film 13. The second protective film 32 is formed by applying a material containing photosensitive polyimide to the passivation film 13, and then curing the material through lithographic patterning. A plurality of second openings 321 are formed in the second protective film 32 by the lithographic patterning. A plurality of electrodes 12 are individually exposed through the plurality of second openings 321.

[0035] 6 is then performed. In the third process P3, oxides and the like formed on the surfaces of the plurality of electrodes 12 are removed by reactive ion etching (RIE), and then the base layer 20A is formed by sputtering. Through this process, the entire second protective film 32 and the plurality of electrodes 12 individually exposed through the plurality of second openings 321 of the second protective film 32 are covered with the base layer 20A.

[0036] Next, a fourth step P4 shown in FIG. 7 is performed. In the fourth step P4, a plurality of conductive layers 20B are formed. To form the plurality of conductive layers 20B, a first resist 81 is first applied to the base layer 20A, and then the first resist 81 is lithographically patterned. As a result, a plurality of openings 811 penetrating the first resist 81 in the first direction z are formed. Next, a plurality of conductive layers 20B are deposited by electrolytic plating using the base layer 20A as a conductive path. As a result, a plurality of conductive layers 20B are formed, each individually accommodated in a plurality of openings 811.

[0037] Next, a fifth process P5 shown in FIG. 8 is performed. In the fifth process P5, the first resist 81 is removed, and then the areas of the base layer 20A exposed from the plurality of conductive layers 20B are removed. The base layer 20A is removed by wet etching using a mixed solution of sulfuric acid (HSO) and hydrogen peroxide (HO). This completes the formation of the plurality of rewirings 20.

[0038] 9 is performed. In the sixth process P6, the first intermediate layer 41 is formed by plasma CVD (Chemical Vapor Deposition) or sputtering. By this process, the first protective film 31 and each of the plurality of rewirings 20 are entirely covered with the first intermediate layer 41.

[0039] Next, a seventh process P7 shown in FIG. 10 is performed. In the seventh process P7, a first protective film 31 is formed to cover the first intermediate layer 41. The first protective film 31 is formed by applying a material containing photosensitive polyimide to the first intermediate layer 41, followed by lithographic patterning and curing. A plurality of first openings 311 are formed in the first protective film 31 by the lithographic patterning. A first region 411A of a first portion 411 of the first intermediate layer 41 is exposed from the plurality of first openings 311.

[0040] 11 is performed. In the eighth process P8, reactive ion etching is performed to remove the first region 411A of the first portion 411 of the first intermediate layer 41 exposed from the first openings 311 of the first protective film 31. By this process, the first surface 211 of any one of the rewirings 20 is exposed from each of the first openings 311.

[0041] 12 is performed. In the ninth step P9, a base layer 50A is formed by sputtering. By this step, the entire first protective film 31 and the first surfaces 211 of any of the rewirings 20 exposed from the first openings 311 of the first protective film 31 are covered with the base layer 50A.

[0042] Next, a tenth step P10 shown in FIG. 13 is performed. In the tenth step P10, a plurality of conductive layers 50B are formed. To form the plurality of conductive layers 50B, first, a second resist 82 is applied to the base layer 50A, and then the second resist 82 is lithographically patterned. This results in a plurality of openings 821 penetrating the second resist 82 in the first direction z. Next, a plurality of conductive layers 50B are deposited by electrolytic plating using the base layer 50A as a conductive path. As a result, a plurality of conductive layers 50B are formed, each individually accommodated in a plurality of openings 821.

[0043] Next, an eleventh process P11 shown in FIG. 14 is performed. In the eleventh process P11, the second resist 82 is removed, and then the areas of the base layer 50A exposed from the plurality of conductive layers 50B are removed. The base layer 50A is removed by wet etching using a mixed solution of sulfuric acid and hydrogen peroxide. This completes the formation of the plurality of terminals 50.

[0044] Next, a twelfth process P12 shown in FIG. 15 is performed. In the twelfth process P12, a plurality of bonding layers 60 are formed. To form the plurality of bonding layers 60, first, a material containing solder is placed on the plurality of terminals 50. Then, the material is melted by reflow. Finally, the melted material is hardened. In this manner, a plurality of bonding layers 60 are formed, each individually placed on the plurality of terminals 50.

[0045] Finally, the main body 11, which is one element of the silicon wafer, is divided into individual pieces by blade dicing, etc. Through the above steps, the semiconductor element A10 is obtained.

[0046] Next, a semiconductor device B on which the semiconductor element A10 is mounted will be described with reference to FIG.

[0047] 16 , the semiconductor device B includes a semiconductor element A10 and a base material 71. The semiconductor element A10 is mounted on the base material 71. The base material 71 includes a substrate 711 and a conductive portion 712. The substrate 711 is an insulator. The conductive portion 712 includes, for example, copper. The multiple terminals 50 of the semiconductor element A10 are conductively bonded to the conductive portion 712 via multiple bonding layers 60.

[0048] In semiconductor device B, the base material 71 is a wiring board. Alternatively, the base material 71 may include only conductive portions 712 that are leads. Furthermore, the base material 71 may include external terminals located on the opposite side of the substrate 711 from the conductive portions 712 in the first direction z. In semiconductor device B, at least a portion of the semiconductor element A10 may be covered with a sealing resin such as underfill.

[0049] Next, the effects of the semiconductor element A10 will be described.

[0050] The semiconductor element A10 includes a body 11, an electrode 12, a redistribution line 20, a first protective film 31, and a first intermediate layer 41. The first intermediate layer 41 includes a first portion 411 located between the redistribution line 20 and the first protective film 31. The first portion 411 is in contact with the first protective film 31. The first intermediate layer 41 is an insulator containing an inorganic compound. The adhesive strength of the first protective film 31 to the first intermediate layer 41 is stronger than the adhesive strength of the first protective film 31 to the redistribution line 20. This configuration allows the first protective film 31 to be more firmly adhered to the first intermediate layer 41 at the interface between the redistribution line 20 and the first protective film 31. Therefore, this configuration makes it possible to suppress peeling of the first protective film 31 from the redistribution line 20 with a simpler configuration in the semiconductor element A10.

[0051] The first portion 411 of the first intermediate layer 41 is in contact with the rewiring 20. By adopting this configuration, unintentional peeling of the first intermediate layer 41 from the rewiring 20 can be prevented.

[0052] The rewiring 20 has a first surface 211 and a second surface 212. The second surface 212 is inclined with respect to the second surface 212. When viewed in the first direction z, the second surface 212 overlaps the first surface 211. The first portion 411 of the first intermediate layer 41 covers the first surface 211 and the second surface 212. With this configuration, a reaction force in the first direction z acts from the rewiring 20 toward the first protective film 31 at the interface between the second surface 212 and the first protective film 31. This makes it possible to suppress peeling of the first protective film 31 from the rewiring 20, starting from the interface between the second surface 212 and the first protective film 31.

[0053] The semiconductor element A10 further includes a second protective film 32 located between the body 11 and the first protective film 31. The second protective film 32 covers a portion of the electrode 12. This configuration can suppress leakage current from the electrode 12 due to the arrangement of the rewiring 20.

[0054] The first intermediate layer 41 includes a second portion 412 located between the first protective film 31 and the second protective film 32. The second portion 412 is in contact with the first protective film 31 and the second protective film 32. This configuration makes it possible to suppress peeling of the first protective film 31 from the second protective film 32, even when the affinity between the first protective film 31 and the second protective film 32 is relatively low.

[0055] The semiconductor element A10 further includes a terminal 50. A portion of the terminal 50 is housed in a first opening 311 of the first protective film 31. When viewed in the first direction z, the first protective film 31 has an extension 52 that protrudes outward from the first opening 311. By adopting this configuration, the bonding area of ​​the terminal 50 with respect to the conductive portion 712 of the substrate 71 can be further increased in the semiconductor device B.

[0056] The semiconductor element A10 further includes a bonding layer 60 located on the opposite side of the terminal 50 from the rewiring 20. The bonding layer 60 is electrically connected to the terminal 50. The melting point of the bonding layer 60 is lower than the melting point of the terminal 50. By adopting this configuration, the terminal 50 can be easily conductively bonded to the conductive portion 712 of the substrate 71 in the semiconductor device B.

[0057] The bonding layer 60 recesses into the recess 53 of the terminal 50. With this configuration, in the semiconductor device B, the bonding layer 60 exhibits an anchoring effect with respect to the terminal 50. This improves the bonding strength of the substrate 71 to the conductive portion 712.

[0058] The semiconductor element A10 further includes a third protective film 33 located on the opposite side of the body 11 from the second protective film 32. The third protective film 33 covers the body 11. This configuration can reduce warping of the body 11 around a direction perpendicular to the first direction z during the process of forming the redistribution lines 20, the first protective film 31, the second protective film 32, the first intermediate layer 41, and the terminals 50 in the manufacture of the semiconductor element A10.

[0059] Second Embodiment: A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to Figures 17 to 19. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are designated by the same reference numerals, and duplicated descriptions will be omitted. Here, Figure 17 corresponds to Figure 1, which shows the semiconductor device A10.

[0060] In the semiconductor element A20, the configuration of the first intermediate layer 41 is different from that of the semiconductor element A10.

[0061] 17 to 19 , the first intermediate layer 41 includes only the first region 411A of the first portion 411. Therefore, the first intermediate layer 41 does not include the second region 411B of the first portion 411 and the second portion 412. The second surface 212 of each of the multiple rewirings 20 is in contact with the first protective film 31. The first protective film 31 is in contact with the second protective film 32.

[0062] Next, an example of a method for manufacturing the semiconductor element A20 will be described with reference to Figures 20 and 21. Each of Figures 20 and 21 corresponds to Figure 17 showing the semiconductor element A20.

[0063] In the manufacturing process of the semiconductor element A20, the first process P1 to the fourth process P4 and the seventh process P7 to the twelfth process P12 are the same as the manufacturing process of the semiconductor element A10 described above. Therefore, in the description of the manufacturing method of the semiconductor element A20, only the fifth process P5 and the sixth process P6 will be described.

[0064] After the fourth process P4 (see FIG. 7 ) is completed, the fifth process P5 shown in FIG. 20 is performed. In the fifth process P5, the first intermediate layer 41 is formed by plasma CVD or sputtering. By this process, the entire surface of the first resist 81 and the entire surfaces of the plurality of conductive layers 20B exposed from the plurality of openings 811 are covered with the first intermediate layer 41.

[0065] Next, a sixth process P6 shown in FIG. 21 is performed. In the sixth process P6, the first resist 81 is removed, and then the regions of the base layer 20A exposed from the plurality of conductive layers 20B are removed. By removing the first resist 81, the region of the first intermediate layer 41 that covers the entire surface of the first resist 81 is removed by lift-off. The base layer 20A is removed by wet etching using a mixed solution of sulfuric acid and hydrogen peroxide. This completes the formation of the plurality of rewirings 20. The second surface 212 of each of the plurality of rewirings 20 and the surface of the second protective film 32 are exposed from the first intermediate layer 41.

[0066] Next, the effects of the semiconductor element A20 will be described.

[0067] The semiconductor element A20 includes a body 11, electrodes 12, redistribution lines 20, a first protective film 31, and a first intermediate layer 41. The first intermediate layer 41 includes a first portion 411 located between the redistribution lines 20 and the first protective film 31. The first portion 411 is in contact with the first protective film 31. The first intermediate layer 41 is an insulator containing an inorganic compound. The adhesive strength of the first protective film 31 to the first intermediate layer 41 is stronger than the adhesive strength of the first protective film 31 to the redistribution lines 20. Therefore, with this configuration, even in the semiconductor element A20, peeling of the first protective film 31 from the redistribution lines 20 can be suppressed with a simpler configuration. Furthermore, by having a configuration common to the semiconductor element A10, the semiconductor element A20 achieves the same effects as the semiconductor element A10.

[0068] In the semiconductor element A20, the first protective film 31 is in contact with the second protective film 32. The composition of the second protective film 32 is the same as the composition of the first protective film 31. Even in this configuration, the affinity between the first protective film 31 and the second protective film 32 is relatively high, so peeling of the first protective film 31 from the second protective film 32 can be suppressed.

[0069] Third Embodiment: A semiconductor device A30 according to a third embodiment of the present disclosure will be described with reference to Figures 22 and 23. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are designated by the same reference numerals, and duplicated descriptions will be omitted. Here, Figure 22 corresponds to Figure 1, which shows the semiconductor device A10.

[0070] The semiconductor element A30 differs from the semiconductor element A10 in that it further includes a second intermediate layer 42.

[0071] As shown in Figures 22 and 23 , the second intermediate layer 42 includes a portion located between the first protective film 31 and the extension portion 52 of each of the multiple terminals 50. The second intermediate layer 42 is an insulator containing an inorganic compound. The composition of the second intermediate layer 42 is the same as the composition of the first intermediate layer 41. As a result, the adhesive strength of the first protective film 31 to the second intermediate layer 42 is stronger than the adhesive strength of the first protective film 31 to each of the multiple terminals 50. The second intermediate layer 42 is in contact with the first protective film 31 and the extension portion 52 of each of the multiple terminals 50.

[0072] Next, an example of a method for manufacturing the semiconductor element A30 will be described with reference to Figures 24 and 25. Each of Figures 24 and 25 corresponds to Figure 22 showing the semiconductor element A30.

[0073] The manufacturing process of the semiconductor element A30 further includes, between the eighth step P8 and the ninth step P9, a step of forming a second intermediate layer 42, in addition to the manufacturing process of the semiconductor element A10 described above. Therefore, in the description of the manufacturing method of the semiconductor element A30, only the step of forming the second intermediate layer 42 will be described.

[0074] After the eighth process P8 (see FIG. 11 ) is completed, the second intermediate layer 42 is formed as shown in FIG. 24 . The second intermediate layer 42 is formed by plasma CVD or sputtering. By this process, the entire surface of the first protective film 31 and the first faces 211 of any of the multiple rewirings 20 exposed from the multiple first openings 311 of the first protective film 31 are covered with the second intermediate layer 42.

[0075] 25 , the portions of the second intermediate layer 42 exposed from the plurality of first openings 311 in the first protective film 31 are removed. The second intermediate layer 42 is removed by reactive ion etching. This process exposes the first surfaces 211 of any of the plurality of rewirings 20 from each of the plurality of first openings 311. This completes the formation of the second intermediate layer 42.

[0076] Next, the effects of the semiconductor element A30 will be described.

[0077] The semiconductor element A30 includes a body 11, electrodes 12, rewirings 20, a first protective film 31, and a first intermediate layer 41. The first intermediate layer 41 includes a first portion 411 located between the rewirings 20 and the first protective film 31. The first portion 411 is in contact with the first protective film 31. The first intermediate layer 41 is an insulator containing an inorganic compound. The adhesive strength of the first protective film 31 to the first intermediate layer 41 is stronger than the adhesive strength of the first protective film 31 to the rewirings 20. Therefore, with this configuration, even in the semiconductor element A30, peeling of the first protective film 31 from the rewirings 20 can be suppressed with a simpler configuration. Furthermore, by having a configuration common to the semiconductor element A10, the semiconductor element A30 achieves the same effects as the semiconductor element A10.

[0078] The semiconductor element A30 further includes a second intermediate layer 42 that includes a portion located between the first protective film 31 and the extension portion 52 of the terminal 50. The composition of the second intermediate layer 42 is the same as the composition of the first intermediate layer 41. The second intermediate layer 42 is in contact with the first protective film 31 and the extension portion 52. With this configuration, even if the area of ​​the terminal 50 is further expanded as viewed in the first direction z, the first protective film 31 remains adhered to the second intermediate layer 42 at the interface between the extension portion 52 and the first protective film 31. The adhesion between the first protective film 31 and the second intermediate layer 42 is relatively strong. This prevents the first protective film 31 from peeling off from the terminal 50.

[0079] Fourth Embodiment: A semiconductor device A40 according to a fourth embodiment of the present disclosure will be described with reference to Figures 26 and 27. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are designated by the same reference numerals, and duplicated descriptions will be omitted. Here, Figure 26 corresponds to Figure 1, which shows the semiconductor device A10.

[0080] The semiconductor element A40 differs from the semiconductor element A10 in that it does not include the passivation film 13.

[0081] 26 and 27, the semiconductor element A40 does not include the passivation film 13. The second protective film 32 covers the main surface 11A of the body 11.

[0082] Next, the effects of the semiconductor element A40 will be described.

[0083] The semiconductor element A40 includes a body 11, electrodes 12, rewirings 20, a first protective film 31, and a first intermediate layer 41. The first intermediate layer 41 includes a first portion 411 located between the rewirings 20 and the first protective film 31. The first portion 411 is in contact with the first protective film 31. The first intermediate layer 41 is an insulator containing an inorganic compound. The adhesive strength of the first protective film 31 to the first intermediate layer 41 is stronger than the adhesive strength of the first protective film 31 to the rewirings 20. Therefore, with this configuration, even in the semiconductor element A40, peeling of the first protective film 31 from the rewirings 20 can be suppressed with a simpler configuration. Furthermore, by having a configuration common to the semiconductor element A10, the semiconductor element A40 achieves the same effects as the semiconductor element A10.

[0084] In the semiconductor element A40, the second protective film 32 covers the main surface 11A of the main body 11. By adopting this configuration, even if the passivation film 13 is not provided, the second protective film 32 can protect and insulate the semiconductor layer 112 of the main body 11.

[0085] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0086] The present disclosure includes embodiments described in the following supplementary notes. Supplementary note 1. A semiconductor device comprising: a body including a semiconductor layer; an electrode located on one side of the body in a first direction and conducting to the semiconductor layer; a redistribution line located on the opposite side of the body with respect to the electrode and conducting to the electrode; a first protective film located on the same side as the redistribution line with respect to the electrode and overlapping the redistribution line when viewed in the first direction; and a first intermediate layer including a first portion located between the redistribution line and the first protective film, wherein the first portion is in contact with the first protective film, the first intermediate layer is an insulator and contains an inorganic compound, and an adhesive strength of the first protective film to the first intermediate layer is stronger than an adhesive strength of the first protective film to the redistribution line. Supplementary note 2. The semiconductor device described in Supplementary note 1, wherein the first portion is in contact with the redistribution line. Supplementary note 3. The semiconductor device described in Supplementary note 2, wherein the first protective film contains an organic compound. Supplementary note 4. The semiconductor element according to Appendix 3, wherein the first intermediate layer has a composition including silicon. Appendix 5. The semiconductor element according to Appendix 3, wherein the redistribution line has a first surface facing the side opposite to the side facing the main body in the first direction, and the first portion covers the first surface. Appendix 6. The semiconductor element according to Appendix 5, wherein the redistribution line has a second surface, a normal direction of the second surface intersects the first direction, and the first portion covers the second surface. Appendix 7. The semiconductor element according to Appendix 6, wherein the second surface is inclined with respect to the first surface. Appendix 8. The semiconductor element according to Appendix 7, wherein the second surface overlaps the first surface as viewed in the first direction. Appendix 9. The semiconductor element according to Appendix 8, wherein the first portion includes a first region covering the first surface and a second region covering the second surface, and wherein a dimension of the second region in a direction perpendicular to the first direction is smaller than a dimension of the first region in the first direction. Appendix 10. The semiconductor device according to any one of claims 5 to 9, further comprising a second protective film, the second protective film being located between the body and the first protective film, and the second protective film covering a portion of each of the electrodes. Appendix 11. The semiconductor device according to claim 10, wherein the composition of the second protective film is the same as the composition of the first protective film.Appendix 12. The semiconductor element according to Appendix 11, wherein the first intermediate layer includes a second portion located between the first protective film and the second protective film, and the second portion is in contact with the first protective film and the second protective film. Appendix 13. The semiconductor element according to Appendix 11, wherein the first protective film is in contact with the second protective film. Appendix 14. The semiconductor element according to Appendix 12, wherein the redistribution line has a main portion including the first surface and a contact portion connected to the main portion, and the contact portion is electrically connected to the electrode and in contact with the second protective film. Appendix 15. The semiconductor element according to Appendix 14, further comprising a terminal electrically connected to the redistribution line, the terminal being located on the opposite side of the redistribution line from the electrode, and the terminal being exposed from the first protective film. Appendix 16. The semiconductor element according to Appendix 15, wherein the first protective film has a first opening that penetrates in the first direction and exposes the rewiring, a portion of the terminal is accommodated in the first opening, and the terminal has an extension that protrudes outward from the first opening as viewed in the first direction. Appendix 17. The semiconductor element according to Appendix 16, further comprising a second intermediate layer including a portion located between the first protective film and the extension, wherein the composition of the second intermediate layer is the same as the composition of the first intermediate layer, and the second intermediate layer is in contact with the first protective film and the extension. Appendix 18. The semiconductor element according to Appendix 16, wherein the extension is in contact with the first protective film. Appendix 19. The semiconductor element according to Appendix 16, further comprising a third protective film located on the opposite side of the main body to the second protective film, and the third protective film covers the main body. Appendix 20. A semiconductor device comprising: a semiconductor element according to Appendix 15; and a substrate including a conductive portion, wherein the semiconductor element is mounted on the substrate, and the terminal is conductively joined to the conductive portion. Appendix 21. A semiconductor element according to Appendix 3, wherein the first protective film includes polyimide. Appendix 22. A semiconductor element according to Appendix 3, wherein the first intermediate layer includes aluminum oxide. Appendix 23. A semiconductor element according to Appendix 4, wherein the first intermediate layer includes at least one of silicon dioxide and silicon nitride.Appendix 24. The semiconductor element according to Appendix 10, wherein the second protective film covers the main body. Appendix 25. The semiconductor element according to Appendix 11, wherein each of the first protective film and the second protective film includes polyimide. Appendix 26. The semiconductor element according to Appendix 24, wherein a dimension of the second protective film in the first direction is smaller than a dimension of the first protective film in the first direction. Appendix 27. The semiconductor element according to Appendix 12, wherein the first protective film is spaced apart from the second protective film. Appendix 28. The semiconductor element according to Appendix 14, wherein the main portion is provided with a recess recessed from the first surface, and the first protective film is recessed into the recess. Appendix 29. The semiconductor element according to Appendix 16, wherein the second protective film is provided with a second opening that penetrates in the first direction and exposes the electrode, and the contact portion is housed in the second opening. Appendix 30. 17. The semiconductor element of claim 16, further comprising a bonding layer electrically connected to the terminal, the bonding layer being located on the opposite side of the terminal from the rewiring, and the melting point of the bonding layer being lower than the melting point of the terminal.

[0087] A10 to A40: semiconductor element B: semiconductor device 11: body 11A: main surface 11B: back surface 111: semiconductor substrate 112: semiconductor layer 12: electrode 13: passivation film 20: rewiring 20A: underlayer 20B: conductive layer 21: main portion 211: first surface 212: second surface 22: contact portion 23: recess 31: first protective film 311: first opening 32: second protective film 321: second opening 33: third protective film 41: first intermediate layer 411: first portion 411A, 411B: first region, second region 412: second portion 42: second intermediate layer 50: terminal 51: base portion 52: extension portion 53: recess 60: bonding layer 71: base material 711: substrate 712: Conductive portion 81: First resist 811: Opening 82: Second resist 821: Opening P1 to P12: First to twelfth steps z: First direction x: Second direction

Claims

1. A semiconductor device comprising: a body including a semiconductor layer; an electrode located on one side of the body in a first direction and conducting to the semiconductor layer; a rewiring located on the opposite side of the body with respect to the electrode and conducting to the electrode; a first protective film located on the same side as the rewiring with respect to the electrode and overlapping the rewiring when viewed in the first direction; and a first intermediate layer including a first portion located between the rewiring and the first protective film, wherein the first portion is in contact with the first protective film, the first intermediate layer is an insulator and contains an inorganic compound, and an adhesive strength of the first protective film to the first intermediate layer is stronger than an adhesive strength of the first protective film to the rewiring.

2. The semiconductor element according to claim 1, wherein the first portion is in contact with the rewiring.

3. The semiconductor element according to claim 2, wherein the first protective film includes an organic compound.

4. The semiconductor device according to claim 3, wherein the composition of the first intermediate layer includes silicon.

5. The semiconductor element according to claim 3, wherein the redistribution line has a first surface facing the opposite side to the side facing the main body in the first direction, and the first portion covers the first surface.

6. The semiconductor element according to claim 5, wherein the redistribution line has a second surface, a normal direction of the second surface intersects with the first direction, and the first portion covers the second surface.

7. The semiconductor device according to claim 6, wherein said second surface is inclined relative to said first surface.

8. The semiconductor element according to claim 7, wherein the second surface overlaps the first surface when viewed in the first direction.

9. The semiconductor element described in claim 8, wherein the first portion includes a first region covering the first surface and a second region covering the second surface, and a dimension of the second region in a direction perpendicular to the first direction is smaller than a dimension of the first region in the first direction.

10. A semiconductor element according to any one of claims 5 to 9, further comprising a second protective film, the second protective film being located between the body and the first protective film, and the second protective film covering a portion of each of the electrodes.

11. The semiconductor device according to claim 10, wherein the composition of the second protective film is the same as the composition of the first protective film.

12. The semiconductor element described in claim 11, wherein the first intermediate layer includes a second portion located between the first protective film and the second protective film, and the second portion is in contact with the first protective film and the second protective film.

13. The semiconductor element according to claim 11, wherein the first protective film is in contact with the second protective film.

14. The semiconductor element described in claim 12, wherein the redistribution line has a main portion including the first surface and a contact portion connected to the main portion, the contact portion being electrically connected to the electrode and in contact with the second protective film.

15. The semiconductor element according to claim 14, further comprising a terminal electrically connected to the rewiring, the terminal being located on the opposite side of the rewiring from the electrode, and the terminal being exposed from the first protective film.

16. A semiconductor element as described in claim 15, wherein the first protective film is provided with a first opening that penetrates in the first direction and exposes the rewiring, a portion of the terminal is accommodated in the first opening, and when viewed in the first direction, the terminal has an extension that protrudes outward beyond the first opening.

17. The semiconductor device described in claim 16, further comprising a second intermediate layer including a portion located between the first protective film and the extension portion, the composition of the second intermediate layer being the same as the composition of the first intermediate layer, and the second intermediate layer being in contact with the first protective film and the extension portion.

18. The semiconductor element according to claim 16, wherein the extension portion is in contact with the first protective film.

19. The semiconductor device according to claim 16, further comprising a third protective film located on the opposite side of the body to the second protective film, the third protective film covering the body.

20. A semiconductor device comprising: a semiconductor element according to claim 15; and a substrate including a conductive portion, the semiconductor element being mounted on the substrate; and the terminal being conductively joined to the conductive portion.

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