Transimpedance amplifier circuit

Abstract

The present invention is provided with a transimpedance amplifier (12) including a control unit (11) that separates an input control signal (st) generated by a reset signal (s1) and a band switching signal (s2) into the reset signal (s1) and the band switching signal (s2), a first input unit (P1) that inputs the reset signal (s1), and a second input unit (P2) that inputs the band switching signal (s2), with the transimpedance amplifier (12) converting a current signal into a voltage signal using the reset signal (s1) and the band switching signal (s2).

Description

Transimpedance Amplifier Circuit

[0001] The present disclosure relates to transimpedance amplifier circuits.

[0002] BACKGROUND ART Optical transmission systems that enable high-speed data transmission, such as passive optical network (PON) systems, use transimpedance amplifiers (hereinafter abbreviated as "TIAs") that convert optical signals into electrical signals.

[0003] A TIA receives the photocurrent obtained by a light-receiving element such as a photodiode as input and outputs a voltage according to the impedance conversion gain, which is proportional to the value of the feedback resistor. In a PON system, upstream packet data from each subscriber device (ONU; Optical Network Unit) to the central office device (OLT; Optical Line Terminal) is sent in bursts using time division multiplexing. Due to differences in the distance and route between the ONU and OLT, each packet arrives at the OLT with different optical power. Therefore, the electrical signal of the photocurrent obtained by optical-to-electrical conversion in the light-receiving element of the optical receiving circuit has different signal amplitudes for each packet.

[0004] Patent documents 1 and 2 disclose that by inputting a reset signal to the TIA, when a packet with a significantly different reception level arrives, a function is activated to instantly complete the AGC (Automatic Gain Control) operation and AOC (Automatic Offset Control) operation within the TIA.

[0005] Furthermore, in order to further enhance the functionality of PON systems, there is a demand for mixed accommodating speeds (1 Gbps and 10 Gbps, 10 Gbps and 25 Gbps, etc.) and for high-speed response of burst signals to improve bandwidth utilization efficiency.

[0006] Patent Document 1 discloses that by inputting a band switching signal (rate signal) to the TIA, the frequency band of the TIA is switched to a band suitable for the bit rate of the signal to be received, thereby improving reception sensitivity.

[0007] JP 2010-178257 A JP 2015-84474 A

[0008] However, in PON systems, the demand for smaller and lower-cost optical transceivers also requires smaller and lower-cost packages for the receiver optical subassembly (ROSA), which is an optical module for optical receivers. To supply the two control signals (reset signal and band switching signal) to the TIA, the reset signal and band switching signal must be assigned to two terminals on the package, increasing the number of terminals. This poses a problem, making it difficult to achieve smaller and lower-cost designs.

[0009] The present disclosure has been made in consideration of the above circumstances, and its purpose is to provide a transimpedance amplifier circuit that can reduce the number of terminals for supplying control signals to a TIA.

[0010] A transimpedance amplifier circuit according to one aspect of the present disclosure includes a control unit that separates an input control signal generated from a first control signal and a second control signal into the first control signal and the second control signal, a first input unit that inputs the first control signal, and a second input unit that inputs the second control signal, and a transimpedance amplifier that converts a current signal into a voltage signal using the first control signal and the second control signal.

[0011] According to the present disclosure, it is possible to reduce the number of terminals for supplying control signals to a TIA.

[0012] FIG. 1 is a block diagram showing the configuration of a TIA circuit according to a first embodiment. FIG. 2 is a block diagram showing the detailed configuration of a control unit mounted in the TIA circuit according to the first embodiment and a circuit connected in front of the TIA circuit. FIG. 3 is a correspondence diagram showing the relationship between the level of an input control signal and the operating state of the TIA according to the first embodiment. FIG. 4 is a timing chart showing changes in the input control signal st, reset signal s1, and band switching signal s2 according to the first embodiment. FIG. 5 is a block diagram showing the detailed configuration of a control unit mounted in a TIA circuit according to a second embodiment and a circuit connected in front of the TIA circuit. FIG. 6 is a circuit diagram showing a specific example of the configuration of a comparator used in a window comparator. FIG. 7A is a circuit diagram showing an example of a Schmitt trigger circuit configured using CMOS. FIG. 7B is a circuit diagram showing an example of a Schmitt trigger circuit configured using a comparator. FIG. 8A is a diagram showing the relationship between the lower limit voltage v3 and the upper limit voltage v4 of the Schmitt trigger circuit, and the third threshold voltage Vth3 and the fourth threshold voltage Vth4, in an example where v3 = Vth3 and v4 = Vth4. FIG. 8B is a diagram showing the relationship between the lower limit voltage v3 and the upper limit voltage v4 of the Schmitt trigger circuit, and the third threshold voltage Vth3 and the fourth threshold voltage Vth4, in an example where v3 > Vth3 and v4 > Vth4. FIG. 9 is a characteristics diagram showing the relationship between the voltage level input to the Schmitt trigger circuit and the output signal. FIG. 10 is a correspondence diagram showing the relationship between the level of the input control signal and the operating state of the TIA according to the second embodiment. FIG. 11 is a timing chart showing changes in the input control signal st, reset signal s1, and band switching signal s2 according to the second embodiment. FIG. 12 is a block diagram showing the detailed configuration of a control unit mounted in a TIA circuit according to a third embodiment and a circuit connected to the front stage of the TIA circuit. FIG. 13 is a block diagram showing the hardware configuration of this embodiment.

[0013] Hereinafter, an embodiment will be described with reference to the drawings.

[0014] [Description of First Embodiment] The first embodiment will be described with reference to Figures 1 to 4. Figure 1 is a block diagram showing the configuration of a transimpedance amplifier circuit 100 (hereinafter abbreviated as "TIA circuit 100") according to the first embodiment, and Figure 2 is a circuit diagram showing the detailed configuration of a control unit 11 mounted in the TIA circuit 100 and a circuit connected in a stage preceding the TIA circuit 100. Figure 3 is a correspondence diagram showing the relationship between the level of a control signal input to the TIA 100 (hereinafter referred to as "input control signal st", details of which will be described later) and the operating state of the TIA 12, and Figure 4 is a timing chart showing changes in the input control signal st, reset signal s1, and band switching signal s2.

[0015] 1, the TIA circuit 100 includes a control unit 11 and a transimpedance amplifier 12 (hereinafter abbreviated as "TIA 12"). The control unit 11 includes one input terminal Q1. The TIA circuit 100 is mounted on the stem of a ROSA TO-CAN (Transistor Outline-CAN) package, for example.

[0016] As shown in FIG. 2, a media access controller 31 (hereinafter abbreviated as "MAC 31"), a tri-state buffer 32, and a bias circuit 33 are provided in the preceding stage of the TIA circuit 100.

[0017] The MAC 21 controls media access for each device. The MAC 21 outputs a reset signal s1 and a band switching signal s2. The band switching signal s2 is a control signal for switching the frequency band of the TIA 12 to a band suitable for the bit rate of the received signal. The reset signal s1 is a control signal for instantly completing the AGC and AOC operations in the TIA 12 when a packet with a significantly different reception level arrives.

[0018] The tri-state buffer 32 receives the band switching signal s2 and the reset signal s1 output from the MAC 31. The tri-state buffer 32 generates an input control signal st that indicates one of three states: L level, intermediate level "(L+H) / 2," and H level. The voltage value of the input control signal st is also denoted by the same symbol "st."

[0019] The bias circuit 33 superimposes a voltage VDD / 2 on the output of the tri-state buffer 32. The bias circuit 33 may be provided within the TIA circuit 100.

[0020] The control unit 11 separates the input control signal st into a band switching signal s2 and a reset signal s1. The control unit 11 outputs the separated band switching signal s2 and reset signal s1 to the TIA 12. The control unit 11 is connected to an input terminal Q1 provided in the TIA circuit 100. The input terminal Q1 is connected to the output unit of the tri-state buffer 32. The input control signal st is input to the input terminal Q1.

[0021] The control unit 11 includes a first comparison unit 21 , a second comparison unit 22 , a first power supply 23 , a second power supply 24 , and an encoding circuit 13 .

[0022] The first power supply 23 outputs a first threshold voltage Vth1. The second power supply 24 outputs a second threshold voltage Vth2 (Vth2>Vth1). The first threshold voltage Vth1 is preferably set to a voltage slightly smaller than the intermediate value "(H+L) / 2" (intermediate level) between the H level and the L level, which will be described later. The second threshold voltage Vth2 is preferably set to a value slightly smaller than the H level.

[0023] An input control signal st is input to the non-inverting input terminal (+ terminal) of the first comparing unit 21, and a first threshold voltage Vth1 is input to the inverting input terminal (- terminal). An input control signal st is input to the non-inverting input terminal of the second comparing unit 22, and a second threshold voltage Vth2 is input to the inverting input terminal. That is, when the input control signal st satisfies "Vth1≦st", the output signal A1 of the first comparing unit 21 becomes H level. When the input control signal st satisfies "Vth2≦st", the output signal A0 of the second comparing unit 22 becomes H level.

[0024] The encoding circuit 13 includes a NOT circuit 25 and AND circuits 26 and 27. The output (output signal A0) of the second comparing section 22 branches into two systems, one of which is connected to the input of the NOT circuit 25 and the other of which is connected to one input of the AND circuit 26. The output of the NOT circuit 25 is connected to one input of the AND circuit 27.

[0025] The output (output signal A1) of the first comparison unit 21 branches into two systems, one branch line is connected to the other input of the AND circuit 26, and the other branch line is connected to the other input of the AND circuit 27.

[0026] The output (output signal Y0) of the AND circuit 26 and the output (output signal Y1) of the AND circuit 27 are respectively connected to the second input P2 and the first input P1 of the TIA 12. The output signal Y0 corresponds to the band switching signal s2, and the output signal Y1 corresponds to the reset signal s1.

[0027] When the input control signal st output from the tri-state buffer 32 is at L level, the output signals A1 and A0 are both at L level, and the output signals Y1 and Y0 are also at L level. That is, the band switching signal s2 at L level is input to the second input port P2 of the TIA 12, and the reset signal s1 is not input to the first input port P1.

[0028] When the input control signal st is at an intermediate level, the output signal A1 is at an H level, the output signal A0 is at an L level, the output signal Y1 is at an H level, and the output signal Y0 is at an L level. Therefore, a reset signal s1 is input to the first input port P1 of the TIA 12, and an L-level band switching signal s2 is input to the second input port P2.

[0029] When the input control signal st is at H level, the output signals A1 and A0 are both at H level, the output signal Y1 is at L level, and the output signal Y0 is at H level. Therefore, the band switching signal s2 is input to the second input port P2 of the TIA 12, and the reset signal s1 is not input to the first input port P1.

[0030] That is, the control unit 11 includes a first comparison unit 21 that compares the input control signal st with a predetermined first threshold voltage Vth1, a second comparison unit 22 that compares the input control signal st with a second threshold voltage Vth2 that is higher than the first threshold voltage Vth1, and an encoding circuit 13 that outputs a first control signal to the first input unit P1 when the input control signal st is equal to or greater than the first threshold voltage Vth1 and less than the second threshold voltage Vth2, and outputs a second control signal to the second input unit P2 when the input control signal st is equal to or greater than the second threshold voltage Vth2.

[0031] The control unit 11 separates the tri-state buffer output (input control signal st) generated by inputting a first control signal (e.g., a reset signal s1) and a second control signal (e.g., a band switching signal s2) into the first control signal and the second control signal.

[0032] The TIA 12 (transimpedance amplifier) ​​converts a current signal detected by, for example, a photoelectric conversion device into a voltage signal. When an H-level band switching signal s2 is input, the TIA 12 sets the reception state to the high band (high frequency band). When a reset signal s1 is input, the TIA 12 sets the reception state to the low band (low frequency band). When an L-level band switching signal s2 is input but the reset signal s1 is not input (when the input control signal st is L level), the TIA 12 sets the reception state to the low band.

[0033] 3, the frequency band of the TIA 12 is switched to either a "high band" or a "low band" depending on the three levels of the input control signal st: "H level," "intermediate level," and "L level." Also, the reset state of the TIA 12 is switched depending on the three levels.

[0034] That is, the TIA 12 has a first input section P1 for inputting a first control signal (reset signal s1) and a second input section P2 for inputting a second control signal (band switching signal s2), and converts a current signal into a voltage signal using the first control signal and the second control signal.

[0035] Next, the operation of the TIA circuit 100 according to the first embodiment configured as described above will be described with reference to the timing chart shown in Fig. 4. The tri-state buffer 32 shown in Fig. 2 outputs an input control signal st generated by a band switching signal s2 (H level or L level) and a reset signal s1. The input control signal st is a signal whose voltage level changes in three stages: L level, an intermediate level "(L+H) / 2", and H level, as shown in Fig. 4(a), for example.

[0036] In the example shown in FIG. 4A, intermediate levels are output at times t11, t13, t15, t17, and t19, H levels are output at times t12, t16, and t18, and L level is output at time t14.

[0037] At time t11, the input control signal st is at an intermediate level, so the output signal Y0 of the AND circuit 26 shown in Fig. 2 is at an L level, and the output signal Y1 of the AND circuit 27 shown in Fig. 2 is at an H level. Therefore, the band switching signal s2 shown in Fig. 4(b) is at an L level at time t11, and the reset signal s1 shown in Fig. 4(c) is at an H level at time t31 (corresponding to t11). Similarly, the reset signal s1 is also at an H level at times t32 (corresponding to t13), t33 (corresponding to t15), t34 (corresponding to t17), and t35 (corresponding to t19).

[0038] At time t12 shown in Fig. 4(a), the input control signal st is at H level, so the output signal Y0 of the AND circuit 26 shown in Fig. 2 is at H level, and the output signal Y1 of the AND circuit 27 shown in Fig. 2 is at L level. Therefore, the reset signal s1 shown in Fig. 4(c) is at L level at time t12, and the band switching signal s2 shown in Fig. 4(b) is at H level at time t21 (corresponding to t12). Similarly, the band switching signal s2 is at H level at times t23 (corresponding to t16) and t25 (corresponding to t18). Furthermore, the band switching signal s2 is at L level at times t22 and t24.

[0039] The output signal Y0 of the AND circuit 26 is output as a band switching signal s2 to the second input port P2 of the TIA 12. The output signal Y1 of the AND circuit 27 is output as a reset signal s1 to the first input port P1 of the TIA 12. That is, the input control signal st generated by the band switching signal s2 and the reset signal s1 is separated into the band switching signal s2 and the reset signal s1 by the control unit 11, and these are output to the second input port P2 and the first input port P1 of the TIA 12, respectively.

[0040] As described above, the TIA circuit 100 according to the first embodiment includes a control unit 11 that separates the input control signal st generated by the first control signal (e.g., a reset signal s1) and the second control signal (e.g., a band switching signal s2) into the first control signal and the second control signal, and a TIA 12 (transimpedance amplifier) ​​that has a first input unit P1 that inputs the first control signal (reset signal s1) and a second input unit P2 that inputs the second control signal (band switching signal s2), and that converts the current signal into a voltage signal using the first control signal and the second control signal.

[0041] In the TIA circuit 100 according to the first embodiment, when an input control signal st generated from a band switching signal s2 and a reset signal s1 is input from the tri-state buffer 32, the input control signal st is separated into the band switching signal s2 and the reset signal s1 and output to the TIA 12. Therefore, with a configuration including one input terminal Q1, two control signals can be acquired, and band change and reset processing can be performed in the TIA 12.

[0042] That is, the band switching signal s2 used for the band switching function and the reset signal s1 used for the reset function can be integrated into a single input terminal Q1. As a result, the number of terminals for supplying control signals to the TIA can be reduced, enabling the miniaturization and cost reduction of the TIA circuit 100, which in turn contributes to the miniaturization and cost reduction of optical transceivers. Furthermore, burst-capable transimpedance amplifiers used in PON (Passive Optical Network) systems and the like can be made to support multiple speeds and achieve high-speed response.

[0043] In the first embodiment described above, if it is required to shorten the settling time (waiting time) when generating the input control signal st, an analog switch circuit may be used instead of the tri-state buffer 32 shown in FIG. 2, and a low-impedance intermediate potential may be actively applied to the input terminal of the input control signal st.

[0044] Furthermore, the three voltages of the input control signal st, "H level," "intermediate level," and "L level," are not limited to the above combinations, but may be set to various combinations. In this case, it is sufficient to change the circuitry of the encoding circuit 13.

[0045] In the first embodiment described above, an example was described in which the input control signal st transmitted from the MAC circuit 31 to the TIA circuit 100 is generated from a reset signal s1 (first control signal) and a band switching signal s2 (second control signal), but it is also possible to assign the first and second control signals to other control signals.

[0046] In the first embodiment described above, an example of a TIA mounted in a TO-CAN package commonly used in optical component assembly (TOSA, ROSA) products is shown, but it can also be applied to other packages.

[0047] [Description of the Second Embodiment] Next, a second embodiment will be described. Fig. 5 is a block diagram showing the configuration of a TIA circuit 101 according to the second embodiment and a circuit installed in the preceding stage thereof. The TIA circuit 101 according to the second embodiment differs from the TIA circuit 100 shown in the first embodiment in the configuration of the control unit. The configuration of the control unit 11A shown in Fig. 5 will be described below.

[0048] The control unit 11A includes a window comparator 14 and a Schmitt trigger circuit 15 .

[0049] The window comparator 14 includes a third comparison unit 41, a fourth comparison unit 42, a third power supply 43, a fourth power supply 44, and an AND circuit 45. The comparators used in the window comparator 14 can be configured with a total of 12 CMOS transistors, P21 to P24 and N21 to N28, as shown in FIG.

[0050] 5 outputs a third threshold voltage Vth3. The fourth power supply 44 outputs a fourth threshold voltage Vth4 (Vth4>Vth3). The third threshold voltage Vth3 is preferably set to a voltage slightly lower than the intermediate level "(L+H) / 2." The fourth threshold voltage Vth4 is preferably set to a voltage slightly lower than the H level.

[0051] The third comparison unit 41 receives the input control signal st at its non-inverting input terminal and the third threshold voltage Vth3 at its inverting input terminal. The fourth comparison unit 42 receives the input control signal st at its inverting input terminal and the fourth threshold voltage Vth4 at its non-inverting input terminal. That is, when the input control signal st satisfies "Vth3≦st<Vth4," the output signals of the third comparison unit 41 and the fourth comparison unit 42 both become H level, and the output signal of the AND circuit 45 (corresponding to the reset signal s1) becomes H level. Therefore, the reset signal s1 becomes H level when the input control signal st is at an intermediate level, and becomes L level when the input control signal st is at L level or H level.

[0052] That is, the window comparator 14 determines whether the input control signal st is in a range that is equal to or greater than a predetermined third threshold voltage Vth3 and less than a fourth threshold voltage Vth4 that is higher than the third threshold voltage Vth3, and outputs a first control signal to the first input section P1 if the input control signal st is within this range.

[0053] The Schmitt trigger circuit 15 outputs a band switching signal s2 so as to maintain the band setting of the packet before the reset signal s1 was input during the reset period. A lower limit voltage (hereinafter referred to as "v3") and an upper limit voltage (hereinafter referred to as "v4") are set in the Schmitt trigger circuit 15. The Schmitt trigger circuit 15 outputs an H level when the input voltage is equal to or greater than the upper limit voltage v4, and outputs an L level when the input voltage is less than the lower limit voltage v3.

[0054] That is, the Schmitt trigger circuit 15 is set with a lower limit voltage v3 and an upper limit voltage v4, and when the input control signal st reaches the upper limit voltage v4, it outputs a second control signal to the second input section P2 and maintains the output of the second control signal until the input control signal st falls below the lower limit voltage v3.

[0055] The Schmitt trigger circuit 15 can be configured, for example, as shown in Figures 7A and 7B. Figure 7A shows an example in which the Schmitt trigger circuit 15 is configured with a total of six CMOS transistors P11, P12, P13, N11, N12, and N13. Figure 7B shows an example in which the Schmitt trigger circuit is configured with a comparator 61 and resistors R1 and R2.

[0056] The lower limit voltage v3 is preferably set to the third threshold voltage Vth3, and the upper limit voltage v4 is preferably set to the fourth threshold voltage Vth4, thereby widening the voltage range recognized as an intermediate level.

[0057] 8A is an explanatory diagram showing the voltage ranges recognized as the L level, intermediate level, and H level when v3=Vth3 and v4=Vth4. In this case, the voltage range d3 recognized as the L level, the voltage range d2 recognized as the intermediate level, and the voltage range d1 recognized as the H level can be clearly separated.

[0058] 8B is an explanatory diagram showing the voltage ranges recognized as the L level, intermediate level, and H level when v3 > Vth3 and v4 > Vth4. In this case, there is a voltage range d14 that is not determined between the voltage range d15 that is recognized as the L level and the voltage range d13 that is recognized as the intermediate level, and there is a voltage range d12 that is not determined between the voltage range d13 that is recognized as the intermediate level and the voltage range d11 that is recognized as the H level.

[0059] That is, by setting v3=Vth3 and v4=Vth4 as shown in FIG. 8A, the existence of the voltage ranges d12 and d14 can be avoided.

[0060] 9 is a characteristic diagram showing the relationship between the voltage level input to the Schmitt trigger circuit 15 and the output signal. When the input voltage is less than the upper limit voltage v4 as shown in FIG. 9(a), the output signal is at the L level as shown in FIG. 9(b). When the input voltage reaches the upper limit voltage v4, the output signal switches to the H level. Thereafter, when the input voltage drops to the lower limit voltage v3, the output signal switches to the L level. That is, the output signal of the Schmitt trigger circuit 15 changes from the H level to the L level with a hysteresis h1.

[0061] Therefore, even if the input control signal st is switched from the H level to the intermediate level, the output of the Schmitt trigger circuit 15 remains at the H level, and the band switching signal s2 continues to be output. In other words, even if the reset signal s1 is input, it does not affect the band switching signal s2. Furthermore, even if noise N1 shown in FIG. 9A is superimposed on the input voltage, this effect can be avoided.

[0062] That is, as shown in the correspondence table of Fig. 10, when the input control signal st is at H level, the TIA 12 enters the high-band mode reception state. When it is at an intermediate level, the TIA 12 enters the band mode before the reset operation and enters the reset state. When it is at L level, the TIA 12 enters the low-band mode reception state.

[0063] 11 is a timing chart showing changes in the input control signal st, band switching signal s2, and reset signal s1 according to the second embodiment. As described above, the Schmitt trigger circuit 15 outputs the band switching signal s2 so as to maintain the band setting of the packet before the reset signal s1 is input during the reset period. That is, when the input control signal st switches to H level at time T1 shown in FIG. 11(a), the output signal (band switching signal s2) of the Schmitt trigger circuit 15 becomes H level as shown in FIG. 11(b). Even when the input control signal st switches from H level to an intermediate level at time T2, the band switching signal s2 remains H level.

[0064] When the input control signal st switches to L level at time T3, the band switching signal s2 switches to L level. Therefore, during time t51 from time T1 to T3 shown in Figure 11(b), the band switching signal s2 maintains H level. Furthermore, when the input control signal st switches from H level to an intermediate level at time T5 and then switches back to H level at time T6, the band switching signal s2 maintains H level. That is, during time t53 from time T4 to T8, the band switching signal s2 maintains H level.

[0065] That is, even during the time period when the reset signal s1 is applied to the TIA 12, it becomes possible to output the H-level band switching signal s2 to the TIA 12. Specifically, at times t43, t47, and t49 shown in Fig. 11(a), it becomes possible to hold the band switching signal s2 at the H-level as shown in Fig. 11(b).

[0066] 11(c), the reset signal s1 goes high when the input control signal st is at an intermediate level. Specifically, the reset signal s1 goes high at times t61, t62, t63, t64, and t65, which correspond to times t41, t43, t45, t47, and t49 shown in FIG. 11(a).

[0067] Therefore, when a packet signal requiring a high bandwidth is adjacent, unnecessary band switching to a low bandwidth can be prevented during the reset operation period within the guard time, making it possible to maintain the high bandwidth. That is, in the TIA circuit 100 according to the first embodiment described above, the input control signal st is separated into three states (L level, intermediate level, and H level), so that the TIA 12 is fixed to the low bandwidth during the time period when the reset signal s1 is input, but in the TIA circuit 101 according to the second embodiment, it is possible to maintain the high bandwidth during the time period when the reset signal s1 is input.

[0068] In this way, the TIA circuit 101 according to the second embodiment can avoid unnecessary band switching operations and can input the band switching signal s2 and the reset signal s1 together into one input terminal Q1. This makes it possible to reduce the size and cost of the semiconductor package, and also has the effect of improving the reception response of packet signals by avoiding unnecessary band switching operations between packets.

[0069] [Description of the Third Embodiment] Next, a description will be given of a third embodiment of the present invention, with reference to Fig. 12, which is a circuit diagram showing the configuration of a TIA circuit 102 according to the third embodiment and a MAC circuit 31 provided in the preceding stage thereof.

[0070] As shown in Figure 12, the TIA circuit 102 of the third embodiment differs from the TIA circuit 101 (see Figure 5) shown in the second embodiment in that it has a first input terminal Q11 and a second input terminal Q12, and the control unit 11B has an OR circuit 51 and a pull-down resistor 52.

[0071] The first input terminal Q11 is connected to ground via a pull-down resistor 52.

[0072] The second input terminal Q12 is connected to an input p2 of the window comparator 14 and an input p3 of the Schmitt trigger circuit 15.

[0073] The input q1 of the OR circuit 51 is connected to the output p1 of the window comparator 14, and the input q2 is connected to the first input terminal Q11. The output q3 of the OR circuit 51 is connected to the first input P1 of the TIA 12.

[0074] That is, the control unit 11B has a first input terminal Q11 and a second input terminal Q12, the first input terminal Q11 is grounded to ground via a pull-down resistor 52 and is connected to one input terminal q2 of an OR circuit 51, the other input terminal q1 of the OR circuit is connected to the output terminal p1 of the window comparator 14, and the output terminal q3 of the OR circuit is connected to the first input terminal P1.

[0075] Other configurations are the same as those of the TIA circuit 101 shown in FIG. 5, so the same components are denoted by the same reference numerals and detailed description of the configuration will be omitted.

[0076] As shown in the second embodiment (see FIG. 5 ), when the output (three-level output) of the tri-state buffer 32 is provided, the TIA circuit 102 according to the third embodiment connects this output to the second input terminal Q12 and opens the first input terminal Q11. Since the input q2 of the OR circuit 51 is fixed to the L level by the pull-down resistor 52, the output of the AND circuit 45 becomes the output of the OR circuit 51 as is. Therefore, it operates in the same manner as the TIA circuit 101 shown in the second embodiment.

[0077] Furthermore, in the third embodiment, when a circuit that outputs the band switching signal s2 and the reset signal s1 separately is installed in the upstream stage as in the conventional case, the output part of the band switching signal s2 is connected to the input terminal Q12, and the output part of the reset signal s1 is connected to the input terminal Q11, as shown in FIG. 12.

[0078] In this case, when the band switching signal s2 is at H level, the output of the Schmitt trigger circuit 15 becomes H level and is output to the second input P2 of the TIA 12. When the reset signal s1 is at H level, an H level is input to the input q2 of the OR circuit 51, so that the output (reset signal s1) of the OR circuit 51 becomes H level and is output to the first input P1 of the TIA 12.

[0079] In this way, in the third embodiment, when an input control signal st indicating three states is supplied, only the second input terminal Q12 is used and the first input terminal Q11 is opened, so that, as shown in the second embodiment, the input control signal st can be separated into a reset signal s1 and a band switching signal s2 and output to the first input part P1 and the second input part P2 of the TIA 12, respectively. In other words, because the first input terminal Q11 is not used, the number of terminals can be reduced.

[0080] Furthermore, if it is desired to input the band switching signal s2 and reset signal s1 output from the MAC circuit 31 provided in the preceding stage of the TIA circuit 102 individually to the TIA, by using the first input terminal Q11, it becomes possible to output each signal s1 and s2 to the first input section P1 and the second input section P2 of the TIA 12, respectively, thereby increasing versatility.

[0081] Therefore, IC manufacturers can deal with both cases where the input control signal st is used and cases where the input control signal st is not used by manufacturing a common TIA circuit 102. This increases versatility and reduces manufacturing costs.

[0082] The TIA circuits 100, 101, and 102 of each of the above-described embodiments can be implemented as a general-purpose computer system including, for example, a CPU (Central Processing Unit, or processor) 901, a memory 902, a storage 903 (HDD: Hard Disk Drive, SSD: Solid State Drive), a communication device 904, an input device 905, and an output device 906, as shown in FIG. 13 . The memory 902 and the storage 903 are storage devices. In this computer system, the CPU 901 executes a predetermined program loaded onto the memory 902, thereby realizing the functions of the TIA circuits 100, 101, and 102.

[0083] The TIA circuits 100, 101, and 102 may be implemented in one computer or in multiple computers, and may also be virtual machines implemented in a computer.

[0084] The programs for the TIA circuits 100, 101, and 102 can be stored in a computer-readable recording medium such as a HDD, SSD, USB (Universal Serial Bus) memory, CD (Compact Disc), or DVD (Digital Versatile Disc), or can be distributed via a network. The computer-readable recording medium is, for example, a nontransitory recording medium.

[0085] The present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the present disclosure.

[0086] 11, 11A, 11B Control unit 12 Transimpedance amplifier (TIA) 13 Encode circuit 14 Window comparator 15 Schmitt trigger circuit 21 First comparison unit 22 Second comparison unit 23 First power supply 24 Second power supply 25 NOT circuit 26, 27 AND circuit 31 Media access controller circuit (MAC circuit) 32 Tri-state buffer 33 Bias circuit 41 Third comparison unit 42 Fourth comparison unit 43 Third power supply 44 Fourth power supply 45 AND circuit 51 OR circuit 52 Pull-down resistor 100, 101, 102 Transimpedance amplifier circuit (TIA circuit) P1 First input unit P2 Second input unit Q1 Input terminal Q11 First input terminal Q12 Second input terminal s1 Reset signal (first control signal) s2 Band switching signal (second control signal) st Input control signal v3 Lower limit voltage v4 Upper limit voltage

Claims

1. A transimpedance amplifier circuit comprising: a control unit that separates an input control signal generated by a first control signal and a second control signal into the first control signal and the second control signal; and a transimpedance amplifier having a first input unit that inputs the first control signal and a second input unit that inputs the second control signal, and that converts a current signal into a voltage signal using the first control signal and the second control signal.

2. The transimpedance amplifier circuit of claim 1, wherein the control unit comprises: a first comparison unit which compares the input control signal with a predetermined first threshold voltage; a second comparison unit which compares the input control signal with a second threshold voltage higher than the first threshold voltage; and an encoding circuit which outputs the first control signal to the first input unit when the input control signal is equal to or greater than the first threshold voltage and less than the second threshold voltage, and which outputs the second control signal to the second input unit when the input control signal is equal to or greater than the second threshold voltage.

3. The transimpedance amplifier circuit according to claim 1, wherein the control unit comprises: a window comparator that determines whether the input control signal is within a range that is equal to or higher than a predetermined third threshold voltage and is less than a fourth threshold voltage that is higher than the third threshold voltage, and outputs a first control signal to the first input unit when the input control signal is within the range; and a Schmitt trigger circuit in which a lower limit voltage and an upper limit voltage are set, and which outputs a second control signal to the second input unit when the input control signal reaches the upper limit voltage, and which maintains the output of the second control signal until the input control signal falls below the lower limit voltage.

4. The transimpedance amplifier circuit of claim 3, wherein the control unit has a first input terminal and a second input terminal, the first input terminal is grounded via a pull-down resistor and is connected to one input of an OR circuit, the other input of the OR circuit is connected to an output of the window comparator, the output of the OR circuit is connected to the first input, and the second input terminal is connected to an input of the window comparator and an input of the Schmitt trigger circuit.

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