Semiconductor device

Abstract

This semiconductor device comprises: a chip having a main surface; a first conductivity type semiconductor region formed on the surface layer portion of the main surface; an active region that is provided in an inner portion of the main surface; an outer peripheral region that is provided in a peripheral edge portion of the main surface; a trench type separation structure that is formed in the main surface so as to be positioned in the semiconductor region and that delimits the active region and the outer peripheral region; and a second conductivity type well region that is formed in a region below the separation structure so as to be positioned in the semiconductor region and is electrically connected to the semiconductor region.

Description

Semiconductor Devices

[0001] This application claims priority to Patent Application No. 2023-203160 filed with the Japan Patent Office on November 30, 2023, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to a semiconductor device.

[0002] Patent Document 1 (US2008 / 0277669A1) discloses a semiconductor device having a termination structure in the peripheral region of a drift layer.

[0003] US Patent Application Publication No. 2008 / 0277669

[0004] SUMMARY The present disclosure provides a semiconductor device having a novel layout.

[0005] The present disclosure provides a semiconductor device including: a chip having a main surface; a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface; an active region provided in an inner portion of the main surface; a peripheral region provided in a peripheral portion of the main surface; a trench-type isolation structure formed in the main surface so as to be located within the semiconductor region and separating the active region and the peripheral region; and a well region of a second conductivity type formed in a region below the isolation structure so as to be located within the semiconductor region and electrically connected to the semiconductor region.

[0006] The present disclosure provides a semiconductor device including: a chip having a main surface; a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface; an active region provided in an inner portion of the main surface; a peripheral region provided in a peripheral portion of the main surface; a trench-type isolation structure formed on the main surface so as to be positioned within the semiconductor region and separating the active region and the peripheral region; and a termination region of a second conductivity type arranged on the peripheral side of the chip relative to the isolation structure so as to be positioned within the semiconductor region in the peripheral region.

[0007] The present disclosure provides a semiconductor device including a chip having a main surface, a trench-type first isolation structure formed in the main surface, a trench-type second isolation structure formed in the main surface adjacent to the first isolation structure, a first well region formed in a region below the first isolation structure, and a second well region formed in a region below the second isolation structure and having a depth greater than a depth of the first well region.

[0008] The present disclosure provides a semiconductor device including: a chip having a main surface; a trench-type gate structure formed in the main surface; a trench-type isolation structure formed in the main surface and spaced apart from the gate structure; and a well region formed in a region below the isolation structure so as to be positioned below a bottom wall of the gate structure.

[0009] The present disclosure provides a semiconductor device including a chip having a main surface, a trench-type source structure formed in the main surface, a trench-type isolation structure formed in the main surface and spaced apart from the source structure, and a well region formed in a region below the isolation structure so as to be positioned below a bottom wall of the source structure.

[0010] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0011] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a plan view showing an example layout of a first main surface. FIG. 4 is an enlarged plan view showing a main portion of the first main surface shown in FIG. 3. FIG. 5 is an enlarged plan view showing a main portion of the first main surface shown in FIG. 3. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is an enlarged cross-sectional view of a region shown in FIG. 6. FIG. 9 is a cross-sectional view showing a structure taken along line IX-IX in FIG. 5, together with a deep well region according to the first embodiment. FIG. 10 is a cross-sectional view showing a cross-sectional structure of a peripheral region taken along line XX in FIG. 1. FIG. 11A is a cross-sectional view showing a deep well region according to a second embodiment. FIG. 11B is a cross-sectional view showing a deep well region according to a third embodiment. FIG. 11C is a cross-sectional view showing a deep well region according to a fourth embodiment. FIG. 11D is a cross-sectional view showing a deep well region according to a fifth embodiment. 11E is a cross-sectional view showing a deep well region according to the sixth embodiment. FIG. 11F is a cross-sectional view showing a deep well region according to the seventh embodiment. FIG. 11G is a cross-sectional view showing a deep well region according to the eighth embodiment. FIG. 12 is a cross-sectional view showing an active region of a semiconductor device according to the second embodiment. FIG. 13 is a cross-sectional view showing a deep well region of the semiconductor device shown in FIG. 12. FIG. 14 is a cross-sectional view showing a peripheral region of the semiconductor device shown in FIG. 12. FIG. 15 is an enlarged plan view showing an active region of a semiconductor device according to the third embodiment. FIG. 16 is a cross-sectional view taken along line XVI-XVI shown in FIG. 15. FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. 15. FIG. 18 is a cross-sectional view showing the peripheral region of the semiconductor device shown in FIG. 15. FIG. 19 is a plan view showing a semiconductor device according to the fourth embodiment. FIG. 20 is a cross-sectional view showing the peripheral portion of the active region of the semiconductor device shown in FIG. 19 together with the termination region according to the first embodiment. FIG. 21A is a cross-sectional view showing the termination region according to the second embodiment. Fig. 21B is a cross-sectional view showing a termination region according to a third embodiment. Fig. 21C is a cross-sectional view showing a termination region according to a fourth embodiment. Fig. 21D is a cross-sectional view showing a termination region according to a fifth embodiment. Fig. 21E is a cross-sectional view showing a termination region according to a sixth embodiment. Fig. 21F is a cross-sectional view showing a termination region according to a seventh embodiment.Fig. 22 is a cross-sectional view showing an active region of a semiconductor device according to a fifth embodiment. Fig. 23 is a cross-sectional view showing a peripheral portion of the active region of the semiconductor device shown in Fig. 22 together with a termination region according to a first embodiment. Fig. 24 is a cross-sectional view showing an active region of a semiconductor device according to a sixth embodiment. Fig. 25 is a cross-sectional view showing a peripheral portion of the active region of the semiconductor device shown in Fig. 24 together with a termination region according to the first embodiment. Fig. 26 is a cross-sectional view showing a semiconductor device according to a modification.

[0012] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0013] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0014] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0015] FIG. 1 is a plan view showing a semiconductor device 1A according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a plan view showing an example layout of a first main surface 3. FIG. 4 is an enlarged plan view showing a main portion of the first main surface 3 shown in FIG. 3. FIG. 5 is an enlarged plan view showing a main portion of the first main surface 3 shown in FIG. 3. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is an enlarged cross-sectional view of a region shown in FIG. 6. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 5.

[0016] 1 to 9, a semiconductor device 1A is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a trench gate vertical structure.

[0017] Semiconductor device 1A includes chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, chip 2 includes a single crystal of a wide bandgap semiconductor. In other words, semiconductor device 1A is a "wide bandgap semiconductor device." Chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0018] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1A is a "SiC semiconductor device."

[0019] Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes.

[0020] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2.

[0021] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0022] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0023] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. The first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. Hereinafter, the direction extending along the first main surface 3 may be referred to as the "horizontal direction." The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0024] The chip 2 (first main surface 3 and second main surface 4) has an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined by the off-angle from a vertical line along the vertical direction Z toward the off-direction. Furthermore, the c-plane of the SiC single crystal is inclined by the off-angle with respect to the horizontal plane.

[0025] The off-direction is preferably the a-axis direction of the SiC single crystal (second direction Y in this embodiment). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0026] The off angle is preferably 5° or less. The off angle is particularly preferably 2° or more and 4.5° or less. The off angle is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0027] The semiconductor device 1A includes an n-type first semiconductor region 6 formed in a surface layer portion of the second main surface 4. A drain potential as a first potential (high potential) is applied to the first semiconductor region 6. The first semiconductor region 6 may also be referred to as a "base region (layer)," a "semiconductor region (layer)," a "drain region (layer)," or the like.

[0028] The first semiconductor region 6 extends in a layered form along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 is made of an n-type semiconductor layer. Specifically, the first semiconductor region 6 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal), and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D. The first semiconductor region 6 (substrate) has the off direction and off angle described above.

[0029] The first semiconductor region 6 may have a thickness of 10 μm or more and 500 μm or less. The thickness of the first semiconductor region 6 may have a value belonging to at least one of the ranges of 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0030] The semiconductor device 1A includes an n-type second semiconductor region 7 formed in a surface layer portion of the first main surface 3. The second semiconductor region 7 may also be referred to as a "semiconductor region (layer)," a "drift region (layer)," or the like. The second semiconductor region 7 has an n-type impurity concentration lower than the n-type impurity concentration of the first semiconductor region 6. The second semiconductor region 7 is formed in a region closer to the first main surface 3 than the first semiconductor region 6 in a cross-sectional view, and is electrically connected to the first semiconductor region 6.

[0031] The second semiconductor region 7 extends in a layered form along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the second semiconductor region 7 is made of an n-type semiconductor layer. Specifically, the second semiconductor region 7 is made of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal), and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0032] The second semiconductor region 7 (epitaxial layer) has the aforementioned off direction and off angle. The second semiconductor region 7 preferably has a thickness less than that of the first semiconductor region 6. The thickness of the second semiconductor region 7 may be greater than that of the first semiconductor region 6.

[0033] The thickness of the second semiconductor region 7 may be 5 μm or more and 15 μm or less. The thickness of the second semiconductor region 7 may have a value belonging to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0034] The semiconductor device 1A includes an active region 8 set in a chip 2. The active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. The active region 8 is set in an inner portion of the chip 2 at a distance from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D).

[0035] The active region 8 is set to a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The ratio (area ratio) of the planar area of ​​the active region 8 to the planar area of ​​the first main surface 3 may be 0.5 or more and 0.95 or less. The area ratio may be 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and 0.95 or less.

[0036] The semiconductor device 1A includes a peripheral region 9 set outside the active region 8 in the chip 2. The peripheral region 9 is a region that does not include a device structure (transistor structure Tr). The peripheral region 9 is set on the periphery of the chip 2. That is, the peripheral region 9 is provided in the region between the periphery of the chip 2 and the active region 8 in plan view. The peripheral region 9 extends in a strip shape along the active region 8 in plan view and is set in the shape of a polygonal ring (a square ring in this embodiment) that surrounds the active region 8.

[0037] The semiconductor device 1A includes a transistor structure Tr formed in an active region 8. The configuration within the active region 8 as the configuration of the transistor structure Tr will be described below.

[0038] The semiconductor device 1A includes a p-type body region 10 formed in the active region 8 (inner portion of the first main surface 3) in a surface layer portion of the first main surface 3. The body region 10 may also be referred to as an "impurity region," a "channel region," or the like. A source potential may be applied to the body region 10. The source potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be a ground potential. The body region 10 has a p-type impurity concentration that is higher than the n-type impurity concentration of the second semiconductor region 7.

[0039] The body region 10 is formed in the inner portion of the first main surface 3 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and is not formed in the outer peripheral region 9. In this embodiment, the body region 10 is formed throughout the active region 8. The body region 10 is formed in the surface layer portion of the second semiconductor region 7, and extends in a layered form along the first main surface 3.

[0040] The body region 10 is formed at a distance from the bottom of the second semiconductor region 7 (first semiconductor region 6) toward the first main surface 3, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. The body region 10 is formed at a distance from a depth position of the middle part of the second semiconductor region 7 toward the first main surface 3.

[0041] The body region 10 is formed in a region on the first main surface 3 side of the second semiconductor region 7 in a cross-sectional view, and is electrically connected to the second semiconductor region 7. The body region 10 forms a pn junction (body diode) with the second semiconductor region 7. The body region 10 spreads a depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer originating in the body region 10 spreads in the horizontal direction and thickness direction within the second semiconductor region 7.

[0042] The semiconductor device 1A includes an n-type source region 11 formed in the active region 8 in a surface layer portion of the first main surface 3. A source potential is applied to the source region 11. The source region 11 has an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The n-type impurity concentration of the source region 11 is higher than the p-type impurity concentration of the body region 10.

[0043] The source region 11 is formed in an inner portion of the first main surface 3 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and is not formed in the outer peripheral region 9. The source region 11 may be formed inwardly at a distance from the periphery of the body region 10. The source region 11 is formed in a surface layer portion of the body region 10, and extends in a layered form along the first main surface 3.

[0044] The source region 11 is formed at a distance from the bottom of the body region 10 toward the first main surface 3, and faces the second semiconductor region 7 across a part of the body region 10. The source region 11 is formed in a region on the first main surface 3 side of the body region 10 in a cross-sectional view, and is electrically connected to the body region 10.

[0045] The semiconductor device 1A includes a plurality of trench-type (trench electrode-type) gate structures 15 formed in an inner portion of the first main surface 3. The gate structures 15 may also be referred to as "trench structures," "trench gate structures," or the like. A gate potential (gate signal) serving as a control potential is applied to the plurality of gate structures 15. The plurality of gate structures 15 controls inversion and non-inversion of the channel in the body region 10 in response to the gate potential.

[0046] The plurality of gate structures 15 are formed in an inner portion of the first main surface 3 at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and are not formed in the outer peripheral region 9. The plurality of gate structures 15 are arranged at intervals in a first direction X (= m-axis direction) in a plan view, and each extends in a band shape in a second direction Y (= a-axis direction). The plurality of gate structures 15 are arranged in a stripe shape extending in the second direction Y in a plan view.

[0047] The extension direction of the multiple gate structures 15 coincides with the off-direction of the SiC single crystal. With respect to the second direction Y, both ends of the multiple gate structures 15 may be located in a region between the peripheral edge of the body region 10 and the peripheral edge of the source region 11. The multiple gate structures 15 may be arranged at intervals in the second direction Y in a plan view, and each extend in a strip shape in the first direction X.

[0048] The plurality of gate structures 15 penetrates the body region 10 and the source region 11 to reach the second semiconductor region 7. The plurality of gate structures 15 are formed at intervals from the depth position of the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 with a part of the second semiconductor region 7 in between.

[0049] The plurality of gate structures 15 may be formed at intervals from a depth position of an intermediate portion of the second semiconductor region 7 toward the first main surface 3, or may be located on the bottom side of the second semiconductor region 7 with respect to the depth position of the intermediate portion of the second semiconductor region 7. The plurality of gate structures 15 are formed substantially perpendicular to the first main surface 3. The plurality of gate structures 15 may be formed in a shape that tapers toward the bottom of the second semiconductor region 7.

[0050] The side walls (long sides) of the plurality of gate structures 15 are formed by the m-plane ((1-100) plane) of the SiC single crystal. The side walls (long sides) of the plurality of gate structures 15 may be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the gate structures 15. The bottom walls of the plurality of gate structures 15 are formed by the c-plane (Si-plane) of the SiC single crystal. It is preferable that the bottom walls of the plurality of gate structures 15 extend substantially flat in the horizontal direction. The bottom walls of the plurality of gate structures 15 may be curved in an arc shape toward the second main surface 4.

[0051] The inclination angle (absolute value) of the sidewall (long side) of the gate structure 15 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0052] The gate structure 15 may have a width of 0.1 μm to 2 μm, and may have a width in at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm.

[0053] The gate structure 15 may have a depth of 0.1 μm or more and 3 μm or less. The depth of the gate structure 15 is measured from the first main surface 3. The depth of the gate structure 15 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the gate structure 15 is preferably 0.5 μm or more and 1.5 μm or less.

[0054] The gate structure 15 may have an aspect ratio of 1 to 3. The aspect ratio of the gate structure 15 is the ratio of the depth of the gate structure 15 to the width of the gate structure 15. The aspect ratio may have a value belonging to at least one of the ranges of 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. The aspect ratio is preferably 1.5 to 2.5.

[0055] Each of the plurality of gate structures 15 includes a first trench 16, a first insulating film 17, and a first buried electrode 18. The first trench 16 is formed in the first main surface 3 and defines the wall surfaces (sidewalls and bottom wall) of the gate structure 15.

[0056] The first insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first insulating film 17 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first insulating film 17 includes a silicon oxide film made of an oxide of the chip 2.

[0057] The first insulating film 17 covers the wall surface of the first trench 16. The first insulating film 17 includes a first film portion and a second film portion. The first film portion covers the sidewall of the first trench 16 in a film-like manner. The second film portion covers the bottom wall of the first trench 16 in a film-like manner and is continuous with the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion.

[0058] The first insulating film 17 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0059] The first buried electrode 18 is buried in the first trench 16 with the first insulating film 17 sandwiched therebetween. The first buried electrode 18 may include either p-type conductive polysilicon or n-type conductive polysilicon, or both. The first buried electrode 18 faces the second semiconductor region 7, the body region 10, and the source region 11 with the first insulating film 17 sandwiched therebetween.

[0060] The first buried electrode 18 has an electrode surface exposed from the first trench 16. The electrode surface is located closer to the bottom wall of the first trench 16 with respect to the height position of the first main surface 3. The electrode surface is located closer to the first main surface 3 with respect to the depth position of the bottom of the source region 11. The electrode surface has a recess in an inner portion that tapers toward the bottom wall of the first trench 16.

[0061] The semiconductor device 1A includes a plurality of trench-type (trench electrode-type) source structures 20 formed in an inner portion of the first main surface 3. The source structures 20 may be referred to as "first source structures," "source structures," "second trench structures," etc. A source potential is applied to the plurality of source structures 20.

[0062] The plurality of source structures 20 are formed in the inner portion of the first main surface 3 at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and are not formed in the outer peripheral region 9. The plurality of source structures 20 are arranged at intervals in the first direction X (= m-axis direction) in plan view, and each extends in a strip shape in the second direction Y (= a-axis direction).

[0063] The source structures 20 are respectively arranged in regions between the gate structures 15 at intervals in the first direction X from the gate structures 15, and face the gate structures 15 in the first direction X. That is, the source structures 20 are arranged alternately with the gate structures 15 in the first direction X, and extend in a strip-like manner in the second direction Y. The source structures 20 are arranged in a strip-like manner extending in the second direction Y.

[0064] The extension direction of the source structures 20 coincides with the off-direction of the SiC single crystal. With respect to the second direction Y, both ends of the source structures 20 may be located in a region between the periphery of the body region 10 and the periphery of the source region 11. The source structures 20 may be arranged at intervals in the second direction Y according to the extension direction of the gate structures 15, and may each extend in a strip shape in the first direction X.

[0065] The plurality of source structures 20 penetrate the body region 10 and the source region 11 to reach the second semiconductor region 7. The plurality of source structures 20 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 with a part of the second semiconductor region 7 in between.

[0066] The source structures 20 may be formed at intervals from a depth position of an intermediate portion of the second semiconductor region 7 toward the first main surface 3, or may be located on the bottom side of the second semiconductor region 7 with respect to the depth position of the intermediate portion of the second semiconductor region 7. The source structures 20 are formed substantially perpendicular to the first main surface 3. The source structures 20 may be formed in a shape tapering toward the bottom of the second semiconductor region 7.

[0067] The side walls of the plurality of source structures 20 are each formed by the m-plane ((1-100) plane) of the SiC single crystal. The side walls of the plurality of source structures 20 may be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the source structures 20. The bottom walls of the plurality of source structures 20 are formed by the c-plane (Si-plane) of the SiC single crystal. It is preferable that the bottom walls of the plurality of source structures 20 extend substantially flat in the horizontal direction. The bottom walls of the plurality of source structures 20 may be curved in an arc shape toward the second main surface 4.

[0068] The inclination angle (absolute value) of the sidewall of the source structure 20 relative to the vertical line may be 85° to 95°. The inclination angle may have a value belonging to at least one of the ranges of 85° to 87.5°, 87.5° to 90°, 90° to 92.5°, and 92.5° to 95°. The inclination angle is preferably 87° to 93°.

[0069] The source structure 20 has a width that is approximately equal to the width of the gate structure 15. The width of the source structure 20 may be greater than the width of the gate structure 15 or may be less than the width of the gate structure 15.

[0070] The width of source structure 20 may be 0.1 μm to 2 μm, or may have a value belonging to at least one of the following ranges: 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm.

[0071] The source structure 20 has a depth approximately equal to the depth of the gate structure 15. The depth of the source structure 20 is measured from the first main surface 3. The depth of the source structure 20 may be greater than the depth of the gate structure 15 or may be less than the depth of the gate structure 15.

[0072] The ratio (depth ratio) of the depth of source structure 20 to the depth of gate structure 15 may be 0.8 to 1.2. The depth ratio may have a value belonging to at least one of the ranges of 0.8 to 0.85, 0.85 to 0.9, 0.9 to 0.95, 0.95 to 1, 1 to 1.05, 1.05 to 1.1, 1.1 to 1.15, and 1.15 to 1.2. The depth ratio is preferably 0.95 to 1.05.

[0073] The depth of the source structure 20 may be 0.1 μm or more and 3 μm or less. The depth of the source structure 20 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the source structure 20 is preferably 0.5 μm or more and 1.5 μm or less.

[0074] The source structure 20 may have an aspect ratio of 1 to 3, inclusive. The aspect ratio of the source structure 20 is the ratio of the depth of the source structure 20 to the width of the source structure 20. The aspect ratio may have a value belonging to at least one of the following ranges: 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3, inclusive. Preferably, the aspect ratio is 1.5 to 2.5, inclusive.

[0075] The pitch between the central portions of the source structures 20 and the gate structures 15 may be 0.1 μm to 2.5 μm, and may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.25 μm, and 2.25 μm to 2.5 μm.

[0076] Each of the plurality of source structures 20 includes a second trench 21, a second insulating film 22, and a second buried electrode 23. The second trench 21 is formed in the first main surface 3 and defines the wall surfaces (sidewalls and bottom wall) of the source structure 20.

[0077] The second insulating film 22 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second insulating film 22 preferably includes the same insulating material as the insulating material of the first insulating film 17. In this embodiment, the second insulating film 22 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second insulating film 22 includes a silicon oxide film made of an oxide of the chip 2.

[0078] The second insulating film 22 covers the wall surface of the second trench 21. The second insulating film 22 includes a first film portion and a second film portion. The first film portion covers the side wall of the second trench 21 in a film-like manner. The second film portion covers the bottom wall of the second trench 21 in a film-like manner and is continuous with the first film portion.

[0079] The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion. The thickness of the first film portion of the second insulating film 22 may be approximately equal to the thickness of the first film portion of the first insulating film 17. The thickness of the second film portion of the second insulating film 22 may be approximately equal to the thickness of the second film portion of the first insulating film 17.

[0080] The second insulating film 22 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0081] The second buried electrode 23 is buried in the second trench 21 with the second insulating film 22 sandwiched therebetween. The second buried electrode 23 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. The second buried electrode 23 preferably contains the same type of conductive material as the conductive material of the first buried electrode 18. The second buried electrode 23 faces the second semiconductor region 7, the body region 10, and the source region 11 with the second insulating film 22 sandwiched therebetween.

[0082] The second buried electrode 23 has an electrode surface exposed from the second trench 21. The electrode surface is located closer to the bottom wall of the second trench 21 with respect to the height position of the first main surface 3. The electrode surface is located closer to the first main surface 3 with respect to the depth position of the bottom of the source region 11. The electrode surface has a recess in an inner portion that tapers toward the bottom wall of the second trench 21.

[0083] The semiconductor device 1A includes gate well regions 25 formed in the chip 2 (second semiconductor region 7) in the active region 8 in regions below the plurality of gate structures 15. The gate well regions 25 may also be referred to as "first well regions" or the like.

[0084] A source potential is applied to the gate well region 25. The gate well region 25 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the gate well region 25 may be higher than the p-type impurity concentration of the body region 10, or may be lower than the p-type impurity concentration of the body region 10. The p-type impurity (trivalent element) of the gate well region 25 is preferably aluminum.

[0085] The multiple gate well regions 25 are formed in the second semiconductor region 7 in regions below (specifically, directly below) the multiple gate structures 15, spaced apart from one another in the horizontal direction (first direction X). The multiple gate well regions 25 are formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the multiple gate structures 15, and overlap the multiple gate structures 15 in a one-to-one correspondence in the thickness direction.

[0086] The multiple gate well regions 25 each extend in a strip shape in the second direction Y in plan view, following the extension direction of the corresponding gate structure 15. In other words, the multiple gate well regions 25 are arranged in stripes extending in the second direction Y in plan view.

[0087] The extension direction of the multiple gate well regions 25 coincides with the off-direction of the SiC single crystal. The multiple gate well regions 25 may extend in the first direction X according to the extension direction of the multiple gate structures 15. In this case, the multiple gate well regions 25 intersect (specifically, are perpendicular to) the off-direction.

[0088] The multiple gate well regions 25 are formed at intervals inward from the periphery (the multiple isolation structures 30) of the active region 8. In the second direction Y, both ends of the multiple gate well regions 25 may be located on the inner side of the multiple gate structures 15 relative to both ends of the multiple gate structures 15, or may be located on the periphery side of the active region 8 relative to both ends of the multiple gate structures 15.

[0089] The plurality of gate well regions 25 are formed at intervals from the bottom of the second semiconductor region 7 toward the bottom wall sides of the plurality of gate structures 15, and face the first semiconductor region 6 across a part of the second semiconductor region 7. The plurality of gate well regions 25 each have an upper end located on the bottom wall side of the corresponding gate structure 15, and a bottom located on the bottom side of the second semiconductor region 7 (the side of the second main surface 4).

[0090] The upper ends of the plurality of gate well regions 25 are formed at intervals from the bottom of the body region 10 toward the bottom wall of the corresponding gate structure 15. The upper ends of the plurality of gate well regions 25 may be connected to the bottom wall of the corresponding gate structure 15. The upper ends of the plurality of gate well regions 25 may have portions that extend along the sidewall of the corresponding gate structure 15. The upper ends of the plurality of gate well regions 25 may be formed at intervals from the bottom wall of the corresponding gate structure 15 toward the bottom of the second semiconductor region 7.

[0091] The bottoms of the multiple gate well regions 25 may be located on the bottom wall side of the multiple gate structures 15 relative to the intermediate portion of the second semiconductor region 7, or may be located on the bottom side of the second semiconductor region 7 (the side toward the second main surface 4) relative to the intermediate portion of the second semiconductor region 7.

[0092] Each of the plurality of gate well regions 25 has a bulging portion 25 a. The bulging portion 25 a extends in an arc shape in the horizontal direction from a region directly below the corresponding gate structure 15 to both sides of the corresponding gate structure 15. Each of the plurality of gate well regions 25 is formed in a tapered shape from the bulging portion 25 a to the bottom.

[0093] The gate well region 25 may have a width greater than or less than the width of the gate structure 15. The width of the gate well region 25 may be 0.1 μm or more and 2 μm or less. The width of the gate well region 25 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0094] The gate well region 25 may have a depth less than the depth of the gate structure 15, or may have a depth greater than the depth of the gate structure 15. The depth of the gate well region 25 is the depth of the gate well region 25 when the bottom wall of the gate structure 15 is used as the reference.

[0095] The depth of the gate well region 25 may be greater than 0 μm and less than or equal to 5 μm. The depth of the gate well region 25 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0096] The gate well region 25 may have an aspect ratio greater than 0 and less than or equal to 2. The aspect ratio of the gate well region 25 is the ratio of the depth of the gate well region 25 to the width of the gate well region 25.

[0097] The aspect ratio may have a value belonging to at least one of the ranges of greater than 0 and less than or equal to 0.25, 0.25 or more and less than or equal to 0.5, 0.5 or more and less than or equal to 0.75, 0.75 or more and less than or equal to 1, 1 or more and less than or equal to 1.25, 1.25 or more and less than or equal to 1.5, 1.5 or more and less than or equal to 1.75, and 1.75 or more and less than or equal to 2.

[0098] The gate well region 25 forms a pn junction with the second semiconductor region 7. When a reverse bias voltage is applied, the gate well region 25 spreads a depletion layer into the second semiconductor region 7. The depletion layer originating from the gate well region 25 spreads in the horizontal and thickness directions, and reduces the electric field applied to the active region 8 (gate structure 15).

[0099] The semiconductor device 1A includes a plurality of source well regions 26 formed in regions below the plurality of source structures 20 within the chip 2 (second semiconductor region 7) of the active region 8. The source well regions 26 may also be referred to as "second well regions" or the like. A source potential is applied to the source well regions 26.

[0100] The source well region 26 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the source well region 26 may be higher than the p-type impurity concentration of the body region 10 or may be lower than the p-type impurity concentration of the body region 10.

[0101] The p-type impurity concentration of the source well region 26 may be approximately equal to the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the source well region 26 may be higher than the p-type impurity concentration of the gate well region 25, or may be lower than the p-type impurity concentration of the gate well region 25. The p-type impurity (trivalent element) of the source well region 26 is preferably aluminum.

[0102] The plurality of source well regions 26 are formed in the second semiconductor region 7 in regions below (specifically, directly below) the plurality of source structures 20, spaced apart in the horizontal direction (first direction X) from the plurality of gate well regions 25. The plurality of source well regions 26 are formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the plurality of source structures 20, and overlap with the plurality of source structures 20 in a one-to-one correspondence in the thickness direction.

[0103] The multiple source well regions 26 each extend in a strip shape in the second direction Y in plan view, following the extension direction of the corresponding source structure 20. In other words, the multiple source well regions 26 are arranged in stripes extending in the second direction Y in plan view.

[0104] The extension direction of the multiple source well regions 26 coincides with the off-direction of the SiC single crystal. The multiple source well regions 26 may extend in the first direction X according to the extension direction of the multiple source structures 20. In this case, the multiple source well regions 26 intersect (specifically, are perpendicular to) the off-direction.

[0105] The multiple source well regions 26 are formed at intervals inward from the periphery of the active region 8. In the second direction Y, both ends of the multiple source well regions 26 may be located inward of the multiple source structures 20 with respect to both ends of the multiple source structures 20, or may be located closer to the periphery of the active region 8 with respect to both ends of the multiple source structures 20.

[0106] The plurality of source well regions 26 are formed at intervals from the bottom of the second semiconductor region 7 toward the bottom wall sides of the plurality of source structures 20, and face the first semiconductor region 6 across a part of the second semiconductor region 7. The plurality of source well regions 26 each have an upper end located on the bottom wall side of the corresponding source structure 20, and a bottom located on the bottom side of the second semiconductor region 7.

[0107] The upper ends of the plurality of source well regions 26 may be connected to the bottom walls of the corresponding source structures 20. The upper ends of the plurality of source well regions 26 may extend along the sidewalls of the corresponding source structures 20 and be connected to the body region 10. The upper ends of the plurality of source well regions 26 may be formed at intervals from the bottom walls of the corresponding source structures 20 toward the bottom of the second semiconductor region 7.

[0108] The bottoms of the multiple source well regions 26 may be located on the bottom wall side of the multiple source structures 20 relative to the intermediate portion of the second semiconductor region 7, or may be located on the bottom side of the second semiconductor region 7 (the side of the second main surface 4) relative to the intermediate portion of the second semiconductor region 7.

[0109] Each of the plurality of source well regions 26 has a bulging portion 26 a. The bulging portion 26 a extends in an arc shape in the horizontal direction from a region directly below the corresponding source structure 20 to both sides of the corresponding source structure 20. Each of the plurality of source well regions 26 is formed in a tapered shape from the bulging portion 26 a to the bottom.

[0110] The source well region 26 may have a width approximately equal to the width of the gate well region 25. The width of the source well region 26 may be greater than the width of the gate well region 25 or less than the width of the gate well region 25. The width of the source well region 26 may be greater than the width of the source structure 20 or less than the width of the source structure 20.

[0111] The width of the source well region 26 may be 0.1 μm or more and 2 μm or less. The width of the source well region 26 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0112] The source well region 26 may have a depth approximately equal to that of the gate well region 25. That is, the bottom of the source well region 26 may be located at a depth approximately equal to that of the bottom of the gate well region 25. The depth of the source well region 26 is the depth of the source well region 26 relative to the bottom wall of the source structure 20. The depth of the source well region 26 may be greater than or less than the depth of the gate well region 25.

[0113] The depth of the source well region 26 may be greater than 0 μm and less than or equal to 5 μm. The depth of the source well region 26 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0114] The source well regions 26 may have an aspect ratio greater than 0 and less than or equal to 2. The aspect ratio of the source well regions 26 is the ratio of the depth of the source well regions 26 to the width of the source well regions 26.

[0115] The aspect ratio may have a value belonging to at least one of the ranges of greater than 0 and less than or equal to 0.25, 0.25 or more and less than or equal to 0.5, 0.5 or more and less than or equal to 0.75, 0.75 or more and less than or equal to 1, 1 or more and less than or equal to 1.25, 1.25 or more and less than or equal to 1.5, 1.5 or more and less than or equal to 1.75, and 1.75 or more and less than or equal to 2.

[0116] The pitch between the centers of the source well regions 26 and the gate well regions 25 (the pitch of the source well regions 26) is approximately equal to the pitch of the source structures 20 and the gate structures 15. The pitch of the source well regions 26 may be 0.1 μm or more and 2.5 μm or less.

[0117] The pitch of the source well regions 26 may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.25 μm, and 2.25 μm to 2.5 μm.

[0118] The source well region 26 forms a pn junction with the second semiconductor region 7. The source well region 26 spreads a depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer originating from the source well region 26 spreads in the horizontal and thickness directions, alleviating the electric field with respect to the active region 8 (source structure 20). The depletion layer originating from the source well region 26 merges with the depletion layer originating from the gate well region 25.

[0119] The semiconductor device 1A includes a plurality of gate contact regions 27 formed in the chip 2 (second semiconductor region 7) in the active region 8. The gate contact regions 27 may also be referred to as "first contact regions" or the like. A source potential is applied to the gate contact regions 27.

[0120] The gate contact region 27 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the gate contact region 27 is higher than the p-type impurity concentration of the body region 10. The p-type impurity concentration of the gate contact region 27 is higher than the p-type impurity concentration of the gate well region 25.

[0121] The plurality of gate contact regions 27 are formed in regions along the plurality of gate structures 15, spaced apart from the plurality of source structures 20. The plurality of gate contact regions 27 are formed in a one-to-many correspondence with the plurality of gate structures 15. The plurality of gate contact regions 27 are formed at intervals in the second direction Y following the extension direction of the corresponding gate structures 15.

[0122] With respect to one and the other gate structures 15, the multiple gate contact regions 27 along one gate structure 15 face the multiple gate contact regions 27 along the other gate structure 15 in the first direction X in plan view. In other words, the multiple gate contact regions 27 are generally arranged in a matrix with gaps in the first direction X and the second direction Y in plan view.

[0123] In plan view, one of the plurality of gate contact regions 27 may face, in the first direction X, a region between the other of the plurality of gate contact regions 27. In other words, the plurality of gate contact regions 27 may be generally arranged in a staggered pattern at intervals in the first direction X and the second direction Y in plan view.

[0124] In this embodiment, the gate contact regions 27 extend in a strip shape along the gate structures 15 in a plan view. The lengths of the gate contact regions 27 in the second direction Y may be equal to or different from one another. The lengths of the gate contact regions 27 in the second direction Y are adjusted depending on the channel area to be formed.

[0125] The channel area is the total area of ​​the portions of the source region 11 exposed from the regions between the plurality of gate structures 15 and the plurality of source structures 20. That is, the channel area increases or decreases depending on the ratio of the total planar area of ​​the plurality of gate contact regions 27. The total planar area of ​​the plurality of gate contact regions 27 is preferably less than the channel area.

[0126] That is, in the region between one adjacent gate structure 15 and one adjacent source structure 20, the total planar area of ​​the plurality of gate contact regions 27 is preferably less than the planar area of ​​the source region 11. With this configuration, an increase in the resistance value (on-resistance) due to a short channel is suppressed.

[0127] The length of the gate contact region 27 may be greater than or less than the width of the gate structure 15. The length of the gate contact region 27 may be greater than or less than the pitch between the gate structure 15 and the source structure 20. The length of the gate contact region 27 may be greater than or less than the pitch between two adjacent gate structures 15.

[0128] The spacing between the multiple gate contact regions 27 may be greater than the width of the gate structures 15 or may be smaller than the width of the gate structures 15. The spacing between the gate contact regions 27 may be greater than the pitch between the gate structures 15 and the source structures 20 or may be smaller than the pitch between the gate structures 15 and the source structures 20. The spacing between the gate contact regions 27 may be greater than the pitch between two adjacent gate structures 15 or may be smaller than the pitch between two adjacent gate structures 15.

[0129] The plurality of gate contact regions 27 are respectively interposed in regions between the bottom walls of the plurality of gate structures 15 and the bottoms of the plurality of gate well regions 25. The plurality of gate contact regions 27 are connected to the bottom walls of the corresponding gate structures 15 and the corresponding gate well regions 25.

[0130] The plurality of gate contact regions 27 increase the p-type impurity concentration at the upper end of the corresponding gate well region 25. The gate contact regions 27 extend from the region directly below the gate structure 15 to both sides of the gate structure 15 and have extensions that extend along the sidewalls of the gate structure 15.

[0131] The thickness in the horizontal direction (first direction X) of the portion (extension) of the gate contact region 27 that runs along the side wall of the gate structure 15 may be less than the thickness in the vertical direction Z of the portion of the gate contact region 27 that runs along the bottom wall of the gate structure 15.

[0132] The extension of the gate contact region 27 is electrically connected to the body region 10 in the surface layer portion of the first main surface 3, and electrically connects the corresponding gate well region 25 to the body region 10. This prevents the gate well region 25 from being electrically floating, and improves the electrical response characteristics of the gate well region 25.

[0133] The gate contact region 27 has an upper end exposed from the first main surface 3. In this embodiment, the upper end of the gate contact region 27 is exposed from the sidewall of the first trench 16 at the opening end of the first trench 16. The upper end of the gate contact region 27 may extend horizontally in the surface portion of the body region 10.

[0134] The semiconductor device 1A includes a plurality of source contact regions 28 formed in the chip 2 (second semiconductor region 7). The source contact regions 28 may also be referred to as "second contact regions," etc. A source potential is applied to the source contact regions 28.

[0135] The source contact region 28 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the source contact region 28 is higher than the p-type impurity concentration of the body region 10.

[0136] The p-type impurity concentration of the source contact region 28 is higher than the p-type impurity concentration of the source well region 26. The p-type impurity concentration of the source contact region 28 may be approximately equal to the p-type impurity concentration of the gate contact region 27. The p-type impurity concentration of the source contact region 28 may be higher than the p-type impurity concentration of the gate contact region 27 or may be lower than the p-type impurity concentration of the gate contact region 27.

[0137] The source contact regions 28 are formed in regions along the source structures 20, spaced apart from the gate structures 15. The source contact regions 28 have a planar layout that differs from the planar layout of the gate contact regions 27. In this embodiment, the source contact regions 28 are formed in a one-to-one correspondence with the source structures 20.

[0138] The source contact regions 28 extend in a strip-like shape in the second direction Y in accordance with the extension direction of the corresponding source structures 20. In other words, the source contact regions 28 are formed in a stripe shape extending along the source structures 20 in a plan view.

[0139] The source contact regions 28 have lengths in the second direction Y that are greater than the lengths of the gate contact regions 27 and cross the gate contact regions 27 in the second direction Y. The source contact regions 28 may have lengths in the second direction Y that are greater than the lengths of the source structures 20 or may have lengths that are less than the lengths of the source structures 20.

[0140] The plurality of source contact regions 28 preferably have a total planar area larger than the total planar area of ​​the plurality of gate contact regions 27. The total planar area of ​​the plurality of source contact regions 28 may be larger than the channel area or may be smaller than the channel area.

[0141] The source contact regions 28 may be formed in a one-to-many correspondence with the source structures 20, similar to the gate contact regions 27. In this case, with respect to one and the other source structures 20, the gate contact regions 27 along one source structure 20 may face the source contact regions 28 along the other source structure 20 in the first direction X in plan view.

[0142] That is, the multiple source contact regions 28 may be generally arranged in a matrix with gaps in the first direction X and the second direction Y in a plan view. One of the multiple source contact regions 28 may face a region between the other multiple source contact regions 28 in the first direction X in a plan view. That is, the multiple source contact regions 28 may be generally arranged in a staggered pattern with gaps in the first direction X and the second direction Y in a plan view.

[0143] The plurality of source contact regions 28 are respectively interposed in regions between the bottom wall of the corresponding source structure 20 and the bottom of the corresponding source well region 26. The plurality of source contact regions 28 are respectively connected to the bottom wall of the corresponding source structure 20 and the corresponding source well region 26.

[0144] The plurality of source contact regions 28 increase the p-type impurity concentration at the upper end of the corresponding source well region 26. The plurality of source contact regions 28 extend from the region directly below the source structure 20 to both sides of the source structure 20 and have extensions that extend along the sidewalls of the source structure 20.

[0145] The thickness in the horizontal direction (first direction X) of the portion (extension) of the source contact region 28 along the side wall of the source structure 20 may be less than the thickness in the vertical direction Z of the portion of the source contact region 28 along the bottom wall of the source structure 20.

[0146] The extension of the source contact region 28 is electrically connected to the body region 10 in the surface layer portion of the first main surface 3, and electrically connects the corresponding source well region 26 to the body region 10. This prevents the source well region 26 from being electrically floating, and improves the electrical response characteristics of the source well region 26.

[0147] The source contact region 28 has an upper end exposed from the first main surface 3. In this embodiment, the upper end of the source contact region 28 is exposed from the sidewall of the second trench 21 at the opening end of the second trench 21. The upper end of the source contact region 28 may extend horizontally in the surface layer portion of the body region 10.

[0148] The upper end of the source contact region 28 is electrically connected to the upper end of the adjacent gate contact regions 27 in the body region 10. In this embodiment, the upper end of the source contact region 28 is integrally formed with the upper end of the gate contact region 27.

[0149] The semiconductor device 1A includes one or more (in this embodiment, multiple) trench-type (trench electrode-type) isolation structures 30 formed on the first main surface 3 in the active region 8. The isolation structures 30 may also be referred to as "trench structures," "third trench structures," "dummy structures," etc.

[0150] The number of isolation structures 30 is arbitrary. The number of isolation structures 30 may be 1 or more and 15 or less. The number of isolation structures 30 may be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15. The number of isolation structures 30 is typically 1 or more and 10 or less. In this embodiment, the semiconductor device 1A includes five isolation structures 30, as an example.

[0151] At least one or all of the plurality of isolation structures 30 may be formed in an electrically floating state. A source potential may be applied to at least one or all of the plurality of isolation structures 30. The plurality of isolation structures 30 may include one or more isolation structures 30 formed in an electrically floating state and one or more isolation structures 30 to which a source potential is applied.

[0152] The plurality of isolation structures 30 are formed in an inner portion of the first main surface 3 at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The plurality of isolation structures 30 define an active region 8 on the inner side of the first main surface 3, and define a peripheral region 9 on the peripheral edge side of the first main surface 3. The active region 8 is located inward from the outermost isolation structure 30, and the peripheral region 9 is located outward from the outermost isolation structure 30.

[0153] The plurality of isolation structures 30 are arranged on the periphery of the active region 8 at intervals from the plurality of gate structures 15 and the plurality of source structures 20. The plurality of isolation structures 30 are arranged at intervals from one another and are adjacent to one another in the horizontal direction with part of the chip 2 sandwiched between them. The plurality of isolation structures 30 each extend in a strip shape along the periphery of the first main surface 3. The plurality of isolation structures 30 have a portion extending in the first direction X and a portion extending in the second direction Y.

[0154] That is, the plurality of isolation structures 30 have portions extending in the extension direction (second direction Y) of the plurality of gate structures 15 (plurality of source structures 20) and portions extending in a direction (first direction X) intersecting the extension direction of the plurality of gate structures 15 (plurality of source structures 20). The plurality of isolation structures 30 may be formed in the shape of a polygonal ring (quadrilateral ring) that collectively surrounds the plurality of gate structures 15 and the plurality of source structures 20 in a plan view.

[0155] The plurality of isolation structures 30 are formed in a region outside the source region 11 and penetrate only the body region 10. The plurality of isolation structures 30 may also penetrate the source region 11. The plurality of isolation structures 30 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 with part of the second semiconductor region 7 in between.

[0156] The plurality of isolation structures 30 may be formed at intervals from a depth position of an intermediate portion of the second semiconductor region 7 toward the first main surface 3, or may be located on the bottom side of the second semiconductor region 7 with respect to the depth position of the intermediate portion of the second semiconductor region 7. The plurality of isolation structures 30 are formed substantially perpendicular to the first main surface 3. The plurality of isolation structures 30 may be formed in a shape tapering toward the bottom of the second semiconductor region 7.

[0157] The side walls of the plurality of isolation structures 30 are formed by the m-plane ((1-100) plane) of the SiC single crystal and the a-plane ((11-20) plane) of the SiC single crystal. The bottom walls of the plurality of isolation structures 30 are formed by the c-plane (Si-plane) of the SiC single crystal. The bottom walls of the plurality of isolation structures 30 preferably extend substantially flat in the horizontal direction. The bottom walls of the plurality of isolation structures 30 may be curved in an arc shape toward the second main surface 4.

[0158] The inclination angle (absolute value) of the sidewall of the isolation structure 30 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0159] The isolation structure 30 may have a width that is approximately equal to the width of the gate structure 15. The width of the isolation structure 30 may be greater than or less than the width of the gate structure 15. The width of the isolation structure 30 may be approximately equal to the width of the source structure 20. The width of the isolation structure 30 may be greater than or less than the width of the source structure 20.

[0160] The width of the isolation structure 30 may be 0.1 μm or more and 2 μm or less. The width of the isolation structure 30 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0161] The isolation structure 30 may have a depth equal to or greater than the depth of the gate structure 15. The depth of the isolation structure 30 is measured from the first main surface 3. The depth of the isolation structure 30 may be greater than the depth of the gate structure 15 or may be less than the depth of the gate structure 15. In this embodiment, the depth of the isolation structure 30 is approximately equal to the depth of the gate structure 15.

[0162] The isolation structure 30 may have a depth equal to or greater than the depth of the source structure 20. The depth of the isolation structure 30 may be greater than the depth of the source structure 20 or may be less than the depth of the source structure 20. In this embodiment, the depth of the isolation structure 30 is approximately equal to the depth of the source structure 20.

[0163] The ratio (depth ratio) of the depth of the isolation structure 30 to the depth of the gate structure 15 (source structure 20) may be 0.8 to 1.2. The depth ratio may have a value belonging to at least one of the following ranges: 0.8 to 0.85, 0.85 to 0.9, 0.9 to 0.95, 0.95 to 1, 1 to 1.05, 1.05 to 1.1, 1.1 to 1.15, and 1.15 to 1.2. The depth ratio is preferably 0.95 to 1.05.

[0164] The depth of the isolation structure 30 may be 0.1 μm or more and 3 μm or less. The depth of the isolation structure 30 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the isolation structure 30 is preferably 0.5 μm or more and 1.5 μm or less.

[0165] The isolation structure 30 may have an aspect ratio of 1 to 3. The aspect ratio of the isolation structure 30 is the ratio of the depth of the isolation structure 30 to the width of the isolation structure 30. The aspect ratio may have a value belonging to at least one of the ranges of 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. The aspect ratio is preferably 1.5 to 2.5.

[0166] The pitch of the centers of the isolation structures 30 (the pitch of the isolation structures 30) is preferably less than the pitch of the gate structures 15 and the source structures 20. The pitch of the isolation structures 30 may be greater than the pitch of the gate structures 15 and the source structures 20.

[0167] The pitch of the isolation structures 30 may be 0.1 μm or more and 2.5 μm or less. The pitch of the isolation structures 30 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, and 2.25 μm or more and 2.5 μm or less.

[0168] Each of the plurality of isolation structures 30 includes a third trench 31, a third insulating film 32, and a third buried electrode 33. The third trench 31 is formed in the first main surface 3, and defines the wall surfaces (side walls and bottom wall) of the isolation structure 30.

[0169] The third insulating film 32 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The third insulating film 32 preferably includes the same insulating material as the insulating material of the first insulating film 17 (second insulating film 22). In this embodiment, the third insulating film 32 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the third insulating film 32 includes a silicon oxide film made of an oxide of the chip 2.

[0170] The third insulating film 32 covers the wall surface of the third trench 31. The third insulating film 32 includes a first film portion and a second film portion. The first film portion covers the side wall of the third trench 31 in a film-like manner. The second film portion covers the bottom wall of the third trench 31 in a film-like manner and is continuous with the first film portion.

[0171] The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion. The thickness of the first film portion of the third insulating film 32 may be approximately equal to the thickness of the first film portion of the first insulating film 17. The thickness of the second film portion of the third insulating film 32 may be approximately equal to the thickness of the second film portion of the first insulating film 17.

[0172] The third insulating film 32 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0173] The third buried electrode 33 is buried in the third trench 31 with the third insulating film 32 sandwiched therebetween. The third buried electrode 33 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The third buried electrode 33 preferably includes the same type of conductive material as the conductive material of the first buried electrode 18. The third buried electrode 33 faces the second semiconductor region 7 and the body region 10 with the third insulating film 32 sandwiched therebetween. The third buried electrode 33 may have a portion facing the source region 11.

[0174] The third buried electrode 33 has an electrode surface exposed from the third trench 31. The electrode surface is located closer to the bottom wall of the third trench 31 with respect to the height position of the first main surface 3. The electrode surface is located closer to the first main surface 3 with respect to the depth position of the bottom of the source region 11. The electrode surface has a recess in an inner portion that tapers toward the bottom wall of the third trench 31.

[0175] The semiconductor device 1A includes one or more (four in this embodiment) shallow well regions 35 formed in the chip 2 (second semiconductor region 7). The shallow well regions 35 may also be referred to as "third well regions," "first isolation well regions," etc. A source potential is applied to the shallow well regions 35. The number of shallow well regions 35 is less than the number of isolation structures 30.

[0176] The shallow well region 35 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the shallow well region 35 may be higher than the p-type impurity concentration of the body region 10 or may be lower than the p-type impurity concentration of the body region 10.

[0177] The p-type impurity concentration of the shallow well region 35 may be approximately equal to the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the shallow well region 35 may be higher than the p-type impurity concentration of the gate well region 25, or may be lower than the p-type impurity concentration of the gate well region 25.

[0178] The p-type impurity concentration of the shallow well region 35 may be approximately equal to the p-type impurity concentration of the source well region 26. The p-type impurity concentration of the shallow well region 35 may be higher than the p-type impurity concentration of the source well region 26, or may be lower than the p-type impurity concentration of the source well region 26. The p-type impurity (trivalent element) of the shallow well region 35 is preferably aluminum.

[0179] The plurality of shallow well regions 35 are formed in regions below (specifically, directly below) the plurality of isolation structures 30 so as to be adjacent to one another in the horizontal direction within the second semiconductor region 7. The plurality of shallow well regions 35 are formed in regions below a plurality (four in this embodiment) of the plurality of isolation structures 30 that are located on the active region 8 side.

[0180] The plurality of shallow well regions 35 are respectively formed in a thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the plurality of isolation structures 30, and overlap the plurality of isolation structures 30 in a one-to-one correspondence in the thickness direction. The plurality of shallow well regions 35 are not formed in a region below one or more (one in this embodiment) isolation structures 30 located on the peripheral side of the first main surface 3 (toward the outer periphery region 9) among the plurality of isolation structures 30.

[0181] The plurality of shallow well regions 35 extend in a strip shape along the corresponding isolation structures 30 in plan view. The plurality of shallow well regions 35 have portions extending in the first direction X along the corresponding isolation structures 30 in plan view, and portions extending in the second direction Y along the corresponding isolation structures 30. In this embodiment, the plurality of shallow well regions 35 each extend in a polygonal ring shape (a square ring shape in this embodiment) along the corresponding isolation structures 30 in plan view.

[0182] The plurality of shallow well regions 35 are formed at intervals in the horizontal direction from the plurality of gate well regions 25 and the plurality of source well regions 26. In this embodiment, the plurality of shallow well regions 35 are connected to one another in the horizontal direction. The plurality of shallow well regions 35 may be formed at intervals in the horizontal direction and may face one another in the horizontal direction with a part of the second semiconductor region 7 sandwiched therebetween.

[0183] The plurality of shallow well regions 35 are formed at intervals from the bottom of the second semiconductor region 7 toward the bottom wall sides of the plurality of isolation structures 30, and face the first semiconductor region 6 across a part of the second semiconductor region 7. Each of the plurality of shallow well regions 35 has an upper end located on the bottom wall side of the corresponding isolation structure 30, and a bottom located on the bottom side of the second semiconductor region 7.

[0184] The upper ends of the plurality of shallow well regions 35 may be connected to the bottom walls of the corresponding isolation structures 30. The upper ends of the plurality of shallow well regions 35 may extend along the side walls of the corresponding isolation structures 30 and be connected to the body region 10. The upper ends of the plurality of shallow well regions 35 may be formed at intervals from the bottom walls of the corresponding isolation structures 30 toward the bottom of the second semiconductor region 7.

[0185] The bottoms of the multiple shallow well regions 35 may be located on the bottom wall side of the isolation structure 30 corresponding to the intermediate portion of the second semiconductor region 7, or may be located on the bottom side of the second semiconductor region 7 (the side of the second main surface 4) relative to the intermediate portion of the second semiconductor region 7.

[0186] Each of the shallow well regions 35 has a bulging portion 35a. The bulging portion 35a extends in an arc shape in the horizontal direction from a region directly below the corresponding isolation structure 30 to both sides of the corresponding isolation structure 30. The bulging portions 35a are connected to each other in the horizontal direction. Each of the shallow well regions 35 is formed in a tapered shape from the bulging portion 35a toward the bottom.

[0187] The shallow well region 35 may have a width greater than or less than the width of the isolation structure 30. The shallow well region 35 may have a width greater than or less than the width of the gate structure 15. The shallow well region 35 may have a width greater than or less than the width of the source structure 20.

[0188] The width of the shallow well region 35 may be approximately equal to the width of the gate well region 25. The width of the shallow well region 35 may be greater than the width of the gate well region 25 or less than the width of the gate well region 25. The width of the shallow well region 35 may be approximately equal to the width of the source well region 26. The width of the shallow well region 35 may be greater than the width of the source well region 26 or less than the width of the source well region 26.

[0189] The width of the shallow well region 35 may be 0.1 μm or more and 2 μm or less. The width of the shallow well region 35 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0190] The shallow well region 35 may have a depth approximately equal to that of the gate well region 25. The depth of the shallow well region 35 is the depth of the shallow well region 35 when the bottom wall of the isolation structure 30 is used as the reference. The bottom of the shallow well region 35 may be located at a depth approximately equal to that of the bottom of the gate well region 25. The depth of the shallow well region 35 may be greater than or less than the depth of the gate well region 25.

[0191] The depth of the shallow well region 35 may be approximately equal to the depth of the source well region 26. The bottom of the shallow well region 35 may be located at a depth approximately equal to the depth of the bottom of the source well region 26. The depth of the shallow well region 35 may be greater than the depth of the source well region 26 or may be less than the depth of the source well region 26.

[0192] The depth of the shallow well region 35 may be greater than 0 μm and less than or equal to 5 μm. The depth of the shallow well region 35 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0193] The shallow well region 35 may have an aspect ratio greater than 0 and less than or equal to 2. The aspect ratio of the shallow well region 35 is the ratio of the depth of the shallow well region 35 to the width of the shallow well region 35.

[0194] The aspect ratio may have a value belonging to at least one of the ranges of greater than 0 and less than or equal to 0.25, 0.25 or more and less than or equal to 0.5, 0.5 or more and less than or equal to 0.75, 0.75 or more and less than or equal to 1, 1 or more and less than or equal to 1.25, 1.25 or more and less than or equal to 1.5, 1.5 or more and less than or equal to 1.75, and 1.75 or more and less than or equal to 2.

[0195] The pitch of the centers of the plurality of shallow well regions 35 (the pitch of the shallow well regions 35) is approximately equal to the pitch of the plurality of isolation structures 30. In this embodiment, the pitch of the shallow well regions 35 is less than the pitch of the gate structures 15 and the source structures 20. The pitch of the shallow well regions 35 may be approximately equal to the pitch of the gate structures 15 and the source structures 20, or may be greater than the pitch of the gate structures 15 and the source structures 20.

[0196] In this embodiment, the pitch of the shallow well regions 35 is less than the pitch of the gate well regions 25 and the source well regions 26. The pitch of the shallow well regions 35 may be approximately equal to the pitch of the gate well regions 25 and the source well regions 26, or may be greater than the pitch of the gate well regions 25 and the source well regions 26.

[0197] The pitch of the shallow well regions 35 may be 0.1 μm or more and 2.5 μm or less. The pitch of the shallow well regions 35 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, and 2.25 μm or more and 2.5 μm or less.

[0198] The shallow well region 35 forms a pn junction with the second semiconductor region 7. The shallow well region 35 expands a depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer originating from the shallow well region 35 expands in the horizontal and thickness directions and merges with the depletion layer originating from the body region 10 (inner portion of the active region 8). The shallow well region 35 expands the depletion layer originating from the body region 10 toward the periphery of the first main surface 3, and relieves the electric field in the multiple isolation structures 30 (periphery portion of the active region 8).

[0199] The semiconductor device 1A includes one or more (one in this embodiment) deep well regions 36 formed in the chip 2 (second semiconductor region 7). The deep well region 36 may also be referred to as a "fourth well region," a "second isolation well region," or the like. A source potential is applied to the deep well region 36.

[0200] The number of deep well regions 36 is less than the number of isolation structures 30. The number of deep well regions 36 is less than the number of shallow well regions 35. The number of deep well regions 36 may be more than the number of shallow well regions 35. The number of deep well regions 36 may be the same as the number of shallow well regions 35.

[0201] The deep well region 36 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the deep well region 36 may be higher than the p-type impurity concentration of the body region 10 or may be lower than the p-type impurity concentration of the body region 10.

[0202] The p-type impurity concentration of the deep well region 36 may be approximately equal to the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the deep well region 36 may be higher than the p-type impurity concentration of the gate well region 25, or may be lower than the p-type impurity concentration of the gate well region 25.

[0203] The p-type impurity concentration of the deep well region 36 may be approximately equal to the p-type impurity concentration of the source well region 26. The p-type impurity concentration of the deep well region 36 may be higher than the p-type impurity concentration of the source well region 26, or may be lower than the p-type impurity concentration of the source well region 26.

[0204] The p-type impurity concentration of the deep well region 36 may be approximately equal to the p-type impurity concentration of the shallow well region 35. The p-type impurity concentration of the deep well region 36 may be higher than the p-type impurity concentration of the shallow well region 35, or may be lower than the p-type impurity concentration of the shallow well region 35. The p-type impurity (trivalent element) of the deep well region 36 is preferably aluminum.

[0205] The deep well region 36 is located on the peripheral side (toward the outer periphery region 9) of the first main surface 3 relative to the plurality of shallow well regions 35 within the chip 2 (second semiconductor region 7). In other words, the deep well region 36 is formed in a region below (specifically, directly below) one of the plurality of isolation structures 30 that is located on the outer periphery region 9 side (toward the peripheral edge of the first main surface 3).

[0206] The deep well region 36 is formed at a distance from the isolation structure 30 for the shallow well region 35 toward the peripheral region 9, and does not overlap the isolation structure 30 for the shallow well region 35 in the thickness direction. In this embodiment, the deep well region 36 is formed in a region below the outermost isolation structure 30, which is arranged closest to the peripheral region 9 among the multiple isolation structures 30.

[0207] The deep well region 36 is formed in a thickness range between the bottom of the second semiconductor region 7 and the bottom wall of the outermost isolation structure 30, and overlaps the outermost isolation structure 30 in a one-to-one correspondence in the thickness direction. The deep well region 36 is not formed in a region below one or more (in this embodiment, multiple) isolation structures 30 that are located on the peripheral side of the first main surface 3 (toward the outer periphery region 9) among the multiple isolation structures 30.

[0208] The deep well region 36 extends in a strip shape along the outermost isolation structure 30 in plan view. The deep well region 36 has a portion extending in the first direction X along the outermost isolation structure 30 in plan view, and a portion extending in the second direction Y along the outermost isolation structure 30.

[0209] In this embodiment, the deep well region 36 is formed in a polygonal ring shape (a square ring shape in this embodiment) extending along the outermost isolation structure 30 in plan view. The deep well region 36 is formed at a distance from the plurality of gate well regions 25 and the plurality of source well regions 26 in the horizontal direction.

[0210] In this embodiment, the deep well region 36 is connected to the outermost shallow well region 35 in the horizontal direction. The deep well region 36 may be formed at a distance from the outermost shallow well region 35 in the horizontal direction. The deep well region 36 is formed at a distance from the bottom of the second semiconductor region 7 toward the bottom wall of the outermost isolation structure 30, and faces the first semiconductor region 6 with a part of the second semiconductor region 7 sandwiched therebetween.

[0211] The deep well region 36 has a depth greater than the depth of the plurality of shallow well regions 35, and is formed in the shape of a vertically elongated column extending in the thickness direction of the chip 2. The depth of the deep well region 36 is the depth of the deep well region 36 when the bottom wall of the outermost isolation structure 30 is used as the reference.

[0212] The depth of the deep well region 36 is greater than the depth of the gate well region 25. The depth of the deep well region 36 is greater than the depth of the source well region 26. The depth of the deep well region 36 may be greater than the depth of the outermost isolation structure 30 or may be less than the depth of the outermost isolation structure 30.

[0213] The depth of the deep well region 36 may be greater than or less than the depth of the gate structure 15. The depth of the deep well region 36 may be greater than or less than the depth of the source structure 20.

[0214] The depth of the deep well region 36 may be greater than 0 μm and less than or equal to 5 μm. The depth of the deep well region 36 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0215] The deep well region 36 may have an aspect ratio greater than 0 and less than or equal to 5. The aspect ratio of the deep well region 36 is the ratio of the depth of the deep well region 36 to the width of the deep well region 36.

[0216] The aspect ratio may have a value belonging to at least one of the ranges of greater than 0 and less than 1, 1 to 1.5, 1.5 to 2, 2 to 2.5, 2.5 to 3, 3 to 3.5, 3.5 to 4, 4 to 4.5, and 4.5 to 5. The aspect ratio of the deep well region 36 is preferably greater than 1.

[0217] The deep well region 36 has an upper end located on the bottom wall side of the outermost isolation structure 30, and a bottom located on the bottom side of the second semiconductor region 7. The upper end of the deep well region 36 is located on the isolation structure 30 side relative to the bottoms of the multiple gate well regions 25, the bottoms of the multiple source well regions 26, and the bottoms of the multiple shallow well regions 35. The upper end of the deep well region 36 faces the multiple gate well regions 25, the multiple source well regions 26, and the multiple shallow well regions 35 in the horizontal direction.

[0218] The upper end of the deep well region 36 may be connected to the bottom wall of the outermost isolation structure 30. The upper end of the deep well region 36 may extend along the sidewall of the outermost isolation structure 30 and be connected to the body region 10. The upper end of the deep well region 36 may be formed at a distance from the bottom wall of the outermost isolation structure 30 toward the bottom of the second semiconductor region 7.

[0219] The bottom of the deep well region 36 is located closer to the bottom of the second semiconductor region 7 than the bottoms of the plurality of gate well regions 25, the bottoms of the plurality of source well regions 26, and the bottoms of the plurality of shallow well regions 35. The bottom of the deep well region 36 does not face the plurality of gate well regions 25, the plurality of source well regions 26, and the plurality of shallow well regions 35 in the horizontal direction.

[0220] The bottom of the deep well region 36 may be located on the bottom wall side of the outermost isolation structure 30 relative to the intermediate portion of the second semiconductor region 7, or may be located on the bottom side of the second semiconductor region 7 (the side of the second main surface 4) relative to the intermediate portion of the second semiconductor region 7.

[0221] The deep well region 36 has a plurality of (two in this embodiment) bulging portions 36a and one or a plurality of (one in this embodiment) constricted portions 36b in the thickness direction of the chip 2.

[0222] The multiple bulging portions 36a are formed at different depth positions in the thickness direction of the chip 2. The multiple bulging portions 36a are each formed by multiple (two in this embodiment) p-type impurity regions (36a) positioned at different depths along the thickness direction of the chip 2. The multiple bulging portions 36a each protrude in an arc shape in the horizontal direction from the region directly below the outermost isolation structure 30 to both sides of the outermost isolation structure 30.

[0223] The multiple bulging portions 36a include an upper bulging portion 36a (on the isolation structure 30 side) and a lower bulging portion 36a (on the bottom of the second semiconductor region 7). The upper bulging portion 36a is positioned at approximately the same depth as the bulging portions 35a of the multiple shallow well regions 35. The upper bulging portion 36a is connected to the bulging portions 36a of the outermost shallow well regions 35. The upper bulging portion 36a may be formed at a distance from the outermost shallow well region 35 in the horizontal direction.

[0224] The upper bulging portion 36a is positioned at a depth substantially equal to that of the bulging portion 25a of the gate well region 25. The upper bulging portion 36a may be positioned closer to the first main surface 3 than the depth position of the bulging portion 25a of the gate well region 25, or may be positioned closer to the bottom of the second semiconductor region 7.

[0225] The upper bulging portion 36a is positioned at a depth substantially equal to that of the bulging portion 26a of the source well region 26. The upper bulging portion 36a may be positioned closer to the first main surface 3 than the depth position of the bulging portion 26a of the source well region 26, or may be positioned closer to the bottom of the second semiconductor region 7.

[0226] The lower bulge portion 36a is located on the bottom side of the second semiconductor region 7 relative to the depth positions of the bottoms of the plurality of shallow well regions 35, and does not face the plurality of shallow well regions 35 in the horizontal direction. The lower bulge portion 36a does not face the plurality of gate well regions 25 in the horizontal direction. The lower bulge portion 36a does not face the plurality of source well regions 26 in the horizontal direction.

[0227] The lower bulge 36a is formed in a tapered shape toward the bottom. The p-type impurity concentration in the middle of the lower bulge 36a is preferably lower than the p-type impurity concentration in the middle of the upper bulge 36a. In other words, the p-type impurity concentration of the multiple bulges 36a preferably gradually decreases toward the bottom of the second semiconductor region 7.

[0228] The bulge portion 36a may have a width greater than or less than the width of the outermost isolation structure 30. The width of the bulge portion 36a may be greater than or less than the width of the gate structure 15. The width of the bulge portion 36a may be greater than or less than the width of the source structure 20.

[0229] The width of the bulge portion 36a may be approximately equal to the width of the gate well region 25. The width of the bulge portion 36a may be greater than the width of the gate well region 25 or less than the width of the gate well region 25. The width of the bulge portion 36a may be approximately equal to the width of the source well region 26. The width of the bulge portion 36a may be greater than the width of the source well region 26 or less than the width of the source well region 26.

[0230] The width of the bulge portion 36a may be approximately equal to the width of the shallow well region 35. The width of the bulge portion 36a may be greater than the width of the shallow well region 35 or may be less than the width of the shallow well region 35.

[0231] The width of the bulging portion 36a may be 0.1 μm or more and 2 μm or less. The width of the bulging portion 36a may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0232] The constricted portion 36b forms a connection between the plurality of bulging portions 36a in the region between the plurality of bulging portions 36a, and is recessed in an arc shape inward in the horizontal direction from the plurality of bulging portions 36a. In other words, the constricted portion 36b is formed by the connection between the plurality of impurity regions (36a) that overlap in the vertical direction.

[0233] The constricted portion 36b contains p-type impurities at the lower end of the upper bulging portion 36a and at the upper end of the lower bulging portion 36a. The p-type impurity concentration of the constricted portion 36b may be higher than the p-type impurity concentrations at the lower end of the upper bulging portion 36a and at the upper end of the lower bulging portion 36a. The p-type impurity concentration of the constricted portion 36b may be lower than the p-type impurity concentrations at the middle of the upper bulging portion 36a and at the middle of the lower bulging portion 36a.

[0234] The constricted portion 36b is formed at a horizontal distance from the outermost shallow well region 35. The constricted portion 36b is formed in a region on the isolation structure 30 side with respect to the bottom of the outermost shallow well region 35, and faces the outermost shallow well region 35 in the horizontal direction. The constricted portion 36b may be located closer to the bottom of the second semiconductor region 7 than the bottom of the outermost shallow well region 35.

[0235] The constricted portion 36b has a width that is less than the width of the bulging portion 36a. The width of the constricted portion 36b may be greater than the width of the outermost isolation structure 30 or less than the width of the outermost isolation structure 30. The width of the constricted portion 36b may be greater than the width of the gate structure 15 or less than the width of the gate structure 15. The width of the constricted portion 36b may be greater than the width of the source structure 20 or less than the width of the source structure 20.

[0236] The width of the constricted portion 36b may be greater than or less than the width of the gate well region 25. The width of the constricted portion 36b may be greater than or less than the width of the source well region 26. The width of the constricted portion 36b may be approximately equal to the width of the shallow well region 35. The width of the constricted portion 36b may be greater than or less than the width of the shallow well region 35.

[0237] The width of the constricted portion 36b may be 0.1 μm or more and 2 μm or less. The width of the constricted portion 36b may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or more, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0238] The pitch of the centers of the deep well regions 36 relative to the centers of the shallow well regions 35 (the pitch of the deep well regions 36) is approximately equal to the pitch of the plurality of isolation structures 30. The pitch of the deep well regions 36 is less than the pitch of the gate structures 15 and the source structures 20. The pitch of the deep well regions 36 may be approximately equal to the pitch of the gate structures 15 and the source structures 20, or may be greater than the pitch of the gate structures 15 and the source structures 20.

[0239] In this embodiment, the pitch of the deep well regions 36 is less than the pitch of the gate well regions 25 and the source well regions 26. The pitch of the deep well regions 36 may be approximately equal to the pitch of the gate well regions 25 and the source well regions 26, or may be greater than the pitch of the gate well regions 25 and the source well regions 26.

[0240] The pitch of the deep well regions 36 is approximately equal to the pitch of the shallow well regions 35. The pitch of the deep well regions 36 may be larger than the pitch of the shallow well regions 35 or may be smaller than the pitch of the shallow well regions 35.

[0241] The pitch of the deep well regions 36 may be 0.1 μm or more and 2.5 μm or less. The pitch of the deep well regions 36 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, and 2.25 μm or more and 2.5 μm or less.

[0242] The deep well region 36 forms a pn junction with the second semiconductor region 7. When a reverse bias voltage is applied, the deep well region 36 spreads a depletion layer into the second semiconductor region 7. The depletion layer originating from the deep well region 36 spreads in the horizontal and thickness directions and merges with the depletion layer originating from the shallow well region 35.

[0243] The depletion layer originating from the deep well region 36 is formed in a region below the second semiconductor region 7 relative to the depletion layer originating from the shallow well region 35. The deep well region 36 expands the depletion layer originating from the shallow well region 35 toward the periphery of the first main surface 3, thereby alleviating the electric field in the plurality of isolation structures 30 (periphery of the active region 8).

[0244] The semiconductor device 1A includes one or more (four in this embodiment) shallow contact regions 37 formed in the chip 2 (second semiconductor region 7). The shallow contact region 37 may also be referred to as a "third contact region," etc. A source potential is applied to the shallow contact region 37. The shallow contact region 37 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the shallow contact region 37 is higher than the p-type impurity concentration of the body region 10.

[0245] The p-type impurity concentration of the shallow contact region 37 is higher than the p-type impurity concentration of the shallow well region 35. The p-type impurity concentration of the shallow contact region 37 is higher than the p-type impurity concentration of the deep well region 36. The p-type impurity concentration of the shallow contact region 37 is higher than the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the shallow contact region 37 is higher than the p-type impurity concentration of the source well region 26.

[0246] The p-type impurity concentration of the shallow contact region 37 may be approximately equal to the p-type impurity concentration of the gate contact region 27. The p-type impurity concentration of the shallow contact region 37 may be higher than the p-type impurity concentration of the gate contact region 27, or may be lower than the p-type impurity concentration of the gate contact region 27.

[0247] The p-type impurity concentration of the shallow contact region 37 may be approximately equal to the p-type impurity concentration of the source contact region 28. The p-type impurity concentration of the shallow contact region 37 may be higher than the p-type impurity concentration of the source contact region 28, or may be lower than the p-type impurity concentration of the source contact region 28.

[0248] The shallow contact regions 37 are formed in regions along the isolation structures 30 for the shallow well region 35. The shallow contact regions 37 are formed at intervals between each other in the regions between the isolation structures 30, and face each other with part of the second semiconductor region 7 interposed therebetween. The shallow contact regions 37 may be connected to each other in the regions between the isolation structures 30.

[0249] The shallow contact regions 37 are formed at intervals from the gate structures 15 and the source structures 20, respectively. The shallow contact regions 37 are formed in a one-to-one correspondence with the isolation structures 30. The shallow contact regions 37 are interposed in regions between the bottom walls of the corresponding isolation structures 30 and the bottoms of the corresponding shallow well regions 35, respectively, and extend in strips along the corresponding isolation structures 30.

[0250] Each of the shallow contact regions 37 has a portion extending in the first direction X along the corresponding isolation structure 30 in plan view, and a portion extending in the second direction Y along the corresponding isolation structure 30. In this embodiment, each of the shallow contact regions 37 extends in a polygonal ring shape (a square ring shape in this embodiment) along the corresponding isolation structure 30 in plan view.

[0251] The plurality of shallow contact regions 37 may be formed at intervals following the extension direction of the corresponding isolation structures 30. In this case, the plurality of shallow contact regions 37 may each extend in a strip shape following the extension direction of the corresponding isolation structures 30.

[0252] The plurality of shallow contact regions 37 are respectively connected to the bottom walls of the corresponding isolation structures 30 and the corresponding shallow well regions 35. The plurality of shallow contact regions 37 increase the p-type impurity concentration at the upper end portions of the corresponding shallow well regions 35. The plurality of shallow contact regions 37 extend from the regions directly below the isolation structures 30 to both sides of the isolation structures 30, and have extensions that extend along the sidewalls of the corresponding isolation structures 30.

[0253] The thickness in the horizontal direction (first direction X) of the portions (extensions) of the plurality of shallow contact regions 37 that extend along the side walls of the isolation structure 30 may be less than the thickness in the vertical direction Z of the portions of the plurality of shallow contact regions 37 that extend along the bottom walls of the isolation structure 30.

[0254] The extensions of the shallow contact regions 37 are electrically connected to the body region 10 in the surface layer portion of the first main surface 3, and electrically connect the corresponding shallow well regions 35 to the body region 10. This prevents the shallow well regions 35 from being electrically floating, and improves the electrical response characteristics of the shallow well regions 35.

[0255] The plurality of shallow contact regions 37 each have an upper end portion exposed from the first main surface 3. In this embodiment, the upper ends of the plurality of shallow contact regions 37 are exposed from the sidewall of the third trench 31 at the opening end of the third trench 31.

[0256] The upper ends of the shallow contact regions 37 may extend horizontally in the surface layer portion of the body region 10. The upper ends of the shallow contact regions 37 are electrically connected to each other in the body region 10. In this embodiment, the upper ends of the shallow contact regions 37 are integrally formed in the body region 10.

[0257] The semiconductor device 1A includes one or more (one) deep contact regions 38 formed in the chip 2 (second semiconductor region 7). The deep contact region 38 may also be referred to as a "fourth contact region" or the like. A source potential is applied to the deep contact region 38. The deep contact region 38 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the deep contact region 38 is higher than the p-type impurity concentration of the body region 10.

[0258] The p-type impurity concentration of the deep contact region 38 is higher than the p-type impurity concentration of the deep well region 36. The p-type impurity concentration of the deep contact region 38 is higher than the p-type impurity concentration of the shallow well region 35. The p-type impurity concentration of the deep contact region 38 is higher than the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the deep contact region 38 is higher than the p-type impurity concentration of the source well region 26.

[0259] The p-type impurity concentration of the deep contact region 38 may be approximately equal to the p-type impurity concentration of the shallow contact region 37. The p-type impurity concentration of the deep contact region 38 may be higher than the p-type impurity concentration of the shallow contact region 37, or may be lower than the p-type impurity concentration of the shallow contact region 37.

[0260] The p-type impurity concentration of the deep contact region 38 may be approximately equal to the p-type impurity concentration of the gate contact region 27. The p-type impurity concentration of the deep contact region 38 may be higher than the p-type impurity concentration of the gate contact region 27, or may be lower than the p-type impurity concentration of the gate contact region 27.

[0261] The p-type impurity concentration of the deep contact region 38 may be approximately equal to the p-type impurity concentration of the source contact region 28. The p-type impurity concentration of the deep contact region 38 may be higher than the p-type impurity concentration of the source contact region 28, or may be lower than the p-type impurity concentration of the source contact region 28.

[0262] The deep contact region 38 is formed in a region along the isolation structure 30 for the deep well region 36 (in this embodiment, the outermost isolation structure 30). The deep contact region 38 is formed at a distance from the isolation structure 30 for the shallow well region 35.

[0263] The deep contact region 38 is formed at a distance from the outermost shallow contact region 37 in the region between the plurality of isolation structures 30, and faces the outermost shallow contact region 37 across a part of the second semiconductor region 7. The deep contact region 38 may be connected to the outermost shallow contact region 37 in the region between the plurality of isolation structures 30.

[0264] The deep contact regions 38 are formed spaced apart from the plurality of gate structures 15 and the plurality of source structures 20. The deep contact regions 38 are formed in one-to-one correspondence with the corresponding isolation structures 30 (i.e., the outermost isolation structures 30).

[0265] The deep contact region 38 is interposed in a region between the bottom wall of the outermost isolation structure 30 and the bottom of the deep well region 36, and extends in a strip shape along the outermost isolation structure 30. The deep contact region 38 has a portion extending in the first direction X along the outermost isolation structure 30 in a plan view, and a portion extending in the second direction Y along the outermost isolation structure 30. In this embodiment, the deep contact region 38 extends in a polygonal ring shape (a square ring shape in this embodiment) along the outermost isolation structure 30 in a plan view.

[0266] The deep contact regions 38 may be formed at intervals following the extension direction of the outermost isolation structures 30. In this case, the deep contact regions 38 may each extend in a strip shape following the extension direction of the outermost isolation structures 30.

[0267] The deep contact region 38 is connected to the bottom wall of the outermost isolation structure 30 and the deep well region 36. The deep contact region 38 increases the p-type impurity concentration at the top end of the deep well region 36. The deep contact region 38 extends from the region directly below the isolation structure 30 to both sides of the isolation structure 30 and has extensions that extend along the sidewalls of the outermost isolation structure 30.

[0268] The deep contact region 38 has an extension on one side that extends along the sidewall of the outermost isolation structure 30 on the active region 8 side, and an extension on the other side that extends along the sidewall of the outermost isolation structure 30 on the peripheral region 9 side. The thickness in the horizontal direction (first direction X) of the portion (extension) of the deep contact region 38 that extends along the sidewall of the outermost isolation structure 30 may be less than the thickness in the vertical direction Z of the portion of the deep contact region 38 that extends along the bottom wall of the outermost isolation structure 30.

[0269] The extension of the deep contact region 38 is electrically connected to the body region 10 in the surface layer portion of the first main surface 3, and electrically connects the deep well region 36 to the body region 10. This prevents the deep well regions 36 from being electrically floating, and improves the electrical response characteristics of the deep well regions 36.

[0270] The deep contact region 38 has an upper end exposed from the first main surface 3. In this embodiment, the upper end of the deep contact region 38 is exposed from the sidewall of the third trench 31 at the opening end of the third trench 31.

[0271] The upper end of the deep contact region 38 may extend horizontally in the surface layer portion of the body region 10. The upper end of the deep contact region 38 is electrically connected to the shallow contact region 37 in the body region 10. In this embodiment, the upper end of the deep contact region 38 is formed integrally with the shallow contact region 37 in the body region 10.

[0272] 9 and 10 , semiconductor device 1A includes a p-type outer well region 40 formed in a surface layer portion of first main surface 3 in peripheral region 9. A source potential is applied to outer well region 40. Outer well region 40 has a p-type impurity concentration higher than the n-type impurity concentration of second semiconductor region 7.

[0273] The p-type impurity concentration of the outer well region 40 is less than the p-type impurity concentration of the deep contact region 38. The p-type impurity concentration of the outer well region 40 is less than the p-type impurity concentration of the shallow contact region 37. The p-type impurity concentration of the outer well region 40 is less than the p-type impurity concentration of the gate contact region 27. The p-type impurity concentration of the outer well region 40 is less than the p-type impurity concentration of the source contact region 28.

[0274] The p-type impurity concentration of the outer well region 40 may be approximately equal to the p-type impurity concentration of the deep well region 36. The p-type impurity concentration of the outer well region 40 may be higher than the p-type impurity concentration of the deep well region 36, or may be lower than the p-type impurity concentration of the deep well region 36.

[0275] The p-type impurity concentration of the outer well region 40 may be approximately equal to the p-type impurity concentration of the shallow well region 35. The p-type impurity concentration of the outer well region 40 may be higher than the p-type impurity concentration of the shallow well region 35, or may be lower than the p-type impurity concentration of the shallow well region 35.

[0276] The p-type impurity concentration of the outer well region 40 may be approximately equal to the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the outer well region 40 may be higher than the p-type impurity concentration of the gate well region 25, or may be lower than the p-type impurity concentration of the gate well region 25.

[0277] The p-type impurity concentration of the outer well region 40 may be approximately equal to the p-type impurity concentration of the source well region 26. The p-type impurity concentration of the outer well region 40 may be higher than the p-type impurity concentration of the source well region 26, or may be lower than the p-type impurity concentration of the source well region 26.

[0278] The p-type impurity concentration of the outer well region 40 may be approximately equal to the p-type impurity concentration of the body region 10. The p-type impurity concentration of the outer well region 40 may be higher than the p-type impurity concentration of the body region 10, or may be lower than the p-type impurity concentration of the body region 10.

[0279] The outer well region 40 is formed in a region between the periphery of the first main surface 3 and the outermost isolation structure 30 (active region 8). The outer well region 40 is formed in a surface layer portion of the second semiconductor region 7 and is electrically connected to the second semiconductor region 7. The outer well region 40 extends in a layered form along the first main surface 3.

[0280] The outer well region 40 is formed at an interval from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 on the inward side (active region 8 side) of the first main surface 3. The outer well region 40 extends in a strip shape along the outermost isolation structure 30 in plan view. The outer well region 40 has a portion extending in the first direction X along the outermost isolation structure 30 in plan view, and a portion extending in the second direction Y along the outermost isolation structure 30.

[0281] In this embodiment, the outer well region 40 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner portion (active region 8) of the first main surface 3. The outer well region 40 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0282] The outer well region 40 has an inner edge on the outermost isolation structure 30 side (inward of the first main surface 3) and an outer edge on the peripheral side of the first main surface 3. In this embodiment, the inner edge of the outer well region 40 is connected to the outermost isolation structure 30. The inner edge of the outer well region 40 may be formed at a distance from the outermost isolation structure 30 on the peripheral side of the first main surface 3.

[0283] The outer well region 40 is formed at a distance from the bottom of the second semiconductor region 7 toward the first main surface 3, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. The outer well region 40 is preferably formed at a distance from a depth position of the middle part of the second semiconductor region 7 toward the first main surface 3.

[0284] The outer well region 40 has an upper end exposed from the first main surface 3 and a bottom located within the second semiconductor region 7. The bottom of the outer well region 40 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the body region 10. The bottom of the outer well region 40 may be located closer to the first main surface 3 than the depth position of the bottom of the body region 10.

[0285] The bottom of the outer well region 40 is located closer to the first main surface 3 than the depth position of the bottom of the deep well region 36. The bottom of the outer well region 40 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the deep well region 36. The bottom of the outer well region 40 is located closer to the first main surface 3 than the depth position of the bottom of the shallow well region 35. The bottom of the outer well region 40 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the shallow well region 35.

[0286] The bottom of the outer well region 40 is located closer to the first main surface 3 than the depth position of the bottom of the gate well region 25. The bottom of the outer well region 40 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the gate well region 25. The bottom of the outer well region 40 is located closer to the first main surface 3 than the depth position of the bottom of the source well region 26. The bottom of the outer well region 40 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the source well region 26.

[0287] The bottom of the outer well region 40 is located closer to the first main surface 3 than the depth position of the bottom wall of the isolation structure 30. The bottom of the outer well region 40 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the isolation structure 30. The bottom of the outer well region 40 is located closer to the first main surface 3 than the depth position of the bottom wall of the gate structure 15. The bottom of the outer well region 40 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the gate structure 15.

[0288] The bottom of the outer well region 40 is located on the first main surface 3 side with respect to the depth position of the bottom wall of the source structure 20. The bottom of the outer well region 40 may be located on the bottom side of the second semiconductor region 7 with respect to the depth position of the bottom wall of the source structure 20.

[0289] In this embodiment, the outer well region 40 is formed at a distance from the depth position of the upper end of the deep well region 36 toward the first main surface 3 , and does not have a direct connection to the deep well region 36 .

[0290] When the bottom of the outer well region 40 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the isolation structure 30, the outer well region 40 may have a portion connected to the deep well region 36. The bottom of the outer well region 40 may be connected to the upper end of the deep well region 36.

[0291] The outer well region 40 has a width greater than the width of the deep well region 36. The width of the outer well region 40 is greater than the width of the outermost isolation structure 30. The width of the outer well region 40 may be greater than the total width of the multiple isolation structures 30. The width of the outer well region 40 may be greater than the total width of the multiple shallow well regions 35 and the deep well region 36.

[0292] The width of the outer well region 40 may be greater than 0 μm and less than 300 μm. The width of the outer well region 40 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, 175 μm to 200 μm, 200 μm to 225 μm, 225 μm to 250 μm, 250 μm to 275 μm, and 275 μm to 300 μm.

[0293] The depth (thickness) of the outer well region 40 may be greater than 0 μm and less than 5 μm. The depth of the outer well region 40 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0294] The outer well region 40 forms a pn junction with the second semiconductor region 7. The outer well region 40 spreads a depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer originating in the outer well region 40 spreads in the horizontal and thickness directions and merges with the depletion layer originating in the deep well region 36. The outer well region 40 expands the depletion layer originating in the deep well region 36 toward the periphery of the first main surface 3, thereby alleviating the electric field in the periphery (outer peripheral region 9) of the first main surface 3.

[0295] The semiconductor device 1A includes a p-type outer contact region 41 formed in the outer peripheral region 9 in a surface layer portion of the first main surface 3. A source potential is applied to the outer contact region 41. The outer contact region 41 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the outer contact region 41 is higher than the p-type impurity concentration of the body region 10.

[0296] The p-type impurity concentration of the outer contact region 41 is higher than the p-type impurity concentration of the deep well region 36. The p-type impurity concentration of the outer contact region 41 is higher than the p-type impurity concentration of the shallow well region 35. The p-type impurity concentration of the outer contact region 41 is higher than the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the outer contact region 41 is higher than the p-type impurity concentration of the source well region 26.

[0297] The p-type impurity concentration of the outer contact region 41 may be approximately equal to the p-type impurity concentration of the deep contact region 38. The p-type impurity concentration of the outer contact region 41 may be higher than the p-type impurity concentration of the deep contact region 38, or may be lower than the p-type impurity concentration of the deep contact region 38.

[0298] The p-type impurity concentration of the outer contact region 41 may be approximately equal to the p-type impurity concentration of the shallow contact region 37. The p-type impurity concentration of the outer contact region 41 may be higher than the p-type impurity concentration of the shallow contact region 37, or may be lower than the p-type impurity concentration of the shallow contact region 37.

[0299] The p-type impurity concentration of the outer contact region 41 may be approximately equal to the p-type impurity concentration of the gate contact region 27. The p-type impurity concentration of the outer contact region 41 may be higher than the p-type impurity concentration of the gate contact region 27, or may be lower than the p-type impurity concentration of the gate contact region 27.

[0300] The p-type impurity concentration of the outer contact region 41 may be approximately equal to the p-type impurity concentration of the source contact region 28. The p-type impurity concentration of the outer contact region 41 may be higher than the p-type impurity concentration of the source contact region 28, or may be lower than the p-type impurity concentration of the source contact region 28.

[0301] The outer contact region 41 is formed in the surface layer portion of the outer well region 40. In other words, the outer contact region 41 is formed in a thickness range between the first main surface 3 and the bottom of the outer well region 40. The outer contact region 41 increases the p-type impurity concentration of the outer well region 40, and improves the electrical response speed of the outer well region 40.

[0302] The outer contact region 41 extends in a strip shape along the outermost isolation structure 30 (outer well region 40) in plan view. The outer contact region 41 has a portion extending in the first direction X along the outermost isolation structure 30 in plan view, and a portion extending in the second direction Y along the outermost isolation structure 30.

[0303] In this embodiment, the outer contact region 41 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner portion (the outermost isolation structure 30) of the first main surface 3. The outer contact region 41 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0304] The outer contact regions 41 may be formed at intervals in the extension direction of the outermost isolation structure 30. In this case, the outer contact regions 41 may each extend in a strip shape in the extension direction of the corresponding isolation structure 30.

[0305] The outer contact region 41 has a width less than that of the outer well region 40, and is formed within the outer well region 40. The outer contact region 41 has an inner edge portion on the inner side of the first main surface 3 (on the active region 8 side) and an outer edge portion on the peripheral side of the first main surface 3.

[0306] In this embodiment, the inner edge of the outer contact region 41 is connected to the outermost isolation structure 30. In this embodiment, the inner edge of the outer contact region 41 is connected to the deep contact region 38 along the outermost isolation structure 30. The outer well region 40 is electrically connected to the body region 10 via the deep contact region 38. The outer well region 40 may be formed spaced apart from the deep contact region 38 (the outermost isolation structure 30).

[0307] The outer edge of the outer contact region 41 is formed at a distance from the outer edge of the outer well region 40 toward the outermost isolation structure 30. The outer contact region 41 may have a portion that crosses the outer edge of the outer well region 40 and is connected to the second semiconductor region 7.

[0308] The outer contact region 41 has a width greater than the width of the deep well region 36. The width of the outer contact region 41 is greater than the width of the outermost isolation structure 30. The width of the outer contact region 41 may be greater than the total width of the multiple isolation structures 30. The width of the outer contact region 41 may be greater than the total width of the multiple shallow well regions 35 and the deep well region 36. The width of the outer contact region 41 may be less than the width of the outer well region 40. The width of the outer contact region 41 may be greater than the width of the outer well region 40.

[0309] The width of the outer contact region 41 may be greater than 0 μm and less than 300 μm. The width of the outer contact region 41 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, 175 μm to 200 μm, 200 μm to 225 μm, 225 μm to 250 μm, 250 μm to 275 μm, and 275 μm to 300 μm.

[0310] The outer contact region 41 has an upper end located on the first main surface 3 side and a bottom located on the bottom side of the outer well region 40. The upper end of the outer contact region 41 is exposed from the first main surface 3.

[0311] The bottom of the outer contact region 41 is located closer to the first main surface 3 than the depth position of the bottom of the deep well region 36. The bottom of the outer well region 40 is located closer to the first main surface 3 than the depth position of the bottom of the shallow well region 35.

[0312] The bottom of the outer well region 40 is located closer to the first main surface 3 than the depth position of the bottom of the gate well region 25. The bottom of the outer well region 40 is located closer to the first main surface 3 than the depth position of the bottom of the source well region 26.

[0313] The bottom of the outer well region 40 is located on the first main surface 3 side relative to the depth position of the bottom wall of the isolation structure 30. The bottom of the outer well region 40 is located on the first main surface 3 side relative to the depth position of the bottom wall of the gate structure 15. The bottom of the outer well region 40 is located on the first main surface 3 side relative to the depth position of the bottom wall of the source structure 20.

[0314] The bottom of the outer contact region 41 is located closer to the first main surface 3 than the depth position of the bottom of the outer well region 40. The bottom of the outer well region 40 may be located closer to the first main surface 3 than the depth position of the bottom of the body region 10, or may be located closer to the bottom of the outer well region 40.

[0315] The bottom of the outer contact region 41 may be located at a depth substantially equal to the bottom of the upper end of the deep contact region 38. The bottom of the outer contact region 41 may be located closer to the first main surface 3 than the depth position of the bottom of the upper end of the deep contact region 38, or may be located closer to the bottom of the deep contact region 38.

[0316] The bottom of the outer contact region 41 may be located at a depth substantially equal to the bottom of the upper end of the shallow contact region 37. The bottom of the outer contact region 41 may be located closer to the first main surface 3 than the depth position of the bottom of the upper end of the shallow contact region 37, or may be located closer to the bottom of the shallow contact region 37.

[0317] The bottom of the outer contact region 41 may be located at a depth substantially equal to the bottom of the upper end of the gate contact region 27. The bottom of the outer contact region 41 may be located closer to the first main surface 3 than the depth position of the bottom of the upper end of the gate contact region 27, or may be located closer to the bottom of the gate contact region 27.

[0318] The bottom of the outer contact region 41 may be located at a depth substantially equal to the depth of the bottom of the upper end of the source contact region 28. The bottom of the outer contact region 41 may be located closer to the first main surface 3 than the depth position of the bottom of the upper end of the source contact region 28, or may be located closer to the bottom of the source contact region 28.

[0319] The depth (thickness) of the outer contact region 41 may be greater than 0 μm and less than or equal to 1 μm. The depth of the outer contact region 41 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.3 μm, 0.3 μm to 0.4 μm, 0.4 μm to 0.5 μm, 0.5 μm to 0.6 μm, 0.6 μm to 0.7 μm, 0.7 μm to 0.8 μm, 0.8 μm to 0.9 μm, and 0.9 μm to 1 μm.

[0320] The semiconductor device 1A includes a p-type termination region 42 formed in the outer periphery region 9 in a surface layer portion of the first main surface 3. The termination region 42 may also be referred to as a "termination well region" or a "JTE region (Junction Termination Extension region)." A source potential is applied to the termination region 42. The termination region 42 has a p-type impurity concentration that is higher than the n-type impurity concentration of the second semiconductor region 7.

[0321] The p-type impurity concentration of the termination region 42 may be lower than the p-type impurity concentration of the deep contact region 38. The p-type impurity concentration of the termination region 42 may be lower than the p-type impurity concentration of the shallow contact region 37. The p-type impurity concentration of the termination region 42 may be lower than the p-type impurity concentration of the gate contact region 27. The p-type impurity concentration of the termination region 42 may be lower than the p-type impurity concentration of the source contact region 28.

[0322] The p-type impurity concentration of the termination region 42 may be higher than or lower than the p-type impurity concentration of the outer well region 40. The p-type impurity concentration of the termination region 42 may be higher than or lower than the p-type impurity concentration of the deep well region 36. The p-type impurity concentration of the termination region 42 may be higher than or lower than the p-type impurity concentration of the shallow well region 35.

[0323] The p-type impurity concentration of the termination region 42 may be higher than or lower than the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the termination region 42 may be higher than or lower than the p-type impurity concentration of the source well region 26. The p-type impurity concentration of the termination region 42 may be higher than or lower than the p-type impurity concentration of the body region 10.

[0324] The termination region 42 is formed in a region between the periphery of the first main surface 3 and the outermost isolation structure 30 (active region 8). Specifically, the termination region 42 is formed in a region between the periphery of the first main surface 3 and the outer well region 40. The termination region 42 extends in a band shape along the outermost isolation structure 30 (outer well region 40) in a plan view.

[0325] The termination region 42 has a portion extending in the first direction X and a portion extending in the second direction Y. In this embodiment, the termination region 42 is formed in a polygonal ring shape (a square ring in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the outermost isolation structure 30 (outer well region 40).

[0326] The termination region 42 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape). A plurality of termination regions 42 may be formed at intervals following the extension direction of the outermost isolation structure 30. In this case, the plurality of termination regions 42 may each extend in a strip shape following the extension direction of the outermost isolation structure 30.

[0327] The termination region 42 has a width greater than the width of the deep well region 36. The width of the termination region 42 is greater than the width of the outermost isolation structure 30. The width of the termination region 42 may be greater than the total width of the multiple isolation structures 30. The width of the termination region 42 may be greater than the total width of the multiple shallow well regions 35 and the deep well region 36. The width of the termination region 42 may be greater than the width of the outer well region 40. The width of the termination region 42 may be less than the width of the outer well region 40.

[0328] The width of termination region 42 may be greater than 0 μm and less than or equal to 300 μm. The width of termination region 42 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, 175 μm to 200 μm, 200 μm to 225 μm, 225 μm to 250 μm, 250 μm to 275 μm, and 275 μm to 300 μm.

[0329] The ratio (width ratio) of the width of the termination region 42 to the width of the outer well region 40 may be 0.5 or more and 5 or less. The width ratio may have a value belonging to any one of the following ranges: 0.5 to 0.75, 0.75 to 1, 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, 2.75 to 3, 4 to 4.25, 4.25 to 4.5, 4.5 to 4.75, and 4.75 to 5 or less.

[0330] The termination region 42 is formed in a surface layer portion of the second semiconductor region 7 and is electrically connected to the second semiconductor region 7. The termination region 42 is formed at a distance from the bottom of the second semiconductor region 7 toward the first main surface 3, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. The termination region 42 is preferably formed at a distance from a depth position in the middle of the second semiconductor region 7 toward the first main surface 3.

[0331] The termination region 42 is formed at a distance from the first main surface 3 in the thickness direction of the chip 2. In other words, the termination region 42 is formed at a distance from the first main surface 3 to the bottom side of the second semiconductor region 7, and has a portion facing the first main surface 3 with a part of the second semiconductor region 7 in between.

[0332] The distance between first main surface 3 and termination region 42 may be greater than 0 μm and less than or equal to 3 μm. The distance may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.5 μm, and 2.5 μm to 3 μm.

[0333] The termination region 42 has an upper end located on the first main surface 3 side and a bottom located on the bottom side of the second semiconductor region 7. The upper end of the termination region 42 extends horizontally along the first main surface 3 and forms a pn junction with the second semiconductor region 7. The upper end of the termination region 42 is located on the first main surface 3 side with respect to the depth position of the bottom of the outer well region 40. The upper end of the termination region 42 is located on the bottom side of the outer well region 40 with respect to the depth position of the bottom of the outer contact region 41.

[0334] The upper end of the termination region 42 is located closer to the first main surface 3 than the depth position of the bottom of the deep well region 36. The upper end of the termination region 42 is located closer to the first main surface 3 than the depth position of the bottom of the shallow well region 35. The upper end of the termination region 42 is located closer to the first main surface 3 than the depth position of the bottom of the gate well region 25. The upper end of the termination region 42 is located closer to the first main surface 3 than the depth position of the bottom of the source well region 26.

[0335] The upper end of the termination region 42 is located closer to the first main surface 3 than the depth position of the bottom wall of the isolation structure 30. The upper end of the termination region 42 is located closer to the first main surface 3 than the depth position of the bottom wall of the gate structure 15. The upper end of the termination region 42 is located closer to the first main surface 3 than the depth position of the bottom wall of the source structure 20. The upper end of the termination region 42 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the body region 10, or may be located closer to the first main surface 3 than the depth position of the bottom of the body region 10.

[0336] The bottom of termination region 42 extends horizontally along first main surface 3 and forms a pn junction with second semiconductor region 7. The bottom of termination region 42 may be located on the bottom side of second semiconductor region 7 relative to the depth position of the bottom of outer well region 40, or may be located on the first main surface 3 side relative to the depth position of the bottom of outer well region 40.

[0337] The bottom of the termination region 42 is located closer to the first main surface 3 than the depth position of the bottom of the deep well region 36. The bottom of the termination region 42 is located closer to the first main surface 3 than the depth position of the bottom of the shallow well region 35. The bottom of the termination region 42 is located closer to the first main surface 3 than the depth position of the bottom of the gate well region 25. The bottom of the termination region 42 is located closer to the first main surface 3 than the depth position of the bottom of the source well region 26.

[0338] The bottom of termination region 42 may be located closer to first main surface 3 than the depth position of the bottom wall of isolation structure 30. The bottom of termination region 42 may be located closer to the bottom of second semiconductor region 7 than the depth position of the bottom wall of isolation structure 30.

[0339] The bottom of termination region 42 may be located on the first main surface 3 side with respect to the depth position of the bottom wall of gate structure 15, or may be located on the bottom side of second semiconductor region 7 with respect to the depth position of the bottom wall of gate structure 15. The bottom of termination region 42 may be located on the first main surface 3 side with respect to the depth position of the bottom wall of source structure 20, or may be located on the bottom side of second semiconductor region 7 with respect to the depth position of the bottom wall of source structure 20.

[0340] Termination region 42 may have a depth (thickness) that is greater than the distance between first major surface 3 and termination region 42. The depth of termination region 42 is the distance between the top end of termination region 42 and the bottom of termination region 42. The depth of termination region 42 may be less than the distance between first major surface 3 and termination region 42.

[0341] The depth of the termination region 42 may be smaller than the distance between the bottom of the second semiconductor region 7 and the termination region 42. The depth of the termination region 42 may be larger than the distance between the bottom of the second semiconductor region 7 and the termination region 42. The depth of the termination region 42 is preferably smaller than the depth of the outer well region 40. The depth of the termination region 42 may be larger than the depth of the outer well region 40.

[0342] The depth (thickness) of termination region 42 may be greater than 0 μm and less than or equal to 4 μm. The depth of termination region 42 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, and 3.5 μm to 4 μm.

[0343] Termination region 42 has an inner edge on the outermost isolation structure 30 (outer well region 40) side and an outer edge on the peripheral side of first main surface 3. The electric field (depletion layer) formed in the vicinity of outermost isolation structure 30 can be adjusted by adjusting the location of the inner edge of termination region 42.

[0344] The inner edge of the termination region 42 is connected to at least the outer edge of the outer well region 40. The inner edge of the termination region 42 may be located closer to the outermost isolation structure 30 than the middle part of the outer well region 40. The inner edge of the termination region 42 may be located closer to the outer edge of the outer well region 40 than the middle part of the outer well region 40.

[0345] The inner edge of the termination region 42 may be located in a region between the outer edge of the outer well region 40 and the outer edge of the outer contact region 41. The inner edge of the termination region 42 may be located closer to the inner edge of the outer well region 40 than the outer edge of the outer contact region 41.

[0346] The inner edge of the termination region 42 may be connected to the outermost isolation structure 30. The inner edge of the termination region 42 may be formed with a gap between the outermost isolation structure 30 (the inner edge of the outer well region 40) and the outer edge of the outer well region 40. In this case, the inner edge of the termination region 42 may have a portion connected to the deep contact region 38. The inner edge of the termination region 42 may have a portion connected to the deep well region 36.

[0347] In this embodiment, the inner edge of the termination region 42 is connected to the outer edge of the outer well region 40 in a region closer to the bottom of the outer well region 40 than the depth position of the middle part of the outer well region 40. As a result, the termination region 42 is electrically connected to the body region 10 and the outer contact region 41 via the outer well region 40.

[0348] The inner edge of the termination region 42 may be formed at a distance from the bottom of the outer contact region 41 toward the bottom of the outer well region 40, and may face the outer contact region 41 across a part of the outer well region 40. The inner edge of the termination region 42 may be connected to the outer contact region 41.

[0349] The connection (overlap) between the outer edge of the outer well region 40 and the inner edge of the termination region 42 contains the p-type impurities of the outer well region 40 and the p-type impurities of the termination region 42. Therefore, the connection (overlap) has a p-type impurity concentration that is higher than both the p-type impurity concentration of the outer well region 40 and the p-type impurity concentration of the termination region 42.

[0350] The termination region 42 expands the depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer originating in the termination region 42 expands in the horizontal and thickness directions and merges with the depletion layer originating in the outer well region 40 (deep well region 36). The termination region 42 expands the depletion layer originating in the outer well region 40 (deep well region 36) toward the periphery of the first main surface 3, thereby alleviating the electric field in the periphery (outer peripheral region 9) of the first main surface 3.

[0351] The semiconductor device 1A includes at least one p-type field region 43 formed in the surface layer of the first main surface 3 in the peripheral region 9 (the peripheral portion of the first main surface 3). The field region 43 may also be referred to as a "guard region," a "field limit region," or the like. The field region 43 is formed in an electrically floating state. A source potential may be applied to the field region 43.

[0352] The number of field regions 43 is arbitrary. The number of field regions 43 may be 1 or more and 15 or less. The number of field regions 43 may be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15. The number of field regions 43 is typically 1 or more and 10 or less. In this embodiment, the semiconductor device 1A includes, as an example, six field regions 43.

[0353] Field region 43 has a p-type impurity concentration higher than the n-type impurity concentration of second semiconductor region 7. The p-type impurity concentration of field region 43 may be approximately equal to the p-type impurity concentration of termination region 42. The p-type impurity concentration of field region 43 may be higher than the p-type impurity concentration of termination region 42, or may be lower than the p-type impurity concentration of termination region 42.

[0354] The p-type impurity concentration of the field region 43 may be lower than the p-type impurity concentration of the deep contact region 38. The p-type impurity concentration of the field region 43 may be lower than the p-type impurity concentration of the shallow contact region 37. The p-type impurity concentration of the field region 43 may be lower than the p-type impurity concentration of the gate contact region 27. The p-type impurity concentration of the field region 43 may be lower than the p-type impurity concentration of the source contact region 28.

[0355] The p-type impurity concentration of the field region 43 may be higher than or lower than the p-type impurity concentration of the outer well region 40. The p-type impurity concentration of the field region 43 may be higher than or lower than the p-type impurity concentration of the deep well region 36. The p-type impurity concentration of the field region 43 may be higher than or lower than the p-type impurity concentration of the shallow well region 35.

[0356] The p-type impurity concentration of the field region 43 may be higher than or lower than the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the field region 43 may be higher than or lower than the p-type impurity concentration of the source well region 26. The p-type impurity concentration of the field region 43 may be higher than or lower than the p-type impurity concentration of the body region 10.

[0357] In this embodiment, the p-type impurity concentrations of the multiple field regions 43 are approximately equal to each other. The p-type impurity concentrations of the multiple field regions 43 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The p-type impurity concentrations of the multiple field regions 43 may also be different from each other.

[0358] The p-type impurity concentrations of the plurality of field regions 43 may increase sequentially toward the periphery of the first main surface 3. The p-type impurity concentrations of the plurality of field regions 43 may increase toward the periphery of the first main surface 3 in units of two or more groups, each group including two or more field regions 43.

[0359] The p-type impurity concentrations of the plurality of field regions 43 may decrease in order toward the periphery of the first main surface 3. The p-type impurity concentrations of the plurality of field regions 43 may decrease toward the periphery of the first main surface 3 in units of two or more groups, each group including two or more field regions 43.

[0360] The plurality of field regions 43 are formed at intervals in the region between the periphery of the first main surface 3 and the outermost isolation structure 30 (active region 8). The plurality of field regions 43 are formed at intervals in the region between the periphery of the first main surface 3 and the outer well region 40. The plurality of field regions 43 are formed at intervals in the region between the periphery of the first main surface 3 and the termination region 42.

[0361] The plurality of field regions 43 are formed in a surface layer portion of the second semiconductor region 7 and are electrically connected to the second semiconductor region 7. The plurality of field regions 43 extend in a strip shape along the outermost isolation structure 30 (termination region 42) in a plan view.

[0362] The plurality of field regions 43 have portions extending in the first direction X and portions extending in the second direction Y. In this embodiment, the plurality of field regions 43 are formed in a polygonal ring shape (a square ring in this embodiment) having four sides parallel to the periphery of the chip 2 in plan view, and surround the outermost isolation structure 30 (active region 8).

[0363] The plurality of field regions 43 may have edge portions that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape). The plurality of field regions 43 may be formed at intervals following the extension direction of the outermost isolation structure 30. In this case, the plurality of field regions 43 may each extend in a strip shape following the extension direction of the outermost isolation structure 30.

[0364] The field regions 43 may have a width that is less than the width of the outer well region 40. The field regions 43 may have a width that is smaller than the width of the termination region 42. The field regions 43 may have a width that is smaller than the width of the deep well region 36 or may have a width that is larger than the width of the deep well region 36.

[0365] The width of the plurality of field regions 43 may be smaller than the width of the shallow well region 35 or may be larger than the width of the shallow well region 35. The width of the plurality of field regions 43 may be larger than the width of the isolation structure 30 or may be smaller than the width of the isolation structure 30.

[0366] In this embodiment, the widths of the field regions 43 are approximately equal to each other. The widths of the field regions 43 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The widths of the field regions 43 may also be different from each other.

[0367] The widths of the field regions 43 may increase sequentially toward the periphery of the first main surface 3. The widths of the field regions 43 may increase toward the periphery of the first main surface 3 in units of two or more groups, each group including two or more field regions 43.

[0368] The widths of the field regions 43 may decrease sequentially toward the periphery of the first main surface 3. The widths of the field regions 43 may decrease toward the periphery of the first main surface 3 in units of two or more groups, each group including two or more field regions 43.

[0369] The width of field region 43 may be greater than 0 μm and less than or equal to 5 μm. The width of field region 43 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0370] The spacing between the multiple field regions 43 may be equal to or less than the width of the field region 43. The spacing between the multiple field regions 43 is preferably less than the width of the field region 43. The spacing between the multiple field regions 43 may be greater than the width of the field region 43.

[0371] In this embodiment, the spacing between the multiple field regions 43 is approximately equal to one another. The spacing between the multiple field regions 43 is arbitrary and can take various values ​​depending on the electric field to be relaxed. The spacing between the multiple field regions 43 may also be different from one another.

[0372] The spacing between the multiple field regions 43 may increase sequentially toward the periphery of the first main surface 3. The spacing between the multiple field regions 43 may increase toward the periphery of the first main surface 3 in units of two or more groups, each group including two or more field regions 43.

[0373] The spacing between the multiple field regions 43 may decrease sequentially toward the periphery of the first main surface 3. The spacing between the multiple field regions 43 may decrease toward the periphery of the first main surface 3 in units of two or more groups, each group including two or more field regions 43.

[0374] The spacing between field regions 43 may be greater than 0 μm and less than 5 μm. The spacing may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0375] The ratio of the spacing of field regions 43 to the width of field regions 43 (spacing ratio) may be 0.1 or greater and 5 or less. The spacing ratio may have a value belonging to at least one of the ranges of 0.1 or greater and 0.5 or less, 0.5 or greater and 1 or less, 1 or greater and 1.5 or less, 1.5 or greater and 2 or less, 2 or greater and 2.5 or less, 2.5 or greater and 3 or less, 3 or greater and 3.5 or less, 3.5 or greater and 4 or less, 4 or greater and 4.5 or less, and 4.5 or greater and 5 or less.

[0376] The plurality of field regions 43 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 across a part of the second semiconductor region 7. The plurality of field regions 43 are preferably formed at intervals from a depth position at the middle of the second semiconductor region 7 toward the first main surface 3.

[0377] The plurality of field regions 43 are formed at intervals from the first main surface 3 in the thickness direction of the chip 2. In other words, the plurality of field regions 43 are formed at intervals from the first main surface 3 toward the bottom of the second semiconductor region 7, and have portions that face the first main surface 3 with part of the second semiconductor region 7 in between. The plurality of field regions 43 are each formed in a depth range between the top end and bottom of the termination region 42, and face the termination region 42 in the horizontal direction.

[0378] The distance between the first major surface 3 and the field region 43 is preferably approximately equal to the distance between the first major surface 3 and the termination region 42. The distance between the first major surface 3 and the field region 43 may be greater than the distance between the first major surface 3 and the termination region 42, or may be smaller than the distance between the first major surface 3 and the termination region 42.

[0379] The distance between first main surface 3 and field region 43 may be greater than 0 μm and less than 3 μm. The distance may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.5 μm, and 2.5 μm to 3 μm.

[0380] Each of the field regions 43 has an upper end located on the first major surface 3 side and a bottom located on the bottom side of the second semiconductor region 7. The upper ends of the field regions 43 extend horizontally along the first major surface 3 and form pn junctions with the second semiconductor regions 7.

[0381] The upper ends of the plurality of field regions 43 are positioned at a depth substantially equal to that of the upper end of the termination region 42. The upper ends of the plurality of field regions 43 may be positioned closer to the first main surface 3 than the depth position of the upper end of the termination region 42, or may be positioned closer to the bottom of the second semiconductor region 7 than the depth position of the upper end of the termination region 42.

[0382] The upper ends of the plurality of field regions 43 are located closer to the first main surface 3 than the depth position of the bottom of the outer well region 40. The upper ends of the plurality of field regions 43 are located closer to the bottom of the outer well region 40 than the depth position of the bottom of the outer contact region 41.

[0383] The upper ends of the plurality of field regions 43 are located closer to the first main surface 3 than the depth position of the bottom of the deep well region 36. The upper ends of the plurality of field regions 43 are located closer to the first main surface 3 than the depth position of the bottom of the shallow well region 35. The upper ends of the plurality of field regions 43 are located closer to the first main surface 3 than the depth position of the bottom of the gate well region 25. The upper ends of the plurality of field regions 43 are located closer to the first main surface 3 than the depth position of the bottom of the source well region 26.

[0384] The upper ends of the plurality of field regions 43 are located closer to the first main surface 3 than the depth position of the bottom wall of the isolation structure 30. The upper ends of the plurality of field regions 43 are located closer to the first main surface 3 than the depth position of the bottom wall of the gate structure 15. The upper ends of the plurality of field regions 43 are located closer to the first main surface 3 than the depth position of the bottom wall of the source structure 20.

[0385] In this embodiment, the upper ends of the plurality of field regions 43 are located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the body region 10. The upper ends of the plurality of field regions 43 may also be located closer to the first main surface 3 than the depth position of the bottom of the body region 10.

[0386] The bottoms of the plurality of field regions 43 extend horizontally along the first major surface 3 and form pn junctions with the second semiconductor region 7. The bottoms of the plurality of field regions 43 are located at a depth substantially equal to that of the bottom of the termination region 42. The bottoms of the plurality of field regions 43 may be located closer to the first major surface 3 than the depth position of the bottom of the termination region 42, or may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the termination region 42.

[0387] The bottoms of the plurality of field regions 43 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the outer well region 40. The bottoms of the plurality of field regions 43 may be located closer to the first main surface 3 than the depth position of the bottom of the outer well region 40.

[0388] The bottoms of the plurality of field regions 43 are located closer to the first main surface 3 than the depth position of the bottom of the deep well region 36. The bottoms of the plurality of field regions 43 are located closer to the first main surface 3 than the depth position of the bottom of the shallow well region 35. The bottoms of the plurality of field regions 43 are located closer to the first main surface 3 than the depth position of the bottom of the gate well region 25. The bottoms of the plurality of field regions 43 are located closer to the first main surface 3 than the depth position of the bottom of the source well region 26.

[0389] The bottoms of the plurality of field regions 43 may be located closer to the first main surface 3 than the depth position of the bottom wall of the isolation structure 30. The bottoms of the plurality of field regions 43 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the isolation structure 30.

[0390] The bottoms of the plurality of field regions 43 may be located closer to the first main surface 3 than the depth position of the bottom wall of the gate structure 15. The bottoms of the plurality of field regions 43 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the gate structure 15. The bottoms of the plurality of field regions 43 may be located closer to the first main surface 3 than the depth position of the bottom wall of the source structure 20. The bottoms of the plurality of field regions 43 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the source structure 20.

[0391] Field region 43 may have a depth (thickness) approximately equal to the depth (thickness) of termination region 42. The depth of field region 43 is the distance between the top and bottom of field region 43. The depth of field region 43 may be greater than the depth of termination region 42 or may be less than the depth of termination region 42.

[0392] The depth of field region 43 may be greater than the distance between first main surface 3 and field region 43. The depth of field region 43 may be less than the distance between first main surface 3 and field region 43. The depth of field region 43 may be less than the distance between the bottom of second semiconductor region 7 and field region 43. The depth of field region 43 may be greater than the distance between the bottom of second semiconductor region 7 and field region 43.

[0393] In this embodiment, the depths of the field regions 43 are approximately equal to each other. The depths of the field regions 43 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The depths of the field regions 43 may also be different from each other.

[0394] The depths of the field regions 43 may increase sequentially toward the periphery of the first main surface 3. The depths of the field regions 43 may increase toward the periphery of the first main surface 3 in units of two or more groups, each group including two or more field regions 43.

[0395] The depths of the field regions 43 may decrease sequentially toward the periphery of the first main surface 3. The depths of the field regions 43 may decrease toward the periphery of the first main surface 3 in units of two or more groups, each group including two or more field regions 43.

[0396] The depth of field region 43 may be greater than 0 μm and less than or equal to 4 μm. The depth of termination region 42 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, and 3.5 μm to 4 μm.

[0397] The multiple field regions 43 expand the depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer originating from the multiple field regions 43 expands in the horizontal and thickness directions and merges with the depletion layer originating from the termination region 42 (deep well region 36). The multiple field regions 43 expand the depletion layer originating from the termination region 42 (deep well region 36) toward the periphery of the first main surface 3, thereby alleviating the electric field in the periphery (outer peripheral region 9) of the first main surface 3.

[0398] The semiconductor device 1A includes a main surface insulating film 45 that selectively covers the first main surface 3. The main surface insulating film 45 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The main surface insulating film 45 preferably includes the same type of insulating material as at least one of the insulating materials of the first insulating film 17, the second insulating film 22, and the third insulating film 32. In this embodiment, the main surface insulating film 45 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 45 include a silicon oxide film made of an oxide of the chip 2.

[0399] The main surface insulating film 45 is selectively connected to the first insulating film 17 of the plurality of gate structures 15, the second insulating film 22 of the plurality of source structures 20, and the third insulating film 32 of the plurality of isolation structures 30 in the active region 8, and exposes the first buried electrodes 18 of the plurality of gate structures 15, the second buried electrodes 23 of the plurality of source structures 20, and the third buried electrodes 33 of the plurality of isolation structures 30.

[0400] The main surface insulating film 45 covers the second semiconductor region 7, the outer well region 40, and the outer contact region 41 in the peripheral region 9. In this embodiment, the main surface insulating film 45 is continuous with the first to fourth side surfaces 5A to 5D in the peripheral portion of the first main surface 3. The main surface insulating film 45 may be formed at a distance inward from the peripheral portion of the first main surface 3, exposing the peripheral portion of the first main surface 3 (the second semiconductor region 7).

[0401] The semiconductor device 1A includes an outer wiring 46 disposed on a main surface insulating film 45 in the peripheral region 9. The outer wiring 46 may also be referred to as a "wiring," "main surface wiring," "peripheral wiring," "side wiring," or the like. The outer wiring 46 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The outer wiring 46 preferably has the same type of conductive material (conductivity type) as at least one of the first buried electrode 18, the second buried electrode 23, and the third buried electrode 33.

[0402] The outer wiring 46 is arranged in the peripheral region 9 at a distance from the periphery of the first main surface 3 toward the active region 8. The outer wiring 46 is arranged on the outer well region 40 and faces the outer well region 40 with the main surface insulating film 45 interposed therebetween.

[0403] The outer wiring 46 extends in a strip shape along the periphery of the first main surface 3 (the periphery of the active region 8) in the same direction as the outer well region 40 in a plan view. The outer wiring 46 has a portion extending in the first direction X and a portion extending in the second direction Y.

[0404] In this embodiment, the outer wiring 46 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner portion (active region 8) of the first main surface 3. The outer wiring 46 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape). The outer wiring 46 may be either terminated or endless.

[0405] The outer wiring 46 has an inner edge portion on the inner side (active region 8 side) of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer wiring 46 is drawn out from the outer periphery region 9 into the active region 8. The inner edge portion of the outer wiring 46 covers one or more isolation structures 30 and is connected to one or more isolation structures 30.

[0406] In this embodiment, the inner edge of the outer wiring 46 covers the outermost isolation structure 30 and is connected to the third buried electrode 33 of the outermost isolation structure 30. In this embodiment, the outer wiring 46 is formed at a distance from the plurality of isolation structures 30 for the shallow well region 35 toward the outer periphery region 9. Therefore, the outer wiring 46 is not electrically connected to the plurality of isolation structures 30 for the shallow well region 35.

[0407] The outer wiring 46 may be connected to at least one or all of the plurality of isolation structures 30 for the shallow well region 35. The outer wiring 46 is formed integrally with the third buried electrode 33 of the isolation structure 30. In other words, the outer wiring 46 is formed as an extension portion of the third buried electrode 33, and is routed over the main surface insulating film 45. The outer wiring 46 faces the deep well region 36 with the outermost isolation structure 30 interposed therebetween.

[0408] The outer edge of outer wiring 46 is formed at a distance inward (toward active region 8) from the innermost field region 43 of the plurality of field regions 43. In other words, the outer edge of outer wiring 46 does not face the plurality of field regions 43 across main surface insulating film 45. With this configuration, the outer wiring 46 is prevented from blocking the electric field dispersion path in the region above the plurality of field regions 43, and the plurality of field regions 43 appropriately distributes the electric field (electric force lines).

[0409] The outer edge of the outer wiring 46 is formed at a distance inward from the outer edge of the termination region 42. In this embodiment, the outer edge of the outer wiring 46 is disposed at a distance inward from the outer edge of the outer contact region 41, and has a portion facing the outer contact region 41 across the main surface insulating film 45. The outer edge of the outer wiring 46 may have a portion facing the termination region 42 in the stacking direction.

[0410] The semiconductor device 1A includes an insulating interlayer film 47 that selectively covers the first main surface 3 with the main surface insulating film 45 sandwiched therebetween. The interlayer film 47 may also be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer film 47 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 47 preferably includes a silicon oxide film.

[0411] The interlayer film 47 covers the plurality of gate structures 15 (first buried electrodes 18) and the plurality of isolation structures 30 (third buried electrodes 33) on the active region 8 side. The interlayer film 47 may cover both ends of the source structure 20 on the active region 8 side. The interlayer film 47 covers the second semiconductor region 7, the outer well region 40, and the outer contact region 41 on the peripheral region 9 side, with the main surface insulating film 45 sandwiched therebetween.

[0412] In this embodiment, the interlayer film 47 is continuous with the first to fourth side surfaces 5A to 5D at the peripheral portion of the first main surface 3. The interlayer film 47 may be formed at a distance inward from the peripheral portion of the first main surface 3, exposing the peripheral portion of the first main surface 3 (the second semiconductor region 7).

[0413] The interlayer film 47 may have a thickness of 0.5 μm or more and 3 μm or less. The thickness of the interlayer film 47 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0414] The semiconductor device 1A includes a plurality of gate openings 48 formed in an interlayer film 47 in the active region 8 (see FIG. 3). The plurality of gate openings 48 are formed in a one-to-many correspondence with a corresponding one of the gate structures 15. In this embodiment, the plurality of gate openings 48 penetrate the interlayer film 47 and expose one end or the other end of each of the plurality of gate structures 15 (first buried electrodes 18).

[0415] The plurality of gate openings 48 may each have an opening end curved in an arc shape. The plurality of gate openings 48 may be formed in a quadrangular shape, a rectangular shape (strip shape) extending in the first direction X, a rectangular shape (strip shape) extending in the second direction Y, a circular shape, or the like in a plan view. The plurality of gate openings 48 may each have an opening end curved in an arc shape.

[0416] The semiconductor device 1A includes a plurality of source openings 49 formed in an interlayer film 47 in the active region 8. The plurality of source openings 49 are formed in a portion of the interlayer film 47 that covers the active region 8. The plurality of source openings 49 are formed in a region between the plurality of gate structures 15 in a one-to-one correspondence with the plurality of source structures 20. The plurality of source openings 49 each extend in a strip shape in the second direction Y along the corresponding source structure 20.

[0417] The plurality of source openings 49 penetrate the main surface insulating film 45 and the interlayer film 47, and expose a corresponding one source structure 20, a source region 11, a plurality of gate contact regions 27, and a plurality of source contact regions 28. Each of the plurality of source openings 49 may have an opening end curved in an arc shape.

[0418] The plurality of source openings 49 may be formed in a one-to-many correspondence with the corresponding one source structure 20. In this case, the plurality of source openings 49 may be formed at intervals along the corresponding one source structure 20. In addition, in this case, the plurality of source openings 49 may be formed in a quadrangular shape, a rectangular shape (strip shape), a circular shape, or the like in a plan view.

[0419] The semiconductor device 1A includes at least one outer opening 50 (one in this embodiment) formed in the interlayer film 47 in the peripheral region 9. The outer opening 50 penetrates the main surface insulating film 45 and the interlayer film 47, exposing the outer edge of the outer wiring 46 and the outer contact region 41. The outer opening 50 extends in a strip shape along the outer edge of the outer wiring 46 and the outer contact region 41 in a plan view.

[0420] In this embodiment, the outer opening 50 is formed in a polygonal ring shape (specifically, a square ring shape) in plan view that surrounds the inner portion (active region 8) of the first main surface 3 along the outer contact region 41 and the outer wiring 46. The outer opening 50 may have an opening end that is curved in an arc shape.

[0421] The semiconductor device 1A may have a plurality of outer openings 50. In this case, the plurality of outer openings 50 may be formed at intervals along the outer contact region 41 and the outer wiring 46 so as to surround the inner portion (active region 8) of the first main surface 3. In this case, the plurality of outer openings 50 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in plan view.

[0422] The semiconductor device 1A includes a source electrode 51 disposed on the first main surface 3. The source electrode 51 is a terminal electrode to which a source potential is applied from the outside. The source electrode 51 may also be referred to as a "source pad electrode," a "first pad electrode," a "first main surface electrode," a "first terminal electrode," or the like.

[0423] The source electrode 51 is disposed on a portion of the interlayer film 47 that covers the active region 8. The source electrode 51 extends from above the interlayer film 47 into the plurality of source openings 49, and is electrically connected to the source region 11, the plurality of gate contact regions 27, and the plurality of source contact regions 28 within the plurality of source openings 49.

[0424] In this embodiment, the source electrode 51 has a first pad portion 51 a, a second pad portion 51 b, and a third pad portion 51 c. The first pad portion 51 a has a relatively large planar area and forms the main body of the source electrode 51. In this embodiment, the first pad portion 51 a is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the fourth side surface 5D than the center of the first main surface 3.

[0425] The second pad portion 51b has a planar area smaller than that of the first pad portion 51a, and extends in a strip shape (rectangular) from one end of the first pad portion 51a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The third pad portion 51c has a planar area smaller than that of the first pad portion 51a, and extends in a strip shape (rectangular) from the other end of the first pad portion 51a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 51b in the second direction Y.

[0426] The plane area of ​​the third pad portion 51c may be approximately equal to the plane area of ​​the second pad portion 51b. The plane area of ​​the third pad portion 51c may be larger than the plane area of ​​the second pad portion 51b, or may be smaller than the plane area of ​​the second pad portion 51b. Either or both of the second pad portion 51b and the third pad portion 51c may be used as a terminal portion for monitoring current.

[0427] The source electrode 51 does not necessarily have to have both the second pad portion 51 b and the third pad portion 51 c at the same time. The source electrode 51 may have only one of the second pad portion 51 b and the third pad portion 51 c. The source electrode 51 may be composed of only the first pad portion 51 a, and may not have both the second pad portion 51 b and the third pad portion 51 c.

[0428] In this embodiment, the source electrode 51 has a layered structure including a lower electrode film 52 and a main electrode film 53, which are layered in this order from the chip 2 side. In this embodiment, the lower electrode film 52 has a layered structure including a first electrode film 54 and a second electrode film 55. In this embodiment, the first electrode film 54 includes a Ti film, and the second electrode film 55 includes a TiN film. The lower electrode film 52 does not necessarily have to have a layered structure, and may have a single-layer structure consisting of either the first electrode film 54 (Ti film) or the second electrode film 55 (TiN film).

[0429] The first electrode film 54 has a thickness less than the thickness of the interlayer film 47. The thickness of the first electrode film 54 may be 10 nm or more and 100 nm or less. The thickness of the first electrode film 54 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0430] The second electrode film 55 has a thickness less than that of the interlayer film 47. The thickness of the second electrode film 55 is preferably greater than that of the first electrode film 54. The thickness of the second electrode film 55 may be 50 nm or more and 200 nm or less. The thickness of the second electrode film 55 may have a value belonging to at least one of the ranges of 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less.

[0431] The first electrode film 54 collectively covers the region of the interlayer film 47 where the multiple source openings 49 are formed, and extends into the multiple source openings 49 from above the interlayer film 47. The first electrode film 54 has a portion that covers the insulating main surface of the interlayer film 47 in a film-like manner, a portion that covers the wall surfaces of the multiple source openings 49 in a film-like manner, and a portion that covers the first main surface 3 within the multiple source openings 49. The first electrode film 54 is mechanically and electrically connected to the source region 11 and the multiple source contact regions 28 within the source openings 49.

[0432] The second electrode film 55 directly covers the first electrode film 54. The second electrode film 55 collectively covers the region of the interlayer film 47 where the plurality of source openings 49 are formed, sandwiching the first electrode film 54 therebetween, and extends from above the interlayer film 47 into the plurality of source openings 49.

[0433] The second electrode film 55 has a portion that covers the insulating main surface of the interlayer film 47 in a film-like manner with the first electrode film 54 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of source openings 49 in a film-like manner with the first electrode film 54 sandwiched therebetween, and a portion that covers the first main surface 3 in a film-like manner with the first electrode film 54 sandwiched therebetween within the plurality of source openings 49. The second electrode film 55 is electrically connected to the source region 11 and the plurality of source contact regions 28 via the first electrode film 54 within the source openings 49.

[0434] The main electrode film 53 contains a different conductive material from the lower electrode film 52 (the first electrode film 54 and the second electrode film 55). The main electrode film 53 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The main electrode film 53 has a thickness greater than the thickness (total thickness) of the lower electrode film 52. The thickness of the main electrode film 53 is preferably greater than the thickness of the interlayer film 47.

[0435] The thickness of the main electrode film 53 may be 0.5 μm or more and 5 μm or less. The thickness of the main electrode film 53 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0436] The main electrode film 53 directly covers the lower electrode film 52 (second electrode film 55). The main electrode film 53 collectively covers the region of the interlayer film 47 where the plurality of source openings 49 are formed, and backfills the plurality of source openings 49.

[0437] The main electrode film 53 has a portion that covers the insulating main surface of the interlayer film 47 with the lower electrode film 52 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of source openings 49 with the lower electrode film 52 sandwiched therebetween, and a portion that covers the first main surface 3 with the lower electrode film 52 sandwiched therebetween. The main electrode film 53 is electrically connected to the source region 11 and the plurality of source contact regions 28 via the lower electrode film 52 within the plurality of source openings 49.

[0438] The semiconductor device 1A includes a source wiring 56 arranged around the source electrode 51 on the interlayer film 47. The same potential (source potential) as the potential (source potential) applied to the source electrode 51 is applied to the source wiring 56. The source wiring 56 may also be referred to as a "termination electrode (wiring)," "wiring," "first wiring," "finger electrode," "source finger," or the like.

[0439] The source wiring 56 has a wiring width less than the electrode width of the source electrode 51, and is selectively routed on the interlayer film 47. In this embodiment, the source wiring 56 is drawn out from the source electrode 51 (first pad portion 51 a) to the fourth side surface 5D side.

[0440] The source wiring 56 is drawn from the active region 8 to the peripheral region 9, and has a portion facing the outer wiring 46 across the interlayer film 47. In this embodiment, the source wiring 56 covers the outer wiring 46 over the entire periphery. The source wiring 56 enters the outer opening 50 from above the interlayer film 47, and is electrically connected to the outer contact region 41 and the outer wiring 46 within the outer opening 50.

[0441] That is, the source wiring 56 is electrically connected to one or more (one in this embodiment) isolation structures 30 (third buried electrodes 33) via the outer wiring 46, and is electrically connected to the outer well region 40 and the termination region 42 via the outer contact region 41. The source potential applied to the source electrode 51 is applied to the isolation structure 30 via the outer wiring 46, and at the same time, is applied to the outer well region 40 and the termination region 42 via the outer wiring 46.

[0442] The source wiring 56 extends in a band shape along the periphery of the first main surface 3 (the periphery of the active region 8) in a plan view, following the extension direction of the outer contact region 41. In this embodiment, the source wiring 56 is formed in a polygonal ring shape (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner part of the first main surface 3 (the active region 8). The source wiring 56 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape). The source wiring 56 may be either ended or endless.

[0443] The source wiring 56 has an inner edge portion on the inner side (active region 8 side) of the first main surface 3 and an outer edge portion on the peripheral edge side of the first main surface 3. The inner edge portion of the source wiring 56 is located within the active region 8 and faces one or more (multiple in this embodiment) isolation structures 30 with the interlayer film 47 interposed therebetween.

[0444] The outer edge of source wiring 56 is formed at a distance inward (toward active region 8) from the periphery of first main surface 3. The outer edge of source wiring 56 is formed at a distance inward from the innermost field region 43 of the plurality of field regions 43. In other words, source wiring 56 does not face the plurality of field regions 43 across interlayer film 47.

[0445] With this configuration, the source wiring 56 is prevented from blocking the electric field dispersion path in the region above the plurality of field regions 43, and the electric field (electric force lines) is dispersed appropriately by the plurality of field regions 43.

[0446] The outer edge of the source wiring 56 is formed at a distance inward from the outer edge of the termination region 42, and faces the termination region 42 across the interlayer film 47. In this embodiment, the outer edge of the source wiring 56 is disposed at a distance from the outer edge of the outer contact region 41 toward the outer edge of the termination region 42, and faces the entire outer contact region 41 across the main surface insulating film 45.

[0447] Like the source electrode 51, the source wiring 56 has a laminated structure including a lower electrode film 52 and a main electrode film 53 laminated in this order from the chip 2 side. In this embodiment, the lower electrode film 52 has a laminated structure including a first electrode film 54 and a second electrode film 55.

[0448] The first electrode film 54 covers the entire region of the interlayer film 47 where the outer opening 50 is formed, and extends into the outer opening 50 from above the interlayer film 47. The first electrode film 54 has a portion that covers the insulating main surface of the interlayer film 47 in a film-like manner, a portion that covers the wall surface of the outer opening 50 in a film-like manner, and a portion that covers the outer wiring 46 and the first main surface 3 within the outer opening 50 in a film-like manner. The first electrode film 54 is mechanically and electrically connected to the outer contact region 41 and the outer wiring 46 within the outer opening 50.

[0449] The second electrode film 55 directly covers the first electrode film 54. The second electrode film 55 collectively covers the region of the interlayer film 47 where the outer opening 50 is formed, sandwiching the first electrode film 54 therebetween, and extends from above the interlayer film 47 into the outer opening 50.

[0450] The second electrode film 55 has a portion that covers the insulating main surface of the interlayer film 47 in a film-like manner with the first electrode film 54 sandwiched therebetween, a portion that covers the wall surface of the outer opening 50 in a film-like manner with the first electrode film 54 sandwiched therebetween, and a portion that covers the first main surface 3 in the outer opening 50 in a film-like manner with the first electrode film 54 sandwiched therebetween. The second electrode film 55 is electrically connected to the outer contact region 41 and the outer wiring 46 via the first electrode film 54 within the outer opening 50.

[0451] The main electrode film 53 directly covers the lower electrode film 52 (second electrode film 55). The main electrode film 53 collectively covers the region of the interlayer film 47 where the outer opening 50 is formed, and backfills the outer opening 50.

[0452] The main electrode film 53 has a portion that covers the insulating main surface of the interlayer film 47 with the lower electrode film 52 in between, a portion that covers the wall surface of the outer opening 50 with the lower electrode film 52 in between, and a portion that covers the first main surface 3 with the lower electrode film 52 in between. The main electrode film 53 is electrically connected to the outer contact region 41 and the outer wiring 46 via the lower electrode film 52 within the outer opening 50.

[0453] The semiconductor device 1A includes a gate electrode 57 disposed on the first main surface 3. The gate electrode 57 is a terminal electrode to which a gate potential is applied from the outside. The gate electrode 57 may also be referred to as a "second pad electrode," a "second main surface electrode," a "second terminal electrode," or the like. Although not shown, the gate electrode 57, like the source electrode 51, includes a lower electrode film 52 and a main electrode film 53 stacked in this order from the interlayer film 47 side.

[0454] The gate electrode 57 is disposed on a portion of the interlayer film 47 that covers the active region 8, with a gap between it and the source electrode 51. In this embodiment, the gate electrode 57 is disposed in a region on the third side surface 5C side of the first pad portion 51a, and faces the first pad portion 51a in the first direction X. The gate electrode 57 is interposed in a region between the second pad portion 51b and the third pad portion 51c, and faces both the second pad portion 51b and the third pad portion 51c in the second direction Y.

[0455] The gate electrode 57 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate electrode 57 has a planar area less than the planar area of ​​the source electrode 51. The gate electrode 57 has a planar area less than the planar area of ​​the first pad portion 51a. The gate electrode 57 may also have a planar area less than the planar area of ​​the second pad portion 51b (third pad portion 51c).

[0456] The gate electrode 57 partially faces the plurality of gate structures 15 and the plurality of source structures 20 across the interlayer film 47. Specifically, the gate electrode 57 is disposed inwardly from both ends of the plurality of gate structures 15 at a distance, and faces inner portions of the plurality of gate structures 15 across the interlayer film 47. In this embodiment, the gate electrode 57 does not have any direct electrical connection points to the plurality of gate structures 15.

[0457] The gate electrode 57 may be electrically connected to the plurality of gate structures 15 via the plurality of gate openings 48. Portions of the plurality of gate structures 15 located under the gate electrode 57 may be removed. In this case, the gate electrode 57 may face the body region 10 with the main surface insulating film 45 and the interlayer film 47 interposed therebetween. The gate electrode 57 may partially face one or more isolation structures 30 with the interlayer film 47 interposed therebetween.

[0458] The semiconductor device 1A includes a gate wiring 58 extending from the gate electrode 57 onto the first main surface 3. The gate wiring 58 may also be referred to as a "wiring," a "second wiring," a "finger electrode," a "gate finger," or the like. The gate wiring 58 transmits the gate potential applied to the gate electrode 57 to other regions. Although not shown, the gate wiring 58 includes a lower electrode film 52 and a main electrode film 53 stacked in this order from the chip 2 side, similar to the source electrode 51 (gate electrode 57).

[0459] The gate wiring 58 is drawn out from the gate electrode 57 onto the portion of the interlayer film 47 that covers the active region 8, and is routed to the region between the source electrode 51 and the source wiring 56 at a distance from the source electrode 51 and the source wiring 56.

[0460] The gate wiring 58 has a portion extending in a strip shape in the first direction X in a plan view and a portion extending in a strip shape in the second direction Y, and intersects (specifically, orthogonally) with ends (both ends in this embodiment) of the plurality of gate structures 15. In this embodiment, the gate wiring 58 is formed in a strip shape with ends having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 51.

[0461] The gate wiring 58 penetrates into the plurality of gate openings 48 from above the interlayer film 47, and is mechanically and electrically connected to the ends (both ends) of the plurality of gate structures 15 (first buried electrodes 18) within the plurality of gate openings 48. As a result, the gate potential applied to the gate electrode 57 is applied to the plurality of gate structures 15 via the gate wiring 58.

[0462] The semiconductor device 1A includes a drain electrode 59 covering the second main surface 4. The drain electrode 59 is a terminal electrode to which a drain potential is applied from the outside. The drain electrode 59 may also be referred to as a "third pad electrode," a "third main surface electrode," a "third terminal electrode," or the like.

[0463] The drain electrode 59 is electrically connected to the first semiconductor region 6. The drain electrode 59 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain electrode 59 may also cover a portion of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0464] A breakdown voltage that can be applied between source electrode 51 and drain electrode 59 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value belonging to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, 2500 V or more and 2750 V or less, and 2750 V or more and 3000 V or less.

[0465] 11A to 11G are cross-sectional views showing deep well regions 36 according to the second to eighth embodiments. The semiconductor device 1A may include at least one of the deep well regions 36 according to the first to eighth embodiments. The semiconductor device 1A may simultaneously include at least two of the deep well regions 36 according to the first to eighth embodiments in the same cross-sectional region or different cross-sectional regions.

[0466] 11A (second embodiment), the semiconductor device 1A may include two deep well regions 36. The number of the deep well regions 36 is smaller than the number of the shallow well regions 35.

[0467] In this embodiment, the two deep well regions 36 have approximately the same depth. The two deep well regions 36 are formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the two isolation structures 30, and overlap the corresponding isolation structures 30 in a one-to-one correspondence in the thickness direction.

[0468] The two deep well regions 36 are formed at an interval from the isolation structure 30 for the shallow well region 35 toward the peripheral region 9, and do not overlap the isolation structure 30 for the shallow well region 35 in the thickness direction. The two deep well regions 36 are formed in regions below the two outermost isolation structures 30 among the plurality of isolation structures 30, respectively.

[0469] The two deep well regions 36 may be connected to each other in the horizontal direction. The innermost deep well region 36 may be connected to the shallow well region 35. Each of the two deep well regions 36 has a plurality of (two or more) bulging portions 36a and one or more constricted portions 36b in the thickness direction of the chip 2.

[0470] One or more bulging portions 36 a of the two deep well regions 36 may be connected to each other in the horizontal direction. The constricted portions 36 b of the two deep well regions 36 may be formed spaced apart from each other in the horizontal direction and may face each other in the horizontal direction with a part of the second semiconductor region 7 interposed therebetween.

[0471] The upper bulging portions 36a of the two deep well regions 36 are positioned at approximately the same depth as the bulging portions 35a of the multiple shallow well regions 35. The lower bulging portions 36a of the two deep well regions 36 are each formed in a shape that tapers toward the bottom. The lower bulging portion 36a is positioned closer to the bottom of the second semiconductor region 7 than the depth positions of the bottoms of the multiple shallow well regions 35, and does not face the multiple shallow well regions 35 in the horizontal direction.

[0472] The upper bulge 36a of the innermost deep well region 36 is connected to the bulge 35a of the outermost shallow well region 35. The upper bulge 36a may be formed at a distance from the outermost shallow well region 35 in the horizontal direction.

[0473] The constricted portion 36b of the innermost deep well region 36 is formed at a horizontal distance from the outermost shallow well region 35. The constricted portion 36b is formed in a region on the isolation structure 30 side with respect to the bottom of the outermost shallow well region 35, and faces the outermost shallow well region 35 in the horizontal direction. The constricted portion 36b may be located closer to the bottom of the second semiconductor region 7 than the bottom of the outermost shallow well region 35.

[0474] 11B (third embodiment), the semiconductor device 1A may include three deep well regions 36. The number of the deep well regions 36 is greater than the number of the shallow well regions 35.

[0475] In this embodiment, the three deep well regions 36 have approximately the same depth as one another. The three deep well regions 36 are formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the three isolation structures 30, and overlap the corresponding isolation structures 30 in a one-to-one correspondence in the thickness direction.

[0476] The three deep well regions 36 are formed at intervals from the isolation structure 30 for the shallow well region 35 toward the outer periphery region 9, and do not overlap the isolation structure 30 for the shallow well region 35 in the thickness direction. The three deep well regions 36 are formed in regions below the three outermost isolation structures 30 among the plurality of isolation structures 30, respectively.

[0477] The three deep well regions 36 may be connected to each other in the horizontal direction. The innermost deep well region 36 may be connected to the shallow well region 35. Each of the three deep well regions 36 has a plurality of (two or more) bulging portions 36a and one or more constricted portions 36b in the thickness direction of the chip 2.

[0478] One or more bulging portions 36 a of the three deep well regions 36 may be connected to each other in the horizontal direction. The constricted portions 36 b of the three deep well regions 36 may be formed spaced apart from each other in the horizontal direction and may face each other in the horizontal direction with a part of the second semiconductor region 7 interposed therebetween.

[0479] The upper bulging portions 36a of the three deep well regions 36 are positioned at approximately the same depth as the bulging portions 35a of the multiple shallow well regions 35. The lower bulging portions 36a of the three deep well regions 36 are each formed in a shape tapering toward the bottom. The lower bulging portions 36a are positioned closer to the bottom of the second semiconductor region 7 than the depth positions of the bottoms of the multiple shallow well regions 35, and do not face the multiple shallow well regions 35 in the horizontal direction.

[0480] The upper bulge 36a of the innermost deep well region 36 is connected to the bulge 35a of the outermost shallow well region 35. The upper bulge 36a may be formed at a distance from the outermost shallow well region 35 in the horizontal direction.

[0481] The constricted portion 36b of the innermost deep well region 36 is formed at a horizontal distance from the outermost shallow well region 35. The constricted portion 36b is formed in a region on the isolation structure 30 side with respect to the bottom of the outermost shallow well region 35, and faces the outermost shallow well region 35 in the horizontal direction. The constricted portion 36b may be located closer to the bottom of the second semiconductor region 7 than the bottom of the outermost shallow well region 35.

[0482] 11C (fourth embodiment), the semiconductor device 1A may include four deep well regions 36. The number of the deep well regions 36 is greater than the number of the shallow well regions 35.

[0483] In this embodiment, the four deep well regions 36 have approximately the same depth as one another. The four deep well regions 36 are formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the four isolation structures 30, and overlap with the corresponding isolation structures 30 in a one-to-one correspondence in the thickness direction.

[0484] The four deep well regions 36 are formed at intervals from the isolation structures 30 for the shallow well regions 35 toward the outer periphery region 9, and do not overlap the isolation structures 30 for the shallow well regions 35 in the thickness direction. The four deep well regions 36 are formed in regions below the four outermost isolation structures 30 among the plurality of isolation structures 30, respectively.

[0485] The four deep well regions 36 may be connected to one another in the horizontal direction. The innermost deep well region 36 may be connected to the shallow well region 35. Each of the four deep well regions 36 has a plurality of (two or more) bulging portions 36a and one or more constricted portions 36b in the thickness direction of the chip 2.

[0486] One or more bulging portions 36 a of the four deep well regions 36 may be connected to each other in the horizontal direction. The constricted portions 36 b of the four deep well regions 36 may be formed at intervals in the horizontal direction and may face each other in the horizontal direction with a part of the second semiconductor region 7 interposed therebetween.

[0487] The upper bulging portions 36a of the four deep well regions 36 are positioned at approximately the same depth as the bulging portions 35a of the multiple shallow well regions 35. The lower bulging portions 36a of the four deep well regions 36 are each formed in a shape tapering toward the bottom. The lower bulging portions 36a are positioned closer to the bottom of the second semiconductor region 7 than the depth positions of the bottoms of the multiple shallow well regions 35, and do not face the multiple shallow well regions 35 in the horizontal direction.

[0488] The upper bulge 36a of the innermost deep well region 36 is connected to the bulge 35a of the outermost shallow well region 35. The upper bulge 36a may be formed at a distance from the outermost shallow well region 35 in the horizontal direction.

[0489] The constricted portion 36b of the innermost deep well region 36 is formed at a horizontal distance from the outermost shallow well region 35. The constricted portion 36b is formed in a region on the isolation structure 30 side with respect to the bottom of the outermost shallow well region 35, and faces the outermost shallow well region 35 in the horizontal direction. The constricted portion 36b may be located closer to the bottom of the second semiconductor region 7 than the bottom of the outermost shallow well region 35.

[0490] 11D (fifth embodiment), the semiconductor device 1A may include one or more (one in this embodiment) deep well regions 36 having three or more bulging portions 36 a and two or more constricted portions 36 b. The multiple bulging portions 36 a include an upper bulging portion 36 a (on the isolation structure 30 side), a middle bulging portion 36 a, and a lower bulging portion 36 a (on the bottom of the second semiconductor region 7).

[0491] The upper bulging portion 36a is positioned at approximately the same depth as the bulging portions 35a of the plurality of shallow well regions 35. In this embodiment, the upper bulging portion 36a is connected to the bulging portions 35a of the shallow well regions 35. The upper bulging portion 36a may be formed at a distance from the shallow well region 35 in the horizontal direction.

[0492] The middle bulge portion 36a is located on the bottom side of the second semiconductor region 7 relative to the depth positions of the bottoms of the plurality of shallow well regions 35, and does not face the plurality of shallow well regions 35 in the horizontal direction. In this embodiment, the p-type impurity concentration in the middle portion of the middle bulge portion 36a is lower than the p-type impurity concentration in the middle portion of the upper bulge portion 36a.

[0493] The lower bulge 36a is located on the bottom side of the second semiconductor region 7 relative to the depth positions of the bottoms of the plurality of shallow well regions 35, and does not face the plurality of shallow well regions 35 in the horizontal direction. The lower bulge 36a is formed in a tapered shape toward the bottom.

[0494] In this embodiment, the p-type impurity concentration in the middle portion of the lower bulging portion 36 a is lower than the p-type impurity concentration in the middle portion of the middle bulging portion 36 a. In other words, the p-type impurity concentration in the plurality of bulging portions 36 a gradually decreases from the bottom wall side of the isolation structure 30 toward the bottom side of the second semiconductor region 7.

[0495] The multiple constricted portions 36b include an upper constricted portion 36b and a lower constricted portion 36b. The upper constricted portion 36b is formed at a distance in the horizontal direction from the outermost shallow well region 35. The upper constricted portion 36b is formed in a region on the isolation structure 30 side with respect to the bottom of the outermost shallow well region 35, and faces the outermost shallow well region 35 in the horizontal direction. The upper constricted portion 36b may be located closer to the bottom of the second semiconductor region 7 than the bottom of the outermost shallow well region 35.

[0496] The upper constricted portion 36b contains p-type impurities at the lower end of the upper bulging portion 36a and at the upper end of the middle bulging portion 36a. The p-type impurity concentration of the upper constricted portion 36b may be higher than the p-type impurity concentration at the lower end of the upper bulging portion 36a and the p-type impurity concentration at the upper end of the middle bulging portion 36a. The p-type impurity concentration of the upper constricted portion 36b may be lower than the p-type impurity concentration at the middle portion of the upper bulging portion 36a and the p-type impurity concentration at the middle portion of the middle bulging portion 36a.

[0497] The lower constricted portion 36b is formed in a region closer to the bottom of the second semiconductor region 7 than the bottoms of the plurality of shallow well regions 35, and does not face the outermost shallow well region 35 in the horizontal direction. The lower constricted portion 36b contains p-type impurities on the lower end side of the middle bulging portion 36a and p-type impurities on the upper end side of the lower bulging portion 36a.

[0498] The p-type impurity concentration of the lower constricted portion 36b may be higher than the p-type impurity concentration at the lower end of the middle bulging portion 36a and the p-type impurity concentration at the upper end of the lower bulging portion 36a.The p-type impurity concentration of the lower constricted portion 36b may be lower than the p-type impurity concentration at the middle portion of the middle bulging portion 36a and the p-type impurity concentration at the middle portion of the lower bulging portion 36a.

[0499] 11E (sixth embodiment), the semiconductor device 1A may include a plurality of deep well regions 36 having different depths. In this embodiment, the plurality of deep well regions 36 include one or more (one in this embodiment) first deep well regions 36A and one or more (one in this embodiment) second deep well regions 36B.

[0500] The first deep well region 36A is located on the peripheral side of the first main surface 3 (toward the outer periphery region 9) with respect to the plurality of shallow well regions 35. The first deep well region 36A is formed in a region below (specifically, directly below) an isolation structure 30 that is located on the outer periphery region 9 side (toward the peripheral edge of the first main surface 3) among the plurality of isolation structures 30. In this embodiment, the first deep well region 36A is formed in a region below an isolation structure 30 that is located more inward than the outermost isolation structure 30.

[0501] The first deep well region 36A has a first depth that is greater than the depths of the plurality of shallow well regions 35. The first deep well region 36A has a bottom that is located closer to the bottom of the second semiconductor region 7 than the bottoms of the plurality of shallow well regions 35.

[0502] The first deep well region 36A is formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom wall of the corresponding isolation structure 30, and overlaps the corresponding isolation structure 30 in a one-to-one correspondence in the thickness direction. In other words, the first deep well region 36A is formed at a distance from the isolation structure 30 for the shallow well region 35 toward the peripheral region 9, and does not overlap the isolation structure 30 for the shallow well region 35 in the thickness direction.

[0503] The first deep well region 36A has a plurality (two or more) of bulging portions 36a and one or more constricted portions 36b in the thickness direction of the chip 2. The plurality of bulging portions 36a include an upper bulging portion 36a and a lower bulging portion 36a.

[0504] The upper bulge portion 36a is positioned at approximately the same depth as the bulge portions 35a of the plurality of shallow well regions 35. The upper bulge portion 36a is connected to the bulge portions 35a of the outermost shallow well regions 35. The upper bulge portion 36a may be formed at a distance from the outermost shallow well region 35 in the horizontal direction.

[0505] The lower bulge 36 a is formed in a shape tapering toward the bottom. The lower bulge 36 a is located on the bottom side of the second semiconductor region 7 relative to the depth positions of the bottoms of the plurality of shallow well regions 35, and does not face the plurality of shallow well regions 35 in the horizontal direction.

[0506] The constricted portion 36b is formed at a horizontal distance from the outermost shallow well region 35. The constricted portion 36b is formed in a region on the isolation structure 30 side with respect to the bottom of the outermost shallow well region 35, and faces the outermost shallow well region 35 in the horizontal direction. The constricted portion 36b may be located closer to the bottom of the second semiconductor region 7 than the bottom of the outermost shallow well region 35.

[0507] The second deep well region 36B is located closer to the periphery of the first main surface 3 (toward the outer periphery region 9) than the first deep well region 36A. The second deep well region 36B is formed in a region below (specifically, directly below) an isolation structure 30 that is located closer to the periphery region 9 (toward the periphery of the first main surface 3) among the multiple isolation structures 30. In this embodiment, the second deep well region 36B is formed in a region below the outermost isolation structure 30.

[0508] The second deep well region 36B has a second depth greater than the first depth of the first deep well region 36A, and has a bottom located closer to the bottom of the second semiconductor region 7 than the bottom of the first deep well region 36A. The depths of the deep well regions 36 gradually increase from the shallow well regions 35 toward the peripheral edge of the first main surface 3 (toward the outer periphery region 9).

[0509] The second deep well region 36B is formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom wall of the corresponding isolation structure 30, and overlaps the corresponding isolation structure 30 in a one-to-one correspondence in the thickness direction. In other words, the second deep well region 36B is formed at a distance from the isolation structure 30 for the first deep well region 36A toward the outer periphery region 9, and does not overlap the isolation structure 30 for the first deep well region 36A in the thickness direction.

[0510] The second deep well region 36B has (three or more) bulging portions 36a and (two or more) constricted portions 36b in the thickness direction of the chip 2. The number of bulging portions 36a in the second deep well region 36B is greater than the number of bulging portions 36a in the first deep well region 36A. The number of constricted portions 36b in the second deep well region 36B is greater than the number of constricted portions 36b in the first deep well region 36A.

[0511] The multiple bulging portions 36a of the second deep well region 36B include an upper bulging portion 36a (on the isolation structure 30 side), a middle bulging portion 36a, and a lower bulging portion 36a (on the bottom of the second semiconductor region 7).

[0512] The upper bulge 36a is positioned at approximately the same depth as the upper bulge 36a of the first deep well region 36A. The upper bulge 36a is connected to the upper bulge 36a of the first deep well region 36A. The upper bulge 36a may be formed at a horizontal distance from the first deep well region 36A.

[0513] The intermediate bulge 36a is positioned at approximately the same depth as the lower bulge 36a of the first deep well region 36A. The intermediate bulge 36a is connected to the lower bulge 36a of the first deep well region 36A. The intermediate bulge 36a may be spaced horizontally from the first deep well region 36A.

[0514] The lower bulge 36a is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the first deep well region 36A, and does not face the first deep well region 36A in the horizontal direction. The lower bulge 36a is formed in a tapered shape toward the bottom.

[0515] The multiple constricted portions 36b of the second deep well region 36B include an upper constricted portion 36b (toward the isolation structure 30) and a lower constricted portion 36b (toward the bottom of the second semiconductor region 7). The upper constricted portion 36b is formed at a distance in the horizontal direction from the constricted portion 36b of the first deep well region 36A and faces the constricted portion 36b of the first deep well region 36A in the horizontal direction, with part of the second semiconductor region 7 sandwiched between them.

[0516] The lower constricted portion 36b is formed horizontally spaced apart from the bottom of the first deep well region 36A and faces the bottom of the first deep well region 36A horizontally with a part of the second semiconductor region 7 in between.

[0517] The upper constricted portion 36b may be located on the isolation structure 30 side relative to the depth position of the constricted portion 36b of the first deep well region 36A, or may be located on the bottom side of the second semiconductor region 7. The lower constricted portion 36b may be located on the isolation structure 30 side relative to the bottom of the first deep well region 36A, or may be located on the bottom side of the second semiconductor region 7.

[0518] 11F (seventh embodiment), the semiconductor device 1A may include a plurality of deep well regions 36 having different depths. In this embodiment, the plurality of deep well regions 36 include one or more (one in this embodiment) first deep well regions 36A and one or more (one in this embodiment) second deep well regions 36B.

[0519] The first deep well region 36A is located on the peripheral side of the first main surface 3 (toward the outer periphery region 9) with respect to the plurality of shallow well regions 35. The first deep well region 36A is formed in a region below (specifically, directly below) an isolation structure 30 that is located on the outer periphery region 9 side (toward the peripheral edge of the first main surface 3) among the plurality of isolation structures 30. In this embodiment, the first deep well region 36A is formed in a region below an isolation structure 30 that is located more inward than the outermost isolation structure 30.

[0520] The first deep well region 36A has a first depth that is greater than the depths of the plurality of shallow well regions 35. The first deep well region 36A has a bottom that is located closer to the bottom of the second semiconductor region 7 than the bottoms of the plurality of shallow well regions 35.

[0521] The first deep well region 36A is formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom wall of the corresponding isolation structure 30, and overlaps the corresponding isolation structure 30 in a one-to-one correspondence in the thickness direction. In other words, the first deep well region 36A is formed at a distance from the isolation structure 30 for the shallow well region 35 toward the peripheral region 9, and does not overlap the isolation structure 30 for the shallow well region 35 in the thickness direction.

[0522] The first deep well region 36A has (three or more) bulging portions 36a and (two or more) constricted portions 36b in the thickness direction of the chip 2. The multiple bulging portions 36a include an upper bulging portion 36a (on the isolation structure 30 side), a middle bulging portion 36a, and a lower bulging portion 36a (on the bottom of the second semiconductor region 7).

[0523] The upper bulging portion 36a is positioned at approximately the same depth as the bulging portions 35a of the plurality of shallow well regions 35. The upper bulging portion 36a is connected to the bulging portions 36a of the outermost shallow well regions 35. The upper bulging portion 36a may be formed at a distance from the outermost shallow well region 35 in the horizontal direction.

[0524] The intermediate bulge portion 36a is located closer to the bottom of the second semiconductor region 7 than the bottom of the outermost shallow well region 35, and does not face the plurality of shallow well regions 35 in the horizontal direction. The intermediate bulge portion 36a may be located closer to the isolation structure 30 than the bottom of the outermost shallow well region 35, and may face the plurality of shallow well regions 35 in the horizontal direction.

[0525] The lower bulge 36a is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the outermost shallow well region 35, and does not face the plurality of shallow well regions 35 in the horizontal direction. The lower bulge 36a is formed in a tapered shape toward the bottom.

[0526] The multiple constricted portions 36b include an upper constricted portion 36b (closer to the isolation structure 30) and a lower constricted portion 36b (closer to the bottom of the second semiconductor region 7). The upper constricted portion 36b is formed at a distance in the horizontal direction from the outermost shallow well region 35. The upper constricted portion 36b is formed in a region on the isolation structure 30 side of the bottom of the outermost shallow well region 35 and faces the outermost shallow well region 35 in the horizontal direction. The upper constricted portion 36b may be located closer to the bottom of the second semiconductor region 7 than the bottom of the outermost shallow well region 35.

[0527] The lower constricted portion 36b is formed in a region closer to the bottom of the second semiconductor region 7 than the bottoms of the plurality of shallow well regions 35, and does not face the outermost shallow well region 35 in the horizontal direction.

[0528] The second deep well region 36B is located closer to the periphery of the first main surface 3 (toward the outer periphery region 9) than the first deep well region 36A. The second deep well region 36B is formed in a region below (specifically, directly below) an isolation structure 30 that is located closer to the periphery region 9 (toward the periphery of the first main surface 3) among the multiple isolation structures 30. In this embodiment, the second deep well region 36B is formed in a region below the outermost isolation structure 30.

[0529] The second deep well region 36B has a second depth smaller than the first depth of the first deep well region 36A, and has a bottom located closer to the isolation structure 30 than the bottom of the first deep well region 36A. The depths of the multiple deep well regions 36 gradually decrease from the first deep well region 36A toward the peripheral edge of the first main surface 3 (toward the outer periphery region 9).

[0530] The second deep well region 36B is formed in a thickness range between the bottom of the second semiconductor region 7 and the bottom wall of the corresponding isolation structure 30, and overlaps the outermost isolation structure 30 in a one-to-one correspondence in the thickness direction. The second deep well region 36B is formed at a distance from the isolation structure 30 for the first deep well region 36A toward the outer periphery region 9, and does not overlap the isolation structure 30 for the first deep well region 36A in the thickness direction.

[0531] The second deep well region 36B has (two or more) bulging portions 36a and one or more constricted portions 36b in the thickness direction of the chip 2. The number of bulging portions 36a in the second deep well region 36B is fewer than the number of bulging portions 36a in the first deep well region 36A. The number of constricted portions 36b in the second deep well region 36B is fewer than the number of constricted portions 36b in the first deep well region 36A.

[0532] The multiple bulging portions 36a include an upper bulging portion 36a (on the isolation structure 30 side) and a lower bulging portion 36a (on the bottom of the second semiconductor region 7). The upper bulging portion 36a is positioned at approximately the same depth as the upper bulging portion 36a of the first deep well region 36A. The upper bulging portion 36a is connected to the upper bulging portion 36a of the first deep well region 36A. The upper bulging portion 36a may be formed at a distance from the first deep well region 36A in the horizontal direction.

[0533] The lower bulge 36a is located on the bottom side of the second semiconductor region 7 relative to the depth positions of the bottoms of the plurality of shallow well regions 35, and does not face the plurality of shallow well regions 35 in the horizontal direction. The lower bulge 36a is located on the isolation structure 30 side relative to the depth position of the bottom of the first deep well region 36A.

[0534] The lower bulging portion 36a is formed to a depth approximately equal to that of the intermediate bulging portion 36a of the first deep well region 36A. The lower bulging portion 36a is connected to the intermediate bulging portion 36a of the first deep well region 36A. The lower bulging portion 36a may be formed at a distance from the first deep well region 36A and may face the first deep well region 36A with a portion of the second semiconductor region 7 interposed therebetween.

[0535] The lower bulging portion 36a may be located closer to the isolation structure 30 than the intermediate bulging portion 36a of the first deep well region 36A, or may be located closer to the bottom of the second semiconductor region 7. The lower bulging portion 36a is formed in a tapered shape toward the bottom.

[0536] The constricted portion 36b is formed at a depth substantially equal to the depth of the bottoms of the plurality of shallow well regions 35. The constricted portion 36b may be located on the isolation structure 30 side relative to the bottoms of the plurality of shallow well regions 35, or may be located on the bottom side of the second semiconductor region 7.

[0537] The constricted portion 36b is formed horizontally spaced apart from the upper constricted portion 36b of the first deep well region 36A and faces the constricted portion 36b of the first deep well region 36A horizontally across a part of the second semiconductor region 7. The upper constricted portion 36b may be located on the isolation structure 30 side relative to the depth position of the constricted portion 36b of the first deep well region 36A, or may be located on the bottom side of the second semiconductor region 7.

[0538] Referring to Figure 11G (eighth embodiment), the semiconductor device 1A includes a shallow well region 35 formed below the outermost isolation structure 30, and may also include a deep well region 36 formed below an isolation structure 30 other than the outermost isolation structure 30.

[0539] That is, the one or more deep well regions 36 according to the first to seventh embodiments do not necessarily have to be formed in the outermost isolation structure 30. In this embodiment, an example is shown in which one deep well region 36 is formed in a region below one isolation structure 30 adjacent to the outermost isolation structure 30.

[0540] As described above, the semiconductor device 1A includes the chip 2, the n-type (first conductivity type) second semiconductor region 7 (semiconductor region), the active region 8, the peripheral region 9, the trench-type isolation structure 30, and the p-type (second conductivity type) deep well region 36. The chip 2 has a first main surface 3. The second semiconductor region 7 is formed in a surface layer portion of the first main surface 3. The active region 8 is provided in an inner portion of the first main surface 3. The peripheral region 9 is provided in the peripheral portion of the first main surface 3.

[0541] The isolation structure 30 is formed on the first main surface 3 so as to be located within the second semiconductor region 7, and defines the active region 8 and the peripheral region 9. The deep well region 36 is formed in a region below the isolation structure 30 so as to be located within the second semiconductor region 7, and is electrically connected to the second semiconductor region 7.

[0542] This configuration provides a semiconductor device 1A with a novel layout. For example, in this semiconductor device 1A, the depletion layer extends from the deep well region 36 into the second semiconductor region 7. This reduces the electric field in the isolation structure 30, suppressing a decrease in breakdown voltage due to electric field concentration. In other words, a decrease in breakdown voltage originating from the boundary region between the active region 8 and the peripheral region 9 is suppressed.

[0543] The chip 2 may include SiC. This configuration provides the semiconductor device 1A as a SiC semiconductor device having a novel layout. The semiconductor device 1A further improves the breakdown voltage due to the physical properties of SiC. In particular, since SiC semiconductor devices are used in relatively high-voltage environments, the electric field relaxation effect (the effect of suppressing a decrease in breakdown voltage) provided by the deep well region 36 is effective.

[0544] The deep well region 36 may be formed in a vertically elongated columnar shape extending in the thickness direction of the chip 2. With this configuration, the electric field in the deep well region 36 can be dispersed in the thickness direction of the deep well region 36. This alleviates localized electric field concentration in the deep well region 36, and suppresses a decrease in breakdown voltage.

[0545] The deep well region 36 may be formed at an interval from the bottom of the second semiconductor region 7 toward the first main surface 3. With this configuration, the depletion layer appropriately spreads from the deep well region 36 in the thickness direction and horizontal direction within the second semiconductor region 7. This appropriately suppresses a decrease in breakdown voltage due to electric field concentration.

[0546] The deep well region 36 may have a bulging portion 36a that juts out in the horizontal direction along the first main surface 3, and a constricted portion 36b that is recessed in the horizontal direction relative to the bulging portion 36a at a depth position different from that of the bulging portion 36a. With this configuration, the bulging portion 36a and the constricted portion 36b can appropriately distribute the electric field concentration in the deep well region 36 in the thickness direction, thereby mitigating the local electric field concentration.

[0547] The deep well region 36 may include a plurality of p-type impurity regions (36 a) formed at different depths so as to be connected to each other. With this configuration, the bulging portion 36 a and the constricted portion 36 b can be appropriately formed by utilizing the plurality of impurity regions (36 a).

[0548] A plurality of isolation structures 30 may be formed at intervals on the first main surface 3. In this case, the deep well region 36 may be formed in a region below at least one of the isolation structures 30. According to this configuration, the electric field for the plurality of isolation structures 30 is alleviated by the deep well region 36.

[0549] The deep well region 36 may be formed in a region below at least one of the multiple isolation structures 30 that is located on the peripheral region 9 side. With this configuration, the electric field for the at least one isolation structure 30 located on the peripheral region 9 side is appropriately relaxed. In this case, the deep well region 36 does not have to be formed in a region below at least one of the multiple isolation structures 30 that is located on the active region 8 side.

[0550] The semiconductor device 1A may include a p-type shallow well region 35. The shallow well region 35 may be formed in a region below at least one isolation structure 30 so as to be located within the second semiconductor region 7, and may be electrically connected to the second semiconductor region 7. In this case, the deep well region 36 may have a depth greater than that of the shallow well region 35, and may be formed in a region below the isolation structure 30 in a region other than the shallow well region 35.

[0551] With this configuration, the depletion layer extends from the shallow well region 35 into the second semiconductor region 7, and at the same time, the depletion layer extends from the deep well region 36 into the second semiconductor region 7. With this configuration, electric field concentration in the multiple isolation structures 30 is suppressed by both the shallow well region 35 and the deep well region 36. The depletion layer on the deep well region 36 side extends in a region below the depletion layer on the shallow well region 35 side. As a result, the deep well region 36 alleviates local electric field concentration in the shallow well region 35.

[0552] A plurality of shallow well regions 35 may be formed in regions below the plurality of isolation structures 30. According to this configuration, electric field concentration on the plurality of isolation structures 30 is suppressed by both the plurality of shallow well regions 35 and the deep well region 36. In addition, local electric field concentration on the plurality of shallow well regions 35 is alleviated by the deep well region 36.

[0553] The one or more shallow well regions 35 may be formed in a region below one or more of the isolation structures 30 located on the active region 8 side among the plurality of isolation structures 30. The deep well region 36 may be formed in a region below one of the isolation structures 30 located on the peripheral region 9 side among the plurality of isolation structures 30.

[0554] According to this configuration, electric field concentration on one or more isolation structures 30 located on the active region 8 side is alleviated by one or more shallow well regions 35. In addition, electric field concentration on one or more isolation structures 30 located on the peripheral region 9 side is alleviated by one or more deep well regions 36.

[0555] Furthermore, with this configuration, the depletion layer spreads from one or more shallow well regions 35 to shallow regions on the active region 8 side. On the other hand, the depletion layer spreads from the deep well region 36 to deep regions on the peripheral region 9 side. Therefore, the edge portions of the depletion layer originating from one or more shallow well regions 35 are pushed downward by the deep well region 36 in the region on the peripheral region 9 side. This appropriately alleviates electric field concentration in the vicinity of the isolation structure 30 located on the peripheral region 9 side.

[0556] In this case, the deep well region 36 may be formed in a region below the outermost isolation structure 30 located on the peripheral region 9 side among the plurality of isolation structures 30. According to this configuration, electric field concentration in the vicinity of the outermost isolation structure 30 is appropriately alleviated.

[0557] The semiconductor device 1A may include a p-type body region 10. The body region 10 may be formed in a surface layer portion of the second semiconductor region 7 in the active region 8. In this case, the isolation structure 30 may be located below the bottom of the body region 10. The deep well region 36 may be located below the bottom of the body region 10.

[0558] With this configuration, the depletion layer in the active region 8 spreads from the body region 10 to a shallow region. On the other hand, the depletion layer in the peripheral region 9 spreads from the deep well region 36 to a deep region. Therefore, the edge of the depletion layer starting from the body region 10 is pushed downward by the deep well region 36 in the region on the peripheral region 9 side. This appropriately alleviates electric field concentration in the vicinity of the isolation structure 30 located on the peripheral region 9 side.

[0559] The semiconductor device 1A may include a trench-type gate structure 15 to which a gate potential is applied. The gate structure 15 may be formed on the first main surface 3 in the active region 8. In this case, the deep well region 36 may be formed below the bottom wall of the gate structure 15.

[0560] With this configuration, the edge portion of the depletion layer extending into the region below the gate structure 15 is appropriately pushed downward by the deep well region 36 in the region on the peripheral region 9 side. As a result, electric field concentration is appropriately alleviated in the vicinity of the isolation structure 30 located on the peripheral region 9 side.

[0561] In this case, the isolation structure 30 may have a depth equal to or greater than the depth of the gate structure 15. According to this configuration, the location where the deep well region 36 is formed can be appropriately set in a region below the bottom wall of the gate structure 15.

[0562] The semiconductor device 1A may include a trench-type source structure 20 to which a source potential is applied. The source structure 20 may be formed on the first main surface 3 in the active region 8. In this case, the deep well region 36 may be formed below the bottom wall of the source structure 20.

[0563] According to this configuration, the edge portion of the depletion layer extending into the region below the source structure 20 is appropriately pushed downward by the deep well region 36 in the region on the peripheral region 9 side. As a result, electric field concentration is appropriately alleviated in the vicinity of the isolation structure 30 located on the peripheral region 9 side.

[0564] In this case, the isolation structure 30 may have a depth equal to or greater than the depth of the source structure 20. According to this configuration, the location where the deep well region 36 is formed can be appropriately set in a region below the bottom wall of the source structure 20.

[0565] The semiconductor device 1A may include a p-type outer well region 40. The outer well region 40 may be formed in the surface layer of the second semiconductor region 7 along the isolation structure 30 in the peripheral region 9. With this configuration, the depletion layer originating from the deep well region 36 is pushed and spread toward the peripheral region 9 by the depletion layer originating from the outer well region 40. This appropriately alleviates electric field concentration near the isolation structure 30.

[0566] The outer well region 40 may have a depth smaller than or greater than the depth of the deep well region 36. The depth of the outer well region 40 may be smaller than or greater than the depth of the isolation structure 30.

[0567] The semiconductor device 1A may include a p-type termination region 42. The termination region 42 may be formed in a surface layer portion of the first main surface 3 of the peripheral region 9 in a region between the periphery of the first main surface 3 and the outer well region 40. With this configuration, the depletion layer originating from the outer well region 40 is pushed and spread toward the peripheral region 9 by the depletion layer originating from the termination region 42. This appropriately alleviates electric field concentration near the isolation structure 30 and near the outer well region 40.

[0568] The semiconductor device 1A may include a plurality of p-type field regions 43. The plurality of field regions 43 may be formed at intervals in the surface layer portion of the second semiconductor region 7 in the region between the periphery of the first main surface 3 of the peripheral region 9 and the isolation structure 30. With this configuration, the depletion layer originating from the deep well region 36 is pushed and spread toward the periphery of the chip 2 by the depletion layer originating from the plurality of field regions 43. This appropriately alleviates electric field concentration near the isolation structure 30.

[0569] The semiconductor device 1A may include an outer wiring 46 and a source electrode 51 (terminal electrode). The outer wiring 46 may be electrically connected to the isolation structure 30 above the isolation structure 30. The source electrode 51 may be electrically connected to the outer wiring 46 above the outer wiring 46. With this configuration, a source potential is applied to the isolation structure 30 as a terminal potential. In other words, the deep well region 36 can be formed in a region below the isolation structure 30 to which a specific potential is applied (i.e., the isolation structure 30 with a source set).

[0570] Fig. 12 is a cross-sectional view showing an active region 8 of a semiconductor device 1B according to the second embodiment. Fig. 13 is a cross-sectional view showing a deep well region 36 of the semiconductor device 1B shown in Fig. 12. Fig. 14 is a cross-sectional view showing a peripheral region 9 of the semiconductor device 1B shown in Fig. 12. Referring to Figs. 12 to 14, the semiconductor device 1B has a configuration in which the configurations of the plurality of gate structures 15, the plurality of source structures 20, and the plurality of isolation structures 30 of the semiconductor device 1A are modified.

[0571] The plurality of source structures 20 have a depth greater than a depth of the plurality of gate structures 15. The bottom walls of the plurality of source structures 20 are located closer to the bottom of the second semiconductor region 7 than the bottom walls of the plurality of gate structures 15.

[0572] The ratio of the depth of source structure 20 to the depth of gate structure 15 (depth ratio) may be greater than 1 and less than or equal to 3. The depth ratio may have a value belonging to at least one of the following ranges: greater than 1 and less than or equal to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3.

[0573] The aforementioned isolation structures 30 have a depth greater than that of the gate structures 15. The bottom walls of the isolation structures 30 are located closer to the bottom of the second semiconductor region 7 than the bottom walls of the gate structures 15.

[0574] The depth of the plurality of isolation structures 30 may be equal to or greater than the depth of the plurality of source structures 20. The depth of the plurality of isolation structures 30 is preferably approximately equal to the depth of the plurality of source structures 20. The bottom walls of the plurality of isolation structures 30 are preferably positioned at a depth approximately equal to the depth of the bottom walls of the plurality of source structures 20. The depth of the plurality of isolation structures 30 may be greater than or less than the depth of the plurality of source structures 20.

[0575] The ratio of the depth of the isolation structure 30 to the depth of the gate structure 15 (depth ratio) may be greater than 1 and less than or equal to 3. The depth ratio may have a value belonging to at least one of the following ranges: greater than 1 and less than or equal to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3.

[0576] The aforementioned multiple gate well regions 25, multiple source well regions 26, multiple gate contact regions 27, multiple source contact regions 28, one or more (multiple in this embodiment) shallow well regions 35, one or more (one in this embodiment) deep well regions 36, one or more (multiple in this embodiment) shallow contact regions 37, and one or more (one in this embodiment) deep contact regions 38 are formed in the same layout as in the first embodiment.

[0577] In this embodiment, the semiconductor device 1B includes the deep well region 36 according to the first embodiment. The semiconductor device 1B may include at least one of the deep well regions 36 according to the first to eighth embodiments. The semiconductor device 1B may simultaneously include at least two of the deep well regions 36 according to the first to eighth embodiments in the same cross-sectional area or different cross-sectional areas.

[0578] In this embodiment, the plurality of source well regions 26 are located closer to the bottom of the second semiconductor region 7 than the bottom walls of the plurality of gate structures 15, and are opposed to one another in the horizontal direction across a part of the second semiconductor region 7. The bottoms of the plurality of source well regions 26 are located closer to the bottom of the second semiconductor region 7 than the bottoms of the plurality of gate well regions 25.

[0579] The plurality of source well regions 26 are located closer to the bottom of the second semiconductor region 7 than the bottoms of the plurality of gate well regions 25, and do not face the plurality of gate well regions 25 in the horizontal direction. The plurality of source well regions 26 may have portions located closer to the first main surface 3 than the bottoms of the plurality of gate well regions 25, and may face the plurality of gate well regions 25 in the horizontal direction.

[0580] In this embodiment, the shallow well regions 35 are located closer to the bottom of the second semiconductor region 7 than the bottom walls of the gate structures 15. The bottoms of the shallow well regions 35 are located closer to the bottom of the second semiconductor region 7 than the bottoms of the gate well regions 25.

[0581] In this embodiment, the plurality of shallow well regions 35 are located closer to the bottom of the second semiconductor region 7 than the bottoms of the plurality of gate well regions 25, and do not face the plurality of gate well regions 25 in the horizontal direction. The plurality of shallow well regions 35 may have portions located closer to the first main surface 3 than the bottoms of the plurality of gate well regions 25, and may face the plurality of gate well regions 25 in the horizontal direction.

[0582] The plurality of shallow well regions 35 are formed at substantially the same depth as the plurality of source well regions 26, and face the plurality of source well regions 26 in the horizontal direction across a part of the second semiconductor region 7. The bottom of the shallow well region 35 may be located at substantially the same depth as the bottom of the source well region 26.

[0583] The bottom of the shallow well region 35 may be located closer to the first main surface 3 than the bottom of the source well region 26, or may be located closer to the bottom of the second semiconductor region 7. The depth of the shallow well region 35 may be greater than the depth of the source well region 26, or may be less than the depth of the source well region 26.

[0584] In this embodiment, the deep well region 36 is located closer to the bottom of the second semiconductor region 7 than the bottom walls of the plurality of gate structures 15. The bottom of the deep well region 36 is located closer to the bottom of the second semiconductor region 7 than the bottoms of the plurality of gate well regions 25, the bottoms of the plurality of source well regions 26, and the bottoms of the plurality of shallow well regions 35.

[0585] In this embodiment, the deep well region 36 is located closer to the bottom of the second semiconductor region 7 than the bottoms of the plurality of gate well regions 25, and does not face the plurality of gate well regions 25 in the horizontal direction. The deep well region 36 may have a portion located closer to the first main surface 3 than the bottoms of the plurality of gate well regions 25, and may face the plurality of gate well regions 25 in the horizontal direction.

[0586] The depth of the deep well region 36 is greater than the depth of the source well region 26. That is, the bottom of the deep well region 36 is located closer to the bottom of the second semiconductor region 7 than the bottom of the source well region 26. The depth of the deep well region 36 is greater than the depth of the shallow well region 35. That is, the bottom of the deep well region 36 is located closer to the bottom of the second semiconductor region 7 than the bottom of the shallow well region 35.

[0587] The deep well region 36 faces the plurality of source well regions 26 and the plurality of shallow well regions 35 in the horizontal direction. The deep well region 36 is located on the bottom side of the second semiconductor region 7 relative to the bottoms of the plurality of source well regions 26, and has a portion that does not face the plurality of source well regions 26 in the horizontal direction.

[0588] The deep well region 36 is connected to the horizontally outermost shallow well region 35. The deep well region 36 may be formed at a distance from the outermost shallow well region 35 in the horizontal direction, and may face the outermost shallow well region 35 in the horizontal direction with a part of the second semiconductor region 7 interposed therebetween.

[0589] The deep well region 36 has a plurality of (two or more) bulging portions 36a and one or more constricted portions 36b in the thickness direction of the chip 2. The plurality of bulging portions 36a include an upper bulging portion 36a and a lower bulging portion 36a.

[0590] The upper bulge portion 36a is positioned at approximately the same depth as the bulge portions 26a of the multiple source well regions 26 and the bulge portions 35a of the multiple shallow well regions 35. The upper bulge portion 36a is connected to the bulge portion 35a of the outermost shallow well region 35. The upper bulge portion 36a may be formed at a distance from the outermost shallow well region 35 in the horizontal direction.

[0591] The lower bulge 36 a is formed in a shape tapering toward the bottom. The lower bulge 36 a is located on the bottom side of the second semiconductor region 7 relative to the depth positions of the bottoms of the plurality of source well regions 26 and the plurality of shallow well regions 35, and does not face the plurality of source well regions 26 and the plurality of shallow well regions 35 in the horizontal direction.

[0592] The constricted portion 36b is formed in a region on the isolation structure 30 side with respect to the bottoms of the plurality of source well regions 26 and the bottoms of the plurality of shallow well regions 35, and faces the plurality of source well regions 26 in the horizontal direction. The constricted portion 36b may be located closer to the bottom of the second semiconductor region 7 than the bottoms of the plurality of source well regions 26 and the bottoms of the plurality of shallow well regions 35.

[0593] The constricted portion 36b is formed at a horizontal distance from the outermost shallow well region 35. The constricted portion 36b is formed in a region on the isolation structure 30 side with respect to the bottom of the outermost shallow well region 35, and faces the outermost shallow well region 35 in the horizontal direction. The constricted portion 36b may be located closer to the bottom of the second semiconductor region 7 than the bottom of the outermost shallow well region 35.

[0594] Fig. 15 is an enlarged plan view showing an active region 8 of a semiconductor device 1C according to a third embodiment. Fig. 16 is a cross-sectional view taken along line XVI-XVI shown in Fig. 15. Fig. 17 is a cross-sectional view taken along line XVII-XVII shown in Fig. 15. Fig. 18 is a cross-sectional view showing a peripheral region 9 of the semiconductor device 1C shown in Fig. 15.

[0595] 15 to 18 , semiconductor device 1C has a configuration obtained by modifying the configurations of multiple gate structures 15, multiple source structures 20, and multiple isolation structures 30 of semiconductor device 1A. Specifically, unlike semiconductor device 1A, semiconductor device 1C includes multiple gate structures 15 and multiple isolation structures 30, but does not include multiple source structures 20. Semiconductor device 1C does not include source well region 26 or source contact region 28.

[0596] In this embodiment, the multiple gate structures 15 are arranged adjacent to one another at intervals in the first direction X (=m-axis direction) and extend in strip shapes in the second direction Y (=a-axis direction). The multiple isolation structures 30 are arranged on the periphery of the active region 8 at intervals from the multiple gate structures 15. The multiple isolation structures 30 may each be formed in a polygonal ring shape (square ring shape) that collectively surrounds the multiple gate structures 15 in plan view.

[0597] The depth of the isolation structures 30 may be equal to or greater than the depth of the gate structures 15. The depth of the isolation structures 30 is preferably approximately equal to the depth of the gate structures 15. The depth of the isolation structures 30 may be greater than the depth of the gate structures 15 or may be less than the depth of the gate structures 15.

[0598] The aforementioned multiple gate well regions 25, multiple gate contact regions 27, one or more (multiple in this embodiment) shallow well regions 35, one or more (one in this embodiment) deep well regions 36, one or more (multiple in this embodiment) shallow contact regions 37, and one or more (one in this embodiment) deep contact regions 38 are formed in the same layout as in the first embodiment.

[0599] In this embodiment, the semiconductor device 1C includes the deep well region 36 according to the first embodiment. The semiconductor device 1C may include at least one of the deep well regions 36 according to the first to eighth embodiments. The semiconductor device 1C may simultaneously include at least two of the deep well regions 36 according to the first to eighth embodiments in the same cross-sectional region or different cross-sectional regions.

[0600] In this embodiment, the plurality of gate contact regions 27 are formed at intervals in the first direction X and the second direction Y. With respect to one gate structure 15 and the other gate structure 15, the plurality of gate contact regions 27 along one gate structure 15 face the plurality of gate contact regions 27 along the other gate structure 15 in the first direction X in a plan view.

[0601] That is, the plurality of gate contact regions 27 are generally arranged in a matrix in plan view at intervals in the first direction X and the second direction Y. In this case, the plurality of gate contact regions 27 along one gate structure 15 may be connected to the plurality of gate contact regions 27 along the other gate structure 15 in the surface layer portion of the body region 10.

[0602] The plurality of gate contact regions 27 along one gate structure 15 may face, in plan view, regions between the plurality of gate contact regions 27 along the other gate structure 15 in the first direction X. In other words, the plurality of gate contact regions 27 may be generally arranged in a staggered pattern in plan view with intervals in the first direction X and the second direction Y.

[0603] In this embodiment, the shallow well regions 35 are located closer to the bottom of the second semiconductor region 7 than the bottom walls of the gate structures 15. The shallow well regions 35 are formed to a depth substantially equal to the depth of the gate well regions 25, and face the gate well regions 25 in the horizontal direction.

[0604] The bottoms of the plurality of shallow well regions 35 may be located at a depth substantially equal to that of the bottom of the gate well region 25. The bottoms of the plurality of shallow well regions 35 may be located on the first main surface 3 side or on the second semiconductor region 7 side of the bottom of the gate well region 25. The depth of the shallow well region 35 may be greater than or less than the depth of the gate well region 25.

[0605] In this embodiment, the deep well region 36 is located closer to the bottom of the second semiconductor region 7 than the bottom walls of the plurality of gate structures 15. The depth of the deep well region 36 is greater than the depth of the gate well region 25 and the depth of the shallow well region 35.

[0606] In this embodiment, the upper end of the deep well region 36 is located closer to the isolation structure 30 than the bottoms of the gate well regions 25 and the shallow well regions 35. The upper end of the deep well region 36 faces the gate well regions 25 and the shallow well regions 35 in the horizontal direction.

[0607] The bottom of the deep well region 36 is located closer to the bottom of the second semiconductor region 7 than the bottoms of the plurality of gate well regions 25 and the bottoms of the plurality of shallow well regions 35. The bottom of the deep well region 36 does not face the plurality of gate well regions 25 and the plurality of shallow well regions 35 in the horizontal direction.

[0608] The deep well region 36 is connected to the horizontally outermost shallow well region 35. The deep well region 36 may be formed at a distance from the outermost shallow well region 35 in the horizontal direction, and may face the outermost shallow well region 35 in the horizontal direction with a part of the second semiconductor region 7 interposed therebetween.

[0609] The deep well region 36 has a plurality of (two or more) bulging portions 36a and one or more constricted portions 36b in the thickness direction of the chip 2. The plurality of bulging portions 36a include an upper bulging portion 36a and a lower bulging portion 36a.

[0610] The upper bulge portion 36a is positioned at approximately the same depth as the bulge portions 25a of the multiple gate well regions 25 and the bulge portions 35a of the multiple shallow well regions 35. The upper bulge portion 36a is connected to the bulge portion 35a of the outermost shallow well region 35. The upper bulge portion 36a may be formed at a distance from the outermost shallow well region 35 in the horizontal direction.

[0611] The lower bulge 36 a is formed in a shape tapering toward the bottom. The lower bulge 36 a is located on the bottom side of the second semiconductor region 7 relative to the depth positions of the bottoms of the plurality of gate well regions 25 and the plurality of shallow well regions 35, and does not face the plurality of gate well regions 25 and the plurality of shallow well regions 35 in the horizontal direction.

[0612] The constricted portion 36b is formed in a region on the isolation structure 30 side with respect to the bottoms of the plurality of gate well regions 25 and the plurality of shallow well regions 35, and faces the plurality of gate well regions 25 and the plurality of shallow well regions 35 in the horizontal direction. The constricted portion 36b may be located closer to the bottom of the second semiconductor region 7 than the bottoms of the plurality of gate well regions 25 and the plurality of shallow well regions 35.

[0613] The constricted portion 36b is formed at a horizontal distance from the outermost shallow well region 35. The constricted portion 36b is formed in a region on the isolation structure 30 side with respect to the bottom of the outermost shallow well region 35, and faces the outermost shallow well region 35 in the horizontal direction. The constricted portion 36b may be located closer to the bottom of the second semiconductor region 7 than the bottom of the outermost shallow well region 35.

[0614] Similar to the semiconductor device 1A, the semiconductor device 1C includes a plurality of source openings 49 formed in the interlayer film 47. In this embodiment, the plurality of source openings 49 are formed in regions between adjacent gate structures 15, respectively, and expose the source regions 11 and the plurality of gate contact regions 27, respectively.

[0615] Similar to the semiconductor device 1A, the semiconductor device 1C includes a source electrode 51 disposed on the first main surface 3. The source electrode 51 has a layered structure including a lower electrode film 52 and a main electrode film 53, which are layered in this order from the chip 2 side. Similar to the semiconductor device 1A, the lower electrode film 52 has a layered structure including a first electrode film 54 and a second electrode film 55.

[0616] The first electrode film 54 collectively covers the region of the interlayer film 47 where the plurality of source openings 49 are formed, and extends into the plurality of source openings 49 from above the interlayer film 47. The first electrode film 54 is mechanically and electrically connected to the source region 11 and the plurality of gate contact regions 27 within the plurality of source openings 49.

[0617] The second electrode film 55 collectively covers the region of the interlayer film 47 where the plurality of source openings 49 are formed, sandwiching the first electrode film 54 therebetween, and extends into the plurality of source openings 49 from above the interlayer film 47. The second electrode film 55 is electrically connected to the source region 11 and the plurality of gate contact regions 27 via the first electrode film 54 within the plurality of source openings 49.

[0618] The main electrode film 53 collectively covers the region of the interlayer film 47 where the plurality of source openings 49 are formed, and backfills the plurality of source openings 49. The main electrode film 53 is electrically connected to the source region 11 and the plurality of gate contact regions 27 via the lower electrode film 52 within the plurality of source openings 49.

[0619] Fig. 19 is a plan view showing a semiconductor device 1D according to the fourth embodiment. Fig. 20 is a cross-sectional view showing the peripheral portion of the active region 8 of the semiconductor device 1D shown in Fig. 19 together with the termination region 42 according to the first embodiment. Although Figs. 19 and 20 show the deep well region 36 according to the first embodiment, the semiconductor device 1D may have at least one of the deep well regions 36 according to the first to eighth embodiments, as in the case of the semiconductor device 1A.

[0620] Similar to the semiconductor device 1A, the semiconductor device 1D includes a termination region 42 formed in the outer peripheral region 9 in the surface layer portion of the first main surface 3. The termination region 42 has a modified form of the termination region 42 of the semiconductor device 1A. In the following, only the parts that are different from the termination region 42 of the semiconductor device 1A will be described, and a description of the common parts will be omitted. For the omitted parts, the description of the termination region 42 of the semiconductor device 1A will apply.

[0621] Similar to the case of semiconductor device 1A, termination region 42 has an inner edge portion on the active region 8 side and an outer edge portion on the peripheral side of first main surface 3. The inner edge portion of termination region 42 has an inner edge portion positioned closer to active region 8 than one or more isolation structures 30.

[0622] In this embodiment, the inner edge of the termination region 42 is located closer to the active region 8 than at least the isolation structures 30 (i.e., the outermost isolation structures 30) located on the first main surface 3 side. That is, in this embodiment, the termination region 42 has a portion (inner edge) located in a region between the multiple isolation structures 30. In this embodiment, the termination region 42 is connected to the body region 10, the shallow contact region 37, and the deep contact region 38 in the active region 8.

[0623] The inner edge of the termination region 42 may be connected to the isolation structure 30 adjacent to the outermost isolation structure 30. The inner edge of the termination region 42 may be spaced apart from the isolation structure 30 adjacent to the outermost isolation structure 30.

[0624] Similar to the semiconductor device 1A, termination region 42 has an upper end located on the first main surface 3 side and a bottom located on the bottom side of second semiconductor region 7. The configuration of termination region 42 on the peripheral region 9 side is similar to that of semiconductor device 1A. The configuration of termination region 42 on the active region 8 side will be described below.

[0625] The upper end of the termination region 42 extends horizontally along the first main surface 3 in the active region 8. The upper end of the termination region 42 is located on the first main surface 3 side with respect to the depth position of the bottom of the deep well region 36 in the active region 8.

[0626] The upper end of the termination region 42 is located closer to the first main surface 3 than the depth position of the bottom of the shallow well region 35 in the active region 8. The upper end of the termination region 42 is located closer to the first main surface 3 than the depth position of the bottom of the gate well region 25 in the active region 8. The upper end of the termination region 42 is located closer to the first main surface 3 than the depth position of the bottom of the source well region 26 in the active region 8.

[0627] The upper end of the termination region 42 is located closer to the first main surface 3 than the depth position of the bottom wall of the isolation structure 30 in the active region 8. The upper end of the termination region 42 is located closer to the first main surface 3 than the depth position of the bottom wall of the gate structure 15 in the active region 8. The upper end of the termination region 42 is located closer to the first main surface 3 than the depth position of the bottom wall of the source structure 20 in the active region 8.

[0628] The upper end of the termination region 42 is located closer to the first main surface 3 than the depth position of the bottom of the body region 10 in the active region 8, and is connected to the body region 10. The upper end of the termination region 42 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the body region 10 in the active region 8.

[0629] The upper end of the termination region 42 may be located closer to the bottom of the second semiconductor region 7 than the depth positions of the upper ends of the shallow contact region 37 and the deep contact region 38. The upper end of the termination region 42 may be connected to the upper ends of the shallow contact region 37 and the deep contact region 38.

[0630] The bottom of the termination region 42 extends horizontally along the first main surface 3 in the active region 8. The bottom of the termination region 42 is located closer to the first main surface 3 than the depth position of the bottom of the deep well region 36 in the active region 8. The bottom of the termination region 42 is located closer to the first main surface 3 than the depth position of the bottom of the shallow well region 35 in the active region 8.

[0631] The bottom of termination region 42 is located closer to first main surface 3 than the depth position of the bottom of gate well region 25 in active region 8. The bottom of termination region 42 is located closer to first main surface 3 than the depth position of the bottom of source well region 26 in active region 8. In this embodiment, the bottom of termination region 42 is located closer to first main surface 3 than the depth position of the bottom wall of isolation structure 30 in active region 8.

[0632] That is, isolation structure 30 penetrates the inner edge of termination region 42 in the thickness direction. In this embodiment, the bottom of termination region 42 is located on the bottom wall side of isolation structure 30 relative to the depth position of the bottom of body region 10, and forms a p-n junction with second semiconductor region 7. That is, the bottom of termination region 42 forms a p-n junction with second semiconductor region 7 in the region between multiple isolation structures 30.

[0633] The bottom of the termination region 42 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the isolation structure 30 in the active region 8. In this case, the bottom of the termination region 42 may be connected to either or both of the shallow well region 35 and the deep well region 36.

[0634] The bottom of termination region 42 may be located on the first main surface 3 side of the depth position of the bottom wall of gate structure 15 in active region 8, or may be located on the bottom side of second semiconductor region 7 side of the depth position of the bottom wall of gate structure 15. The bottom of termination region 42 may be located on the first main surface 3 side of the depth position of the bottom wall of source structure 20 in active region 8, or may be located on the bottom side of second semiconductor region 7 side of the depth position of the bottom wall of source structure 20.

[0635] 21A to 21F are cross-sectional views showing termination regions 42 according to the second to seventh embodiments. A semiconductor device 1D may include at least one of the termination regions 42 according to the first to seventh embodiments. The semiconductor device 1D may simultaneously include at least two of the termination regions 42 according to the first to seventh embodiments in the same cross-sectional region or different cross-sectional regions.

[0636] 21A (second embodiment), the inner edge of the termination region 42 may be located closer to the active region 8 than the plurality of isolation structures 30. In this embodiment, the inner edge of the termination region 42 is located closer to the active region 8 than two isolation structures 30, including the outermost isolation structure 30. The inner edge of the termination region 42 may be connected to the isolation structure 30 on the active region 8 side, or may be spaced apart from the isolation structure 30 on the active region 8 side.

[0637] 21B (third embodiment), the inner edge of the termination region 42 may be located closer to the active region 8 than the plurality of isolation structures 30. In this embodiment, the inner edge of the termination region 42 is located closer to the active region 8 than three isolation structures 30, including the outermost isolation structure 30. The inner edge of the termination region 42 may be connected to the isolation structure 30 on the active region 8 side, or may be spaced apart from the isolation structure 30 on the active region 8 side.

[0638] 21C (fourth embodiment), the inner edge of the termination region 42 may be located closer to the active region 8 than the plurality of isolation structures 30. In this embodiment, the inner edge of the termination region 42 is located closer to the active region 8 than four isolation structures 30, including the outermost isolation structure 30. The inner edge of the termination region 42 may be connected to the isolation structure 30 on the active region 8 side, or may be spaced apart from the isolation structure 30 on the active region 8 side.

[0639] 21D (fifth embodiment), the inner edge of termination region 42 may be located closer to active region 8 than all of the isolation structures 30. The inner edge of termination region 42 may be located in a region between the innermost isolation structure 30 and the outermost gate structure 15. In this case, the inner edge of termination region 42 may be connected to gate structure 15, or may be formed spaced apart from gate structure 15. The inner edge of termination region 42 may be connected to body region 10 in a region between the innermost isolation structure 30 and the outermost gate structure 15.

[0640] The inner edge of the termination region 42 may be located in the region between the innermost isolation structure 30 and the outermost source structure 20. In this case, the inner edge of the termination region 42 may be connected to the source structure 20 or may be spaced apart from the source structure 20. The inner edge of the termination region 42 may be connected to the body region 10 in the region between the innermost isolation structure 30 and the outermost source structure 20.

[0641] Referring to Figure 21E (sixth embodiment), when the inner edge of the termination region 42 is located closer to the active region 8 than one or more isolation structures 30, it is not necessarily necessary to form a deep well region 36, and a shallow well region 35 and a shallow contact region 37 may be formed for one or more isolation structures 30.

[0642] 21F (seventh embodiment), when the inner edge of termination region 42 is located closer to active region 8 than one or more isolation structures 30, it is not necessarily necessary to form either or both of shallow well region 35 and deep well region 36. In this case, either or both of shallow contact region 37 and deep contact region 38 may not be formed.

[0643] As described above, the semiconductor device 1D includes the chip 2, the n-type second semiconductor region 7 (semiconductor region), the active region 8, the peripheral region 9, the trench-type isolation structure 30, and the p-type (second conductivity type) termination region 42. The chip 2 has a first main surface 3. The second semiconductor region 7 is formed in a surface layer portion of the first main surface 3. The active region 8 is provided in an inner portion of the first main surface 3. The peripheral region 9 is provided in the peripheral portion of the first main surface 3.

[0644] The isolation structure 30 is formed on the first main surface 3 so as to be located within the second semiconductor region 7, and defines the active region 8 and the peripheral region 9. The termination region 42 is arranged on the peripheral edge side of the chip 2 relative to the isolation structure 30 so as to be located within the second semiconductor region 7 in the peripheral region 9.

[0645] This configuration provides a semiconductor device 1D with a novel layout. For example, in this semiconductor device 1D, the depletion layer extends from the termination region 42 into the second semiconductor region 7. This reduces the electric field near the isolation structure 30, suppressing a decrease in breakdown voltage due to electric field concentration. In other words, a decrease in breakdown voltage originating from the boundary region between the active region 8 and the peripheral region 9 is suppressed.

[0646] The chip 2 may include SiC. This configuration provides a semiconductor device 1D as a SiC semiconductor device having a novel layout. The physical properties of SiC further improve the breakdown voltage of the semiconductor device 1D. In particular, since SiC semiconductor devices are used in relatively high-voltage environments, the electric field relaxation effect (the effect of suppressing a decrease in breakdown voltage) provided by the termination region 42 is effective.

[0647] Termination region 42 may have an inner edge located closer to active region 8 than isolation structure 30. With this configuration, in the region closer to active region 8 than isolation structure 30, a depletion layer extends from termination region 42 into second semiconductor region 7. This reduces the electric field near isolation structure 30, and suppresses a decrease in breakdown voltage due to electric field concentration.

[0648] A plurality of isolation structures 30 may be formed at intervals on the first main surface 3. In this case, the inner edge of the termination region 42 may be located closer to the active region 8 than the outermost isolation structure 30 arranged on the periphery of the chip 2. This configuration alleviates the electric field near the outermost isolation structure 30, thereby suppressing a decrease in breakdown voltage (breakdown voltage) due to electric field concentration. The inner edge of the termination region 42 may be located closer to the active region 8 than the plurality of isolation structures 30. This configuration appropriately alleviates the electric field near the plurality of isolation structures 30.

[0649] Termination region 42 may have a portion located closer to first main surface 3 than the depth position of the bottom wall of isolation structure 30. Termination region 42 may have a bottom located closer to first main surface 3 than the depth position of the bottom wall of isolation structure 30. Termination region 42 may be formed in a surface layer portion of first main surface 3 at a distance from first main surface 3.

[0650] The semiconductor device 1D may include a p-type shallow well region 35 (well region). The shallow well region 35 may be formed in a region below the isolation structure 30 so as to be located within the second semiconductor region 7, and may be electrically connected to the second semiconductor region 7.

[0651] With this configuration, the depletion layer extends from the shallow well region 35 into the second semiconductor region 7, and at the same time, the depletion layer extends from the termination region 42 into the second semiconductor region 7. With this configuration, electric field concentration in the isolation structure 30 is suppressed by both the shallow well region 35 and the termination region 42. In this case, the termination region 42 may be electrically connected to the shallow well region 35. The termination region 42 may have a bottom located closer to the first main surface 3 than the depth position of the bottom of the shallow well region 35.

[0652] The semiconductor device 1D may include a p-type deep well region 36 (well region). The deep well region 36 may be formed in a region below the isolation structure 30 so as to be located within the second semiconductor region 7, and may be electrically connected to the second semiconductor region 7.

[0653] With this configuration, the depletion layer extends from the deep well region 36 into the second semiconductor region 7, and at the same time, the depletion layer extends from the termination region 42 into the second semiconductor region 7. With this configuration, electric field concentration in the isolation structure 30 is suppressed by both the deep well region 36 and the termination region 42. In this case, the termination region 42 may be electrically connected to the deep well region 36. The termination region 42 may have a bottom located closer to the first main surface 3 than the depth position of the bottom of the deep well region 36.

[0654] The semiconductor device 1D may include a p-type outer well region 40. The outer well region 40 may be arranged on the peripheral side of the chip 2 relative to the isolation structure 30 so as to be located within the second semiconductor region 7 in the peripheral region 9. In this case, the termination region 42 may have a portion located on the peripheral side of the chip 2 relative to the outer well region 40.

[0655] According to this configuration, the depletion layer originating from the outer well region 40 is pushed out toward the periphery of the chip 2 by the depletion layer originating from the termination region 42. This appropriately alleviates the electric field concentration near the isolation structure 30.

[0656] The termination region 42 may be located below the bottom of the outer well region 40. With this configuration, the depletion layer originating from the outer well region 40 is appropriately pushed out toward the periphery of the chip 2 by the depletion layer originating from the termination region 42.

[0657] The semiconductor device 1D may include a p-type body region 10. The body region 10 may be formed in a surface layer portion of the semiconductor region in the active region 8. In this case, the isolation structure 30 may be located in a region below the bottom of the body region 10. The termination region 42 may have a portion located below the bottom of the body region 10.

[0658] With this configuration, the depletion layer in the active region 8 spreads from the body region 10 to a shallow region. On the other hand, the depletion layer in the peripheral region 9 spreads from the termination region 42 to a deep region. Therefore, the edge of the depletion layer starting from the body region 10 is pushed downward by the termination region 42 in the region on the peripheral region 9 side. This appropriately alleviates electric field concentration in the vicinity of the isolation structure 30 located on the peripheral region 9 side.

[0659] The semiconductor device 1D may include a trench-type gate structure 15. The gate structure 15 may be formed on the first main surface 3 in the active region 8. In this case, the termination region 42 may be formed below the bottom wall of the gate structure 15.

[0660] With this configuration, the edge portion of the depletion layer extending into the region below the gate structure 15 is appropriately pushed downward by the termination region 42 in the region on the peripheral region 9 side. This appropriately alleviates electric field concentration in the vicinity of the isolation structure 30 located on the peripheral region 9 side. The isolation structure 30 may have a depth equal to or greater than the depth of the gate structure 15.

[0661] The semiconductor device 1D may include a trench-type source structure 20. The source structure 20 may be formed on the first main ...

Claims

1. A semiconductor device comprising: a chip having a main surface; a semiconductor region of a first conductivity type formed on a surface layer portion of the main surface; an active region provided in an inner portion of the main surface; a peripheral region provided on a peripheral portion of the main surface; a trench-type isolation structure formed on the main surface so as to be located within the semiconductor region, separating the active region and the peripheral region; and a well region of a second conductivity type formed in a region below the isolation structure so as to be located within the semiconductor region, and electrically connected to the semiconductor region.

2. The semiconductor device according to claim 1, wherein the chip comprises SiC.

3. The semiconductor device according to claim 1 or 2, wherein said well region is formed in a vertically elongated columnar shape extending in a thickness direction of said chip.

4. The semiconductor device according to claim 1, wherein the well region is formed at a distance from the bottom of the semiconductor region toward the main surface.

5. A semiconductor device according to any one of claims 1 to 4, wherein the well region has a bulge extending horizontally along the main surface, and a constriction recessed in the horizontal direction relative to the bulge at a depth position different from that of the bulge.

6. The semiconductor device according to claim 1, wherein the well region includes a plurality of impurity regions of the second conductivity type formed at different depth positions so as to be connected to each other.

7. A semiconductor device according to any one of claims 1 to 6, wherein a plurality of said isolation structures are formed at intervals on said main surface, and said well region is formed in a region below at least one of said isolation structures.

8. The semiconductor device according to claim 7, wherein said well region is formed in a region below said isolation structure that is located on the outer periphery region side among the plurality of said isolation structures.

9. The semiconductor device according to claim 7 or 8, wherein said well region is not formed in a region below said isolation structure located on the active region side among said plurality of isolation structures.

10. A semiconductor device as claimed in any one of claims 7 to 9, further comprising a shallow well region of a second conductivity type formed in a region below at least one of said isolation structures so as to be positioned within said semiconductor region and electrically connected to said semiconductor region, said well region having a depth greater than a depth of said shallow well region, and formed in a region below said isolation structure in a region other than said shallow well region.

11. The semiconductor device according to claim 10, wherein a plurality of said shallow well regions are formed in regions below a plurality of said isolation structures, respectively.

12. A semiconductor device according to any one of claims 1 to 11, further comprising a body region of a second conductivity type formed in a surface layer portion of the semiconductor region in the active region, the isolation structure being positioned in a region below a bottom of the body region, and the well region being positioned below a bottom of the body region.

13. The semiconductor device according to any one of claims 1 to 12, further comprising a trench-type gate structure formed on the main surface in the active region, the well region being formed below a bottom wall of the gate structure.

14. The semiconductor device according to claim 13, wherein said isolation structure has a depth equal to or greater than a depth of said gate structure.

15. The semiconductor device according to any one of claims 1 to 14, further comprising a trench-type source structure formed in the main surface in the active region, the well region being formed below a bottom wall of the source structure.

16. The semiconductor device according to claim 15, wherein said isolation structure has a depth equal to or greater than a depth of said source structure.

17. The semiconductor device according to claim 1, further comprising an outer well region of a second conductivity type formed in a surface layer of said semiconductor region along said isolation structure in said peripheral region.

18. The semiconductor device according to claim 17, wherein the outer well region has a depth smaller than a depth of the well region.

19. The semiconductor device according to any one of claims 1 to 18, further comprising a plurality of field regions of the second conductivity type formed at intervals in a surface layer portion of the semiconductor region in a region between the periphery of the main surface and the isolation structure.

20. The semiconductor device according to any one of claims 1 to 19, further comprising: an outer wiring electrically connected to said isolation structure on said main surface; and a terminal electrode electrically connected to said outer wiring on said main surface.

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