Neuromorphic device and operating method thereof

Abstract

The present invention relates to a neuromorphic device and an operating method thereof. The neuromorphic device includes a non-volatile memory array including: a plurality of bit lines; a plurality of word lines; and an ambipolar transistor disposed in a region in which the bit lines and the word lines cross each other. Therefore, the present invention can perform a two-layer operation by implanting different weights into two current regions present in the bipolar transistor.

Description

Neuromorphic device and its operating method

[0001] The present invention relates to a neuromorphic hardware structure, and more particularly, to a neuromorphic device capable of performing multi-layer artificial neural network operations in a single non-volatile memory array by utilizing the characteristics of an ambipolar transistor, and an operating method thereof.

[0002]

[0003] With the recent rapid advancements in deep learning technology, the amount of data and the number of layers required for training and operating neural networks are rapidly increasing. To process this massive data volume, parallel computing circuits such as GPUs (Graphics Processing Units) are being used. However, data communication consumes significant power, leading to a rapidly growing need for semiconductor devices capable of more efficient neural network computation.

[0004] Existing hardware operates based on the switching behavior of logic elements, making it unsuitable for neural network operations that require parallel multi-operation. Furthermore, due to the limitations of the von Neumann architecture, intensive data transfer between memory and processors is a major cause of reduced speed and energy efficiency.

[0005] Neuromorphic hardware with various architectures, such as Static Random Access Memory (SRAM) and Resistive RAM (RRAM), has been proposed for large-scale parallel computation. However, due to extremely low memory density and low technological maturity, it is difficult to simultaneously achieve high-precision and low-power characteristics. Furthermore, the need for circuits such as the Analog-to-Digital Converter (ADC) to convert the results of analog parallel computations results in additional area and power consumption in the overall hardware, resulting in no significant advantages in performance or power efficiency compared to conventional digital parallel computation. Therefore, reducing the amount of driving circuits, such as ADCs, is of utmost importance.

[0006]

[0007] [Prior Art Literature]

[0008] [Patent Document]

[0009] (Patent Document 1) Publication No. 10-2021-0115735 (September 27, 2021)

[0010]

[0011] One embodiment of the present invention provides a neuromorphic device capable of performing two-layer operations with one array in a multi-layer artificial neural network operation by applying a bipolar transistor-based non-volatile memory device in which two current mechanisms exist in one device, and an operating method thereof.

[0012] One embodiment of the present invention provides a neuromorphic device and an operating method thereof that can be configured in a much smaller area than existing neuromorphic hardware and can greatly increase power efficiency by reducing by half the number of ADCs that sense output values, which account for the largest power consumption in neuromorphic hardware operations.

[0013]

[0014] In one embodiment, the neuromorphic device includes a nonvolatile memory array comprising a plurality of bit lines; a plurality of word lines; and an ambipolar transistor disposed in an area where the bit lines and the word lines intersect.

[0015] The above non-volatile memory array can use the above bipolar transistor as a synaptic element.

[0016] The above non-volatile memory array can perform two-layer operations by implanting different weights into two current regions present in the bipolar transistor.

[0017] The above non-volatile memory array can perform weight transplantation for learning of multiple layers by alternately applying specific voltages of first polarity and second polarity to word lines and bit lines connected to specific synaptic elements among the plurality of bit lines and the plurality of word lines.

[0018] The above non-volatile memory array can implant different weights into each region by applying a specific voltage of a first polarity to a forward region of the bipolar transistor and applying a specific voltage of a second polarity different from the first polarity to an ambipolar region of the bipolar transistor.

[0019] The above non-volatile memory array can perform weight transplantation by applying a specific voltage to a word line and a bit line connected to a target element among the plurality of bit lines and the plurality of word lines, and causing the remaining word lines and bit lines to be grounded (GND) or floating.

[0020] Among the embodiments, the neuromorphic element is a multi-layer artificial neural network processing neuromorphic element, including a plurality of bit lines arranged to extend along a first direction; a plurality of word lines arranged to extend along a second direction perpendicular to the first direction; and a plurality of synaptic elements positioned in an area where the bit lines and the word lines intersect, wherein the synaptic element may include a bipolar transistor configured with two current regions.

[0021] The above bipolar transistor may include a tunneling transistor or a ferroelectric tunneling transistor.

[0022] The above bipolar transistor has two or more different current mechanisms depending on the gate voltage, and may include a forward region and an ambipolar region with symmetrical current characteristics depending on the voltage.

[0023] Among the embodiments, the neuromorphic element can store two weights in one synaptic element by controlling the forward region and the ambipolar region, respectively, in the bipolar transistor-based non-volatile memory element.

[0024] In embodiments, a neuromorphic element may perform two analog vector matrix operations (VMMs) on a single synaptic array when storing different weights in the forward region and the ambipolar region.

[0025] Among the embodiments, a method of operating a neuromorphic device includes a method of operating a neuromorphic device using a bipolar transistor arranged in an array of nonvolatile memories formed along a plurality of bit lines and a plurality of word lines, the method comprising: transplanting a first weight into a first region of the bipolar transistor; transplanting a second weight into a second region of the bipolar transistor; performing a first layer operation using a current of the first region and the transplanted first weight; and performing a second layer operation using a current of the second region and the transplanted second weight.

[0026] The above bipolar transistor has two or more different current mechanisms depending on the gate voltage, and may include a forward region and an ambipolar region with symmetrical current characteristics depending on the voltage.

[0027] The step of transplanting the first weight may perform weight transplantation in one of the forward region and the ambipolar region of the bipolar transistor by applying a specific voltage of the first polarity to the gate of the bipolar transistor.

[0028] The step of transplanting the second weight may perform weight transplantation to the remaining region of the bipolar transistor by applying a specific voltage of the second polarity to the gate of the bipolar transistor.

[0029] The steps of transplanting the first and second weights can store two weights in one synaptic element by controlling the forward region and the ambipolar region of the bipolar transistor, respectively.

[0030] The above first layer operation step operates with the weight of the forward region of the bipolar transistor and the voltage time (T) applied to the gate of the bipolar transistor pluse ) can be used to adjust the size of the input signal.

[0031] The second layer operation step is operated with the weight of the ambipolar region of the bipolar transistor and the voltage time (T) applied to the gate of the bipolar transistor pluse ) can be used to adjust the size of the input signal.

[0032] The above first and second layer operation steps can perform a weight and voltage multiplication operation by reading the current of the forward region and the ambipolar region of the bipolar transistor, respectively.

[0033] The above first and second layer operation steps can obtain operation results by sensing current through an ADC.

[0034]

[0035] The disclosed technology may have the following effects. However, this does not mean that a particular embodiment must include all or only the following effects, and thus the scope of the disclosed technology should not be construed as being limited thereby.

[0036] A neuromorphic device and its operating method according to one embodiment of the present invention can perform two layer operations with one array in a multi-layer artificial neural network operation by applying a bipolar transistor-based non-volatile memory device in which two current mechanisms exist in one device.

[0037] A neuromorphic device and its operating method according to one embodiment of the present invention can be configured in a much smaller area than existing neuromorphic hardware, and the number of ADCs that sense output values, which account for the largest power consumption in neuromorphic hardware operations, can be reduced by half, thereby greatly increasing power efficiency.

[0038]

[0039] Figure 1 is a drawing for explaining the structure and operation method of neuromorphic hardware.

[0040] Figure 2 is a diagram illustrating a neuromorphic hardware structure for multi-layer artificial neural network operations using a conventional MOSFET-based NVM.

[0041] FIGS. 3A-3C are drawings illustrating a neuromorphic device according to one embodiment of the present invention.

[0042] FIG. 4 is a diagram for explaining a weight transplant operation of a neuromorphic device according to one embodiment of the present invention.

[0043] Fig. 5 is a drawing for explaining an embodiment using a FeTFET device.

[0044] FIG. 6 is a diagram for explaining a neuromorphic hardware structure according to one embodiment of the present invention.

[0045] Figure 7 is a diagram showing the individual weight measurement results by two current mechanisms of a bipolar transistor.

[0046] FIGS. 8A-8C are diagrams for explaining a neuromorphic hardware structure and operating method according to one embodiment of the present invention.

[0047]

[0048] The description of the present invention is merely an example for structural and functional explanation, and therefore, the scope of the present invention should not be construed as being limited by the embodiments described in the text. That is, since the embodiments can be modified in various ways and can take various forms, the scope of the present invention should be understood to include equivalents that can realize the technical idea. In addition, the purposes or effects presented in the present invention do not mean that a specific embodiment must include all of them or only such effects, and therefore, the scope of the present invention should not be construed as being limited thereby.

[0049] Meanwhile, the meaning of the terms described in this application should be understood as follows.

[0050] Terms such as "first" and "second" are intended to distinguish one component from another, and the scope of the rights should not be limited by these terms. For example, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

[0051] When a component is said to be "connected" to another component, it should be understood that while it may be directly connected to that other component, there may also be other components intervening. Conversely, when a component is said to be "directly connected" to another component, it should be understood that there are no other intervening components. Similarly, other expressions describing relationships between components, such as "between" and "directly between," or "adjacent to" and "directly adjacent to," should be interpreted similarly.

[0052] Singular expressions should be understood to include plural expressions unless the context clearly indicates otherwise, and terms such as "comprises" or "have" should be understood to specify the presence of a feature, number, step, operation, component, part or combination thereof, but not to exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0053] For each step, the identifiers (e.g., a, b, c, etc.) are used for convenience of explanation and do not describe the order of the steps. The steps may occur in a different order than stated unless the context clearly dictates a specific order. That is, the steps may occur in the same order as stated, may be performed substantially simultaneously, or may be performed in the opposite order.

[0054] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted to be consistent with their meaning within the context of the relevant technology, and should not be interpreted as having an idealized or overly formal meaning unless explicitly defined herein.

[0055] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are designated by the same reference numerals, and redundant descriptions of identical components are omitted.

[0056]

[0057] As AI technology advances, more data processing becomes essential for AI computation. However, existing computing methods suffer from a bottleneck between the processor and memory, resulting in slow processing speeds and high power consumption during AI computations. Various technologies have been reported to reduce this bottleneck, but fundamental limitations of the bottleneck necessitate innovation in hardware architecture. Among these, neuromorphic hardware, which implements artificial neural networks by leveraging fundamental physical phenomena of circuits, is attracting attention.

[0058] This neuromorphic hardware has attracted attention as a next-generation technology because it can dramatically reduce computational speed and power compared to conventional computing hardware by leveraging the analog parallel computational characteristics of the devices. Research is ongoing to implement neuromorphic hardware using various non-volatile memory devices (NVM). Parallel matrix multiplication is a crucial operation in AI computation, and neuromorphic hardware enables this by training analog weights on non-volatile memory devices and then activating the devices simultaneously. However, because the computation is performed on the analog side, it is crucial to convert the obtained results into digital form for additional computations crucial for artificial neural networks, such as activation and batch normalization. This requires circuits such as ADCs, which incur additional power and processing time. Furthermore, the circuit complexity increases the ADC area relatively when the array is small, significantly reducing computational efficiency per area.

[0059] Figure 1 is a drawing for explaining the structure and operation method of neuromorphic hardware, and shows a representative operation method when performing artificial neural network operations on neuromorphic hardware.

[0060] As shown in Fig. 1, when an input signal is given using the PWM (pulse width modulation) method, the NVM (non-volatile memory) element is turned on, and the output of each line is obtained by sensing the current in the ADC. Here, the weight matrix stored in the transconductance and conductance formats of the NVM is simultaneously multiplied by the voltage signal (X) of the word line (WL) and output as the bit line (BL) current (I), thereby performing large-scale parallel operations.

[0061] At this time, the ADC consumes the most power during neuromorphic computation, and its circuit complexity also leads to a significant area footprint. Therefore, neuromorphic hardware utilizing existing NVM elements consumes significant energy during computation.

[0062]

[0063] Figure 2 is a diagram illustrating a neuromorphic hardware structure for multi-layer artificial neural network operations using a conventional MOSFET-based NVM.

[0064] As shown in Fig. 2, most non-volatile memories used in conventional neuromorphic devices only transplant one weight from one synaptic element. In other words, NVM-based neuromorphic hardware structures, such as MOSFETs, use multiple arrays (1) in which different weights are learned for multi-layer artificial neural network operations. ST Array, 2 nd Array) is essential. In this case, the increase in the number of arrays inevitably leads to an increase in the required chip area and driving circuitry, which limits the TOPs / W and TOPs / mm2 essential for low-power neuromorphic hardware. Furthermore, due to the high current characteristics, there is a limitation on the array size.

[0065] Accordingly, the present invention proposes a neuromorphic hardware structure and operating method capable of multi-layer artificial neural network computation using ambipolar transistor-based NVM devices, which feature two current mechanisms per device. This can significantly reduce chip area and reduce the number of driving circuits by more than half, enabling more efficient artificial neural network computation.

[0066]

[0067] FIGS. 3A to 3C are drawings for explaining a neuromorphic device according to one embodiment of the present invention, and are drawings for explaining a multi-layer artificial neural network processing neuromorphic hardware using a bipolar transistor.

[0068] First, Fig. 3a illustrates a conceptual diagram of a non-volatile memory based on an ambipolar transistor. Unlike a metal-oxide-semiconductor field-effect transistor (MOSFET), an ambipolar transistor can be configured with two or more different current mechanisms depending on the gate voltage, which are usually composed of a forward region and an ambipolar region, which are symmetrical current characteristics depending on the voltage. By utilizing this characteristic, an ambipolar transistor-based NVM can store two independent weights in a single element, as shown in Fig. 3b, by controlling the two current mechanisms differently. At this time, if different weights are transplanted into the two different current regions, two analog vector matrix operations (VMM) are possible in a single synapse array. Therefore, by using a single ambipolar transistor-based NVM array with two independent weights, as shown in Fig. 3c, a neuromorphic hardware structure capable of performing two artificial neural network operations can be completed. Here, the bipolar transistor may include, but is not necessarily limited to, a tunneling transistor or a ferroelectric tunneling transistor.

[0069]

[0070] FIG. 4 is a diagram for explaining a weight transplant operation of a neuromorphic device according to one embodiment of the present invention.

[0071] Referring to FIG. 4, a neuromorphic device (100) may be configured with an array of nonvolatile memories (NVM) formed along a plurality of bit lines (BL) and a plurality of word lines (WL). The neuromorphic device (100) may be implemented by including a nonvolatile memory array including ambipolar transistors arranged in an area where the bit lines (BL) and the word lines (WL) intersect. Here, the nonvolatile memory array may use the ambipolar transistors as synaptic elements. For multi-layer operations, it is most important to transplant two different weights into the ambipolar transistor-based nonvolatile memory (NVM). That is, the neuromorphic device (100) can perform two-layer operations by transplanting different weights into two current regions existing in the ambipolar transistors. At this time, the weight transplantation may be performed in a manner similar to a conventional NOR or AND type array. Specifically, the neuromorphic device (100) can perform weight transplantation for learning of multiple layers by alternately applying specific voltages of the first polarity and the second polarity to a word line (WL) and a bit line (BL) connected to a specific synaptic device among a plurality of bit lines and a plurality of word lines. The neuromorphic device (100) can transplant different weights to each region by applying a specific voltage of the first polarity to a forward region of a bipolar transistor and applying a specific voltage of the second polarity different from the first polarity to an ambipolar region of the bipolar transistor.

[0072] For example, as shown in Fig. 4, the transconductance or conductance of the forward region can be controlled by applying a high voltage to the word line (WL) and bit line (BL) connected to the target element for which weight transplantation is desired. At this time, the remaining word lines and bit lines are made to be grounded (GND) or floating. In addition, in the case of the weight of the ambipolar region, the transconductance or conductance can be controlled by applying a high voltage of a different polarity from the weight transplantation of the forward region. Here, the polarity of the voltage can be switched depending on the material that stores the weight.

[0073] For example, in the case of charge storage memory, when transplanting a negative weight into the forward region, it can be performed by applying a strong positive voltage to the word line (WL) and the bit line (BL). When transplanting a negative weight into the ambipolar region, it can be performed by applying a strong negative voltage to the word line (WL) and a strong positive voltage to the bit line (BL).

[0074] Conversely, in the case of ferroelectric memory, transplanting a positive weight to the forward region can be accomplished by applying a strong positive voltage to the word line (WL) and the bit line (BL), and transplanting a positive weight to the ambipolar region can be accomplished by applying a strong negative voltage to the word line (WL) and a strong positive voltage to the bit line (BL). In addition, as in the AND type array, weight transplantation is also possible by floating the word line (WL) and the bit line (BL).

[0075]

[0076] Fig. 5 is a drawing for explaining an embodiment using a FeTFET device.

[0077] Referring to Fig. 5, the forward region or ambipolar region can be controlled by applying voltage to a word line (WL) and a bit line (BL) using the ISPP (Incremental Step Pulse Program) method in a ferroelectric memory, as follows. Here, the ISPP method refers to a method of increasing the voltage little by little in steps by dividing the voltage.

[0078] Referring to Figure 5, the difference between the gate voltage and the source voltage of the element to be updated (V GS ) or the difference between the gate voltage and drain voltage (V GD ) can be used to control the forward region or the ambipolar region, respectively.

[0079] Figure 5(a) is a graph explaining how to control only the forward region of a device for which weight transplantation is desired. Here, only the forward region of a device for which weight transplantation is desired can be controlled by applying a strong positive voltage to the word line (WL) and bit line (BL). For example, assuming that the word line (WL) and bit line (BL) are each 4 V, a high V GS (4V) and low V GD (0V) can be applied to update only the forward region.

[0080] Figure 5(b) is a graph illustrating control of only the ambipolar region. Here, only the ambipolar region can be controlled by applying a strong negative voltage to the word line (WL) and a strong positive voltage to the bit line (BL).

[0081] This shows that the forward region and the ambipolar region can be controlled differently.

[0082]

[0083] FIG. 6 is a drawing for explaining a neuromorphic hardware structure according to one embodiment of the present invention, which is a multi-layer artificial neural network processing neuromorphic hardware structure composed of bipolar transistors with completed weight transplantation.

[0084] The neuromorphic hardware of the present invention utilizes bipolar transistors to express different weights in the forward and ambipolar regions. This enables two-layer artificial neural network operations.

[0085] Referring to Figure 6, first the first layer (1 st After the operation is performed using the weights of the forward region, the second layer (2) nd The layer) operation can be performed using the weights of the ambipolar region. In order to implement a conventional two-layer artificial neural network, an array using two NVM elements was required as shown in Fig. 2, but in the present invention, two-layer operations can be performed using a single array, that is, neuromorphic hardware capable of processing multi-layer artificial neural networks can be designed.

[0086]

[0087] Figure 7 is a diagram showing the individual weight measurement results by two current mechanisms of a bipolar transistor, and the bipolar transistor is a silicon-based ferroelectric tunneling transistor (FeTFET).

[0088] Referring to Fig. 7, it can be confirmed that the highest weight '1' and the lowest weight '0' of each area can be independently transplanted as a result of transplanting the weights of the two areas (forward, ambipolar) using the weight transplant method described in Fig. 4, and that read and multiplication operations are also possible. This enables neuromorphic hardware operation for processing multi-layer artificial neural networks, and it can be confirmed that this can be applied not only to FeTFETs but also to various types of bipolar transistor-based non-volatile memory devices.

[0089]

[0090] FIGS. 8A to 8C are drawings for explaining a neuromorphic hardware structure and an operating method according to one embodiment of the present invention. FIG. 8A is a drawing for explaining a multi-bit FeTFET operating method, FIG. 8B is a drawing for explaining weight extraction for multi-layer operation, and FIG. 8C is a drawing for explaining a neuromorphic hardware structure and an operating method.

[0091] Neuromorphic hardware according to the present invention has a multi-layer artificial neural network processing structure using bipolar transistors arranged in an array of non-volatile memories formed along a plurality of bit lines (BLs) and a plurality of word lines (WLs). A neuromorphic device having such a hardware structure can perform multi-layer artificial neural network operations by transplanting a first weight into a first region of the bipolar transistor, transplanting a second weight into a second region of the bipolar transistor, performing a first layer operation using the current of the first region and the transplanted first weight, and performing a second layer operation using the current of the second region and the transplanted second weight.

[0092] To explain more specifically, first, as shown in Fig. 8a, since a bipolar transistor has two different current regions, a forward region and an ambipolar region, it is possible to confirm the current characteristics by reading the current in each region to perform a weight-voltage product operation (G*V).

[0093] Afterwards, the weights of the multi-layer artificial neural network extracted through software can be extracted as in Fig. 8b. The extracted weights are transplanted to an ambipolar transistor array using the weight transplantation method described in Fig. 4. In the first layer operation, the operation is performed using the weights of the forward region, and in the second layer operation, the operation is performed using the weights of the ambipolar region. At this time, the voltage time (T pulse ) can be used to control the size of the input signal, and the final operation result can be obtained by sensing the current through the ADC. Here, the same bit line switch matrix (BL switch matrix), ADC, and word line switch matrix (WL swich matrix) (DAC, PWM operation method) are used for each layer operation, so the number of driving circuits can be reduced, and the number of additionally used weight cells is also reduced, which can drastically reduce the overall chip area and power consumption.

[0094] In addition, although the artificial neural network is described as an ADC for understanding, it can also be used in SNN (spiking neural network application), and can be applied to reduce the number of output neurons, and can also be applied to various artificial neural network neuromorphic hardware structures.

[0095]

[0096] As described above, when computing data of a multi-layer artificial neural network using an ambipolar transistor-based NVM array, the number of elements can be reduced by half, allowing for a very high degree of integration, and the number of input / output terminals, for example, analog-to-digital conversion circuits, digital-to-analog conversion circuits (DACs), and neuron circuits, can also be reduced by half, allowing for a very large reduction in area.

[0097] Furthermore, the present invention can utilize not only a specific ambipolar transistor but also a variety of ambipolar transistors, making it applicable to a variety of neuromorphic hardware architectures. Therefore, the present invention can significantly improve the integration and performance of neuromorphic hardware.

[0098] The present invention enables two-layer computations with a single array when computing multi-layer artificial neural networks, enabling a configuration with a much smaller footprint than existing neuromorphic hardware. Furthermore, the number of ADCs, which sense output values ​​and account for the largest power consumption in neuromorphic hardware computations, can be halved, significantly increasing power efficiency. These advantages are essential for artificial neural network technologies, such as GPT-4, which are recently increasing the number of parameters and multiple layers.

[0099]

[0100] Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

[0101]

[0102] [Explanation of symbols]

[0103] 100: Neuromorphic devices

[0104] WL: Wordline BL: Bitline

Claims

1. Multiple bitlines; multiple word lines; and A neuromorphic device comprising a nonvolatile memory array including ambipolar transistors arranged in an area where the bitline and wordline intersect.

2. In the first paragraph, the nonvolatile memory array A neuromorphic device characterized by using the above bipolar transistor as a synaptic device.

3. In the first paragraph, the nonvolatile memory array A neuromorphic device characterized in that two-layer operation is possible by transplanting different weights into two current regions existing in the above bipolar transistor.

4. In the first paragraph, the nonvolatile memory array A neuromorphic device characterized in that weight transplantation for learning of multiple layers is performed by alternately applying specific voltages of first and second polarities to word lines and bit lines connected to specific synaptic devices among the plurality of bit lines and the plurality of word lines.

5. In the first paragraph, the nonvolatile memory array A neuromorphic device characterized in that a specific voltage of a first polarity is applied to a forward region of the bipolar transistor, and a specific voltage of a second polarity different from the first polarity is applied to an ambipolar region of the bipolar transistor, thereby transplanting different weights to each region.

6. In the first paragraph, the nonvolatile memory array A neuromorphic device characterized in that a weight transplant is performed by applying a specific voltage to a word line and a bit line connected to a target device among the plurality of bit lines and the plurality of word lines and causing the remaining word lines and bit lines to be grounded (GND) or floating.

7. In a multi-layer artificial neural network processing neuromorphic device, A plurality of bitlines arranged and extending along the first direction; A plurality of word lines arranged to extend along a second direction perpendicular to the first direction; and It comprises a plurality of synaptic elements located in an area where the bit line and word line intersect, A neuromorphic device characterized in that the synaptic device comprises a bipolar transistor having two current regions.

8. In the 7th paragraph, the bipolar transistor A neuromorphic device comprising a tunneling transistor or a ferroelectric tunneling transistor.

9. In the 7th paragraph, the bipolar transistor A neuromorphic device characterized by the presence of two or more different current mechanisms depending on the gate voltage, and including a forward region and an ambipolar region with symmetrical current characteristics depending on the voltage.

10. In paragraph 9, A neuromorphic device characterized in that the forward region and the ambipolar region are each controlled in the nonvolatile memory device based on the bipolar transistor to store two weights in one synaptic device.

11. In paragraph 9, A neuromorphic device characterized in that two analog vector matrix operations (VMMs) are performed in a single synapse array when storing different weights in the forward region and the ambipolar region.

12. A method for operating a neuromorphic device using a bipolar transistor arranged in an array of nonvolatile memories formed along a plurality of bit lines and a plurality of word lines, A step of transplanting a first weight into a first region of the above bipolar transistor; A step of transplanting a second weight into a second region of the above bipolar transistor; A step of performing a first layer operation with the current of the first region and the transplanted first weight; and A method of operating a neuromorphic device, comprising the step of performing a second layer operation with the current of the second region and the transplanted second weight.

13. In the 12th paragraph, the bipolar transistor An operating method of a neuromorphic device characterized by the presence of two or more different current mechanisms depending on the gate voltage, and including a forward region and an ambipolar region with symmetrical current characteristics depending on the voltage.

14. In the 12th paragraph, the step of transplanting the first weight is A method of operating a neuromorphic device, characterized in that a specific voltage of a first polarity is applied to the gate of the bipolar transistor to perform weight transplantation in one of the forward region and the ambipolar region of the bipolar transistor.

15. In the 14th paragraph, the step of transplanting the second weight is A method of operating a neuromorphic device, characterized in that a weight transplantation is performed on the remaining region of the bipolar transistor by applying a specific voltage of a second polarity to the gate of the bipolar transistor.

16. In the 12th paragraph, the step of transplanting the first and second weights is A method of operating a neuromorphic device, characterized in that two weights are stored in one synaptic device by respectively controlling the forward region and the ambipolar region of each of the bipolar transistors.

17. In the 12th paragraph, the first layer operation step The voltage time (T) applied to the gate of the bipolar transistor is calculated as the weight of the forward region of the bipolar transistor. pluse ) for controlling the size of an input signal.

18. In the 13th paragraph, the second layer operation step The voltage time (T) applied to the gate of the bipolar transistor is calculated by weighting the ambipolar region of the bipolar transistor. pluse ) for controlling the size of an input signal.

19. In the 12th paragraph, the first and second layer operation steps An operating method of a neuromorphic device, characterized in that it performs a weight and voltage product operation by reading the current of the forward region and the ambipolar region of each of the bipolar transistors.

20. In the 19th paragraph, the first and second layer operation steps An operating method of a neuromorphic device, characterized in that each device senses current through an ADC and obtains an operation result.

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