Compute express link switch with integrated optical communications device

Abstract

The present disclosure includes a compute express link (CXL) switch having a switch fabric, that includes a first plurality of electrical ports, each electrical port of the first plurality of electrical ports configured for electrical communication to a host. There are a second plurality of electrical ports and at least one processor communicatively coupled to the first and second pluralities of electrical ports. There is a memory and an optical engine directly coupled to the switch fabric. The optical engine includes a plurality of converters, each converter of the plurality of converters corresponding to one electrical port of the second plurality of electrical ports and configured to at least one of convert an electrical signal to an optical signal or an optical signal to an electrical signal. There are a plurality of optical ports, each optical port of the plurality of optical ports corresponding to one converter of the plurality of converters and configured for optical communication to a device.

Description

COMPUTE EXPRESS LINK SWITCHWITH INTEGRATED OPTICAL COMMUNICATIONS DEVICECROSS-REFERENCE TO RELATED APPLICATION

[0001] This Application claims the benefit of provisional U.S. Application No. 63 / 603,946, filed on November 29, 2023, and entitled “COMPUTE EXPRESS LINK SWITCH WITH INTEGRATED OPTICAL COMMUNICATIONS DEVICE” and U.S. Application No. 63 / 614,508, filed on December 22, 2023, and entitled “INTEGRATED SWITCH OPTICAL ENGINE PLATFORM INCLUDING ELECTRICAL SWITCH OVER OPTICS DEVICE” which are hereby incorporated by reference in their entireties.

[0002] In cases where the present application conflicts with a document incorporated by reference, the present application controls.BACKGROUND

[0003] Section 1: A data center includes multiple networked computing systems to process, store, and distribute large amounts of data. Conventional data centers typically include aggregated computational resources, such as rack servers with central processing units (CPUs) and memory mounted to a single printed circuit board (PCB). For these data centers, the CPUs are configured to perform a wide array of workloads, such as managing databases and providing applications and services to a large user base. However, some workloads, particularly workloads involving high performance computing, artificial intelligence, and data analytics, have grown in size to such an extent that CPUs alone are no longer suitable to facilitate execution of these workloads without incurring significant time and costs for computation. For example, large language models have recently doubled in size every few months.

[0004] Accordingly, data centers configured to execute these workloads have undergone significant changes in recent years to accommodate the rapid growth of these workloads. For example, data centers have introduced graphics processing units (GPUs) as workload accelerators. The GPUs provide high levels of parallel computing, which can be beneficial for certain workloads, such as training machine learning models, running simulations, or performing data analytics. For example, the process of training some machine learning models, such as a large language model, is often accomplished using multiple GPUs distributed across multiple networked servers.

[0005] Section 2: High performance computing (HPC) involves the use of aggregated computing systems, such as in a cluster, a supercomputer, and / or a data center, to execute computationally expensive workloads. In recent years, the demand for HPC has increased appreciably, particularly in applications involving artificial intelligence (e.g., the training of large machine learning models), numerical simulations, and data analytics.

[0006] One example of a HPC system is a data center, which includes multiple networked computing systems to process, store, and distribute large amounts of data. Conventional data centers typically include disaggregated computational resources, such as rack servers with multiple server blades that each contain a central processing unit (CPU) and memory mounted to a single printed circuit board (PCB). More recently, data centers have introduced graphics processing units (GPUs) as workload accelerators. The GPUs provide high levels of parallel computing, which can be beneficial for certain workloads, such as training machine learning models, running simulations, or performing data analytics. Multiple GPUs are typically distributed across multiple networked servers and allocated to one or more CPUs to execute a workload.SUMMARY

[0007] Section 1: To address the growing size of workloads, new architectures for data centers are being developed to include disaggregated pools of computational resources, which can be accessed and shared between multiple computing systems. For example, the compute express link (CXL) standard provides an open standard interconnect based on peripheral interconnect express (PCIe). Under the CXL standard, disaggregated computational resources, such as memory or GPUs, may be readily allocated to execute a particular workload using a CXL switch while maintaining high-speed and high-bandwidth communication with one or more CPUs coordinating execution of the workload. Moreover, the CXL standard provides a way to more efficiently utilize computational resources by reducing the likelihood of computational resources becoming stranded.

[0008] The Inventors have thus recognized and appreciated the CXL standard can, in principle, facilitate high-speed communication between multiple hosts (e.g., a central processing unit (CPU)) and multiple devices (e.g., a graphics processing unit (GPU), memory, a storage device). Accordingly, the CXL standard is well-suited to address the rapid growth of workloads, such as in high performance computing, artificial intelligence, and data analytics applications. However, the Inventors have also recognized previous implementations of CXL are limited, in part, by the architecture of conventional CXL switches.

[0009] Specifically, conventional CXL switches only provide electrical connections to hosts and devices. The lossy nature of electrical connections limits the distance that signals can be transmitted before signal degradation causes errors or, in some instances, failures in a computing system. For example, a copper wire trace on a printed circuit board (PCB) or a copper cable can only transmit signals over a distance of a few meters. This distance is further reduced for high-bandwidth signals and / or high data rates, such as signals encoded in the Pulse Amplitude Modulation 4-level (PAM4) format. By comparison, a data center often includes computing systems separated by hundreds of meters or, in some instances, several kilometers.

[0010] To transmit signals to and from a conventional CXL switch over a longer distance, optical communication is typically used, which is appreciably less lossy compared to the electrical connections described above. The conversion between an electrical signal and an optical signal is accomplished, in part, using a retimer, which is a component that eliminates noise in a signal by generating a new copy of that signal for transmission. The retimer may be incorporated into a network interface controller (NIC) or a similar device electrically coupled to the CXL switch or as a digital signal processor (DSP) in a pluggable optical transceiver connected to the NIC. The optical transceiver, in turn, is configured to support a fiber optic cable. If the optical transceiver includes a DSP, the DSP can facilitate the conversion between an electrical signal and an optical signal.

[0011] Although this approach provides a way to transmit signals over a longer distance, there are several drawbacks. First, the retimer (e.g., the DSP) adds latency (e.g., on the order of 200 ns per conversion) each time a signal is generated when converting an electrical signal to an optical signal and vice versa, which is detrimental for applications involving high performance computing, artificial intelligence, and data analytics. Second, the DSP of an optical transceiver consumes power, thus increasing the power requirements and operating costs of the computing system. These drawbacks together limit the scalability of this approach.

[0012] Moreover, even with optical communication, computing assemblies (e.g., a server rack) that incorporate computing systems with conventional CXL switches still require an external switch (e.g., an Ethernet switch with optical transceivers, or an external optical switch) to direct signals between computing systems and / or devices within a data center. The external switches, however, add additional hardware costs and operating costs (e.g., by increasing power consumption). Additionally, conventional external switches typically add appreciable latencies (e.g., about 200 ns per switch) and only support low bandwidth densities (e.g., about 20 Gbps / mm for 800G SR4 (Short Range, 4 Channels) Octal Small Form Factor Pluggable (OSFP).Bandwidth density refers to the spatial density of communication interconnects disposed around a processor (e.g., application-specific integrated circuit (ASIC)). For conventional external switches, optical transceivers with standardized dimensions are typically used, thus limiting the density of communication interconnects around the processor, hence the low bandwidth density.

[0013] Additionally, conventional external switches are typically designed for operation in an air environment and are thus not suitable for deployment in other environments. For example, some data centers have introduced immersion cooling systems to provide energy-efficient cooling of high-density computing systems. An immersion cooling system typically requires submerging at least a portion of a computing system into a coolant liquid. When a conventional external switch is exposed to a coolant liquid, the optical components in an external switch (e.g., the optical components in an optical transceiver coupled to an Ethernet switch, or the optical components of an external optical switch) may suffer impaired performance or, in some instances, cease operation entirely due to the optical properties of the coolant liquid being appreciably different from air. In the case of a two-phase immersion cooling system where the coolant liquid is boiled to generate coolant vapor during operation, the coolant vapor itself may have sufficiently different optical properties from air such that exposure to the coolant vapor may also impair or impede performance of the optical components in an external switch. The exposure of the optical components in an external switch to coolant liquid or coolant vapor may be reduced using specialized enclosures and / or sealing mechanisms, but at appreciable expense.

[0014] As an illustrative example, FIG. 1.1 A shows a conventional CXL switch 10. As shown, the CXL switch 10 includes a switch fabric 16, electrical ports 12a-12n (generally referred to as ports 12) for connection to corresponding hosts 20a- 20n (generally referred to herein as a host 20) via respective electrical connections 21, and electrical ports 14a-14m (generally referred to herein as a port 14) for connection to corresponding devices 22a- 22m (generally referred to herein as a device 22) via respective electrical connections 23. The host 20 is a central controller that generates and manages transaction requests to one or more devices 22 through the CXL switch 10. The device 22 may be any device that connects to the CXL switch 10 to send or receive data. The switch fabric 16 includes one or more processors to route electrical signals between respective ports 12 and 14 to facilitate communication between a particular host 20 and a particular device 22.

[0015] EIG. LIB shows a typical computing system 42 incorporating the CXL switch 10. As shown, the computing system 42 includes a host 20 coupled to the CXL switch 10 via an electrical connection 21 and multiple devices 22 electrically coupled to the CXL switch 10 viarespective electrical connections 23. Due to the limited range of transmission for electrical signals, the CXL switch 10, the host 20, and the devices 22 are often mounted to a single PCB. The computing system 42 further includes a NIC 30 to facilitate transmission of signals to and from the CXL switch 10 over a longer distance. As shown, the NIC 30 is electrically coupled to the CXL switch 10 via an electrical connection 23 and includes an electrical connector 31 to receive a pluggable optical transceiver 32. The optical transceiver 32 includes a DSP 34 to facilitate conversion between an electrical signal and an optical signal and is coupled to an optical fiber 36 to transmit the optical signal. The DSP 34 in this example functions as a retimer.

[0016] FIG. 1.2 shows a typical architecture for a data center with multiple computing systems 42. As shown, a computing assembly 40a (e.g., a server rack) includes a pair of computing system 42a and 42b (e.g., server blades) and a top-of-rack (ToR) switch 50. The computing systems 42a and 42b are connected to the switch 50 via respective fiber optic cables 36. Each fiber optic cable 36 includes a pair of optical transceivers 32 disposed at opposing ends of the cable 36. The optical transceivers connect to the NICs 30 of the computing systems 42a and 42b and electrical ports of the switch 50. The switch 50 converts the optical signals from the fiber optic cables 36a and 36b into electrical signals. A processor 51 thereafter routes the electrical signals to an electrical port for transmission, for example, to an electrical port coupled to a spine 52 via fiber optic cable 36c, which also includes an optical transceiver 32, or an electrical port coupled to the computing systems 42a or 42b. The spine 52 typically includes multiple high bandwidth network switches to facilitate communication between computing assemblies. In this manner, the switch 50 is used to facilitate communication between different computing systems, which may be located within the same computing assembly (e.g., the computing systems 42a and 42b) or different computing assemblies (e.g., the computing assemblies 40a-40c).

[0017] With the architecture shown in FIG. 1.2, the electrical signals originating from a CXL switch 100 are converted to an optical signal and back to an electrical signal multiple times using multiple optical transceivers before reaching its destination. This results in higher latencies (e.g., greater than 1 ps) for signals transmitted between a host 20 and a device 22. Also, every conversion requires an optical transceiver 32 with a DSP 34, thus increasing overall power consumption. Moreover, each computing assembly 40 requires a ToR switch 50, which is typically incompatible with an immersion cooling environment with coolant liquid and / or coolant vapor present.

[0018] In view of the foregoing limitations, the present disclosure is directed to various inventive implementations of a CXL switch with a switch fabric and an integrated opticalcommunications device. In one aspect, the optical communications device may include an optical engine with a plurality of electrical-to-optical and optical-to-electrical (EO / OE) converters (referred to herein as a “converter”) and optical ports to facilitate direct optical communication between the CXL switch and a device. The close proximity of the optical engine to the switch fabric provides a way to convert electrical signals to optical signals and vice versa without requiring any signals to be regenerated, i.e., using a retimer. Moreover, the optical transmission of a signal between the CXL switch and a device may be accomplished without requiring any intermediate electrical-to-optical or optical-to-electrical conversion. Said another way, the CXL switch may transmit signals to a device without using an intermediate retimer, such as in a NIC or a DSP in an optical transceiver (e.g., the DSP 34 in FIG. LIB). Accordingly, the CXL switches disclosed herein may transmit lower device-added latency signals (e.g., less than 5 nanoseconds (ns)) over a longer distance (e.g., up to 1000 meters) compared to conventional CXL switches.

[0019] In another aspect, the optical communications device may include an optical switch to route and direct multiple optical signals from the optical engine to various devices connected to the CXL switch. The optical switch may incorporate photonic integrated circuitry to facilitate on-chip communication between the optical engine and one or more optical ports for communication with one or more devices. The integration of the optical switch into the CXL switch may appreciably reduce the number of external switches deployed in a data center or, in some instances, eliminate external switches entirely. Additionally, the deployment of multiple CXL switches across different computing systems where each CXL switch includes an optical switch allows greater flexibility to configure and reconfigure the connections between computing systems in the same or different computing assemblies.

[0020] Furthermore, the optical engine and the optical switch may be compatible with an immersion cooling environment. For instance, the optical switch, the optical engine, or, more generally, the optical communications device may rely on on-chip optical components to transmit optical signals, such as a waveguide. These optical components may be more easily sealed compared to the optical components in a conventional external switch, which typically transmit optical signals in free space.

[0021] In one example implementation, a CXL switch includes: a switch fabric, including: a first plurality of electrical ports, each electrical port of the first plurality of electrical ports configured for electrical communication to a host; a second plurality of electrical ports; at least one processor communicatively coupled to the first and second pluralities of electrical ports; and memory; and an optical engine directly coupled to the switch fabric, the optical engine including:a plurality of converters, each converter of the plurality of converters corresponding to one electrical port of the second plurality of electrical ports and configured to at least one of convert an electrical signal to an optical signal or an optical signal to an electrical signal; and a plurality of optical ports, each optical port of the plurality of optical ports corresponding to one converter of the plurality of converters and configured for optical communication to a device.

[0022] In another example implementation, a CXL switch includes: a switch fabric, including: a first plurality of electrical ports, each electrical port of the first plurality of electrical ports configured for electrical communication to a host; a second plurality of electrical ports; at least one processor communicatively coupled to the first and second pluralities of electrical ports; and memory; and an optical communications device, including: an optical engine, directly coupled to the second plurality of electrical ports of the switch fabric, to convert an electrical signal to an optical signal or an optical signal to an electrical signal; a first plurality of optical ports communicatively coupled to the optical engine; a second plurality of optical ports, each optical port of the second plurality of optical ports being configured for optical communication to a device; and an optical switch, directly coupled to the first plurality of optical ports and the second plurality of optical ports, to direct optical signals between the first plurality of optical ports and the second plurality of optical ports.

[0023] In another example implementation, a method for transmitting a signal from a host to an end point device using a CXL switch includes: receiving, at a first electrical port of the CXL switch, an electrical signal from the host corresponding to the signal; transmitting, from a second electrical port of the CXL switch, the electrical signal to an converter of the CXL switch, the second electrical port and the converter corresponding to the end point device; converting, by the converter, the electrical signal to an optical signal corresponding to the signal; and transmitting, from an optical port communicatively coupled to the converter, the optical signal to the end point device.

[0024] In another example implementation, a method for transmitting a signal from an end point device to a host using a CXL switch includes: receiving, at an optical port of the CXL switch, an optical signal from the end point device corresponding to the signal; converting, by an converter of the CXL switch coupled to the optical port, the optical signal to an electrical signal corresponding to the signal; receiving, at a first electrical port of the CXL switch, the electrical signal; and transmitting, from a second electrical port of the CXL switch corresponding to the host, the electrical signal to the host.

[0025] In another example implementation, a method for transmitting a signal from a host to an end point device using a CXL switch includes: receiving, at a first electrical port of the CXL switch, an electrical signal from the host corresponding to the signal; routing, by a switch fabric of the CXL switch coupled to the first electrical port, the electrical signal to a second electrical port of the CXL switch; transmitting, from the second electrical port, the electrical signal to an optical engine of the CXL switch; converting, by the optical engine, the electrical signal to an optical signal corresponding to the signal; transmitting, from a first optical port of the CXL switch coupled to the optical engine, the optical signal to an optical switch of the CXL switch; routing, by the optical switch, the optical signal to a second optical port of the CXL switch; and transmitting, from the second optical port, the optical signal to the end point device.

[0026] In another example implementation, a method for transmitting a signal from an end point device to a host using a CXL switch includes: receiving, at a first optical port of the CXL switch, an optical signal from the end point device corresponding to the signal; routing, by an optical switch of the CXL switch, the optical signal to a second optical port of the CXL switch; transmitting, from the second optical port, the optical signal to an optical engine of the CXL switch; converting, by the optical engine, the optical signal to an electrical signal corresponding to the signal; transmitting, from a first electrical port of the CXL switch coupled to the optical engine, the electrical signal to a switch fabric of the CXL switch; routing, by the switch fabric, the electrical signal to a second electrical port of the CXL switch; and transmitting, from the second electrical port, the electrical signal to the host.

[0027] It should be appreciated that all combinations of the foregoing concepts and additional concepts discussed in greater detail below (provided such concepts are not mutually inconsistent) are contemplated as being part of the inventive subject matter disclosed herein. In particular, all combinations of claimed subject matter appearing at the end of this disclosure are contemplated as being part of the inventive subject matter disclosed herein. It should also be appreciated that terminology explicitly employed herein that also may appear in any disclosure incorporated by reference should be accorded a meaning most consistent with the particular concepts disclosed herein.

[0028] Section 2: The Inventors have recognized and appreciated the performance of conventional HPC systems is limited, in part, by the speed and the bandwidth of communication between the various electronic devices in the HPC system. In particular, conventional electronic devices with integrated circuit (IC) chips generally rely on electrical connections to transmit and receive signals. For example, these electronic devices may include a processing unit (PU) (alsosometimes referred to herein as a “host IC” or a “host”), such as a CPU, a GPU, an applicationspecific integrated circuit (ASIC), a field-programmable gate array (FPGA), or the like. The lossy nature of electrical connections limits the distance that signals can be transmitted before signal degradation causes errors or, in some instances, failures in a computing system. For example, a copper wire trace on a printed circuit board (PCB) or a copper cable can only transmit signals over a distance of a few meters. This operating distance is further reduced for high-band- width signals and / or high data rates, such as signals encoded in the Pulse Amplitude Modulation 4-level (PAM4) format.

[0029] By comparison, the computing systems (e.g., servers) in HPC systems may be separated by hundreds of meters or, in some instances, several kilometers, such as in a data center. To transmit signals over a longer distance, optical communication is typically used. Compared to the electrical connections described above, optical communication is appreciably less lossy and can provide greater bandwidth and speed for communication. However, the Inventors have recognized the potential performance benefits of optical communication / interconnect have not been fully realized due, in part, to the need to convert between electrical signals and optical signals to accommodate conventional electronic devices.

[0030] In one conventional approach, the conversion between an electrical signal and an optical signal is accomplished using a retimer, which is a component that eliminates noise in a signal by generating a new copy of that signal for transmission. The retimer is typically incorporated into a network interface controller (NIC) or as a digital signal processor (DSP) in a pluggable optical transceiver connected to the NIC. The optical transceiver, in turn, is configured to support a fiber optic cable. The NIC is often mounted to a PCB together with one or more electronic devices or as part of a separate network switch (e.g., an Ethernet switch with optical transceivers) to direct signals between computing systems and / or devices within a data center.

[0031] However, the above approach has several drawbacks. First, the retimer (e.g., the DSP) adds latency (e.g., on the order of 200 ns per conversion) each time a signal is generated when converting an electrical signal to an optical signal and vice versa, which is detrimental for applications involving high performance computing, artificial intelligence, and data analytics. Second, the DSP of an optical transceiver consumes power, thus increasing the power requirements and operating costs of the computing system. Third, each NIC and / or external switch included in the system adds hardware costs and operating costs (e.g., by increasing power consumption). Moreover, conventional external switches typically add appreciable latencies (e.g., about 200 ns per switch) and only support low bandwidth densities (e.g., about 20 Gbps / mm for800G SR4 (Short Range, 4 Channels) Octal Small Form Factor Pluggable (OSFP). Bandwidth density refers to the spatial density of communication interconnects disposed around a processor (e.g., ASIC). For conventional external switches, optical transceivers with standardized dimensions are typically used, thus limiting the density of communication interconnects around the processor, hence the low bandwidth density. These drawbacks limit the performance (e.g., due to latency and limited bandwidth density), energy efficiency (e.g., due to increased power consumption), cost effectiveness (e.g., due to additional hardware and operating costs), space utilization (e.g., due to the space occupied by the additional hardware), and scalability.

[0032] Accordingly, the Inventors recognized the drawbacks associated with the above approach may be largely mitigated by moving the components responsible for converting between optical and electrical signals closer to the electronic devices with IC chips. For example, co-packaged optics (CPO) and / or in-package optics (IPO) can provide components directly integrated into the package of the electronic device to (i) facilitate the conversion between electrical signals and optical signals (also referred to as an optical engine (OE)) and (ii) transmit and receive optical signals via optical input / output (OIO). This approach significantly reduces the latency of converting between electrical and optical signals as well as greatly increase the bandwidth density required for Al training / inference, improve the overall efficiency and reliability of a HPC system.

[0033] Despite the potential benefits of CPO / IPO, the Inventors have recognized the adoption of CPO / IPO has been limited, in part, because conventional approaches of heterogeneously integrating CPO / IPO typically require customizing the components of the CPO / IPO to meet the unique requirements of a particular electronic device. The cost and complexity associated with designing and heterogeneously integrating CPO and / or IPO for one particular electronic device can be appreciable. Moreover, requirements typically vary between different types of electronic devices (e.g., a CPU and a GPU) and / or different models of the same type of electronic devices (e.g., different models / brands of a CPU). As a result, the design and integration of customized CPO / IPO for multiple electronic devices in a HPC system is typically cost prohibitive and too time consuming especially given the relatively short product lifecycles for many electronic devices.

[0034] In particular, the typical integration of a PU and an OE / OIO involves a complex and heterogeneous process where various components that employ diverse technologies, materials, and manufacturing methods are merged together. For example, different IC chips (e.g., GPUs and CPUs) have unique physical, electrical, packaging, and operational requirements.Achieving compatibility with the PU typically requires extensive customization of the OE / OIO in terms of packaging, assembly processes, layout, configuration, and architecture. These cus- tomizations include the design and modification of electrical connections, Electronic Integrated Circuits (EIC), Photonic Integrated Circuits (PIC), and associated processes. Accordingly, the OE / OIO developed for one PU is typically not suitable for another PU. For example, GPUs from different brands or GPUs and CPUs often have distinct pin patterns, pin functions, and operational specifications. Thus, an OE / OIO designed for one GPU, which typically involves designing both the electrical and optical components of the OE / OIO to accommodate that GPU, generally does not work with another GPU or a CPU.

[0035] Additionally, the integration of a PU with an OE / OIO can vary depending on the electrical interfaces used by the PU, such as Peripheral Component Interconnect Express (PCIe), Universal Chiplet Interconnect Express (UCIe), or Non-Volatile Memory Express (NVMe). The electrical interface used for different devices in a HPC system depends on several factors, such as the specific workload, performance requirements, or the system's hardware components. Accordingly, the electrical interface between the PU and the OE / OIO is also often customized in addition to the OE / OIO to ensure compatibility with the PU. For example, PCIe sideband signals are low-frequency signals commonly used for a range of control and management functions. To ensure efficient and reliable optical transmission of PCIe sideband signals, several adaptions should be made including: (1) modifying the electrical interface to utilize low-frequency optical signals as the original DC functions; and (2) adding supplementary optical links or wavelengths for sideband signal functions.

[0036] The OE / OIO is also customized to accommodate a particular communication protocol used by the PU. As a result, the OE / OIO may not support other communication protocols used by other PUs. It should also be appreciated that the foregoing customizations of the OE / OIO are in addition to the baseline requirements of the OE / OIO to support a HPC system, such as providing sufficient bandwidth density, low latency, energy efficiency, scalability, and future proofing.

[0037] In view of the foregoing limitations of CPO / IPO integration, the present disclosure is directed to various inventive implementations of an Integrated Switch Optical Engine (IS- WOE) platform with a ready-made OE / OIO (also referred to herein as an “optical communications device”) that can be used with different PUs (e.g., different models / brands of CPUs or GPUs) where the OE / OIO incorporate CPO / IPO technology. This is accomplished, in part, by the ISWOE platform including an electrical switch over optics (ESOO) device to facilitate theintegration of the OE / OIO with a PU. The ESOO device includes an electrical switch integrated with the OE / OIO, an electrical interface to facilitate the transmission and receipt of electrical signals (e.g., to / from the PU) and an optical interface to facilitate the transmission and receipt of optical signals.

[0038] The ESOO device may be readily customized to accommodate the particular requirements and / or specifications of a particular PU by modifying only the electrical switch and / or the electrical interface. In other words, the ESOO device may be compatible with different PUs without requiring any modifications to the OE / OIO or the optical interface. In this manner, the integration of CPO / IPO technology or, more generally, optical communication technology for different PUs may be appreciably simplified by eliminating the need to customize the components of the OE / OIO for a particular PU. Instead, the ESOO device may be customized for a particular PU by only modifying the electrical switch and the electrical interface, which can be readily accomplished using standard board / sy stem-level integration techniques. For example, the electrical switch and the electrical interface may accommodate different hardware requirements for the PU, different types of electrical interfaces used by the PU, and / or different communication protocols used by the PU.

[0039] Accordingly, the ISWOE platform provides an appreciably simpler, faster, and cost-effective way of incorporating optical communication for a variety of electronic devices compared to the more complex, customized, and heterogeneous integration process typically used previously. The ISWOE platform thus provides a way to readily incorporate different electronic devices with CPO / IPO technology into a HPC system to leverage the benefits of optical communication for greater performance.

[0040] The ESOO device may be integrated with a PU in several ways including, but not limited to, a low-dimensional integration architecture (e.g., the ESOO device and the PU are mounted to the same PCB), a 2.5d integration architecture (e.g., the ESOO device and the PU are mounted to an interposer), and a 3d integration architecture (e.g., the ESOO device is mounted directly onto the PU).

[0041] The ESOO device may include an electrical switch with a switch fabric and an integrated optical communications device. The electrical switch and the optical communications device are integrated into a common package (e.g., as in co-packaged optics or as in-packaged optics).

[0042] In some implementations, the optical communications device may include an optical engine with a plurality of electrical-to-optical and optical-to-electrical (EO / OE) converters(referred to herein as a “converter”), electrical ports to facilitate direct electrical communication with the electrical switch, and optical ports to facilitate direct optical communication between the electrical switch and one or more peripheral devices. The close proximity of the optical engine to the switch fabric provides a way to convert electrical signals to optical signals and vice versa without requiring any signals to be regenerated, i.e., using a retimer. Moreover, the optical transmission of a signal between the electrical switch and the peripheral device(s) may be accomplished without requiring any intermediate electrical-to-optical or optical-to-electrical conversion. Said another way, the electrical switch may transmit signals to the peripheral device(s) without using an intermediate retimer, such as in a NIC or a DSP in an optical engine (e.g., the DSP 34 in FIG. 1.1B). Accordingly, the electrical switches disclosed herein may transmit lower device-added latency signals (e.g., less than 5 nanoseconds (ns)) over a longer distance (e.g., up to 1000 meters) compared to conventional electrical switches (e.g., conventional CXL switches).

[0043] In some implementations, the optical communications device may further include an optical switch to route and direct multiple optical signals from the optical engine to various devices connected to the electrical switch. The optical switch may incorporate photonic integrated circuitry to facilitate on-chip communication between the optical engine and one or more optical ports for communication with one or more devices. The integration of the optical switch into the electrical switch may appreciably reduce the number of external switches deployed in a data center or, in some instances, eliminate external switches entirely. Additionally, the deployment of multiple ESOO devices across different computing systems where each electrical switch includes an optical switch allows greater flexibility to configure and reconfigure the connections between computing systems in the same or different computing assemblies.

[0044] Furthermore, the ESOO device including the optical engine and the optional optical switch may be compatible with an immersion cooling environment. For instance, the optical switch, the optical engine, or, more generally, the optical communications device, may rely on on-chip optical components to transmit optical signals, such as a waveguide. These optical components may be more easily sealed compared to the optical components in a conventional external switch, which typically transmit optical signals in free space.

[0045] In one example implementation, an ESOO device includes: an electric switch including: a switch fabric; a first plurality of electrical ports, each electrical port of the first plurality of electrical ports configured for electrical communication to a host; a second plurality of electrical ports; at least one processor communicatively coupled to the first and second pluralities of electrical ports and configured to route electrical signals between the first and secondpluralities of the electrical ports; and memory operatively coupled to the at least one processor; an optical engine electrically coupled to the electric switch, the optical engine including: a plurality of converters, each converter of the plurality of converters corresponding to one electrical port of the second plurality of electrical ports and configured to at least one of convert an electrical signal to an optical signal and / or of an optical signal to an electrical signal; and aa plurality of optical ports, each optical port of the plurality of optical ports corresponding to one converter of the plurality of converters and configured for optical communication to a device; and a common semiconductor package in which the electrical switch and the optical engine are disposed.

[0046] In another example implementation, an ESOO device includes: an electric switch including: a switch fabric: a first plurality of electrical ports, each electrical port of the first plurality of electrical ports configured for electrical communication to a host; a second plurality of electrical ports; at least one processor communicatively coupled to the first and second pluralities of electrical ports; and memory; an optical communications device, including: an optical engine, electrically coupled to the second plurality of electrical ports of the electrical switch, to convert an electrical signal to an optical signal and / or an optical signal to an electrical signal; a first plurality of optical ports communicatively coupled to the optical engine; a second plurality of optical ports, each optical port of the second plurality of optical ports being configured for optical communication to a device; and an optical switch, directly coupled to the first plurality of optical ports and the second plurality of optical ports, to direct optical signals between the first plurality of optical ports and the second plurality of optical ports; and a common semiconductor package in which the electrical switch and the optical communications device are disposed.

[0047] In another example implementation, a method for transmitting a signal from a host to an end point device using an ESOO device, the method including: receiving, at a first electrical port of an electrical switch in the ESOO device, an electrical signal from the host corresponding to the signal; transmitting, from a second electrical port of the electrical switch, the electrical signal to a converter of the ESOO device, the second electrical port and the converter corresponding to the end point device; converting, by the converter, the electrical signal to an optical signal corresponding to the signal; and transmitting, from an optical port communicatively coupled to the converter, the optical signal to the end point device, wherein the ESOO device includes a common semiconductor package in which the electrical switch and the converter are disposed.

[0048] In another example implementation, a method for transmitting a signal from an end point device to a host using an ESOO device, the method including: receiving, at an opticalport of the ESOO device, an optical signal from the end point device corresponding to the signal; converting, by a converter of the ESOO device coupled to the optical port, the optical signal to an electrical signal corresponding to the signal; receiving, at a first electrical port of an electrical switch in the ESOO device, the electrical signal; and transmitting, from a second electrical port of the electrical switch corresponding to the host, the electrical signal to the host, wherein the ESOO device includes a common semiconductor package in which the electrical switch and the converter are disposed.

[0049] In another example implementation, a method for transmitting a signal from a host to an end point device using an ESOO device, the method including: receiving, at a first electrical port of an electrical switch in the ESOO device, an electrical signal from the host corresponding to the signal; routing, by a switch fabric of the electrical switch, the electrical signal to a second electrical port of the electrical switch; transmitting, from the second electrical port, the electrical signal to an optical engine of the ESOO device; converting, by the optical engine, the electrical signal to an optical signal corresponding to the signal; transmitting, from a first optical port coupled to the optical engine, the optical signal to an optical switch of the ESOO device; routing, by the optical switch, the optical signal to a second optical port coupled to the optical switch; and transmitting, from the second optical port, the optical signal to the end point device, wherein the ESOO device includes a common semiconductor package in which the electrical switch, the converter, the optical engine, and the optical switch are disposed.

[0050] In another example implementation, a method for transmitting a signal from an end point device to a host using an ESOO device, the method including: receiving, at a first optical port of the ESOO device, an optical signal from the end point device corresponding to the signal; routing, by an optical switch of the ESOO device, the optical signal to a second optical port of the ESOO device; transmitting, from the second optical port, the optical signal to an optical engine of the ESOO device; converting, by the optical engine, the optical signal to an electrical signal corresponding to the signal; transmitting, from a first electrical port of the optical engine, the electrical signal to an electrical switch of the ESOO device; routing, by a switch fabric of the electrical switch, the electrical signal to a second electrical port of the electrical switch; and transmitting, from the second electrical port, the electrical signal to the host.

[0051] In another example implementation, a semiconductor structure includes: a substrate having electrical interconnection fabric defined in the substrate; a host mounted on and electrically coupled to a first side of the substrate; an ESOO device mounted on and electrically coupled to the first side of the substrate, the ESOO device including: an electric switchincluding: a switch fabric; a first plurality of electrical ports, at least some of the plurality of first plurality of electrical ports electrically connected to the host through the electrical interconnection fabric in the substrate; a second plurality of electrical ports; at least one processor communicatively coupled to the first and second pluralities of electrical ports and configured to route electrical signals between the first and second pluralities of the electrical ports; and memory operatively coupled to the at least one processor; an optical device having an optical engine electrically coupled to the electric switch, the optical engine including: a plurality of converters, each converter of the plurality of converters corresponding to one electrical port of the second plurality of electrical ports and configured to at least one of convert an electrical signal to an optical signal and / or of an optical signal to an electrical signal; and a plurality of optical ports, each optical port of the plurality of optical ports corresponding to one converter of the plurality of converters and configured for optical communication to a device; and a common semiconductor package in which the electrical switch and the optical engine are disposed.

[0052] In another example implementation, a semiconductor structure includes: a substrate; an interposer mounted on and electrically coupled to the substrate, the interposer having electrical interconnection fabric defined in the interposer; a host mounted on and electrically coupled to a first side of the interposer; an ESOO device mounted on and electrically coupled to the first side of the interposer, the ESOO device including: an electric switch including: a switch fabric; a first plurality of electrical ports, at least some of the plurality of first plurality of electrical ports electrically connected to the host through the electrical interconnection fabric in the interposer; a second plurality of electrical ports; at least one processor communicatively coupled to the first and second pluralities of electrical ports and configured to route electrical signals between the first and second pluralities of the electrical ports; and memory operatively coupled to the at least one processor; an optical engine electrically coupled to the electric switch, the optical engine including: a plurality of converters, each converter of the plurality of converters corresponding to one electrical port of the second plurality of electrical ports and configured to at least one of convert an electrical signal to an optical signal and / or of an optical signal to an electrical signal; and a plurality of optical ports, each optical port of the plurality of optical ports corresponding to one converter of the plurality of converters and configured for optical communication to a device; and a common semiconductor package in which the electrical switch and the optical engine are disposed.

[0053] In another example implementation, a semiconductor structure includes: a substrate; a host mounted on and electrically coupled to the substrate; an ESOO device mounted onand electrically coupled to the host, the ESOO device including: an electric switch including: a switch fabric; a first plurality of electrical ports, at least some of the plurality of first plurality of electrical ports electrically connected to the host through electrical connections; a second plurality of electrical ports; at least one processor communicatively coupled to the first and second pluralities of electrical ports and configured to route electrical signals between the first and second pluralities of the electrical ports; and memory operatively coupled to the at least one processor; an optical engine electrically coupled to the electric switch, the optical engine including: a plurality of converters, each converter of the plurality of converters corresponding to one electrical port of the second plurality of electrical ports and configured to at least one of convert an electrical signal to an optical signal and / or of an optical signal to an electrical signal; and a plurality of optical ports, each optical port of the plurality of optical ports corresponding to one converter of the plurality of converters and configured for optical communication to a device; and a common semiconductor package in which the electrical switch and the optical engine are disposed.

[0054] In another example implementation, a semiconductor structure includes: a substrate having electrical interconnection fabric defined in the substrate; a host mounted on and electrically coupled to a first side of the substrate; an ESOO device mounted on and electrically coupled to the first side of the substrate, the ESOO device including: an electric switch including: a switch fabric; a first plurality of electrical ports, at least some of the plurality of first plurality of electrical ports electrically connected to the host through the electrical interconnection fabric in the substrate; a second plurality of electrical ports; at least one processor communicatively coupled to the first and second pluralities of electrical ports; and memory; an optical communications device, including: an optical engine, electrically coupled to the second plurality of electrical ports of the electrical switch, to convert an electrical signal to an optical signal and / or an optical signal to an electrical signal; a first plurality of optical ports communicatively coupled to the optical engine; a second plurality of optical ports, each optical port of the second plurality of optical ports being configured for optical communication to a device; and an optical switch, directly coupled to the first plurality of optical ports and the second plurality of optical ports, to direct optical signals between the first plurality of optical ports and the second plurality of optical ports; and a common semiconductor package in which the electrical switch and the optical communications device are disposed.

[0055] In another example implementation, a semiconductor structure includes: a substrate; an interposer mounted on and electrically coupled to the substrate, the interposer having electrical interconnection fabric defined in the interposer; a host mounted on and electricallycoupled to a first side of the interposer; an ESOO device mounted on and electrically coupled to the first side of the interposer, the ESOO device including: an electric switch including: a switch fabric; a first plurality of electrical ports, at least some of the plurality of first plurality of electrical ports electrically connected to the host through the electrical interconnection fabric in the interposer; a second plurality of electrical ports; at least one processor communicatively coupled to the first and second pluralities of electrical ports; and memory; an optical communications device, including: an optical engine, electrically coupled to the second plurality of electrical ports of the electrical switch, to convert an electrical signal to an optical signal and / or an optical signal to an electrical signal; a first plurality of optical ports communicatively coupled to the optical engine; a second plurality of optical ports, each optical port of the second plurality of optical ports being configured for optical communication to a device; and an optical switch, directly coupled to the first plurality of optical ports and the second plurality of optical ports, to direct optical signals between the first plurality of optical ports and the second plurality of optical ports; and a common semiconductor package in which the electrical switch and the optical communications device are disposed.

[0056] In another example implementation, a semiconductor structure includes: a substrate; a host mounted on and electrically coupled to the substrate; an ESOO device mounted on and electrically coupled to the host, the ESOO device including: an electric switch including: a switch fabric: a first plurality of electrical ports, at least some of the plurality of first plurality of electrical ports electrically connected to the host through electrical connections; a second plurality of electrical ports; at least one processor communicatively coupled to the first and second pluralities of electrical ports; and memory; an optical communications device, including: an optical engine, electrically coupled to the second plurality of electrical ports of the electrical switch, to convert an electrical signal to an optical signal and / or an optical signal to an electrical signal; a first plurality of optical ports communicatively coupled to the optical engine; a second plurality of optical ports, each optical port of the second plurality of optical ports being configured for optical communication to a device; and an optical switch, directly coupled to the first plurality of optical ports and the second plurality of optical ports, to direct optical signals between the first plurality of optical ports and the second plurality of optical ports; and a common semiconductor package in which the electrical switch and the optical communications device are disposed.

[0057] In another example implementation, a semiconductor structure includes: a substrate; a host mounted on and electrically coupled to the substrate; an ESOO device mounted on and electrically coupled to the host, the ESOO device including: an electric switch including: aswitch fabric; a first plurality of electrical ports, at least some of the plurality of first plurality of electrical ports electrically connected to the host through electrical connections; a second plurality of electrical ports; at least one processor communicatively coupled to the first and second pluralities of electrical ports; and memory; an optical communications device, including: an optical engine, electrically coupled to the second plurality of electrical ports of the electrical switch, to convert an electrical signal to an optical signal and / or an optical signal to an electrical signal; a first plurality of optical ports communicatively coupled to the optical engine; a second plurality of optical ports, each optical port of the second plurality of optical ports being configured for optical communication to a device; and an optical switch, directly coupled to the first plurality of optical ports and the second plurality of optical ports, to direct optical signals between the first plurality of optical ports and the second plurality of optical ports; and a common semiconductor package in which the electrical switch and the optical communications device are disposed.

[0058] In another example implementation, a method for coupling a host to a plurality of devices using electrical and optical connections, includes: electrically integrating the electrical switch of an ESOO with the host using standard system-level or standard board-level integration; and optically coupling the plurality of optical ports in the ESOO to the plurality of devices, whereby: the host can transmit signals to each of the plurality of devices using a common optical interface and a common electrical interface, and each of the plurality of devices can transmit signals to the host using the common optical interface and the common electrical interface.

[0059] In another example implementation, a method for coupling a host to a plurality of devices using electrical and optical connections, includes: electrically integrating the electrical switch of an ESOO with the host using standard system-level or standard board-level integration; and optically coupling the second plurality of optical ports in the ESOO to the plurality of devices, whereby: the host can transmit signals to each of the plurality of devices using a common optical interface and a common electrical interface, and each of the plurality of devices can transmit signals to the host using the common optical interface and the common electrical interface.

[0060] It should be appreciated that all combinations of the foregoing concepts and additional concepts discussed in greater detail below (provided such concepts are not mutually inconsistent) are contemplated as being part of the inventive subject matter disclosed herein. In particular, all combinations of claimed subject matter appearing at the end of this disclosure are contemplated as being part of the inventive subject matter disclosed herein. It should also be appreciated that terminology explicitly employed herein that also may appear in any disclosureincorporated by reference should be accorded a meaning most consistent with the particular concepts disclosed herein.BRIEF DESCRIPTION OF THE DRAWINGS

[0061] The skilled artisan will understand that the drawings primarily are for illustrative purposes and are not intended to limit the scope of the inventive subject matter described herein. The drawings are not necessarily to scale; in some instances, various aspects of the inventive subject matter disclosed herein may be shown exaggerated or enlarged in the drawings to facilitate an understanding of different features. In the drawings, like reference characters generally refer to like features (e.g., functionally similar and / or structurally similar elements).

[0062] FIG. 1.1 A shows a logical diagram of a conventional compute express link (CXL) switch.

[0063] FIG. LIB shows a physical diagram of a computing system that includes the CXL switch of FIG. 1.1 A.

[0064] FIG. 1.2 shows a physical diagram of multiple computing assemblies communicatively coupled together via a spine where each computing assembly includes the computing system of FIG. LIB.

[0065] FIG. 1.3A shows a logical diagram of an example CXL switch with an integrated optical engine.

[0066] FIG. 1.3B shows a physical diagram of a computing system that includes the CXL switch of FIG. 1.3A.

[0067] FIG. 1.4 shows a physical diagram of several example computing assemblies communicatively coupled together via a spine where each computing assembly includes the computing system of FIG. 1.3B.

[0068] FIG. 1.5 shows a physical diagram of several example computing assemblies communicatively coupled directly together where at least one computing assembly includes the computing system of FIG. 1.3B.

[0069] FIG. 1.6A shows a logical diagram of an example CXL switch with an integrated optical engine, optical switch, and a microcontroller unit (MCU) separate from a switch fabric.

[0070] FIG. 1.6B shows a logical diagram of another example CXL switch with an integrated optical engine, optical switch, and a switch fabric. The switch fabric includes an integrated MCU.

[0071] FIG. 1.6C shows a physical diagram of an example optical switch in the CXL switches of FIGs. 1.6A and 1.6B.

[0072] FIG. 1.7 shows a physical diagram of a computing system that includes the CXL switch of FIG. 1.6 A.

[0073] FIG. 1.8A shows a physical diagram of an example computing assembly communicatively coupled to a spine where each computing assembly includes the computing system of FIG. 1.7.

[0074] FIG. 1.8B shows a physical diagram of example computing assemblies communicatively coupled directly together where each computing assembly includes the computing systems of FIG. 1.7.

[0075] FIG. 1.9 shows an example two-phase immersion cooling system with a tank containing the CXL switches of FIGs. 1.3B and 1.7.

[0076] FIG. 2.1 A shows a logical diagram of a conventional electrical switch.

[0077] FIG. 2. IB shows a physical diagram of a conventional computing system that includes the electrical switch of FIG. 2.1 A.

[0078] FIG. 2.1C shows a physical diagram of another conventional computing system that includes the electrical switch of FIG. 2.1 A and optical engines between the host and the devices.

[0079] FIG. 2. ID shows a physical diagram of another conventional computing system that includes optical engines for each host and device as well as an optical switch.

[0080] FIG. 2.2 shows a physical diagram of multiple computing assemblies communicatively coupled together via a spine where each computing assembly includes the computing system of FIG. 2. IB.

[0081] FIG. 2.3 shows cross-sectional views of different integration architectures for (a) a conventional electrical switch and / or a processing unit and (b) an optical engine.

[0082] FIG. 2.4A shows a logical diagram of an example ESOO device which includes an integrated optical engine.

[0083] FIG. 2.4B shows a physical diagram of a computing system that includes the ESOO device of FIG. 2.4A.

[0084] FIG. 2.5 shows a physical diagram of several example computing assemblies communicatively coupled together via a spine where each computing assembly includes the computing system of FIG. 2.4B.

[0085] FIG. 2.6 shows a physical diagram of several example computing assemblies communicatively coupled directly together where at least one computing assembly includes the computing system of FIG. 2.4B.

[0086] FIG. 2.7A shows a logical diagram of an example ESOO device that includes an integrated optical engine, optical switch, and a microcontroller unit (MCU) separate from a switch fabric.

[0087] FIG. 2.7B shows a logical diagram of another example ESOO device that includes an integrated optical engine, optical switch, and a switch fabric. The switch fabric includes an integrated MCU.

[0088] FIG. 2.7C shows a physical diagram of an example optical switch in the ESOO devices of FIGs. 2.7A and 2.7B.

[0089] FIG. 2.8 shows a physical diagram of a computing system that includes the ESOO device of FIG. 2.7 A.

[0090] FIG. 2.9A shows a physical diagram of an example computing assembly communicatively coupled to a spine where each computing assembly includes the computing system of FIG. 2.8.

[0091] FIG. 2.9B shows a physical diagram of example computing assemblies communicatively coupled directly together where each computing assembly includes the computing systems of FIG. 2.8.

[0092] FIG. 2.10 shows an example two-phase immersion cooling system with a tank containing the ESOO devices of FIGs. 2.4A and 2.7A.

[0093] FIG. 2.11A shows a cross section of a low-dimensional integration architecture for a semiconductor structure that includes an ESOO device and a host according to an embodiment.

[0094] FIG. 2.1 IB shows a cross section of a 2.2.5D integration architecture for a semiconductor structure that includes an ESOO device and a host according to another embodiment.

[0095] FIG. 2.11C shows a cross section of a 3D integration architecture for a semiconductor structure that includes an ESOO device and a host according to another embodiment.

[0096] FIG. 2.1 ID shows a cross section of a 3D integration architecture for a semiconductor structure that includes an ESOO device and a host according to another embodiment. Here, the ESOO device is disposed underneath the PU and the electrical switch (E-SW).

[0097] FIG. 2.12 is a flow chart of a method for coupling a host to a plurality of devices using electrical and optical connections.DETAILED DESCRIPTION

[0098] Section 1 : Following below are more detailed descriptions of various concepts related to, and implementations of, a compute express link (CXL) switch with an integrated optical communications device that includes an optical engine and / or an optical switch and methods for using the CXL switch to transmit signals (e.g., instructions, data) between a host and a device. It should be appreciated that various concepts introduced above and discussed in greater detail below may be implemented in multiple ways. Examples of specific implementations and applications are provided primarily for illustrative purposes so as to enable those skilled in the art to practice the implementations and alternatives apparent to those skilled in the art.

[0099] The figures and example implementations described below are not meant to limit the scope of the present implementations to a single embodiment. Other implementations are possible by way of interchange of some or all of the described or illustrated elements. Moreover, where certain elements of the disclosed example implementations may be partially or fully implemented using known components, in some instances only those portions of such known components that are necessary for an understanding of the present implementations are described, and detailed descriptions of other portions of such known components are omitted so as not to obscure the present implementations.

[0100] In the discussion below, various examples of a CXL switch are provided, wherein a given example or set of examples showcases a switch fabric, an optical engine, an optical switch, electrical port(s) for connection to a host, electrical port(s) for connection between the switch fabric and the optical engine, optical port(s) for connection between the optical engine and the optical switch and optical port(s) for connection to a device. Various examples of a computing system incorporating the CXL switch and computing assemblies incorporating the computing system are also provided. It should be appreciated that one or more features discussed in connection with a given example of a CXL switch, a computing system, or a computing assembly may be employed in other examples of CXL switches, computing systems, and computing assemblies respectively, according to the present disclosure, such that the various features disclosed herein may be readily combined in a given CXL switch, computing system, and computing assembly according to the present disclosure (provided that respective features are not mutually inconsistent).

[0101] Certain features of the CXL switch, the computing system, and the computing assembly are described herein using the terms “approximately,” “about,” “substantially,” and / or “similar.” As used herein, the terms “approximately,” “about,” “substantially,” and / or “similar”indicates that each of the described dimensions or features is not a strict boundary or parameter and does not exclude functionally similar variations therefrom. Unless context or the description indicates otherwise, the use of the terms “approximately,” “about,” “substantially,” and / or “similar” in connection with a numerical parameter indicates that the numerical parameter includes variations that, using mathematical and industrial principles accepted in the art (e.g., rounding, measurement or other systematic errors, manufacturing tolerances, etc.), would not vary the least significant digit.1. An Example CXL Switch with an Integrated Optical Engine

[0102] FIG. 1.3A shows an example CXL switch 100a with an integrated optical engine 130. In this example, the optical engine 130 may also be referred to as an optical communications device 130. As shown, the CXL switch 100a includes a switch fabric 110 with multiple electrical ports 112a- 112n (generally referred to herein as an electrical port 112) for connection to corresponding hosts 101a- lOln via electrical connections 102 and multiple electrical ports 114a-l 14m (generally referred to herein as an electrical port 114) for connection to the optical engine 130 via electrical connections 140. The optical engine 130 further includes multiple optical ports 132a- 132m (generally referred to herein as an optical port 132) for connection to devices 103a- 103m via corresponding optical connections 142.

[0103] The CXL switches disclosed herein (e.g., the CXL switches 100a, 100b, and 100c) may generally meet the requirements of the CXL 1.0 standard, the CXL 2.0 standard, the CXL 3.0 standard, and / or the CXL 3.1 standard, each of which are incorporated herein by reference in their entirety. It should be appreciated that the CXL switch 100a may also be compatible and / or adhere to the requirements of future versions of the CXL standard and / or other communication standards between computing devices deployed in data centers, cloud platforms, and / or the like.

[0104] The electrical ports 112 and 114 may support electrical communication according to various protocols including, but not limited to, the Peripheral Component Interconnect Express (PCIe) standard Versions 1.0 through 7.0, which is also incorporated by reference herein in its entirety.

[0105] Each electrical port 114 may be communicatively coupled to one corresponding optical port 132 via the optical engine 130. For example, the electrical port 114a may be communicatively coupled to the optical port 132a, the electrical port 114b may be communicatively coupled to the optical port 132b, and so on. Thus, a device 103 communicatively coupled to aparticular optical port 132 is also communicatively coupled to the electrical port 114 corresponding to that optical port 132.

[0106] The CXL switch 100a may generally support connection to multiple hosts and devices. In some implementations, the number of electrical ports 112 may be equal to 16. In other words, the CXL switch 100a may be communicatively coupled to 16 different hosts. More generally, the number of ports 112 may range from 2 to 32, including all values and sub-ranges in between. In some implementations, the number of electrical ports 114 may be equal to 256. In other words, the CXL switch 100a may be communicatively coupled to 256 different devices. More generally, the number of electrical ports 114 may range from 2 to 512, including all values and sub-ranges in between. The number of optical ports 132 may equal to the number of electrical ports 114. It should be appreciated that the foregoing ranges and numbers of electrical ports 112, electrical ports 114, and / or optical ports 132 in the CXL switch 100a are non-limiting examples. More generally, the CXL switch 100a may be designed to support an arbitrary number of electrical ports and / or optical ports.

[0107] The switch fabric 110 includes one or more processor(s) (not shown) and memory (not shown). The processor(s) may generally include one or more integrated circuits. For example, the processor(s) may include, but are not limited to, an ASIC and a field-programmable gate array (FPGA). The processor(s) may be configured to route electrical signals (e.g., instructions, data) between the ports 112a- 112n and the ports 114a- 114m. Thus, the processor(s) may facilitate communication between a host 101 and a device 103 by directing an electrical signal to and from the electrical port 112 communicatively coupled to the host 101 from and to the electrical port 114 that corresponds to the optical port 132 communicatively coupled to the device 103. The memory may store instructions, which when executed by the processor(s), cause the processors) to route electrical signals as described above.

[0108] In some implementations, the processor(s) may further allocate one or more devices 103 to a particular host 101. This may be accomplished, for example, by storing a record in the memory of the switch fabric 110 that indicates an assignment of one or more ports 114 to a particular port 112. For example, port 112a may be assigned ports 114a-l 14c and port 112b may be assigned ports 114d-l 14m. During operation, the processor(s) in the switch fabric 110 may use the record to direct signals between a host 101 and the allocated devices 103. The record may further identify the device 103 communicatively coupled to every port 114, e.g., via a corresponding optical port 132, to facilitate allocation of different types of devices 103 to each host 101. For example, the host 101a may be assigned devices 103a-103c, which each includemultiple GPUs and the host 101b may be assigned devices 103d-103m, which each include multiple memory modules. It should be appreciated that the processor(s) may dynamically assign different device(s) 103 to different hosts 101 during operation according to the desired allocation of resources for each host 101 to execute a particular workload.

[0109] The optical engine 130 includes multiple electrical-to-optical and optical-to-elec- trical (EO / OE) optical converters (referred to herein as a “converter”) (not shown) to facilitate the conversion of an electrical signal to an optical signal and / or an optical signal to an electrical signal. In some implementations, the optical engine 130 may include a converter for each electrical port 114 and a corresponding optical port 132. In some implementations, the optical engine 130 may not include a processor. Instead, the optical engine 130 may rely upon a processor external to the optical engine 130 (e.g., a host 101 connected to the CXL switch 100a, or a processor in the switch fabric 110) for operation.

[0110] Each converter may include various components to facilitate the conversion of an electrical signal to an optical signal and / or an optical signal to an electrical signal. For example, the converter may include a light source, such as a light emitting diode, or a laser (e.g., a vertical-cavity surface-emitting laser, an edge-emitting laser), to emit electromagnetic radiation. The light source may be used to convert an electrical signal from the electrical port 114 to an optical signal. In another example, the converter may include a photodetector (e.g., a photodiode) to detect electromagnetic radiation. The photodetector may be used to convert an optical signal from the optical port 132 to an electrical signal. The optical engine 130 may include one or more electrical connections (e.g., a wire trace, a cable) to electrically couple the converter(s) to the electrical port(s) 114 and / or one or more optical connections (e.g., a waveguide, an optical fiber) to optically couple the converter(s) to the optical port(s) 132. Other components in the optical engine 130 include, but are not limited to, amplifiers, modulators, demodulators, polarizers, and the like.

[0111] In some implementations, each converter may support bidirectional communication between an electrical port 114 and an optical port 132. Thus, the CXL switch 100a may support bidirectional communication between the host(s) 101 and the device(s) 103. This may be accomplished, for example, by the converter providing both optical-to-electrical conversion (e.g., when a signal is transmitted from a device 103 to a host 101) and electrical-to-optical conversion (e.g., when a signal is transmitted from a host 101 to a device 103). For example, each converter may include a light source to generate optical signals for transmission to a device 103 and a photodetector to receive an optical signal from the device 103. The light source may emit radiation at wavelengths corresponding to one or more bands commonly used for fiber opticcommunication including, but not limited to, the O-band (wavelength: 1260-1360 nm), the E- band (wavelength: 1360-1460 nm), the S-band (wavelength: 1460-1530 nm), the C-band (wavelength: 1530-1565 nm), and the L-band (wavelength: 1565-1625 nm).

[0112] In some implementations, the optical engine 130 may support multiplexing where multiple optical signals are transmitted to and from a single optical port 132 simultaneously. This may be accomplished, for example, by each converter including multiple light sources configured to generate optical signals at different frequencies and / or a frequency converting component to generate two or more frequencies from a single light source. In another example, each converter may include one or more polarizers to generate optical signals with different polarizations.

[0113] The optical engine 130 is generally packaged together with the switch fabric 110. For example, the switch fabric 110 and the optical engine 130 may be mounted to a common substrate and thereafter sealed by a single enclosure (e.g., a lid). In some implementations, the optical engine 130 may be a co-packaged optic device. For example, the optical engine 130 may be implemented as a photonic integrated circuit. In other words, the optical engine 130 may be a microchip with, for example, one or more converters, optical connections, and / or optical ports 132 fabricated onto a substrate. The optical engine 130, in turn, may be mounted to second substrate (e.g., a PCB, an interposer) that also supports the switch fabric 110. The second substrate may thus provide the electrical connections to facilitate communication between the switch fabric 110 and the optical engine 130.

[0114] The optical engine 130 may thus be disposed in close proximity to the switch fabric 110, thus appreciably reducing or, in some instances, mitigating the effects of signal degradation for signals transmitted between the switch fabric 110 and the optical engine 130. This, in turn, may allow the CXE switch 100a to convert between an electrical signal and an optical signal without requiring a retimer, thus eliminating one source of latency and power consumption. In some implementations, the optical engine 130 may thus convert an electrical signal and an optical signal and vice-versa with latencies less than about 5 nanoseconds (ns), which is appreciably lower than the 200 ns latencies typically incurred when using a retimer with a conventional CXE switch.

[0115] FIG. 1.3B shows an example physical layout of a computing system 162a incorporating the CXE switch 100a. As shown the computing system 162a may include a host 101 electrically coupled to the CXE switch 100a via an electrical connection 102 coupled to an electrical port 112 of the CXL switch 100a. This may be accomplished, for example, by mounting the CXL switch 100a and the host 101 to a single PCB. In some implementations, the host 101 1and / or the CXL switch 100a may each be fabricated as a discrete device and thereafter mounted to corresponding electrical contacts on the PCB, e.g., via solder, one or more pin connections, and / or the like. It should be appreciated that, in some implementations, the CXL switch 100a and the host 101 may be mounted to different PCBs and communicatively coupled together via one or more electrical cables. The CXL switch 100a may generally be coupled to various hosts 101 including, but not limited to, a CPU, a GPU, and a root complex (e.g., to facilitate transactions to and from the CPU and / or the GPU). It should be appreciated the computing system 162a may include multiple hosts 101 that are each electrically coupled to the CXL switch 100a via respective electrical connections 102.

[0116] FIG. 1.3B also shows the computing system 162a may include one or more devices 103 and the CXL switch 100a may be optically coupled to the device(s) 103 via optical connections 142. The optical connections 142 may thus be coupled to respective optical ports 132 of the CXL switch 100a. In some implementations, the devices 103 may be mounted to the same PCB as the CXL switch 100a. Accordingly, the optical connections 142 may include waveguides formed directly onto the PCB. Alternatively, the optical connections 142 may include flyover cables with one or more optical fibers. In some implementations, the devices 103 may be mounted to a different PCB than the CXL switch 100a and thus communicatively coupled together via one or more cables with one or more optical fibers.

[0117] The CXL switch 100a may generally be compatible with various devices 103. In some implementations, the device 103 may be an end point device, i.e., a device that is at the end of a communication pathway with the CXL switch 100a. The device 103 may include, but is not limited to, a GPU, memory (e.g., rapid access memory, volatile memory), storage (e.g., a hard disk drive, a solid-state drive, non-volatile memory), a storage controller, a NIC, and a switch (e.g., a programmable switch, such as a top-of-rack switch). In some implementations, the devices 103 may be configured to directly receive an optical signal. In some implementations, the devices 103 may be configured only to receive an electrical signal. Accordingly, the optical connection 142 may include an optical transceiver to convert between an optical signal and an electrical signal for communication with the device 103.

[0118] The CXL switch 100a may also be communicatively coupled to one or more external devices located outside the computing system 162a. For example, FIG. 1.3B shows the CXL switch 100a may also have an optical connection 142 to an optical feedthrough 150. As shown, the optical feedthrough 150 may include an optical fiber connector 151 coupled to the optical connection 142 and a corresponding optical fiber connector 152. The optical fiberconnector 152 may be connected to a fiber optic cable 154 to transmit optical signals between the CXL switch 100a and the external device(s). Compared to conventional CXL switches, the CXL switch 100a allows optical signals to be transmitted directly between the CXL switch 100a and the device 103. As a result, the computing system 162a does not require an intervening retimer (e.g., a retimer in a NIC, or a DSP in an optical transceiver) to facilitate communication with the CXL switch 100a, thus eliminating a source of latency and reducing power consumption. Moreover, the CXL switch 100a may transmit a signal to a device 103 without converting the signal from an electrical signal to an optical signal or an optical signal to an electrical signal.

[0119] In some implementations, the CXL switch 100a and, in particular, the optical engine 130 may be a passive device in the sense that it does not provide any functions to encode or decode an electrical signal or an optical signal. Rather, the CXL switch 100a may be configured to rely on the host 101 to execute a protocol converter (or bridge) algorithm to encode and / or decode a signal according to a particular signal protocol. Additionally, the devices 103 may each include an integrated microcontroller (e.g., a microcontroller in a NIC) to execute a protocol converter (or bridge) algorithm at the device 103. Accordingly, the computing system 162a may be configured to perform all encoding and decoding processes before the electrical signals are converted into optical signals. Thus, the optical engine 130 itself may support any communication protocols used by the computing system 162a and / or the device 103. As described above, the signal protocols may include, but are not limited to, the PCIe standard and the CXL standard.

[0120] Moreover, the optical engine 130 of the CXL switch 100a allows the CXL switch 100a to be communicatively coupled directly to devices 103 separated from the CXL switch 100a by appreciably greater distances compared to conventional CXL switches (e.g., hundreds to thousands of meters). The CXL switch 100a may further transmit higher bandwidth and / or lower latency optical signals to and from the device 103. In some implementations, the CXL switch 100a may directly transmit to a device 103 and / or directly receive an optical signal from a device 103 located up to about 1000 meters from the CXL switch 100a, including all values and subranges in between. This, in turn, may allow the CXL switch 100a to be communicatively coupled directly to most or, in some instances, all devices 103 in a data center. In some implementations, the CXL switch 100a may transmit optical signals (e.g., via the optical port(s) 132) having a bandwidth up to about 128 gigatransfers per second (GT / s), including all values and sub-ranges in between.

[0121] The optical engine 130 may be compatible for operation in an immersion cooling environment. This may be facilitated, in part, by the optical engine 130 relying upon opticalcomponents, such as a waveguide, to transmit optical signals. Accordingly, the optical components may be readily sealed to reduce exposure to the coolant fluid of an immersion cooling system.

[0122] As described above, the CXL switch 100a may transmit signals between a host 101 and a device 103. Following below are several example methods of using the CXL switch 100a to transmit signals between a host 101 and a device 103.

[0123] In one example, a method for transmitting a signal from a host 101 to a device 103 (e.g., an end point device) using the CXL switch 100a may include the following steps: (A) receiving, at an electrical port 112 of the CXL switch 100a, an electrical signal from the host 101 corresponding to the signal; (B) transmitting, from an electrical port 114 of the CXL switch 100a, the electrical signal to an converter of the CXL switch 100a disposed within the optical engine 130 where the electrical port 114 and the converter correspond to the device 103; (C) converting, by the converter, the electrical signal to an optical signal corresponding to the signal; and (D) transmitting, from an optical port 132 communicatively coupled to the converter, the optical signal to the device 103.

[0124] In another example, a method for transmitting a signal from a device 103 (e.g., an end point device) to a host 101 using the CXL switch 100a may include the following steps: (A) receiving, at an optical port 132 of the CXL switch 100a, an optical signal from the device 103 corresponding to the signal; (B) converting, by a converter of the CXL switch 100a coupled to the optical port 132 and disposed within the optical engine 130, the optical signal to an electrical signal corresponding to the signal; (C) receiving, at an electrical port 114 of the CXL switch 100a, the electrical signal; and (D) transmitting, from an electrical port 112 of the CXL switch 100a corresponding to the host 101, the electrical signal to the host 101.2. Example Computing Assembly Architectures

[0125] As described above, the CXL switch 100a is configured to provide a direct optical connection to a device 103. This optical connection allows the CXL switch 100a and the device 103 to be separated by distances on the order of hundreds of meters or even thousands of meters without incurring significant signal degradation or device-added latency, e.g., by a retimer (e.g., a DSP in an optical transceiver). Moreover, the CXL switch 100a may appreciably simplify integration in a computing system, for example, by eliminating NICs. These aspects of the CXL switch 100a allow for greater flexibility in the overall design and architecture of a data center and, in particular, how computing systems are connected to one another. Following below areseveral illustrative examples of different architectures for computing assemblies to showcase the flexibility afforded by incorporating the CXL switch 100a.

[0126] FIG. 1.4 shows an example computing assembly 160a that adopts a similar architecture as a conventional computing system (see, for example, the computing system 40a). This example shows that the CXL switch 100a may be readily integrated into conventional architectures while still providing improvements to performance, in part, by eliminating NICs in the computing systems. As shown, the computing assembly 160a includes computing systems 162a-1 and 162a-2 communicatively coupled to a ToR switch 50 via respective fiber optic cables 154a. Each fiber optic cable 154a may be connected to the computing systems 162a-l and 162a-2 via respective optical feedthroughs 150 and to electrical ports of the ToR switch 50 via respective optical transceivers 32. In this example, the host 101 of each computing system 162a-l and 162a-2 and the processor 51 of the ToRs switch 50 may execute a protocol converter / bridge algorithm to encode and decode signals transmitted between the computing systems 162a-l / 162a-2 and the ToR switch 50. Compared to the fiber optic cables 36 in the computing assembly 40a, the fiber optic cable 154a includes only one optical transceiver 32, thus reducing latency and power consumption by eliminating one NIC and, thus, one optical transceiver between the computing systems 162a- 1 and 162a-2 and the ToR switch 50. In some implementations, the computing assembly 160a may be implemented using a conventional server rack structure. For example, the computing systems 162a-l and 162a-2 and the ToR switch 50 may each be a modular system installed onto a rack.

[0127] FIG. 1.4 further shows an example computing assembly 160b that includes an optical switch 170 instead of the ToR switch 50 of the computing assembly 160a. As shown, the computing assembly 160b once again includes the computing systems 162a- 1 and 162a-2. In this example, the computing systems 162a- 1 and 162a-2 are each connected to the optical switch 170 via fiber optic cables 154b where each fiber optic cable 154b does not include any optical transceivers. In particular, the fiber optic cable 154b is connected to the computing systems 162a-l and 162a-2 and the optical switch 170 via respective optical feedthroughs 150. The optical switch 170, in turn, may include a controller 171 and various optical components (not shown) to direct optical signals between the computing systems 162a-l and 162a-2 and / or between each of the computing systems 162a-l and 162a-2 and the spine 52. With this architecture, the computing assembly 160b may not include any NICs between each of the computing systems 162a- 1 and 162a-2 and the spine 52, further reducing latency and power consumption.

[0128] FIG. 1.4 shows yet another example computing assembly 160c that does not include a programmable switch. Rather, the computing systems 162a-l and 162a-2 are directly connected to the spine 52. This example may further simplify the computing assembly 160c, in part, by eliminating the programmable switch.

[0129] The above examples showcase how the CXL switch 100a may facilitate connection with other computing assemblies. It should be appreciated that the CXL switch 100a may also allow computing systems to be directly connected to one another. Further, the computing systems may not be physically co-located (e.g., on the same server rack).

[0130] For example, FIG. 1.5 shows a computing assembly 160d that includes a computing system 162b with the CXL switch 100a and optical feedthroughs 150a, 150b, and 150c optically coupled to the CXL switch 100a. For instance, each of the optical feedthroughs 150a, 150b, and 150c may be coupled to respective optical ports 132 of the CXL switch 100a.

[0131] As shown, the computing system 162b may be directly connected to a computing system 162a in the computing assembly 160d by connecting the optical feedthrough 150a of the computing system 162b to an optical feedthrough 150 of the computing system 162a with a fiber optic cable 154b. The computing system 162a may also include the CXL switch 100a, a host 101, and a device 103. Thus, the computing systems 162b and 162a may directly communicate with one another without a programmable switch (e.g., the ToR switch 50, the optical switch 170) or a NIC, thus reducing latency and power consumption.

[0132] The computing system 162b may also be directly connected to a computing system 162a in a computing assembly 160e that is physically separate from the computing assembly 160d. As shown in FIG. 1.5, the optical feedthrough 150b may be directly coupled to the optical feedthrough 150 of the computing system 162a via a fiber optic cable 154b. The computing system 162a may also include the CXL switch 100a, a host 101, and a device 103. Accordingly, the computing systems 162b and 162a may also directly communicate with one another without a programmable switch or a NIC.

[0133] It should be appreciated that computing systems incorporating the CXL switch 100a do not necessarily require connection to another computing system with the CXL switch 100a. Rather, the CXL switch 100a may also connect to conventional computing systems with NICs using, in part, to a fiber optic cable with an optical transceiver to facilitate conversion between an optical signal and an electrical signal for communication with devices 103 that are configured to communicate using only electrical signals. A microcontroller integrated in the NIC ora DSP in the optical transceiver may execute a protocol converter / bridge algorithm to encode and / or decode signals transmitted from or to the conventional computing system.

[0134] For example, FIG. 1.5 shows the computing system 162b may directly connect to a computing system 162c in a computing assembly 160f that is physically separate from the computing assembly 160d. As shown, the computing system 162c may include devices 103 and a NIC 30 electrically coupled to the devices 103. The optical feedthrough 150c may thus be connected to the NIC 30 via a fiber optic cable 154a, which includes an optical transceiver 32 for connection to the NIC 30. Although the addition of the NIC 30 may increase latency and power consumption, this arrangement may be preferable in applications where the devices 103 are off- the-shelf devices.

[0135] As shown in FIG. 1.5, the CXL switch 100a may readily facilitate connection between physically separate computing systems. As described above, the optical connections supported by the CXL switch 100a may allow connections between computing systems located at appreciably large distances (e.g., hundreds to thousands of meters). This, in turn, may allow computing assemblies to be constructed in a physically disaggregated manner. For example, the computing assemblies 160d, 160e, and 160f in FIG. 1.5 may function as a single disaggregated computing assembly within a data center. Any one of the computing systems 162b- 162c may further be connected to a spine (e.g., the spine 52) to facilitate communication between the disaggregated computing assembly with another computing assembly in the data center.3. An Example CXL Switch with an Integrated Optical Engine and Optical Switch

[0136] FIG. 1.6A shows an example CXL switch 100b with an optical communications device 172 that includes an integrated optical engine 130 and an integrated optical switch 173 (also referred to herein as an “optical switch 173”). As shown, the CXL switch 100b includes a switch fabric 110 with multiple electrical ports 112a- 112n for connection to corresponding hosts lOla-lOln via electrical connections 102 and multiple electrical ports 114a-l 14m for connection to the optical communications device 172 and, in particular, the optical engine 130 via electrical connections 140. The switch fabric 110 and the optical engine 130 of the CXL switch 100b may incorporate some or all of the features described above with respect to the switch fabric 110 and the optical engine 130 of the CXL switch 100a. Accordingly, a discussion of these features is not repeated below for brevity.

[0137] The optical switch 173 and the optical engine 130 may be integrated into the optical communications device 172 in the sense that they are fabricated as a single cohesive device.For example, the optical communications device 172 may be fabricated as a microchip with various components of the optical switch 173 and the optical engine 130 formed therein. The optical communications device 172, in turn, may be packaged together with other components of the CXL switch 100b (e.g., the switch fabric 110).

[0138] The integration of the optical switch 173 into the CXL switch 100b provides several benefits. For example, the optical switch 173 may provide the same or similar functionality as a conventional external switch (e.g., an Ethernet switch with optical transceivers, or an external optical switch) connected to a conventional CXL switch. By integrating the optical switch 173 into the CXL switch 100b, the number of external switches used in a data center may be appreciably reduced or, in some instances, external switches may be eliminated entirely. Lor example, ToR switches may be eliminated while higher tier switches (e.g., switches located in the spine 52, or other higher tier switches deployed in a data center) may be retained. As a result, a computing assembly that includes one or more computing systems with respective CXL switches 100b may be readily expanded to include other computing systems and / or devices that may or may not be physically collocated with the computing assembly without introducing additional hardware.

[0139] Additionally, the optical switch 173 may provide appreciably less latency compared to conventional external switches. Lor example, conventional external switches may provide a latency around 200 ns while the optical switch 173 may provide latencies of about 5 ns. Moreover, the optical switch 173 may provide relatively higher bandwidth densities compared to conventional external switches. Lor example, the optical switch 173 may provide bandwidth densities greater than or equal to about 500Gbps / mm.

[0140] In another example, the integration of an optical switching function into the CXL switch 100b may provide greater flexibility to configure and reconfigure connections between the hosts 101 and the devices 103 across a data center (see, for example, EIGs. 1.8A and 1.8B). This, in turn, may facilitate the transmission of signals between computing systems located at different locations within the data center in a scalable and cost-efficient manner. In some implementations, the connections / topology configurations between the optical switch 173 of the CXL switch 100b and the devices 103 may be reconfigured in near real-time (e.g., less than 1 second) unlike conventional PCIe Switch and Ethernet switches-based Al infrastructure.

[0141] In yet another example, the optical switch 173 may be compatible for operation in an immersion cooling environment unlike conventional external switches. This may be facilitated, in part, by the optical switch 173 relying upon optical components, such as a waveguide, totransmit optical signals rather than free space transmission as is typical in conventional external switches. Accordingly, the optical components may be readily sealed to reduce exposure to the coolant fluid of an immersion cooling system, as discussed in further detail below.

[0142] The optical communications device 172 includes multiple optical ports 133a- 133m (generally referred to herein as an optical port 133) to facilitate connection between the optical engine 130 and the optical switch 173 and multiple optical ports 134a-134k (generally referred to herein as an optical port 134) for connection to devices 103a- 103m via corresponding optical connections 142. The CXL switch 100b may further include a microcontroller unit (MCU) 174 to electronically control the optical switch 173 during operation. The MCU 174 may include electronic circuitry to transmit electrical signals to the optical switch 173 to control the transmission of optical signals between optical ports 133 and optical ports 134. For example, the MCU 174 may provide electrical signals that cause a voltage to be applied across a switching device resulting in an optical signal being transmitted to a particular output of the switching device (see, for example, details of the switching devices 175 below).

[0143] In some implementations, the MCU 174 may be a standalone device (e.g., a standalone chip). As shown in FIG. 1.6A, the MCU 174 may be connected to one or more electrical ports 116 of the switch fabric 110 via electrical connections 146. The MCU 174 may further be connected to one or more electrical ports 135 of the optical switch 173 via electrical connections 144. In this manner, the MCU 174 may be communicatively coupled to the hosts 101 via the switch fabric 110 and to the optical switch 173, thus providing a way for the hosts 101 to transmit instructions to the MCU 174 to facilitate transmission of signals between the host 101 and a particular device 103.

[0144] It should be appreciated that the MCU 174 of FIG. 1.6A is a non-limiting example. In another example, FIG. 1.6B shows a CXL switch 100c with a MCU 174 integrated into the switch fabric 110. This may be accomplished, in part, by the switch fabric 110 providing one or more electrical ports 117 for connection to the electrical port(s) 135 of the optical switch 173 via electrical connections 144. In some implementations, the switch fabric 110 of the CXL switch 100c may thus incorporate all of the electronic circuity in the CXL switch 100c. Additionally, the optical communications device 172 may incorporate all of the optical components (e.g., the photonic circuitry) in the CXL switch 100c.

[0145] The optical switch 173 provides a way to dynamically route optical signals between the optical engine 130 and the devices 103a- 103m communicatively coupled to the CXL switch 100b. For example, the optical switch 173 may initially transmit signals from the opticalport 133a to the optical port 134a. During operation, the optical switch 173 may be reconfigured to transmit signals from the optical port 133a to the optical port 134b. Generally, the optical switch 173 may be configured to transmit optical signals from each of the optical ports 133a- 133m to any one of the optical ports 134a- 134k and from each of the optical ports 134a- 134k to any one of the optical ports 133a-133m. In this manner, the optical switch 173 may dynamically route optical signals from each host 101 to any of the devices 103a- 103m as desired.

[0146] The number of optical ports 133 and the number of optical ports 134 may be equal or may be different. For example, the number of optical ports 133 may be less than, equal to, or greater than the number of optical ports 134. In some implementations, the number of optical ports 133 may be equal to 256. More generally, the number of optical ports 133 may range from 2 to 512, including all values and sub-ranges in between. In some implementations, the number of optical ports 134 may be equal to 256. In other words, the CXL switch 100b and 100c may be communicatively coupled to 256 different devices 103. More generally, the number of optical ports 134 may range from 2 to 512, including all values and sub-ranges in between. It should be appreciated that the foregoing ranges and numbers of optical ports 133 and 134 in the CXL switch 100b and 100c are non-limiting examples. More generally, the CXL switch 100b and 100c may be designed to support an arbitrary number of electrical ports and / or optical ports.

[0147] The optical switch 173 may provide its switching functionality by incorporating one or more switching devices to route optical signals between the desired optical ports 133 and 134. As an illustrative example, FIG. 1.6C shows an example layout of an optical switch 173 with multiple switching devices 175. As shown, each switching device 175 provides routing functionality and is thus configured to route an optical signal from one input path to one of two output paths. For example, a switching device 175-1 may receive an optical signal being transmitted from one optical port 133 to one optical port 134 at an input path 180a and direct the optical signal to either the output path 180b or the output path 180c. In some implementations, the switching devices 175 may provide bidirectional communication to facilitate transmission of optical signals from the optical ports 133 to the optical ports 134 and from the optical ports 134 to the optical ports 133. In another example, a switching device 175-2 may receive an optical signal being transmitted from one optical port 134 to one optical port 133 at an input path 181a and direct the optical signal to either the output path 181b or the output path 181c.

[0148] FIG. 1.6C further shows the switching devices 175 may be arranged in an array where each switching device 175 is optically coupled to one another, the optical ports 133, and / or the optical ports 134 via respective optical connections 175. During operation, opticalsignals originating from one optical port 133 may pass through one or more switching devices 175 with each switching device 175 directing the optical signal such that the optical signal is transmitted to the desired optical port 134. In the example shown in FIG. 1.6C, the optical switch 173 may include a four by five array of switching devices 175 with four switching devices 175 connected to the ports 133 and the ports 134 arranged such that optical signals pass through five switching devices 175. More generally, the size of the array of switching devices 175 may scale depending on the number of ports 133 and 134 in the optical switch 172. For example, a switching device 175 may be included for each port 133 and 134. In some implementations, one switching device 175 may provide connections to two ports 133 or 134. It should also be appreciated that the number of switching devices 175 may vary between the ports 133 and 134. For example, the optical switch 173 may include switching devices 175 arranged in a cascade manner with more switching devices 175 disposed on one side than the other. This may occur, for example, if the number of optical ports 133 and 134 are not equal.

[0149] The switching device 175 may include a switching device element with at least one input port and two or more output ports. In some implementations, the switching device 175 may include two input ports and two output ports as shown in FIG. 1.6C. However, it should be appreciated that, in some implementations, the switching device 175 may support more than two inputs and / or more than two outputs. The switching device 175 may further support bidirectional communication meaning optical signals may be transmitted from the input ports to the output ports and vice-versa. The switching element is responsible for directing an optical signal from the input port(s) to one of the output ports. The switching element may be based on various types of switching devices including, but not limited to, a Mach-Zehnder interferometer (MZI), and a multimode interferometer (MMI). The switching element may be electrically coupled to electrical port(s) 135 of the optical switch 173 via electrical connections 177 to receive electrical signals from the MCU 174. As described above, the electrical signals may configure the switching element to transmit optical signals to a particular output path.

[0150] The optical switch 173 may support the transmission of optical signals emitted at wavelengths corresponding to one or more bands commonly used for fiber optic communication including, but not limited to, the O-band (wavelength: 1260-1360 nm), the E-band (wavelength: 1360-1460 nm), the S-band (wavelength: 1460-1530 nm), the C-band (wavelength: 1530-1565 nm), and the L-band (wavelength: 1565-1625 nm). In some implementations, the optical switch 173 may support transmission of optical signals corresponding to only one band. In someimplementations, the optical switch 173 may support transmission of optical signals corresponding to multiple bands (e.g., to support multiplexing of optical signals at different frequencies).

[0151] The optical communications device 172 is generally packaged together with the switch fabric 110. For example, the switch fabric 110 and the optical communications device 172 may be mounted to a common substrate and thereafter sealed by a single enclosure (e.g., a lid).

[0152] In some implementations, the optical communications device 172 may be a copackaged optic device. For example, the optical communications device 172 may be implemented as a photonic integrated circuit that incorporates both the optical engine 130 and the optical switch 173. For example, the optical communications device 172 may be a microchip that includes the various components of the optical engine 130 (e.g., light source(s), photodetector(s)) and the optical switch 173 (e.g., switching device(s)), the optical connections between the optical engine 130 and the optical switch 173, any electrical ports to facilitate connection to the switch fabric 110 and / or the MCU 174, and / or any optical ports to facilitate connection to the devices 103. The foregoing components may be fabricated onto a substrate of the microchip. The optical communications device 172, in turn, may be mounted to a second substrate (e.g., a PCB, an interposer) that also supports the switch fabric 110. The second substrate may thus provide the electrical connections to facilitate communication between the switch fabric 110 and the optical communications device 172.

[0153] The optical communications device 172 may be mounted to one or more electrical contacts on the second substrate, e.g., via solder, one or more pin connections, and / or the like. The optical communications device 172 may further include integrated electrical connections that connect the electrical contacts of the second substrate to the optical engine 130 and the optical switch 173 via the electrical ports 135. The optical communications device 172 may include, as part of the optical ports 133, on-chip optical components to facilitate the transmission of optical signals between the optical engine 130 and the optical switch 173. For example, the on-chip optical components may include a plurality of waveguides. Thus, in some implementations, the optical switch 173 may not transmit any optical signals in free space. The optical ports 134 of the optical communications device 172 may be connected to a plurality of fiber optic cables to carry optical signals to and from the CXL switch 100b. In some implementations, the fiber optic cables may be connected to the optical ports 134 via a permanent connection, such as a pigtail connection.

[0154] In some implementations, the CXL switches disclosed herein may be sealed devices to significantly reduce or, in some instances, prevent exposure of the components of theCXL switch (e.g., the switch fabric 110, the optical communications device 172, the MCU 174) to the coolant liquid of an immersion cooling system. The connections between the optical ports 134 and the fiber optic cables may also be sealed to limit exposure to the coolant liquid. This may be accomplished, for example, by applying a sealant compound to surround and / or otherwise encase the CXL switches and / or the connections between the optical ports 134 and the fiber optic cables. Various sealant compounds may be used including, but not limited to, 3M Scotch- Weld DP420 (see Appendix B), Zymet X2821 (see Appendix C), Zymet UA-2605-B (see Appendix D), Zymet UVE- 1017-2 (see Appendix E), Zymet CN- 1780-5 (see Appendix F), Zymet X2824, and Zymet UA-2701.

[0155] FIG. 1.7 shows an example physical layout of a computing system 162d incorporating the CXL switch 100b. Similar to the computing system 162a, the computing system 162d may include a host 101 electrically coupled to the CXL switch 100b via an electrical connection102 coupled to an electrical port 112 of the CXL switch 100b. This may be accomplished, for example, by mounting the CXL switch 100b and the host 101 to a single PCB. In some implementations, the host 101 and / or the CXL switch 100b may each be fabricated as a discrete device and thereafter mounted to corresponding electrical contacts on the PCB, e.g., via solder, one or more pin connections, and / or the like. It should be appreciated that, in some implementations, the CXL switch 100b and the host 101 may be mounted to different PCBs and communicatively coupled together via one or more electrical cables. The CXL switch 100b may generally be coupled to various hosts 101 including, but not limited to, a CPU, a GPU, and a root complex (e.g., to facilitate transactions to and from the CPU and / or the GPU). It should be appreciated that the computing system 162d may include multiple hosts 101 that are each electrically coupled to the CXL switch 100b via respective electrical connections 102.

[0156] FIG. 1.7 also shows the computing system 162d may include one or more devices103 and the CXL switch 100b may be optically coupled to the device(s) 103 via optical connections 142a. The optical connections 142a may thus be coupled to respective optical ports 134 of the CXL switch 100b. In some implementations, the devices 103 may be mounted to the same PCB as the CXL switch 100b. Accordingly, the optical connections 142a may include waveguides formed directly onto the PCB. Alternatively, the optical connections 142a may include flyover cables with one or more optical fibers. As described above the optical fiber(s) may be connected to respective ports 134 via corresponding pigtail connections. In some implementations, the devices 103 may be mounted to a different PCB than the CXL switch 100b and thus communicatively coupled together via one or more cables with one or more optical fibers.

[0157] The CXL switch 100b may also be communicatively coupled to one or more external devices located outside the computing system 162d. For example, FIG. 1.7 shows the computing system 162d may include multiple optical connections 142b connected to the CXL switch 100b and extending away from the computing system 162d for connection with other devices, computing systems, and / or computing assemblies. Similar to the CXL switch 100a, the CXL switch 100b may provide direct transmission of optical signals between the CXL switch 100b and another device, computing system, and / or computing assembly. Accordingly, the computing system 162d may also not include any intervening retimer (e.g., a retimer in a NIC, or a DSP in an optical transceiver) to facilitate communication with the CXL switch 100b.

[0158] As described above, the CXL switch 100b may transmit signals between a host 101 and a device 103. Following below are several example methods of using the CXL switch 100b to transmit signals between a host 101 and a device 103.

[0159] In one example, a method for transmitting a signal from a host 101 to a device 103 (e.g., an end point device) using the CXL switch 100b may include the following steps: (A) receiving, at an electrical port 112 of the CXL switch 100b, an electrical signal from the host 101 corresponding to the signal; (B) routing, by a switch fabric 110 of the CXL switch 100b coupled to the electrical port 112, the electrical signal to an electrical port 114 of the CXL switch 100b; (C) transmitting, from the electrical port 114, the electrical signal to an optical engine 130 of the CXL switch 100b; (D) converting, by the optical engine 130, the electrical signal to an optical signal corresponding to the signal; (E) transmitting, from an optical port 133 of the CXL switch 100b coupled to the optical engine 130, the optical signal to an optical switch 173 of the CXL switch 100b; (F) routing, by the optical switch 173, the optical signal to an optical port 134 of the CXL switch 100b; and (G) transmitting, from the optical port 134, the optical signal to the device 103.

[0160] In another example, a method for transmitting a signal from a device 103 to a host 101 using the CXL switch 100b may include the following steps: (A) receiving, at an optical port 134 of the CXL switch 100b, an optical signal from the device 103 corresponding to the signal; (B) routing, by the optical switch 173 of the CXL switch 100b, the optical signal to an optical port 133 of the CXL switch 100b; (C) transmitting, from the optical port 133, the optical signal to an optical engine 130 of the CXL switch 100b; (D) converting, by the optical engine 130, the optical signal to an electrical signal corresponding to the signal; (E) transmitting, from an electrical port 114 of the CXL switch 100b coupled to the optical engine 130, the electrical signal to a switch fabric 110 of the CXL switch 100b; (F) routing, by the switch fabric 110, the electricalsignal to an electrical port 112 of the CXL switch 100b; and (G) transmitting, from the electrical port 112, the electrical signal to the host 101.4. Example Computing Assembly Architectures

[0161] The integration of the optical switch 173 into the CXL switch 100b may provide additional flexibility to connect a computing system with the CXL switch 100b to other devices, computing systems, and / or computing assemblies compared to the CXL switch 100a. In particular, computing systems that incorporate the CXL switch 100b may appreciably reduce the number of conventional external switches or, in some instances, eliminate external switches entirely as described above. Following below are several illustrative examples of different architectures for computing assemblies to showcase the flexibility afforded by incorporating the CXL switch 100b.

[0162] FIG. 1.8A shows an example computing assembly 160g that includes computing systems 162d-l and 162d-2. As shown, each of the computing systems 162d-l and 162d-2 may include a CXL switch 100b that directly connects to a spine 52 via respective optical connections 142b. In this example, the CXL switches 100b may eliminate the need for a separate ToR switch in the computing assembly 160g.

[0163] Additionally, the CXL switch 100b may facilitate direct connections to other computing systems and / or devices. For example, FIG. 1.8B shows computing assemblies 160h and 160i, which each include computing systems 162d-l and 162d-2. For each of the computing assemblies 160h and 160i, the CXL switches 100b of the respective computing systems 162d-l and 162d-2 may be connected together via an optical connection 142b. Additionally, the respective CXL switches 100b in the computing systems 162d-l of the computing assemblies 160h and 160i may be connected together via an optical connection 142b. By connecting the computing systems 162d-l and 162d-2 in the manner shown in FIG. 1.8B, the computing assemblies 160h and 160i may effectively operate as a single computing assembly with each computing system directly connected to at least one other computing system.

[0164] As described above, the CXL switches 100 disclosed herein may be compatible in an immersion cooling environment. Specifically, the CXL switches 100 may be readily submerged in the coolant liquid of an immersion cooling system. FIG. 1.9 shows an example two- phase immersion cooling system 200 that includes the computing systems 162a and 162d. As shown, the system 200 includes a tank 211 defining a tank volume 212 to contain coolant liquid 220. The computing systems 162a and 162d include CXL switches 100 and 100b, respectively,which are submerged in the coolant liquid 220. The system 210 further includes a cooling distribution unit 213 with a condenser coil 214 that carries a secondary coolant. The condenser coil 214 is partially disposed in the tank volume 212 above the coolant liquid 220. During operation, the electronic components of the computing systems 162a and 162d may generate heat, which is dissipated to the coolant liquid. When the coolant liquid is sufficiently heated, the coolant liquid vaporizes producing coolant vapor 221, which rises above into a gas space 224 within the tank volume 212 containing a mixture 223 of air and coolant vapor. As the coolant vapor 221 physically contacts the condenser coil 214, heat from the coolant vapor 221 is transferred to the secondary coolant carried by the condenser coil 214, thus causing the coolant vapor 221 to condense to liquid droplets 222 that falls back into the coolant liquid 220 below. The secondary coolant is circulated to the cooling distribution unit 213 where the heat is thereafter dissipated from the secondary coolant.5. Conclusion

[0165] All parameters, dimensions, materials, and configurations described herein are meant to be example and the actual parameters, dimensions, materials, and / or configurations will depend upon the specific application or applications for which the inventive teachings is / are used. It is to be understood that the foregoing embodiments are presented primarily by way of example and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and / or method described herein.

[0166] In addition, any combination of two or more such features, systems, articles, materials, kits, and / or methods, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure. Other substitutions, modifications, changes, and omissions may be made in the design, operating conditions and arrangement of respective elements of the example implementations without departing from the scope of the present disclosure. The use of a numerical range does not preclude equivalents that fall outside the range that fulfill the same function, in the same way, to produce the same result.

[0167] The above-described embodiments can be implemented in multiple ways. For example, embodiments may be implemented using hardware, software or a combination thereof. When implemented in software, the software code can be executed on a suitable processor orcollection of processors, whether provided in a single computer or distributed among multiple computers.

[0168] Further, it should be appreciated that a computer may be embodied in any of a number of forms, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer. Additionally, a computer may be embedded in a device not generally regarded as a computer but with suitable processing capabilities, including a Personal Digital Assistant (PDA), a smart phone or any other suitable portable or fixed electronic device.

[0169] Also, a computer may have one or more input and output devices. These devices can be used, among other things, to present a user interface. Examples of output devices that can be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound generating devices for audible presentation of output. Examples of input devices that can be used for a user interface include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computer may receive input information through speech recognition or in other audible format.

[0170] Such computers may be interconnected by one or more networks in a suitable form, including a local area network or a wide area network, such as an enterprise network, an intelligent network (IN) or the Internet. Such networks may be based on a suitable technology, may operate according to a suitable protocol, and may include wireless networks, wired networks or fiber optic networks.

[0171] The various methods or processes outlined herein may be coded as software that is executable on one or more processors that employ any one of a variety of operating systems or platforms. Additionally, such software may be written using any of a number of suitable programming languages and / or programming or scripting tools, and also may be compiled as executable machine language code or intermediate code that is executed on a framework or virtual machine. Some implementations may specifically employ one or more of a particular operating system or platform and a particular programming language and / or scripting tool to facilitate execution.

[0172] Also, various inventive concepts may be embodied as one or more methods, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

[0173] All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety.

[0174] All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0175] The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”

[0176] The phrase “and / or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and / or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and / or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and / or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

[0177] As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and / or” as defined above. For example, when separating items in a list, “or” or “and / or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of’ or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e., “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.” “Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.

[0178] As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows thatelements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and / or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

[0179] In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of’ and “consisting essentially of’ shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.

[0180] Section 2: Following below are more detailed descriptions of various concepts related to, and implementations of, an Integrated Switch Optical Engine (ISWOE) platform that includes an electrical-switch-over-optics (ESOO) device that functions as a bridging structure between PUs (e.g., integrated-circuit (IC) chips), such as hosts, and an optical engine or optical input / output device. The ESOO device allows standard board / system-level electrical integration, which is appreciably simpler compared to conventional heterogeneous processes to integrate an OE / OIO with a PU. The ISWOE platform encompasses both electrical and optical interfaces. Accordingly, the ISWOE platform may readily accommodate different PUs by customizing only the electrical integration while maintaining a universal approach for optical integration.

[0181] The ESOO device includes an electrical switch and an optical communications device that includes an optical engine and / or an optical switch. The electrical switch and the optical communications device are electrically integrated in a common package, such as in co-packaged optics or as in-packaged optics. Also disclosed are methods for using the ESOO device to transmit signals (e.g., instructions, data) between one or more hosts and one or more peripheral devices. It should be appreciated that various concepts introduced above and discussed in greater detail below may be implemented in multiple ways. Examples of specific implementations and applications are provided primarily for illustrative purposes so as to enable those skilled in the art to practice the implementations and alternatives apparent to those skilled in the art.

[0182] The figures and example implementations described below are not meant to limit the scope of the present implementations to a single embodiment. Other implementations are possible by way of interchange of some or all of the described or illustrated elements. Moreover, where certain elements of the disclosed example implementations may be partially or fully implemented using known components, in some instances only those portions of such known components that are necessary for an understanding of the present implementations are described, and detailed descriptions of other portions of such known components are omitted so as not to obscure the present implementations.

[0183] In the discussion below, various examples of an ESOO device are provided, wherein a given example or set of examples showcases a switch fabric, an optical engine, an optional optical switch, electrical port(s) for connection to a host, electrical port(s) for connection between the switch fabric and the optical engine, optical port(s) for connection between the optical engine and the optical switch, and optical port(s) for connection to a device. Various examples of a computing system incorporating the ESOO device and computing assemblies incorporating the computing system are also provided. It should be appreciated that one or more features discussed in connection with a given example of an ESOO device, a computing system, or a computing assembly may be employed in other examples of ESOO devices, computing systems, and computing assemblies respectively, according to the present disclosure, such that the various features disclosed herein may be readily combined in a given ESOO device, computing system, and computing assembly according to the present disclosure (provided that respective features are not mutually inconsistent).

[0184] Certain features of the IS WOE platform and / or the ESOO device, the computing system, and the computing assembly are described herein using the terms “approximately,” “about,” “substantially,” and / or “similar.” As used herein, the terms “approximately,” “about,” “substantially,” and / or “similar” indicates that each of the described dimensions or features is not a strict boundary or parameter and does not exclude functionally similar variations therefrom. Unless context or the description indicates otherwise, the use of the terms “approximately,” “about,” “substantially,” and / or “similar” in connection with a numerical parameter indicates that the numerical parameter includes variations that, using mathematical and industrial principles accepted in the art (e.g., rounding, measurement or other systematic errors, manufacturing tolerances, etc.), would not vary the least significant digit.1. Examples of Conventional Electronic Devices for HPC Systems

[0185] As an illustrative example, FIG. 2.1 A shows a conventional electrical switch 210. As shown, the electrical switch 210 includes a switch fabric 216, electrical ports 212a-212n (generally referred to as ports 212) for connection to corresponding hosts 220a- 220n (generally referred to herein as a host 220) via respective electrical connections 221, and electrical ports 214a-214m (generally referred to herein as a port 214) for connection to corresponding devices 222a-222m (generally referred to herein as a device 222) via respective electrical connections 223. The host 220 is a central controller that generates and manages transaction requests to one or more devices 222 through the electrical switch 210. The device 222 may be any device that connects to the electrical switch 210 to send and / or receive data. The switch fabric 216 includes one or more processors to route electrical signals between respective ports 212 and 214 to facilitate communication between a particular host 220 and a particular device 222. The electrical switch 210 can be or comprise a convention CXL switch, a conventional PCIe switch, a conventional UCIe switch, a conventional NVMe switch, a conventional Ethernet switch, or the like.

[0186] FIG. 2. IB shows a typical conventional computing system 242 incorporating the conventional electrical switch 210. As shown, the computing system 242 includes a host 220 coupled to the electrical switch 210 via an electrical connection 221 and multiple devices 222 electrically coupled to the electrical switch 210 via respective electrical connections 223. Due to the limited range of transmission for electrical signals, the electrical switch 210, the host 220, and the devices 222 are often mounted to a single PCB. The computing system 242 further includes a NIC 230 to facilitate transmission of signals to and from the electrical switch 210 over a longer distance. As shown, the NIC 230 is electrically coupled to the electrical switch 210 via an electrical connection 223 and includes an electrical connector 231 to receive a pluggable optical engine 232. The optical engine 232 includes a DSP 234 to facilitate conversion between an electrical signal and an optical signal and is coupled to an optical fiber 236 to transmit the optical signal. The DSP 234 in this example functions as a retimer.

[0187] FIG. 2.1C shows another conventional computing system 244 incorporating optical engines 232 between the host 220 and the devices 222. One optical engine 232 is coupled to the electrical switch 210 to convert electrical signals transmitted from the electrical switch 210 to the devices 222 into optical signals for transmission over an optical line to one or more of the devices 222. An optical engine 232 is coupled to each device 222 to convert optical signals to electrical signals that can be received by the respective device 222. The optical engine coupled to each device 222 also converts electrical signals sent by the respective device 222 to opticalsignals for transmission over the optical line to the host 220 via the electrical switch 210. The optical engine 232 coupled to the electrical switch 210 converts the optical signals to electrical signals that can be received by the electrical switch 210 and host 220.

[0188] One problem with the architecture shown in FIG. 2.1C is that each optical engine 232 requires highly customized hybrid integration with the corresponding electrical component (e.g., switch 210 or device 222). Examples of problems with hybrid integration are discussed below.

[0189] Another problem with the architecture shown in FIG. 2.1C is that it is a static architecture that does not allow additional electrical components to be added (or removed) dynamically to increase (or decrease) a change in processing power. To add additional devices 222, such as additional GPUs, to the architecture shown in FIG. 2.2 to increase processing power, an additional optical engine 232 would need to be integrated for each added device 222. Moreover, if the devices 222 are not identical (e.g., the devices 222 include different models of GPUs), the respective optical engines 232 for each device 222 should be highly customized for that device 222, thus increasing costs and time for development.

[0190] FIG. 2. ID shows another conventional computing system 246 incorporating optical engines 232a-h between the hosts 220a-d (in general, host 220) and the devices 222a-d (in general, device 222) and an optical switch 239. The optical switch 239 is optically coupled to a first set of optical engines 232a-d and to a second set of optical engines 232e-h. Each host 220 sends electrical signals to one or more of the devices 222. The electrical signals are converted to optical signals by a respective optical engine in the first set of optical engines 232a-d. The optical switch 239 routes the optical signals to the appropriate device 222, which are then converted back to electrical signals by a respective optical engine in the second set of optical engines 232e- h.

[0191] Each host 220 and a respective optical engine in the first set of optical engines 232a-d is integrated in a common package 238a. In addition, each device 222 and a respective optical engine in the second set of optical engines 232e-h is integrated in a common package 238b. The integrations in packages 238a, 238b are highly customized hybrid integrations. Examples of problems with hybrid integration are discussed below.

[0192] FIG. 2.2 shows a typical architecture for a data center with multiple computing systems 242. As shown, a computing assembly 240a (e.g., a server rack) includes a pair of computing system 242a and 242b (e.g., server blades) and a top-of-rack (ToR) switch 250. The computing systems 242a and 242b are connected to the ToR switch 250 via respective fiber opticcables 236. Each fiber optic cable 236 includes a pair of optical engines 232 disposed at opposing ends of the cable 236. The optical engines connect to the NICs 230 of the computing systems 242a and 242b and electrical ports of the ToR switch 250. The ToR switch 250 converts the optical signals from the fiber optic cables 236 into electrical signals. A processor 251 thereafter routes the electrical signals to an electrical port for transmission, for example, to an electrical port coupled to a spine 252 via fiber optic cable 236c, which also includes an optical engine 232, or an electrical port coupled to the computing systems 242a or 242b. The spine 252 typically includes multiple high-bandwidth network switches to facilitate communication between computing assemblies. In this manner, the ToR switch 250 is used to facilitate communication between different computing systems, which may be located within the same computing assembly (e.g., the computing systems 242a and 242b) or different computing assemblies (e.g., the computing assemblies 240a-240c).

[0193] With the architecture shown in FIG. 2.2, the electrical signals originating from a conventional electrical switch 210 are converted to an optical signal and back to an electrical signal multiple times using multiple optical engines 232 before reaching its destination. This results in higher latencies (e.g., greater than 1 ps) for signals transmitted between a host 220 and a device 222. Also, every conversion requires an optical engine 232 with a DSP 234, thus increasing overall power consumption. Moreover, each computing assembly 240 requires a ToR switch 250, which is typically incompatible with an immersion cooling environment with coolant liquid and / or coolant vapor present.

[0194] The architecture shown in FIG. 2.2 also suffers the same problems as the architecture of FIG. 2.1C. Namely, each optical engine 232 requires hybrid integration with the electrical switch 210. Examples of problems with hybrid integration are discussed below. The architecture shown in FIG. 2.2 is also a static architecture that does not allow additional electrical components to be added (or removed) dynamically to increase (or decrease) a change in processing. For example, additional optical engines 232 would be needed to add additional computing systems 242 to the computing assembly 240a. If the additional computing systems 242 are not identical, the respective optical engines 232 for each computing system 242 should be highly customized for that computing system 242, thus increasing costs and time for development.

[0195] FIG. 2.3 illustrates cross-sectional views of different hybrid integration architectures for (a) a conventional electrical switch and / or a processing unit 260 and (b) an optical engine 232. The integration architecture illustrated in FIG. 2.3(a) is a low-dimensional (ID, 2D) co-packaging architecture in which the electrical switch and / or processing unit 260 and theoptical engine 232 are mounted onto a common assembly substrate 262. The electrical switch and / or processing unit 260 and the optical engine 232 are positionally offset from each other with respect to the common assembly substrate 262. The electrical switch and / or processing unit 260 includes an electrical switch (e.g., electrical switch 210) and / or a processing unit (e.g., a CPU, a GPU, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or another processing unit). When the electrical switch and / or processing unit 260 including both an electrical switch and a processing unit, the electrical switch and the processing unit are electrically coupled, such as in a common package or through other electrical connections.

[0196] The assembly substrate is mounted on a PCB 264, such as through microbumps 266. The integration architecture illustrated in FIG. 2.3(b) is a 2.5D co-packaging architecture in which the electrical switch and / or processing unit 260 and the optical engine 232 are mounted onto a common interposer 268. The interposer 268 is electrically coupled to the substrate 262. The electrical switch and / or processing unit 260 and the optical engine 232 are positionally offset from each other with respect to the interposer 268.

[0197] The integration architectures illustrated in FIGs. 2.3(c) and 2.3(d) are 3D in-pack- aging architectures in which the electrical switch and / or processing unit 260 and the optical engine 232 are 3D integrated on each other. In FIG. 2.3(c), the electrical switch and / or processing unit 260 is mounted on (e.g., above) the optical engine 232. An interposer 268 is disposed between and electrically couples the electrical switch and / or processing unit 260 and the optical engine 232. The optical engine 232 is mounted on the substrate 262. In FIG. 2.3(d), the optical engine 232 is mounted on (e.g., above) the electrical switch and / or processing unit 260. An interposer 268 is disposed between and electrically couples the electrical switch and / or processing unit 260 and the optical engine 232. The electrical switch and / or processing unit 260 is mounted on the substrate 262.

[0198] Each of the integration architectures illustrated in FIG. 2.3 (i.e., in FIG. 2.3(a)- (d)) requires heterogenous integration between the electrical switch or processing unit 260 and the optical engine 232. In heterogenous integration, devices formed of different materials, comprising different technologies, and / or formed using different manufacturing methods are electrically integrated to form a larger device or system. One problem with heterogenous integration architectures is the complexity in customizing the components. For example, integrated circuit chips, such as CPUs and GPUs, have unique physical, electrical, packaging, and operational requirements. Achieving compatibility with a processing unit (PU) (e.g., host 220) requiresextensive customization in terms of packaging, assembly processes, layout, configuration, and architecture. For example, GPUs from different brands may have distinct pin patterns, pin functions, form factors and operational specifications. To integrate various GPUs with an optical engine, the optical engine must tailor both electrical and optical designs to accommodate the different GPUs. These customizations can include the electrical connections, Electronic Integrated Circuits (EICs), Photonic Integrated Circuits (PICs), and associated processes / components. For example, GPUs typically have thousands of electrical connection points (e.g., balls or pins) which are unique based on the brand or even the particular GPU. It is a complex (and expensive) task to electrically connect some or all of the GPU’s electrical connections to corresponding electrical connections in an optical engine to achieve the same level of performance in terms of signal integrity, bandwidth, thermal performance and processing speed. This complexity may be compounded for optical engines that include a different number of lasers which would require different electrical connections.

[0199] Another problem is that a customized hybrid integration would be needed for each electronic device that is optically connected to the PU through a respective optical engine. Each such electronic device would need its own optical engine to convert optical signals to electrical signals to receive signals from the PU and to convert electrical signals to optical signals to send signals to the PU. Since components of a data center are typically sourced from multiple suppliers (e.g., to improve supply-chain resiliency), the customized hybrid integrations would need to be performed additional times for each supplier and part number.

[0200] Another problem with heterogenous integration architectures is the complexity of supporting multiple communication interfaces and / or communication protocols. For example, when integrating the PU with an optical engine, there may be various electrical interfaces such as those complying with the PCIe standard, those complying with the UCIe standard, and / or those complying with the NVMe standard. The choice of electrical interfaces in high-performance computing systems depends on factors such as the specific workload, performance demands, and the system's hardware components. Typically, customizations are required for both the electrical interface and optical engine to ensure compatibility. For instance, in the case of PCIe sideband signals, which are low-frequency and commonly used for a range of control and management functions, efficient and reliable optical transmission necessitates specific adaptations including (a) modifying the electrical interface to utilize low-frequency optical signals that are the same frequency as the original data-center electrical signals and (b) adding supplementary optical links or wavelengths for sideband signal functions.

[0201] Another problem with heterogenous integration architectures is the challenges to meet the demanding requirements of artificial intelligence, high-performance computing, and data centers in terms of bandwidth density, latency, energy efficiency, scalability, and futureproofing.2. Examples of IS WOE Platforms with an ESOO Device

[0202] The ISWOE platforms disclosed herein include an ESOO device to facilitate the integration of an OE / OIO with a variety of different PUs. Specifically, the ESOO device may include an electrical switch integrated with the OE / OIO, an electrical interface to facilitate the transmission and receipt of electrical signals (e.g., to / from the PU) and an optical interface to facilitate the transmission and receipt of optical signals. The ESOO device may readily meet different requirements and / or specifications of different PUs by allowing the electrical switch and / or the electrical interface to be customized using standard board / system-level integration techniques. The OE / OIO and the optical interface, however, may remain unchanged. In other words, the ISWOE platform may readily accommodate different PUs without requiring any modifications to be made to the components of the OE / OIO or the optical interface.

[0203] As an illustrative example, a HPC system may include multiple electronic devices (e.g., a CPU, a GPU, memory, or the like) where each electronic device preferably communicates with other devices via optical communication. Conventional approaches would require a custom-designed OE / OIO for each electronic device. In contrast, the ISWOE platform disclosed herein may allow the same OE / OIO to be used for each electronic device of the HPC system. Specifically, each electronic device may be paired with its own ISWOE platform. The ISWOE platform may further be customized for each electronic device by customizing only the electrical switch and the electrical interface. As a result, the HPC system may include multiple electronic devices that are each coupled to a ISWOE platform and the OE / OIO for all the ISWOE platforms may be identical.

[0204] FIG. 2.12 further illustrates an example method 21200 for coupling a host to a plurality of devices using the ISWOE platform disclosed herein. In step 21201, the electrical switch of an ESOO device is electrically integrated with a host using standard system-level or standard board-level integration. In step 21202, the optical VO ports of the ESOO device are optically coupled to a plurality of devices. The optical VO ports can be optically integrated and / or coupled to the devices using a plurality of optical fibers (see, for example, the optical fibers 21210 in FIGs. 2.11 A-D). The optical fibers can be bundled in one or more fiber-optic cables.The method 21200 thus illustrates the ease of integration possible using the ISWOE platforms disclosed herein.

[0205] Following below is a description of example implementations of ESOO devices, which may be integrated into the ISWOE platforms disclosed herein. It should be appreciated the examples discussed below are non-limiting examples. It should also be appreciated that respective features of one ESOO device may be readily incorporated into other implementations of ESOO devices provided those features aren’t conflicting.2.1 An Example ESOO device with an Electrical Switch and an Integrated Optical Engine

[0206] FIG. 2.4A shows an example ESOO device 2100a that includes an electrical switch 2104 and an optical engine 2130 that are integrated or combined in a common package 2145. In this example, the optical engine 2130 may also be referred to as an optical communications device 2130. As shown, the ESOO device 2100a includes an electrical switch 2104 having a switch fabric 2110 with multiple electrical ports 2112a-2112n (generally referred to herein as an electrical port 2112) for connection to one or more corresponding hosts 2101a-2101n (generally referred to herein as host(s) 2101) via electrical connections 2102. The switch fabric 2110 further includes multiple electrical ports 2114a-2114m (generally referred to herein as an electrical port 2114) for electrical connection to multiple optical ports 213 la-213 Im (generally referred to herein as an electrical port 2131) in the optical engine 2130 via electrical connections 2140. The optical engine 2130 further includes multiple optical ports 2132a-2132m (generally referred to herein as an optical port 2132) for optical connection to one or more devices 2103a-2103m (generally referred to herein as device(s) 2103) via corresponding optical connections 2142. The host(s) 2101 is / are in communication with the device(s) 2103 via the electrical and optical connections. Likewise, the device(s) 2103 is / are in communication with the host(s) 2101 via the optical and electrical connections.

[0207] The electrical switch 2104 in the ESOO devices disclosed herein (e.g., in the ESOO devices 2100a, 2100b, and 2100c) can be or can comprise a CXL switch, a PCIe switch, a UCIe switch, an NVMe switch, or an Ethernet switch. A CXL switch may generally meet the requirements of the CXL 1.0 standard, the CXL 2.0 standard, the CXL 3.0 standard, and / or the CXL 3.1 standard, developed by the Compute Express Link Consortium, Inc., which are each incorporated herein by reference in their entirety. It should be appreciated that the CXL switch may also be compatible and / or adhere to the requirements of future versions of the CXL standard and / or other communication standards between computing devices deployed in data centers,cloud platforms, and / or the like. Examples of an ESOO device in which the electrical switch 2104 is a CXL switch is disclosed in U.S. Provisional Patent Application No. 63 / 713,947, filed on October 30, 2024 and entitled, “COMPUTE EXPRESS LINK SWITCH WITH INTEGRATED OPTICAL ENGINE,” U.S. Provisional Patent Application No. 63 / 603,946, filed on November 29, 2023 and entitled, “COMPUTE EXPRESS LINK SWITCH WITH INTEGRATED OPTICAL COMMUNICATIONS DEVICE.” Each of the aforementioned applications is hereby incorporated by reference in its entirety.

[0208] A PCIe switch may generally meet the requirements of the PCIe standard Versions 1.0 through 7.0, developed by PCI-SIG, which are each incorporated herein by reference in their entirety. It should be appreciated that the ESOO device may also be compatible and / or adhere to the requirements of future versions of the PCIe standard and / or other communication standards between computing devices deployed in data centers, cloud platforms, and / or the like. A UCIe switch may generally meet the requirements of the UCIe 1.0 standard and / or the UCIe 1.1 standard, developed by the Universal Chiplet Interconnect Express Consortium, which are each incorporated herein by reference in their entirety. It should be appreciated that the UCIe switch may also be compatible and / or adhere to the requirements of future versions of the UCIe standard and / or other communication standards between computing devices deployed in data centers, cloud platforms, and / or the like. An NVMe switch may generally meet the requirements of the NVMe 1.0 standard and / or the NVMe 2.0 standard, developed by NVM Express, Inc., which are each incorporated herein by reference in their entirety. It should be appreciated that the NVMe switch may also be compatible and / or adhere to the requirements of future versions of the NVMe standard and / or other communication standards between computing devices deployed in data centers, cloud platforms, and / or the like. An Ethernet switch may generally meet the requirements of the Institute of Electrical and Electronics Engineers (IEEE) 802.3 standard, developed by IEEE. It should be appreciated that the Ethernet switch may also be compatible and / or adhere to the requirements of future versions of the IEEE 802.3 standard and / or other communication standards between computing devices deployed in data centers, cloud platforms, and / or the like.

[0209] The electrical ports 2112 and 2114 may support electrical communication according to various protocols including, but not limited to, one or more PCIe standards, one or more UCIe standards, or more NVMe standards, and / or one or more Ethernet standards (e.g., the IEEE 802.3 standard).

[0210] Each electrical port 2114 may be communicatively coupled to one corresponding optical port 2132 via the optical engine 2130. For example, the electrical port 2114a may be communicatively coupled to the optical port 2132a, the electrical port 2114b may be communicatively coupled to the optical port 2132b, and so on. Thus, a device 2103 communicatively coupled to a particular optical port 2132 is also communicatively coupled to the electrical port 2114 corresponding to that optical port 2132.

[0211] The ESOO device 2100a may generally support connection to multiple hosts and devices. In some implementations, the number of electrical ports 2112 may be equal to 16. In other words, the electrical switch 2104 may be communicatively coupled to 16 different hosts. More generally, the number of ports 2112 may range from 2 to 32, including all values and subranges in between. In some implementations, the number of electrical ports 2114 and / or the number of electrical ports 2131 may be equal to 256. In other words, the electrical switch 2104 may be communicatively coupled to 256 different devices 2103. More generally, the number of electrical ports 2114 and / or the number of electrical ports 2131 may range from 2 to 512, including all values and sub-ranges in between. The number of optical ports 2132 maybe equal to the number of electrical ports 2114 and / or to the number of electrical ports 2131. It should be appreciated that the foregoing ranges and numbers of electrical ports 2112, electrical ports 2114, and / or optical ports 2132 in the ESOO device 2100a are non-limiting examples. More generally, the electrical switch 2104 may be designed to support an arbitrary number of electrical ports and / or optical ports.

[0212] The switch fabric 2110 includes one or more processor(s) (not shown) and memory (not shown). The processor(s) may generally include one or more integrated circuits. For example, the processor(s) may include, but are not limited to, an ASIC and / or an FPGA. The processor(s) may be configured to route electrical signals (e.g., instructions and / or data) between the electrical ports 2112a-2112n and the electrical ports 2114a-2114m. Thus, the processor(s) may facilitate communication between a given host 2101 and a given device 2103 by directing an electrical signal to and from the electrical port 2112 communicatively coupled to the host 2101 from and to the electrical port 2114 that corresponds to the optical port 2132 communicatively coupled to the device 2103. The memory may store instructions, which when executed by the processor(s), cause the processor(s) to route electrical signals as described above.

[0213] In some implementations, the processor(s) may further allocate one or more devices 2103 to a particular host 2101. This may be accomplished, for example, by storing a record in the memory of the switch fabric 2110 that indicates an assignment of one or more electricalports 2114 to a particular electrical port 2112. For example, port 2112a may be assigned ports 2114a-2114c and port 2112b may be assigned ports 2114d-2114m. During operation, the processors) in the switch fabric 2110 may use the record to direct signals between a host 2101 and the allocated devices 2103. The record may further identify the device 2103 communicatively coupled to every port 2114, e.g., via a corresponding optical port 2132, to facilitate allocation of different types of devices 2103 to each host 2101. For example, the host 2101a may be assigned devices 2103a-2103c, which each include multiple GPUs and the host 2101b may be assigned devices 2103d-2103m, which each include multiple memory modules. It should be appreciated that the processor(s) may dynamically assign different device(s) 2103 to different hosts 2101 during operation according to the desired allocation of resources for each host 2101 to execute a particular workload.

[0214] The optical engine 2130 includes multiple electrical-to-optical and optical-to-elec- trical (EO / OE) optical converters (referred to herein as a “converter”) (not shown) to facilitate the conversion of an electrical signal to an optical signal and / or of an optical signal to an electrical signal. In some implementations, the optical engine 2130 may include a converter for each electrical port 2114 and a corresponding optical port 2132. In some implementations, the optical engine 2130 may not include a processor. Instead, the optical engine 2130 may rely upon a processor external to the optical engine 2130 (e.g., a host 2101 connected to the ESOO device 2100a, or a processor in the switch fabric 2110) for operation.

[0215] Each converter may include various components to facilitate the conversion of an electrical signal to an optical signal and / or an optical signal to an electrical signal. For example, the converter may include a light source, such as a light emitting diode, or a laser (e.g., a vertical-cavity surface-emitting laser, an edge-emitting laser), to emit electromagnetic radiation. The light source may be used to convert an electrical signal from the electrical port 2114 to an optical signal. In another example, the converter may include a photodetector (e.g., a photodiode) to detect electromagnetic radiation. The photodetector may be used to convert an optical signal from the optical port 2132 to an electrical signal. The optical engine 2130 may include one or more electrical connections (e.g., a wire trace, a cable) to electrically couple the converter(s) to the electrical port(s) 2114 and / or one or more optical connections (e.g., a waveguide, an optical fiber) to optically couple the converter(s) to the optical port(s) 2132. Other components in the optical engine 2130 include, but are not limited to, amplifiers, modulators, demodulators, polarizers, and the like.

[0216] In some implementations, each converter may support bidirectional communication between an electrical port 2114 and an optical port 2132. Thus, the ESOO device 2100a may support bidirectional communication between the host(s) 2101 and the device(s) 2103. This may be accomplished, for example, by the converter providing both optical-to-electrical conversion (e.g., when a signal is transmitted from a device 2103 to a host 2101) and electrical-to-optical conversion (e.g., when a signal is transmitted from a host 2101 to a device 2103). For example, each converter may include a light source to generate optical signals for transmission to a device 2103 and a photodetector to receive an optical signal from the device 2103. The light source may emit radiation at wavelengths corresponding to one or more bands commonly used for fiber optic communication including, but not limited to, the O-band (wavelength: 1260-1360 nm), the E- band (wavelength: 1360-1460 nm), the S-band (wavelength: 1460-1530 nm), the C-band (wavelength: 1530-1565 nm), and the L-band (wavelength: 1565-1625 nm).

[0217] In some implementations, the optical engine 2130 may support multiplexing where multiple optical signals are transmitted to and from a single optical port 2132 simultaneously. This may be accomplished, for example, by each converter including multiple light sources configured to generate optical signals at different frequencies and / or a frequency converting component to generate two or more frequencies from a single light source. In another example, each converter may include one or more polarizers to generate optical signals with different polarizations.

[0218] The optical engine 2130 is generally packaged together with the electrical switch 2104. For example, the switch fabric 2110 and the optical engine 2130 may be mounted to a common substrate and thereafter sealed by a single enclosure (e.g., a lid). In some implementations, the optical engine 2130 may be a co-packaged optic device or an in-packaged optic device. For example, the optical engine 2130 may be implemented as a photonic integrated circuit. In other words, the optical engine 2130 may be a microchip with, for example, one or more converters, optical connections, and / or optical ports 2132 fabricated onto a substrate. The optical engine 2130, in turn, may be mounted to second substrate (e.g., a PCB, an interposer) that also supports the electrical switch 2104. The second substrate may thus provide the electrical connections to facilitate communication between the electrical switch 2104 and the optical engine 2130.

[0219] The optical engine 2130 may thus be disposed in close proximity to the electrical switch 2104, thus appreciably reducing or, in some instances, mitigating the effects of signal degradation for signals transmitted between the electrical switch 2104 and the optical engine 2130. This, in turn, may allow the ESOO device 2100a to convert between an electrical signaland an optical signal without requiring a retimer, thus eliminating one source of latency and power consumption. In some implementations, the optical engine 2130 may thus convert an electrical signal and an optical signal and vice-versa with latencies less than about 5 nanoseconds (ns), which is appreciably lower than the 200 ns latencies typically incurred when using a retimer with a conventional electrical switch (e.g., a conventional CXL switch).

[0220] FIG. 2.4B shows an example physical layout of a computing system 2162a incorporating the ESOO device 2100a. As shown the computing system 2162a may include one or more hosts 2101 electrically coupled to the ESOO device 2100a via an electrical connection 2102 coupled to an electrical port 2112 of the ESOO device 2100a. This may be accomplished, for example, by mounting the ESOO device and the host 2101 to a single PCB. In some implementations, the host(s) 2101 and / or the ESOO device 2100a may each be fabricated as a discrete device and thereafter mounted to corresponding electrical contacts on the PCB, e.g., via solder, one or more pin connections, and / or the like. It should be appreciated that, in some implementations, the ESOO device 2100a and the host(s) 2101 may be mounted to different PCBs and communicatively coupled together via one or more electrical cables. The ESOO device 2100a may generally be coupled to various hosts 2101 including, but not limited to, a CPU, a GPU, an ASIC, an FPGA, and / or a root complex (e.g., to facilitate transactions to and from the CPU, GPU, ASIC / and / or the FPGA). It should be appreciated the computing system 2162a may include multiple hosts 2101 that are each electrically coupled to the ESOO device 2100a via respective electrical connections 2102.

[0221] FIG. 2.4B also shows the computing system 2162a may include one or more devices 2103 and the ESOO device 2100a may be optically coupled to the device(s) 2103 via optical connections 2142. The optical connections 2142 may thus be coupled to respective optical ports 2132 of the ESOO device 2100a. In some implementations, the devices 2103 may be mounted to the same PCB as the ESOO device 2100a. Accordingly, the optical connections 2142 may include waveguides formed directly onto the PCB. Alternatively, the optical connections 2142 may include flyover cables with one or more optical fibers. In some implementations, the devices 2103 may be mounted to a different PCB than the ESOO device 2100a and thus communicatively coupled together via one or more cables with one or more optical fibers.

[0222] The ESOO device 2100a may generally be compatible with various devices 2103. In some implementations, the device 2103 may be an end point device, i.e., a device that is at the end of a communication pathway with the ESOO device 2100a. The devices 2103 may include, but is not limited to, a GPU, memory (e.g., rapid access memory, volatile memory), storage (e.g.,a hard disk drive, a solid-state drive, non-volatile memory), a storage controller, a NIC, and / or a switch (e.g., a programmable switch, such as a top-of-rack switch).

[0223] In some implementations, the devices 2103 may be configured to directly receive an optical signal. For example, the device 2103 may include an integrated optical engine to convert between an optical signal and an electrical signal. The optical engine may be integrated using another ESOO device dedicated for that device 2103 similar to the ESOO device 2100a (see, for example, FIGs. 2.11A-2.1 ID). It should also be appreciated that the optical engine may be integrated using any one of the conventional heterogeneous approaches described above in FIG. 2.3.

[0224] In some implementations, the devices 2103 may be configured only to receive an electrical signal. Accordingly, the optical connection 2142 may include an optical engine to convert between an optical signal and an electrical signal for communication with the device 2103. For example, an optical transceiver (e.g., the optical transceiver 21220 illustrated in FIGs. 2.11A-C) can be coupled to the optical connection 2142 and one or more devices 2103. Furthermore, the optical transceiver may be located in close proximity to the device 2103 (e.g., less than or equal to 1 meter).

[0225] The ESOO device 2100a may also be communicatively coupled to one or more external devices located outside the computing system 2162a. For example, FIG. 2.4B shows the ESOO device 2100a may also have an optical connection 2142 to an optical feedthrough 2150. As shown, the optical feedthrough 2150 may include an optical fiber connector 2151 coupled to the optical connection 2142 and a corresponding optical fiber connector 2152. The optical fiber connector 2152 may be connected to a fiber optic cable 2154 to transmit optical signals between the ESOO device 2100a and the external device(s).

[0226] The external device(s) may similarly be configured to directly receive an optical signal or an electrical signal. Accordingly, the same approaches described above with respect to the devices 2103 may also be applied to the external device(s). This includes, for example, integrating an optical engine into the external device using another ESOO device or a heterogeneous process, or incorporating an optical transceiver (e.g., the optical transceiver 21220 illustrated in FIGs. 2.11A-2.11C) along the optical connection 2142 between the ESOO device 2100a and the external device. In the example of an optical transceiver, the optical transceiver(s) can be located in close physical proximity (e.g., less than or equal to 1 meter) to the external device(s).

[0227] Compared to conventional computing systems incorporating optical communication, the ESOO device 2100a allows optical signals to be transmitted directly between the ESOOdevice 2100a and the devices 2103. As a result, the computing system 2162a does not require an intervening retimer (e.g., a retimer in a NIC, or a DSP in an optical engine) to facilitate communication with the electrical switch 2104, thus eliminating a source of latency and reducing power consumption. Moreover, the ESOO device 2100a may transmit a signal to a device 2103 without converting the signal from an electrical signal to an optical signal or an optical signal to an electrical signal.

[0228] In some implementations, the electrical switch 2104 and / or the optical engine 2130 may be a passive device in the sense that it does not provide any functions to encode or decode an electrical signal or an optical signal. Rather, the electrical switch 2104 and / or the optical engine 2130 may be configured to rely on the host(s) 2101 to execute a protocol converter (or bridge) algorithm to encode and / or decode a signal according to a particular signal protocol. Additionally, the devices 2103 may each include an integrated microcontroller (e.g., a microcontroller in a NIC) to execute a protocol converter (or bridge) algorithm at the device 2103. Accordingly, the computing system 2162a may be configured to perform all encoding and decoding processes before the electrical signals are converted into optical signals. Thus, the optical engine 2130 itself may support any communication protocols used by the computing system 2162a and / or the device 2103. As described above, the signal protocols may include, but are not limited to, the PCIe standard(s), the CXL standard(s), the UCIe standard(s), the NVMe standard(s), and / or the Ethernet standard(s).

[0229] Moreover, the optical engine 2130 of the ESOO device 2100a allows the electrical switch 2104 to be communicatively coupled directly to devices 2103 separated from the electrical switch 2104 by appreciably greater distances compared to conventional electrical switches (e.g., hundreds to thousands of meters). The electrical switch 2104 may further transmit higher bandwidth and / or lower latency optical signals to and from the device(s) 2103. In some implementations, the electrical switch 2104 may directly transmit to a device 2103 and / or directly receive an optical signal from a device 2103 located up to about 1000 meters from the electrical switch 2104, including all values and sub-ranges in between. This, in turn, may allow the electrical switch 2104 to be communicatively coupled directly to most or, in some instances, all devices 2103 in a data center. In some implementations, the ESOO device 2100a may transmit optical signals (e.g., via the optical port(s) 2132) having a bandwidth up to about 128 gigatransfers per second (GT / s), including all values and sub-ranges in between.

[0230] The optical engine 2130 may be compatible for operation in an immersion cooling environment. This may be facilitated, in part, by the optical engine 2130 relying upon opticalcomponents, such as a waveguide, to transmit optical signals. Accordingly, the optical components may be readily sealed to reduce exposure to the coolant fluid of an immersion cooling system.

[0231] As described above, the ESOO device 2100a may transmit signals between a host 2101 and a device 2103. Following below are several example methods of using the ESOO device 2100a to transmit signals between one or more hosts 2101 and one or more devices 2103.

[0232] In one example, a method for transmitting a signal from a host 2101 to a device 2103 (e.g., an end point device) using the ESOO device 2100a may include the following steps:(A) receiving, at an electrical port 2112 of the electrical switch 2104, an electrical signal from the host(s) 2101 corresponding to the signal; (B) transmitting, from an electrical port 2114 of the electrical switch 2104, the electrical signal to an converter (e.g., an optical-to-electrical converter) of the ESOO device 2100a disposed within the optical engine 2130 where the electrical port 2114 and the converter correspond to the device 2103; (C) converting, by the converter, the electrical signal to an optical signal corresponding to the signal; and (D) transmitting, from an optical port 2132 communicatively coupled to the converter, the optical signal to the device 2103. If the device 2103 includes an integrated optical engine (e.g., via a second ESOO device dedicated to the device 2103, or via a heterogeneous integration process), the method can further include (E) converting, by the optical engine of the device 2103, the optical signal to an electrical signal for subsequent processing. If the device 2103 does not include an integrated optical engine, the method can further include (E) converting, by an optical transceiver 21220 in close physical proximity (e.g., less than or equal to 1 meter) to the device 2103, the optical signal to an electrical signal corresponding to the signal; and (F) receiving the electrical signal by the device 2103.

[0233] In another example, a method for transmitting a signal from a device 2103 (e.g., an end point device) to a host 2101 using the ESOO device 2100a may include the following steps: (A) receiving, at an optical port 2132 of the ESOO device 2100a, an optical signal from the device 2103 corresponding to the signal, the optical port coupled to an optical engine 2130;(B) converting, by a converter (e.g., an electrical-to-optical converter) of the ESOO device 2100a coupled to the optical port 2132 and disposed within the optical engine 2130, the optical signal to an electrical signal corresponding to the signal; (C) receiving, at an electrical port 2114 of an electrical switch 2104 in the ESOO device 2100a, the electrical signal; and (D) transmitting, from an electrical port 2112 of the electrical switch 2104 corresponding to the host 2101, the electrical signal to the host 2101. If the device 2103 includes an integrated optical engine (e.g.,via a second ESOO device dedicated to the device 2103, or via a heterogeneous integration process), the method can further include before step (A), (E) converting, by the optical engine of the device 2103, an electrical signal to the optical signal for transmission to the optical port 2132 of the ESOO device 2100a. If the device 2103 does not include an integrated optical engine, the method can further include before step (A), (E) converting, by an optical transceiver 21220 in close physical proximity (e.g., less than or equal to 1 meter) to the device 2103, an electrical signal to the optical signal corresponding to the signal; and (F) transmitting the optical signal from the optical transceiver 21220 to the optical port 2132 of the ESOO device 2100a.2.2 Example Architectures for Integrating the ESOO Device with a PU

[0234] It should be appreciated that the example layout of FIG. 2.4B is a non-limiting example. More generally, the ESOO device 2100a may be integrated with the host 2101 (i.e., the PU) in several ways as discussed below.

[0235] FIG. 2.11A shows a cross section of a standard board-level 2D integration architecture for a semiconductor structure 2300a that includes an ESOO device 2310 and a host 2101 according to an embodiment. The ESOO device 2310 can be the same as the ESOO device 2100a, the ESOO device 2100b, or the ESOO device 2100c. The host 2101 can include or can be a CPU, a GPU, an ASIC, an FPGA, or another PU. In some embodiments, the processor unit 2320 can include one or more CPUs, one or more GPUs, one or more ASICs, one or more FPGAs, and / or one or more other PUs.

[0236] The ESOO device 2310 includes an electrical switch 2104 and an optical device 2312. The optical device 2312 includes an optical engine. The optical device 2312 can be the same as the optical engine 2130 or the optical communications device 2172 (which includes the optical engine 2130). The ESOO device 2310 also includes a common package 2314 in which the electrical switch 2104 and the optical device 2312 are packaged (e.g., co-packaged), such as in co-packaged optics or as in-package optics. The electrical switch and the optical device 2312 are electrically connected through electrical connections 2316. The electrical connections 2316 can include or can be microbumps, hybrid bonds, or other electrical connections.

[0237] The ESOO device 2310 and the host 2101 are mounted on and electrically coupled to the same side (e.g., a first side) of a common substrate 2320 which can be an assembly substrate. The substrate 2320 can include a silicon substrate, an interposer, or another substrate. The electrical switch 2104 and the host 2101 are electrically coupled through customized electrical interconnection fabric 2322 defined in the substrate 2320. For example, at least some or all ofthe electrical ports 2112 of the electrical switch 2104 are electrically connected to the host 2101 (e.g., to electrical ports of the host 2101) via the electrical interconnection fabric 2322. The electrical interconnection fabric 2322 is customized according to the electrical input / output (I / O) configuration and / or number of electrical I / O ports of the host 2101, which may vary by manufacturer of the host 2101 and / or by part number of the host 2101.

[0238] The electrical switch 2104 is located between the optical device 2312 and the substrate 2320 so that the electrical interconnection fabric 2322 can be electrically coupled to the electrical switch 2104 in the ESOO device 2310. In other embodiments, the optical device 2312 can be located between the electrical switch 2104 and the substrate 2320 and electrical connections, such as wiring, are included in the common package 2314 to electrically connect the electrical switch 2104 to the host 2101 through the electrical interconnection fabric 2322. The substrate 2320 can be mounted on and electrically coupled to (e.g., via microbumps 2324 or other electrical connections) an optional PCB 2330.

[0239] FIG. 2.1 IB shows a cross section of a standard board-level 2.5D integration architecture for a semiconductor structure 2300b that includes an ESOO device 2310 and a host 2101 according to another embodiment. The semiconductor structure 2300b is the same as the semiconductor structure 2300a except that in the semiconductor structure 2300b an interposer 2340 is disposed on the substrate 2320 and between (a) the substrate 2320 and (b) the host 2101 and the ESOO device 2310. In FIG. 2.1 IB, the host 2101 and the ESOO device 2310 are mounted on and electrically coupled to the interposer 2340. The electrical switch 2104 and the host 2101 are electrically coupled through customized electrical interconnection fabric 2342 defined in the interposer 2340. The electrical interconnection fabric 2342 is customized according to the electrical I / O configuration and / or number of electrical I / O ports of the host 2101, which may vary by manufacturer of the host 2101 and / or by part number of the host 2101.

[0240] The electrical switch 2104 is located between the optical device 2312 and the interposer 2340 so that the electrical interconnection fabric 2342 can be electrically coupled to the electrical switch 2104 in the ESOO device 2310. The electrical interconnection fabric 2342 can also electrically couple the host 2101 and / or the ESOO device 2310 to the substrate 2320, and the substrate 2320 is electrically coupled to the optional PCB 2330 such as through microbumps 2324, as discussed above.

[0241] FIG. 2.11C shows a cross section of a standard system- level 3D integration architecture for a semiconductor structure 2300c that includes an ESOO device 2310 and a host 2101 according to another embodiment. The semiconductor structure 2300c is the same as thesemiconductor structure 2300a except that in the semiconductor structure 2300c, the ESOO device 2310 and the host 2101 are vertically stacked on the substrate 2320. In FIG. 2.11C, the host 2101 is disposed on the substrate 2320 and the ESOO device 2310 is disposed on the host 2101. The electrical switch 2104 and the host 2101 are electrically coupled and integrated through customized electrical connections 2352. The electrical connections 2352 can include or can be microbumps, hybrid bonds, or other electrical connections. The electrical connections 2352 are customized according to the electrical VO configuration and / or number of electrical VO ports of the host 2101, which may vary by manufacturer of the host 2101 and / or by part number of the host 2101.

[0242] FIG. 2.1 ID shows a cross section of another standard system-level 3D integration architecture for a semiconductor structure 2300d that includes an ESOO device 2310 and a host 2101 according to another embodiment. In this example, the placement of the ESOO device 2310, the electrical switch 2104 and the host 2101 are reversed compared to the semiconductor structure 2300c. In particular, the ESOO device 2310 is disposed directly onto the assembly substrate 2320. The optical engine 2312 is disposed on the ESOO device 2310, the electrical switch 2104 is disposed on the optical engine 2312, and the host 2101 is disposed on the electrical switch 2104.

[0243] The electrical switch 2104 is located between the optical device 2312 and the host 2101 so that the electrical connections 2352 can be electrically coupled to the electrical switch 2104 in the ESOO device 2310.

[0244] In semiconductor structures 2300a-c, the electrical switch 2104 in the ESOO device 2310 functions as a bridging structure for electrically connecting the optical engine 2310 with the host 2101. There are two interfaces and integrations needed for the electrical switch 2104. The first integration is the electrical interface between the electrical switch 2104 and the host 2101. The second integration is the electrical interface between the electrical switch 2104 and the optical engine 2310 (e.g., the optical engine 2130 within optical engine 2310).

[0245] In the first integration, the electrical interconnection fabric 2322, 2342 or electrical connections 2352 are customized based on the electrical VO configuration and / or the number of electrical VO ports of a particular host 2101 (e.g., the electrical configuration of a particular PU for the host 2101). The customization of the electrical interconnection fabric 2322, 2342 or electrical connections 2352 based on the electrical VO configuration of a particular host 2101 is a standard board / system-level integration. A standard board / system-level integration is much simpler (e.g., considerably less complex) and less expensive than the highly customized integrationneeded for the conventional heterogenous integration architectures illustrated in FIGs. 2.3(a)- 2.3(d).

[0246] In the second integration, the configuration and / or arrangement of the electrical ports 2114 in the electrical switch 2104 are standardized and correspond to the electrical ports 2131 in the optical engine 2130. Thus, the integration between the electrical switch 2104 and the optical engine 2130 is a universal hybrid integration where no customization is needed (e.g., of the electrical ports 2114 or of the electrical ports 2131).

[0247] The combination of the standard board / system-level integration (first integration) and the universal hybrid integration (second integration) for integrating a host PU and an optical engine allows the semiconductor structure to function as a versatile yet universally applicable platform for integrating a range of optical electronics, silicon photonics, and IC chips without the customization and expense of the conventional heterogenous integration architectures illustrated in FIGs. 2.1B-2.1D, 2.2, and 2.3(a)-2.3(d).

[0248] Referring to step 21201 of the method 21200 shown in FIG. 2.12, examples of electrically integrating the electrical switch 2104 of an ESOO device 2310 and a host 2101 are illustrated in FIGs. 2.11A-2.11C. For example, in FIG. 2.11 A, the electrical integration of the electrical switch 2104 and the host 2101 includes electrically coupling some or all of the electrical ports 2112 of the electrical switch 2104 to electrical VO ports of the host 2101 using the electrical interconnection fabric 2322 in the common substrate 2320. The electrical interconnection fabric 2322 is customized according to the electrical VO ports of the host 2101 and the electrical ports 2112 of the electrical switch 2104. The configuration and arrangement of the electrical VO ports of the host 2101 can vary according to the manufacturer and / or part number of the PU. The configuration and arrangement of the electrical ports 2112 of the electrical switch 2104 are standardized. Customizing the electrical interconnection fabric 2322 is a standard board-level integration process that is known in the art and is considerably less complex and expensive than hybrid integration, as discussed herein.

[0249] In FIG. 2.1 IB, the electrical integration of the electrical switch 2104 of an ESOO device 2310 and the host 2101 includes electrically coupling some or all of the electrical ports 2112 of the electrical switch 2104 to electrical VO ports of the host 2101 using the electrical interconnection fabric 2342 in the interposer 2340. The electrical interconnection fabric 2342 is customized according to the electrical VO ports of the host 2101 and the electrical ports 2112 of the electrical switch 2104. Customizing the electrical interconnection fabric 2342 is a standardboard-level integration process that is known in the art and is considerably less complex and expensive than hybrid integration, as discussed herein.

[0250] In FIG. 2.11C, the electrical integration of the electrical switch 2104 of an ESOO device 2310 and the host 2101 includes electrically coupling some or all of the electrical ports 2112 of the electrical switch 2104 to electrical VO ports of the host 2101 using the electrical connections 2352 (e.g., microbumps or hybrid bonds). The electrical connections 2352 are customized according to the electrical VO ports of the host 2101 and the electrical ports 2112 of the electrical switch 2104. Customizing the electrical connections 2352 is a standard system-level integration process that is known in the art and is considerably less complex and expensive than hybrid integration, as discussed herein. Similar customizations may be applied to the semiconductor device 2300d shown in FIG. 2.1 ID.

[0251] Since standard system-level or standard board-level integration is used to electrically integrate the electrical switch 2104 of an ESOO device 2310 and the host 2101, it is considerably simpler and inexpensive to perform alternative electrical integrations for hosts 2101 from different suppliers (and / or part numbers from the same supplier), for example to increase supplychain redundancy.

[0252] The electrical ports 2112 of the electrical switch 2104 (e.g., the electrical VO ports of the ESOO device 2310) are standardized and compatible with any host 2101 such as with different hosts manufactured by different entities. As such, the host 2101 can transmit signals to each device 2103 using a common electrical interface (e.g., the electrical ports 2112 of the electrical switch 2104) in the ESOO 2310. Similarly, each device 2103 can send signals to the host 2101 using the common electrical interface in the ESOO 2310.

[0253] In some embodiments, two or more hosts 2101 are electrically integrated with the ESOO device 2310. Each host 2101 can be electrically integrated with the ESOO device 2310 in the same or similar manner as described above (e.g., with reference to FIGs. 2.11A-2.11C). Each host 2101 can be supplied by a different manufacturer or can be from the same manufacturer but can have different part numbers, such that the electrical VO ports of each host 2101 are configured and / or arranged differently.

[0254] Referring to step 21202 of the method 21200 shown in FIG. 2.12, the optical VO ports of the ESOO device 2310 are standardized and compatible with each of the devices 2103. As such, the host 2101 can transmit signals to each device 2103 using a common optical interface in the ESOO 2310. Similarly, each device 2103 can send signals to the host 2101 using the common optical interface in the ESOO 2310. The optical integration and / or coupling of opticalI / O ports of the ESOO device 2310 to each device 2103 is a universal integration process. The optical VO ports of the ESOO device 2310 and the optical fibers 21210 can support multiple protocols for optical communication the devices 2103. The protocol for transmission of signals from the host 2101 to a given device 2103 can be selected or determined by the host 2101.

[0255] In ESOO device 2100a, the optical VO ports and the optical interface of the ESOO device 2100a are or include the optical ports 2132. In ESOO device 2100b and 2100c, the optical VO ports and the optical interface of the ESOO device 2100b and 2100c are or include the optical ports 2134.

[0256] An optical transceiver 21220 can be coupled to the optical fibers 21210 and each device 2103, as illustrated in FIGs. 2.11A-2.11C. The optical transceiver 21220 is configured to convert optical signals sent from the host 2101 to a respective device 2103 into electrical signals that can be received by the respective device 2103. The optical transceiver 21220 is also configured to convert electrical signals sent from the respective device 2103 to optical signals that can be transmitted over the optical fibers 21210 to be received by the optical VO ports of the ESOO device 2310 where the optical signals are converted to electrical signals that can be received by the host 2101. The optical transceiver 21220 can include or can be a pluggable optical transceiver (e.g., a pluggable optical engine 232), an onboard optical transceiver, a co-packaged optical transceiver, or another ESOO device (e.g., an ESOO device 2310). In some embodiments, an optical transceiver 21220 can be coupled to a plurality of devices 2103, for example when the optical transceiver 21220 includes or is coupled to a switch such as in an ESOO device. Each optical transceiver 21220 can be located in close physical proximity to the respective device(s) 2103, such as less than or equal to 1 meter and greater than or equal to about 1 millimeter or any distance or sub-range therebetween.

[0257] It should also be appreciated that the device(s) 2103 may be configured to directly receive an optical signal. For example, the device 2103 may include an integrated optical engine (e.g., via a dedicated ESOO device for that device 2103, or via a heterogenous integration process). Accordingly, the optical transceivers 21220 in FIGs. 2.11A-2.1 ID may not be present if the device(s) 2103 are able to receive optical signals directly.

[0258] In some embodiments, the host 2101 can be coupled to all devices 2103 but can transmit signals to only a subset of the devices 2103 (e.g., to perform tasks assigned by the host 2101) at a first point in time. The host 2101 can monitor the processing requirements of the various tasks performed by the subset of the devices 2103, under the control of the host 2101, and can compare the processing requirements with the processing capacity of the subset of thedevices 2103. When the processing requirements exceed a predetermined upper threshold (e.g., at a second point in time), the host 2101 can transmit signals to one or more additional devices 2103, to increase the number of the subset of the devices and to increase the processing capacity of the subset of the devices. The predetermined upper threshold can be equal to the processing capacity of the subset of the devices or can be related to (e.g., a predetermined percentage of) the processing capacity of the subset of the devices.

[0259] In some embodiments, when the processing requirements fall below a predetermined low threshold (e.g., at a third point in time), the host 2101 can decrease the number of the subset of devices 2103 that are performing tasks assigned by the host. Decreasing the number of the subset of devices decrease the processing capacity of the subset of the devices and reduces energy consumption. The predetermined lower threshold can be related to (e.g., a predetermined percentage of) the processing capacity of the subset of the devices.

[0260] As such, the number of devices 2103 used to perform tasks under the control of the host 2101 can be changed to increase or decrease the effective processing capacity of the devices based on the load or demand from the host 2101.2.3 Example Computing Assembly Architectures

[0261] As described above, the ESOO device 2100a is configured to provide a direct optical connection to one or more devices 2103. This optical connection allows the ESOO device 2100a and the device(s) 2103 to be separated by distances on the order of hundreds of meters or even thousands of meters without incurring significant signal degradation or device-added latency, e.g., by a retimer (e.g., a DSP in an optical engine). Moreover, the ESOO device 2100a may appreciably simplify integration in a computing system, for example, by eliminating NICs. These aspects of the ESOO device 2100a allow for greater flexibility in the overall design and architecture of a data center and, in particular, how computing systems are connected to one another. Following below are several illustrative examples of different architectures for computing assemblies to showcase the flexibility afforded by incorporating the ESOO device 2100a.

[0262] FIG. 2.5 shows an example computing assembly 2160a that adopts a similar architecture as a conventional computing system (see, for example, the computing system 240a). This example shows that the ESOO device 2100a may be readily integrated into conventional architectures while still providing improvements to performance, in part, by eliminating NICs in the computing systems. As shown, the computing assembly 2160a includes computing systems 2162a-l and 2162a-2 communicatively coupled to a ToR switch 250 via respective fiber opticcables 2154a. Each fiber optic cable 2154a may be connected to the computing systems 2162a-l and 2162a-2 via respective optical feedthroughs 2150 and to electrical ports of the ToR switch 250 via respective optical engines 232. In this example, the host 2101 of each computing system 2162a-l and 2162a-2 and the processor 251 of the ToRs switch 250 may execute a protocol con- verter / bridge algorithm to encode and decode signals transmitted between the computing systems 2162a-l / 2162a-2 and the ToR switch 250. Compared to the fiber optic cables 236 in the computing assembly 240a, the fiber optic cable 2154a includes only one optical engine 232, thus reducing latency and power consumption by eliminating one NIC and, thus, one optical engine between the computing systems 2162a- 1 and 2162a-2 and the ToR switch 250. In some implementations, the computing assembly 2160a may be implemented using a conventional server rack structure. For example, the computing systems 2162a-l and 2162a-2 and the ToR switch 250 may each be a modular system installed onto a rack.

[0263] FIG. 2.5 further shows an example computing assembly 2160b that includes an optical switch 2170 instead of the ToR switch 250 of the computing assembly 2160a. As shown, the computing assembly 2160b once again includes the computing systems 2162a-l and 2162a- 2. In this example, the computing systems 2162a-l and 2162a-2 are each connected to the optical switch 2170 via fiber optic cables 2154b where each fiber optic cable 2154b does not include any optical engines. In particular, the fiber optic cable 2154b is connected to the computing systems 2162a-l and 2162a-2 and the optical switch 2170 via respective optical feedthroughs 2150. The optical switch 2170, in turn, may include a controller 2171 and various optical components (not shown) to direct optical signals between the computing systems 2162a-l and 2162a-2 and / or between each of the computing systems 2162a-l and 2162a-2 and the spine 252. With this architecture, the computing assembly 2160b may not include any NICs between each of the computing systems 2162a-l and 2162a-2 and the spine 252, further reducing latency and power consumption.

[0264] FIG. 2.5 shows yet another example computing assembly 2160c that does not include a programmable switch. Rather, the computing systems 2162a-l and 2162a-2 are directly connected to the spine 252. This example may further simplify the computing assembly 2160c, in part, by eliminating the programmable switch.

[0265] The above examples showcase how the ESOO device 2100a may facilitate connection with other computing assemblies. It should be appreciated that the ESOO device 2100a may also allow computing systems to be directly connected to one another. Further, the computing systems may not be physically co-located (e.g., on the same server rack).

[0266] For example, FIG. 2.6 shows a computing assembly 2160d that includes a computing system 2162b with the ESOO device 2100a and optical feedthroughs 2150a, 2150b, and 2150c optically coupled to the ESOO device 2100a. For instance, each of the optical feedthroughs 2150a, 2150b, and 2150c may be coupled to respective optical ports 2132 of the ESOO device 2100a.

[0267] As shown, the computing system 2162b may be directly connected to a computing system 2162a in the computing assembly 2160d by connecting the optical feedthrough 2150a of the computing system 2162b to an optical feedthrough 2150 of the computing system 2162a with a fiber optic cable 2154b. The computing system 2162a may also include the ESOO device 2100a, a host 2101, and a device 2103. Thus, the computing systems 2162b and 2162a may directly communicate with one another without a programmable switch (e.g., the ToR switch 250, the optical switch 2170) or a NIC, thus reducing latency and power consumption.

[0268] The computing system 2162b may also be directly connected to a computing system 2162a in a computing assembly 2160e that is physically separate from the computing assembly 2160d. As shown in FIG. 2.6, the optical feedthrough 2150b may be directly coupled to the optical feedthrough 2150 of the computing system 2162a via a fiber optic cable 2154b. The computing system 2162a may also include the ESOO device 2100a, a host 2101, and a device 2103. Accordingly, the computing systems 2162b and 2162a may also directly communicate with one another without a programmable switch or a NIC.

[0269] It should be appreciated that computing systems incorporating the ESOO device 2100a do not necessarily require connection to another computing system with the ESOO device 2100a. Rather, the ESOO device 2100a may also connect to conventional computing systems with NICs using, in part, to a fiber optic cable with an optical engine to facilitate conversion between an optical signal and an electrical signal for communication with devices 2103 that are configured to communicate using only electrical signals. A microcontroller integrated in the NIC or a DSP in the optical engine may execute a protocol converter / bridge algorithm to encode and / or decode signals transmitted from or to the conventional computing system.

[0270] For example, FIG. 2.6 shows the computing system 2162b may directly connect to a computing system 2162c in a computing assembly 2160f that is physically separate from the computing assembly 2160d. As shown, the computing system 2162c may include devices 2103 and a NIC 230 electrically coupled to the devices 2103. The optical feedthrough 2150c may thus be connected to the NIC 230 via a fiber optic cable 2154a, which includes an optical engine 232 for connection to the NIC 230. Although the addition of the NIC 230 may increase latency andpower consumption, this arrangement may be preferable in applications where the devices 2103 are off-the-shelf devices.

[0271] As shown in FIG. 2.6, the ESOO device 2100a may readily facilitate connection between physically separate computing systems. As described above, the optical connections supported by the ESOO device 2100a may allow connections between computing systems located at appreciably large distances (e.g., hundreds to thousands of meters). This, in turn, may allow computing assemblies to be constructed in a physically disaggregated manner. For example, the computing assemblies 2160d, 2160e, and 2160f in FIG. 2.6 may function as a single disaggregated computing assembly within a data center. Any one of the computing systems 2162b- 2162c may further be connected to a spine (e.g., the spine 252) to facilitate communication between the disaggregated computing assembly with another computing assembly in the data center.2.4 An Example ESOO device with an Integrated Optical Engine and Optical Switch

[0272] FIG. 2.7A shows an example ESOO device 2100b that includes an optical communications device 2172 that includes an integrated optical engine 2130 and an integrated optical switch 2173 (also referred to herein as an “optical switch 2173”). As shown, the ESOO device 2100b includes an electrical switch 2104 having a switch fabric 2110 with multiple electrical ports 2112a-2112n for connection to corresponding hosts 2101a-2101n via electrical connections 2102 and multiple electrical ports 2114a-2114m for connection to the optical communications device 2172 and, in particular, the optical engine 2130 via electrical connections 2140. The switch fabric 2110 and the optical engine 2130 of the ESOO device 2100b may incorporate some or all of the features described above with respect to the switch fabric 2110 and the optical engine 2130 of the ESOO device 2100a. Accordingly, a discussion of these features is not repeated below for brevity.

[0273] The optical switch 2173 and the optical engine 2130 may be integrated into the optical communications device 2172 in the sense that they are fabricated as a single cohesive device. For example, the optical communications device 2172 may be fabricated as a microchip with various components of the optical switch 2173 and the optical engine 2130 formed therein. The optical communications device 2172, in turn, may be packaged together with other components of the

[0274] ESOO device 2100b (e.g., the electrical switch 2104 and / or the switch fabric2110).

[0275] The integration of the optical switch 2173 into the ESOO device 2100b provides several benefits. For example, the optical switch 2173 may provide the same or similar functionality as a conventional external switch (e.g., an Ethernet switch with optical engines, or an external optical switch) connected to a conventional electrical switch. By integrating the optical switch 2173 into the ESOO device 2100b, the number of external switches used in a data center may be appreciably reduced or, in some instances, external switches may be eliminated entirely. For example, ToR switches may be eliminated while higher tier switches (e.g., switches located in the spine 252, or other higher tier switches deployed in a data center) may be retained. As a result, a computing assembly that includes one or more computing systems with respective ESOO devices 2100b may be readily expanded to include other computing systems and / or devices that may or may not be physically collocated with the computing assembly without introducing additional hardware.

[0276] Additionally, the optical switch 2173 may provide appreciably less latency compared to conventional external switches. For example, conventional external switches may provide a latency around 200 ns while the optical switch 2173 may provide latencies of about 5 ns. Moreover, the optical switch 2173 may provide relatively higher bandwidth densities compared to conventional external switches. For example, the optical switch 2173 may provide bandwidth densities greater than or equal to about 500Gbps / mm.

[0277] In another example, the integration of an optical switching function into the ESOO device 2100b may provide greater flexibility to configure and reconfigure connections between the hosts 2101 and the devices 2103 across a data center (see, for example, FIGs. 2.9A and 2.9B). This, in turn, may facilitate the transmission of signals between computing systems located at different locations within the data center in a scalable and cost-efficient manner. In some implementations, the connections / topology configurations between the optical switch 2173 of the ESOO device 2100b and the devices 2103 may be reconfigured in near real-time (e.g., less than 1 second) unlike conventional PCIe Switch and Ethernet switches-based Al infrastructure.

[0278] In yet another example, the optical switch 2173 may be compatible for operation in an immersion cooling environment unlike conventional external switches. This may be facilitated, in part, by the optical switch 2173 relying upon optical components, such as a waveguide, to transmit optical signals rather than free space transmission as is typical in conventional external switches. Accordingly, the optical components may be readily sealed to reduce exposure to the coolant fluid of an immersion cooling system, as discussed in further detail below.

[0279] The optical communications device 2172 includes multiple optical ports 2133a- 2133m (generally referred to herein as an optical port 2133) to facilitate connection between the optical engine 2130 and the optical switch 2173 and multiple optical ports 2134a-2134k (generally referred to herein as an optical port 2134) for connection to devices 2103a-2103m via corresponding optical connections 2142. The optical switch 2173 is optically coupled to the optical ports 2133a-2133m and to the optical ports 2134a-2134k. The ESOO device 2100b may further include a microcontroller unit (MCU) 2174 to electronically control the optical switch 2173 during operation. The MCU 2174 may include electronic circuitry to transmit electrical signals to the optical switch 2173 to control the transmission of optical signals between optical ports 2133 and optical ports 2134. For example, the MCU 2174 may provide electrical signals that cause a voltage to be applied across a switching device resulting in an optical signal being transmitted to a particular output of the switching device (see, for example, details of the switching devices 2175 below).

[0280] In some implementations, the MCU 2174 may be a standalone device (e.g., a standalone chip). As shown in FIG. 2.7A, the MCU 2174 may be connected to one or more electrical ports 2116 of the switch fabric 2110 via electrical connections 2146. The MCU 2174 may further be connected to one or more electrical ports 2135 of the optical switch 2173 via electrical connections 2144. In this manner, the MCU 2174 may be communicatively coupled to the host(s) 2101, via the electrical switch 2104 and / or via the switch fabric 2110, and to the optical switch 2173, thus providing a way for the host(s) 2101 to transmit instructions to the MCU 2174 to facilitate transmission of signals between a host 2101 and a particular device 2103.

[0281] It should be appreciated that the MCU 2174 of FIG. 2.7A is a non-limiting example. In another example, FIG. 2.7B shows an ESOO device 2100c that includes an MCU 2174 integrated into the electrical switch 2104, such as the switch fabric 2110. This may be accomplished, in part, by the electrical switch 2104 providing one or more electrical ports 2117 for connection to the electrical port(s) 2135 of the optical switch 2173 via electrical connections 2144. In some implementations, the electrical switch 2104 and / or via the switch fabric 2110 may thus incorporate all of the electronic circuity in the ESOO device 2100c. Additionally, the optical communications device 2172 may incorporate all of the optical components (e.g., the photonic circuitry) in ESOO device 2100c.

[0282] The optical switch 2173 provides a way to dynamically route optical signals between the optical engine 2130 and the devices 2103a-2103m communicatively coupled to the ESOO device 2100b. For example, the optical switch 2173 may initially transmit signals fromthe optical port 2133a to the optical port 2134a. During operation, the optical switch 2173 may be reconfigured to transmit signals from the optical port 2133a to the optical port 2134b. Generally, the optical switch 2173 may be configured to transmit optical signals from each of the optical ports 2133a-2133m to any one of the optical ports 2134a-2134k and from each of the optical ports 2134a-2134k to any one of the optical ports 2133a-2133m. In this manner, the optical switch 2173 may dynamically route optical signals from each host 2101 to any of the devices 2103a-2103m as desired.

[0283] The number of optical ports 2133 and the number of optical ports 2134 may be equal or may be different. For example, the number of optical ports 2133 may be less than, equal to, or greater than the number of optical ports 2134. In some implementations, the number of optical ports 2133 may be equal to 256. More generally, the number of optical ports 2133 may range from 2 to 512, including all values and sub-ranges in between. In some implementations, the number of optical ports 2134 may be equal to 256. In other words, the ESOO device 2100b and 2100c may be communicatively coupled to 256 different devices 2103. More generally, the number of optical ports 2134 may range from 2 to 512, including all values and sub-ranges in between. It should be appreciated that the foregoing ranges and numbers of optical ports 2133 and 2134 in the ESOO device 2100b and 2100c are non-limiting examples. More generally, the ESOO device 2100b and 2100c may be designed to support an arbitrary number of electrical ports and / or optical ports.

[0284] The optical switch 2173 may provide its switching functionality by incorporating one or more switching devices to route optical signals between the desired optical ports 2133 and 2134. As an illustrative example, FIG. 2.7C shows an example layout of an optical switch 2173 with multiple switching devices 2175. As shown, each switching device 2175 provides routing functionality and is thus configured to route an optical signal from one input path to one of two output paths. For example, a switching device 2175-1 may receive an optical signal being transmitted from one optical port 2133 to one optical port 2134 at an input path 2180a and direct the optical signal to either the output path 2180b or the output path 2180c. In some implementations, the switching devices 2175 may provide bidirectional communication to facilitate transmission of optical signals from the optical ports 2133 to the optical ports 2134 and from the optical ports 2134 to the optical ports 2133. In another example, a switching device 2175-2 may receive an optical signal being transmitted from one optical port 2134 to one optical port 2133 at an input path 2181a and direct the optical signal to either the output path 2181b or the output path 2181c.

[0285] FIG. 2.7C further shows the switching devices 2175 may be arranged in an array where each switching device 2175 is optically coupled to one another, the optical ports 2133, and / or the optical ports 2134 via respective optical connections 2175. During operation, optical signals originating from one optical port 2133 may pass through one or more switching devices 2175 with each switching device 2175 directing the optical signal such that the optical signal is transmitted to the desired optical port 2134. In the example shown in FIG. 2.7C, the optical switch 2173 may include a four by five array of switching devices 2175 with four switching devices 2175 connected to the ports 2133 and the ports 2134 arranged such that optical signals pass through five switching devices 2175. More generally, the size of the array of switching devices 2175 may scale depending on the number of ports 2133 and 2134 in the optical switch 2172. For example, a switching device 2175 may be included for each port 2133 and 2134. In some implementations, one switching device 2175 may provide connections to two ports 2133 or 2134. It should also be appreciated that the number of switching devices 2175 may vary between the ports 2133 and 2134. For example, the optical switch 2173 may include switching devices 2175 arranged in a cascade manner with more switching devices 2175 disposed on one side than the other. This may occur, for example, if the number of optical ports 2133 and 2134 are not equal.

[0286] The switching device 2175 may include a switching device element with at least one input port and two or more output ports. In some implementations, the switching device 2175 may include two input ports and two output ports as shown in FIG. 2.7C. However, it should be appreciated that, in some implementations, the switching device 2175 may support more than two inputs and / or more than two outputs. The switching device 2175 may further support bidirectional communication meaning optical signals may be transmitted from the input ports to the output ports and vice-versa. The switching element is responsible for directing an optical signal from the input port(s) to one of the output ports. The switching element may be based on various types of switching devices including, but not limited to, a Mach-Zehnder interferometer (MZI), and a multimode interferometer (MMI). The switching element may be electrically coupled to electrical port(s) 2135 of the optical switch 2173 via electrical connections 2177 to receive electrical signals from the MCU 2174. As described above, the electrical signals may configure the switching element to transmit optical signals to a particular output path.

[0287] The optical switch 2173 may support the transmission of optical signals emitted at wavelengths corresponding to one or more bands commonly used for fiber optic communication including, but not limited to, the O-band (wavelength: 1260-1360 nm), the E-band (wavelength: 1360-1460 nm), the S-band (wavelength: 1460-1530 nm), the C-band (wavelength: 1530-1565nm), and the L-band (wavelength: 1565-1625 nm). In some implementations, the optical switch 2173 may support transmission of optical signals corresponding to only one band. In some implementations, the optical switch 2173 may support transmission of optical signals corresponding to multiple bands (e.g., to support multiplexing of optical signals at different frequencies).

[0288] The optical communications device 2172 is generally packaged together (e.g., copackaged) with the electrical switch 2104. For example, the electrical switch 2104 (e.g., the switch fabric 2110) and the optical communications device 2172 may be mounted to a common substrate and thereafter sealed by a single enclosure (e.g., a lid).

[0289] In some implementations, the optical communications device 2172 may be a copackaged optic device. For example, the optical communications device 2172 may be implemented as a photonic integrated circuit that incorporates both the optical engine 2130 and the optical switch 2173. For example, the optical communications device 2172 may be a microchip that includes the various components of the optical engine 2130 (e.g., light source(s), photodetectors)) and the optical switch 2173 (e.g., switching device(s)), the optical connections between the optical engine 2130 and the optical switch 2173, any electrical ports to facilitate connection to the electrical switch 2104 (e.g., the switch fabric 2110) and / or to the MCU 2174, and / or any optical ports to facilitate connection to the devices 2103. The foregoing components may be fabricated onto a substrate of the microchip. The optical communications device 2172, in turn, may be mounted to a second substrate (e.g., a PCB, an interposer) that also supports the electrical switch 2104 (e.g., the switch fabric 2110). The second substrate may thus provide the electrical connections to facilitate communication between the electrical switch 2104 and the optical communications device 2172.

[0290] The optical communications device 2172 may be mounted to one or more electrical contacts on the second substrate, e.g., via solder, one or more pin connections, and / or the like. The optical communications device 2172 may further include integrated electrical connections that connect the electrical contacts of the second substrate to the optical engine 2130 and the optical switch 2173 via the electrical ports 2135. The optical communications device 2172 may include, as part of the optical ports 2133, on-chip optical components to facilitate the transmission of optical signals between the optical engine 2130 and the optical switch 2173. For example, the on-chip optical components may include a plurality of waveguides. Thus, in some implementations, the optical switch 2173 may not transmit any optical signals in free space. The optical ports 2134 of the optical communications device 2172 may be connected to a plurality of fiber optic cables to carry optical signals to and from the ESOO device 2100b, 2100c. In someimplementations, the fiber optic cables may be connected to the optical ports 2134 via a permanent connection, such as a pigtail connection.

[0291] In some implementations, the ESOO devices disclosed herein may be sealed devices to significantly reduce or, in some instances, prevent exposure of the components of the ESOO device (e.g., electrical switch 2104, the switch fabric 2110, the optical communications device 2172, and / or the MCU 2174) to the coolant liquid of an immersion cooling system. The connections between the optical ports 2134 and the fiber optic cables may also be sealed to limit exposure to the coolant liquid. This may be accomplished, for example, by applying a sealant compound to surround and / or otherwise encase the ESOO devices and / or the connections between the optical ports 2134 and the fiber optic cables. Various sealant compounds may be used including, but not limited to, 3M Scotch-Weld DP420, Zymet X2821, Zymet UA-2605-B, Zymet UVE- 1017-2, Zymet CN- 1780-5, Zymet X2824, and / or Zymet UA-2701.

[0292] FIG. 2.8 shows an example physical layout of a computing system 2162d incorporating the ESOO device 2100b. Similar to the computing system 2162a, the computing system 2162d may include one or more hosts 2101 electrically coupled to the ESOO device 2100b via an electrical connection 2102 coupled to an electrical port 2112 of the electrical switch 2104. This may be accomplished, for example, by mounting the ESOO device 2100b and the host 2101 to a single PCB. In some implementations, the host 2101 and / or the ESOO device 2100b may each be fabricated as a discrete device and thereafter mounted to corresponding electrical contacts on the PCB, e.g., via solder, one or more pin connections, and / or the like. It should be appreciated that, in some implementations, the ESOO device 2100b and the host 2101 may be mounted to different PCBs and communicatively coupled together via one or more electrical cables. The ESOO device 2100b may generally be coupled to various hosts 2101 including, but not limited to, a CPU, a GPU, an ASIC, an FPGA, and / or a root complex (e.g., to facilitate transactions to and from the CPU, the GPU, the ASIC, and / or the FPGA). It should be appreciated that the computing system 2162d may include multiple hosts 2101 that are each electrically coupled to the ESOO device 2100b via respective electrical connections 2102.

[0293] FIG. 2.8 also shows the computing system 2162d may include one or more devices 2103 and the ESOO device 2100b may be optically coupled to the device(s) 2103 via optical connections 2142a. The optical connections 2142a may thus be coupled to respective optical ports 2134 of the ESOO device 2100b. In some implementations, the devices 2103 may be mounted to the same PCB as the ESOO device 2100b. Accordingly, the optical connections 2142a may include waveguides formed directly onto the PCB. Alternatively, the opticalconnections 2142a may include flyover cables with one or more optical fibers. As described above the optical fiber(s) may be connected to respective ports 2134 via corresponding pigtail connections. In some implementations, the devices 2103 may be mounted to a different PCB than the ESOO device 2100b and thus communicatively coupled together via one or more cables with one or more optical fibers.

[0294] In some implementations, the devices 2103 may be configured to directly receive an optical signal. For example, the device 2103 may include an integrated optical engine to convert between an optical signal and an electrical signal. The optical engine may be integrated using another ESOO device dedicated for that device 2103 similar to the ESOO device 2100a (see, for example, FIGs. 2.11A-2.1 ID). It should also be appreciated that the optical engine may be integrated using any one of the conventional heterogeneous approaches described above in FIG. 2.3.

[0295] In some implementations, the devices 2103 may be configured only to receive an electrical signal. Accordingly, the optical connection 2142a may include an optical engine to convert between an optical signal and an electrical signal for communication with the device 2103. For example, an optical transceiver (e.g., the optical transceiver 21220 illustrated in FIGs. 2.11 A-2.11C) can be coupled to the optical connection 2142a and one or more devices 2103. Furthermore, the optical transceiver may be located in close proximity to the device 2103 (e.g., less than or equal to 1 meter).

[0296] The ESOO device 2100b may also be communicatively coupled to one or more external devices located outside the computing system 2162d. For example, FIG. 2.8 shows the computing system 2162d may include multiple optical connections 2142b connected to the ESOO device 2100b and extending away from the computing system 2162d for connection with other devices, computing systems, and / or computing assemblies. Similar to the ESOO device 2100a, the ESOO device 2100b may provide direct transmission of optical signals between the ESOO device 2100b and another device, computing system, and / or computing assembly. Accordingly, the computing system 2162d may also not include any intervening retimer (e.g., a retimer in a NIC, or a DSP in an optical engine) to facilitate communication with the ESOO device 2100b.

[0297] The device(s), computing system(s), and / or computing assembl(ies) connected to the ESOO device 2100b may be configured to directly receive an optical signal or an electrical signal. Accordingly, the same approaches described above with respect to the devices 2103 may also be applied to the device(s), computing system(s), and / or computing assembl(ies). Thisincludes, for example, integrating an optical engine into the device(s), computing system(s), and / or computing assembl(ies) using another ESOO device or a heterogeneous process, or incorporating an optical transceiver (e.g., the optical transceiver 21220 illustrated in FIGs. 2.11A- 2.11C) along the optical connection 2142b between the ESOO device 2100a and the external device. In the example of an optical transceiver, the optical transceiver(s) can be located in close physical proximity (e.g., less than or equal to 1 meter) to the device(s), computing system(s), and / or computing assembl(ies).

[0298] It is noted that in the above discussion of FIG. 2.8, the ESOO device 2100b can be replaced with the ESOO device 2100c.

[0299] As described above, the ESOO device 2100b, 2100c may transmit signals between a host 2101 and a device 2103. Following below are several example methods of using the ESOO device 2100b, 2100c to transmit signals between a host 2101 and a device 2103.

[0300] In one example, a method for transmitting a signal from a host 2101 to a device2103 (e.g., an end point device) using the ESOO device 2100b, 2100c may include the following steps: (A) receiving, at an electrical port 2112 of the electrical switch 2104, the electrical switch2104 in the ESOO device 2100b, 2100c, an electrical signal from the host 2101 corresponding to the signal; (B) routing, by a switch fabric 2110 of the electrical switch 2104 coupled to the electrical port 2112, the electrical signal to an electrical port 2114 of the electrical switch 2104; (C) transmitting, from the electrical port 2114, the electrical signal to an optical engine 2130 of the ESOO device 2100b, 2100c; (D) converting, by the optical engine 2130, the electrical signal to an optical signal corresponding to the signal; (E) transmitting, from an optical port 2133 of the ESOO device 2100b, 2100c coupled to the optical engine 2130, the optical signal to an optical switch 2173 of the ESOO device 2100b, 2100c; (F) routing, by the optical switch 2173, the optical signal to an optical port 2134 of the ESOO device 2100b, 2100c; and (G) transmitting, from the optical port 2134, the optical signal to the device 2103. If the device 2103 includes an integrated optical engine (e.g., via a second ESOO device dedicated to the device 2103, or via a heterogeneous integration process), the method can further include (H) converting, by the optical engine of the device 2103, the optical signal to an electrical signal for subsequent processing. If the device 2103 does not include an integrated optical engine, the method can further include (H) converting, by an optical transceiver 21220 in close physical proximity (e.g., less than or equal to 1 meter) to the device 2103, the optical signal to an electrical signal corresponding to the signal; and (I) receiving the electrical signal by the device 2103.

[0301] In another example, a method for transmitting a signal from a device 2103 to a host 2101 using the ESOO device 2100b, 2100c may include the following steps: (A) receiving, at an optical port 2134 of the ESOO device 2100b, 2100c, an optical signal from the device 2103 corresponding to the signal; (B) routing, by the optical switch 2173 of the ESOO device 2100b, 2100c, the optical signal to an optical port 2133 of the ESOO device 2100b, 2100c; (C) transmitting, from the optical port 2133, the optical signal to an optical engine 2130 of the ESOO device 2100b, 2100c; (D) converting, by the optical engine 2130, the optical signal to an electrical signal corresponding to the signal; (E) transmitting, from an electrical port 2114 of the ESOO device 2100b, 2100c coupled to the optical engine 2130, the electrical signal to a switch fabric 2110 of the electrical switch 2104, the electrical switch 2104 in the ESOO device 2100b, 2100c; (F) routing, by the switch fabric 2110 of the electrical switch 2104, the electrical signal to an electrical port 2112 of the ESOO device 2100b, 2100c; and (G) transmitting, from the electrical port 2112, the electrical signal to the host 2101. If the device 2103 includes an integrated optical engine (e.g., via a second ESOO device dedicated to the device 2103, or via a heterogeneous integration process), the method can further include before step (A), (H) converting, by the optical engine of the device 2103, an electrical signal to the optical signal for transmission to the optical port 2134 of the ESOO device 2100b, 2100c. If the device 2103 does not include an integrated optical engine, the method can further include before step (A), (H) converting, by an optical transceiver 21220 in close physical proximity (e.g., less than or equal to 1 meter) to the device 2103, an electrical signal to the optical signal corresponding to the signal; and (I) transmitting the optical signal from the optical transceiver 21220 to the optical port 2134 of the ESOO device 2100b, 2100c.2.5 Example Computing Assembly Architectures

[0302] The integration of the optical switch 2173 into the ESOO device 2100b, 2100c may provide additional flexibility to connect a computing system with the ESOO device 2100b, 2100c to other devices, computing systems, and / or computing assemblies compared to the ESOO device 2100a. In particular, computing systems that incorporate the ESOO device 2100b, 2100c may appreciably reduce the number of conventional external switches or, in some instances, eliminate external switches entirely as described above. Following below are several illustrative examples of different architectures for computing assemblies to showcase the flexibility afforded by incorporating the ESOO device 2100b, 2100c.

[0303] FIG. 2.9A shows an example computing assembly 2160g that includes computing systems 2162d-l and 2162d-2. As shown, each of the computing systems 2162d-l and 2162d-2 may include an ESOO device 2100b that directly connects to a spine 252 via respective optical connections 2142b. In this example, the ESOO devices 2100b may eliminate the need for a separate ToR switch in the computing assembly 2160g. It is noted that although FIG. 2.9A illustrates ESOO devices 2100b, one, some, or all ESOO devices 2100b can be replaced with ESOO devices 2100c.

[0304] Additionally, the ESOO device 2100b, 2100c may facilitate direct connections to other computing systems and / or devices. For example, FIG. 2.9B shows computing assemblies 2160h and 2160i, which each include computing systems 2162d-l and 2162d-2. For each of the computing assemblies 2160h and 2160i, the ESOO devices 2100b of the respective computing systems 2162d-l and 2162d-2 may be connected together via an optical connection 2142b. Additionally, the respective ESOO devices 2100b in the computing systems 2162d-l of the computing assemblies 2160h and 2160i may be connected together via an optical connection 2142b. By connecting the computing systems 2162d-l and 2162d-2 in the manner shown in FIG. 2.9B, the computing assemblies 2160h and 2160i may effectively operate as a single computing assembly with each computing system directly connected to at least one other computing system. It is noted that although FIG. 2.9B illustrates ESOO devices 2100b, one, some, or all ESOO devices 2100b can be replaced with ESOO devices 2100c.

[0305] As described above, the ESOO devices 2100a-c disclosed herein may be compatible in an immersion cooling environment. Specifically, the ESOO devices 2100a-c may be readily submerged in the coolant liquid of an immersion cooling system. FIG. 2.10 shows an example two-phase immersion cooling system 2200 that includes the computing systems 22162a and 22162d. As shown, the system 2200 includes a tank 2211 defining a tank volume 2212 to contain coolant liquid 2220. The computing systems 2162a and 2162d include ESOO devices 2100a and 2100b, respectively, which are submerged in the coolant liquid 2220. The system 2210 further includes a cooling distribution unit 2213 with a condenser coil 2214 that carries a secondary coolant. The condenser coil 2214 is partially disposed in the tank volume 2212 above the coolant liquid 2220. During operation, the electronic components of the computing systems 2162a and 2162d may generate heat, which is dissipated to the coolant liquid. When the coolant liquid is sufficiently heated, the coolant liquid vaporizes producing coolant vapor 2221, which rises above into a gas space 2224 within the tank volume 2212 containing a mixture 2223 of air and coolant vapor. As the coolant vapor 2221 physically contacts the condenser coil 2214, heat from thecoolant vapor 2221 is transferred to the secondary coolant carried by the condenser coil 2214, thus causing the coolant vapor 2221 to condense to liquid droplets 1 that fall back into the coolant liquid 2220 below. The secondary coolant is circulated to the cooling distribution unit 2213 where the heat is thereafter dissipated from the secondary coolant.

[0306] It is noted that although FIG. 2.10 illustrates an ESOO device 2100a and an ESOO device 2100b in computing systems 2162a and 2162d, respectively, the computing systems 2162a and 2162d can include an ESOO device 2100b and an ESOO device 2100a, respectively, in other embodiments. Additionally or alternatively, the ESOO device 2100a and / or the ESOO device 2100b can be replaced with an ESOO device 2100c.3. Conclusion

[0307] All parameters, dimensions, materials, and configurations described herein are meant to be example and the actual parameters, dimensions, materials, and / or configurations will depend upon the specific application or applications for which the inventive teachings is / are used. It is to be understood that the foregoing embodiments are presented primarily by way of example and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and / or method described herein.

[0308] In addition, any combination of two or more such features, systems, articles, materials, kits, and / or methods, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure. Other substitutions, modifications, changes, and omissions may be made in the design, operating conditions and arrangement of respective elements of the example implementations without departing from the scope of the present disclosure. The use of a numerical range does not preclude equivalents that fall outside the range that fulfill the same function, in the same way, to produce the same result.

[0309] The above-described embodiments can be implemented in multiple ways. For example, embodiments may be implemented using hardware, software or a combination thereof. When implemented in software, the software code can be executed on a suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers.

[0310] Further, it should be appreciated that a computer may be embodied in any of a number of forms, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer. Additionally, a computer may be embedded in a device not generally regarded as a computer but with suitable processing capabilities, including a Personal Digital Assistant (PDA), a smart phone or any other suitable portable or fixed electronic device.

[0311] Also, a computer may have one or more input and output devices. These devices can be used, among other things, to present a user interface. Examples of output devices that can be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound generating devices for audible presentation of output. Examples of input devices that can be used for a user interface include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computer may receive input information through speech recognition or in other audible format.

[0312] Such computers may be interconnected by one or more networks in a suitable form, including a local area network or a wide area network, such as an enterprise network, an intelligent network (IN) or the Internet. Such networks may be based on a suitable technology, may operate according to a suitable protocol, and may include wireless networks, wired networks or fiber optic networks.

[0313] The various methods or processes outlined herein may be coded as software that is executable on one or more processors that employ any one of a variety of operating systems or platforms. Additionally, such software may be written using any of a number of suitable programming languages and / or programming or scripting tools, and also may be compiled as executable machine language code or intermediate code that is executed on a framework or virtual machine. Some implementations may specifically employ one or more of a particular operating system or platform and a particular programming language and / or scripting tool to facilitate execution.

[0314] Also, various inventive concepts may be embodied as one or more methods, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

[0315] All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety.

[0316] All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0317] The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”

[0318] The phrase “and / or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and / or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and / or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and / or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

[0319] As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and / or” as defined above. For example, when separating items in a list, “or” or “and / or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of’ or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e., “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.” “Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.

[0320] As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to thoseelements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and / or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

[0321] In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of’ and “consisting essentially of’ shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.

Claims

CLAIMS1. A compute express link (CXL) switch, comprising: a switch fabric, comprising: a first plurality of electrical ports, each electrical port of the first plurality of electrical ports configured for electrical communication to a host; a second plurality of electrical ports; at least one processor communicatively coupled to the first and second pluralities of electrical ports; and memory; and an optical engine directly coupled to the switch fabric, the optical engine comprising: a plurality of converters, each converter of the plurality of converters corresponding to one electrical port of the second plurality of electrical ports and configured to at least one of convert an electrical signal to an optical signal or an optical signal to an electrical signal; and a plurality of optical ports, each optical port of the plurality of optical ports corresponding to one converter of the plurality of converters and configured for optical communication to a device.

2. The CXL switch of claim 1, wherein the CXL switch is configured to at least one of directly transmit an optical signal or directly receive an optical signal from a device located up to 1000 meters from the CXL switch.

3. The CXL switch according to claims 1 or 2, wherein the CXL switch is configured to transmit, via an optical port of the plurality of optical ports, an optical signal having a bandwidth up to about 128 gigatransfers per second (GT / s).

4. The CXL switch according to claims 1 or 2, wherein the CXL switch is configured to transmit, via an optical port of the plurality of optical ports, an optical signal having a latency less than about 5 nanoseconds (ns).

5. The CXL switch of claim 1, wherein the first plurality of electrical ports is configured for electrical communication with up to 16 hosts.

6. The CXL switch of claim 1, wherein the plurality of optical ports is configured for optical communication with up to 256 devices.

7. The CXL switch of claim 1, wherein each optical port of the plurality of optical ports is configured to at least one of transmit a multiplexed signal or receive a multiplexed signal.

8. The CXL switch of claim 1, wherein the first and second pluralities of electrical ports are configured to transmit electrical signals that meets at least one of a peripheral component interconnect express (PCIe) standard or a CXL standard.

9. A computing system, comprising: the CXL switch of claim 1 ; a host communicatively coupled to a first electrical port of the first plurality of electrical ports of the CXL switch; and a device communicatively coupled to an optical port of the plurality of optical ports of the CXL switch.

10. The computing system of claim 9, wherein the host comprises at least one of a central processing unit, or a graphics processing unit.

11. The computing system of claim 9, wherein the device comprises at least one of a graphics processing unit, a network interface controller, a storage controller, volatile memory, non-volatile memory, or a programmable switch.

12. The computing system of claim 9, wherein the CXL switch is configured to transmit a signal to the device without converting the signal from an electrical signal to an optical signal or an optical signal to an electrical signal.

13. The computing system of claim 9, wherein the computing system does not include a retimer communicatively disposed between the CXL switch and the device.

14. The computing system of claim 9, wherein the computing system does not include a network interface controller communicatively disposed between the CXL switch and the device.

15. A method for transmitting a signal from a host to an end point device using a compute express link (CXL) switch, the method comprising: receiving, at a first electrical port of the CXL switch, an electrical signal from the host corresponding to the signal; transmitting, from a second electrical port of the CXL switch, the electrical signal to a converter of the CXL switch, the second electrical port and the converter corresponding to the end point device; converting, by the converter, the electrical signal to an optical signal corresponding to the signal; and transmitting, from an optical port communicatively coupled to the converter, the optical signal to the end point device.

16. A method for transmitting a signal from an end point device to a host using a compute express link (CXL) switch, the method comprising: receiving, at an optical port of the CXL switch, an optical signal from the end point device corresponding to the signal; converting, by a converter of the CXL switch coupled to the optical port, the optical signal to an electrical signal corresponding to the signal; receiving, at a first electrical port of the CXL switch, the electrical signal; and transmitting, from a second electrical port of the CXL switch corresponding to the host, the electrical signal to the host.

17. A compute express link (CXL) switch, comprising: a switch fabric, comprising: a first plurality of electrical ports, each electrical port of the first plurality of electrical ports configured for electrical communication to a host; a second plurality of electrical ports; at least one processor communicatively coupled to the first and second pluralities of electrical ports; andmemory; and an optical communications device, comprising: an optical engine, directly coupled to the second plurality of electrical ports of the switch fabric, to convert an electrical signal to an optical signal or an optical signal to an electrical signal; a first plurality of optical ports communicatively coupled to the optical engine; a second plurality of optical ports, each optical port of the second plurality of optical ports being configured for optical communication to a device; and an optical switch, directly coupled to the first plurality of optical ports and the second plurality of optical ports, to direct optical signals between the first plurality of optical ports and the second plurality of optical ports.

18. The CXL switch of claim 17, wherein the optical engine comprises: a plurality of converters, each converter of the plurality of converters corresponding to one electrical port of the second plurality of electrical ports and configured to at least one of convert an electrical signal to an optical signal or an optical signal to an electrical signal.

19. The CXL switch of claim 17, wherein the optical switch comprises: a plurality of switching devices, each switching device comprising: at least one input port to receive at least one optical signal; two or more output ports to transmit the at least one optical signal; and a switching element coupled to the at least one input port and the two or more output ports; and a microcontroller unit, communicatively coupled to the plurality of switching devices, to direct the at least one optical signal from the at least one input port to one output port of the two or more output ports via the switching element.

20. The CXL switch of claim 19, wherein the microcontroller unit is integrated into the switch fabric.

21. The CXL switch of claim 19, wherein the microcontroller unit is physically separate from the switch fabric and communicatively coupled to the switch fabric.

22. The CXL switch of claim 17, wherein the first plurality of optical ports and the second plurality of optical ports differ in quantity.

23. The CXL switch of claim 17, wherein the first plurality of optical ports comprises: a plurality of waveguide optically coupled to the optical engine and the optical switch.

24. The CXL switch of claim 17, further comprising: a plurality of optical fibers, each optical fiber of the plurality of optical fibers being optically coupled to a corresponding optical port of the second plurality of optical ports via a pigtail type connection.

25. A computing system, comprising: the CXL switch of claim 17; a host communicatively coupled to a first electrical port of the first plurality of electrical ports of the CXL switch; and a device communicatively coupled to an optical port of the second plurality of optical ports of the CXL switch.

26. The computing system of claim 25, wherein the computing system is not communicatively coupled to an Ethernet switch.

27. The computing system of claim 25, wherein the computing system is not communicatively coupled to an external optical switch.

28. The computing system of claim 25, wherein the computing system does not include a retimer communicatively disposed between the CXL switch and the device.

29. The computing system of claim 25, wherein: the computing system is configured for submersion in a coolant liquid; the CXL switch is communicatively coupled to the device via a fiber optic cable; andthe CXL switch and the fiber optic cable are sealed such that the coolant liquid does not affect the optical signals carried by the optical communications device and the fiber optic cable when the computing system is submerged in the coolant liquid.

30. A method for transmitting a signal from a host to an end point device using a compute express link (CXL) switch, the method comprising: receiving, at a first electrical port of the CXL switch, an electrical signal from the host corresponding to the signal; routing, by a switch fabric of the CXL switch coupled to the first electrical port, the electrical signal to a second electrical port of the CXL switch; transmitting, from the second electrical port, the electrical signal to an optical engine of the CXL switch; converting, by the optical engine, the electrical signal to an optical signal corresponding to the signal; transmitting, from a first optical port of the CXL switch coupled to the optical engine, the optical signal to an optical switch of the CXL switch; routing, by the optical switch, the optical signal to a second optical port of the CXL switch; and transmitting, from the second optical port, the optical signal to the end point device.

31. A method for transmitting a signal from an end point device to a host using a compute express link (CXL) switch, the method comprising: receiving, at a first optical port of the CXL switch, an optical signal from the end point device corresponding to the signal; routing, by an optical switch of the CXL switch, the optical signal to a second optical port of the CXL switch; transmitting, from the second optical port, the optical signal to an optical engine of the CXL switch; converting, by the optical engine, the optical signal to an electrical signal corresponding to the signal; transmitting, from a first electrical port of the CXL switch coupled to the optical engine, the electrical signal to a switch fabric of the CXL switch;routing, by the switch fabric, the electrical signal to a second electrical port of the CXL switch; and transmitting, from the second electrical port, the electrical signal to the host.

32. An electrical-switch-over-optics (ESOO) device comprising: an electric switch comprising: a switch fabric; a first plurality of electrical ports, each electrical port of the first plurality of electrical ports configured for electrical communication to a host; a second plurality of electrical ports; at least one processor communicatively coupled to the first and second pluralities of electrical ports and configured to route electrical signals between the first and second pluralities of the electrical ports; and memory operatively coupled to the at least one processor; an optical engine electrically coupled to the electric switch, the optical engine comprising: a plurality of converters, each converter of the plurality of converters corresponding to one electrical port of the second plurality of electrical ports and configured to at least one of convert an electrical signal to an optical signal and / or of an optical signal to an electrical signal; and a plurality of optical ports, each optical port of the plurality of optical ports corresponding to one converter of the plurality of converters and configured for optical communication to a device; and a common semiconductor package in which the electrical switch and the optical engine are disposed.

33. The ESOO device of claim 32, wherein the electrical switch comprises a compute express link (CXL) switch, a peripheral component interconnect express (PCIe) switch, a Universal Chiplet Interconnect Express (UCIe) switch, a Non-Volatile Memory Express (NVMe) switch, or an Ethernet switch.

34. The ESOO device of claim 32, wherein the electrical switch is configured to at least one of directly transmit an optical signal and / or directly receive an optical signal from a device located up to 1000 meters from the ESOO device.

35. The ESOO device according to any of the foregoing claims, wherein the ESOO device is configured to transmit, via an optical port of the plurality of optical ports, an optical signal having a bandwidth up to about 128 gigatransfers per second.

36. The ESOO device according to any of the foregoing claims, wherein the ESOO device is configured to transmit, via an optical port of the plurality of optical ports, an optical signal having a latency less than about 5 nanoseconds.

37. The ESOO device according to any of the foregoing claims wherein the first plurality of electrical ports is configured for electrical communication with up to 16 hosts.

38. The ESOO device according to any of the foregoing claims, wherein the plurality of optical ports is configured for optical communication with up to 256 devices.

39. The ESOO device according to any of the foregoing claims, wherein each optical port of the plurality of optical ports is configured to at least one of transmit a multiplexed signal and / or receive a multiplexed signal.

40. The ESOO device according to any of the foregoing claims, wherein the first and second pluralities of electrical ports are configured to transmit electrical signals that meet at least one of a compute express link (CXL) standard, a peripheral component interconnect express (PCIe) standard, a Universal Chiplet Interconnect Express (UCIe) standard, a Non-Volatile Memory Express (NVMe) standard, and / or an Ethernet standard.

41. A computing system, comprising: the ESOO device of claim 32; a host communicatively coupled to a first electrical port of the first plurality of electrical ports of the ESOO device; anda device communicatively coupled to an optical port of the plurality of optical ports of the ESOO device.

42. The computing system of claim 41, wherein the host comprises at least one of a central processing unit, a graphics processing unit, an application-specific integrated circuit, and / or a field-programmable gate array.

43. The computing system of claim 41 or 42, wherein the device comprises at least one of a graphics processing unit, a network interface controller, a storage controller, volatile memory, non-volatile memory, and / or a programmable switch.

44. The computing system according to any of claims 41-43, wherein the computing system does not include a retimer communicatively disposed between the ESOO device and the device.

45. The computing system according to any of claims 41-44, wherein the computing system does not include a network interface controller communicatively disposed between the ESOO device and the device.

46. A method for transmitting a signal from a host to an end point device using an electrical-switch-over-optics (ESOO) device, the method comprising: receiving, at a first electrical port of an electrical switch in the ESOO device, an electrical signal from the host corresponding to the signal; transmitting, from a second electrical port of the electrical switch, the electrical signal to a converter of the ESOO device, the second electrical port and the converter corresponding to the end point device; converting, by the converter, the electrical signal to an optical signal corresponding to the signal; and transmitting, from an optical port communicatively coupled to the converter, the optical signal to the end point device, wherein the ESOO device includes a common semiconductor package in which the electrical switch and the converter are disposed.

47. The method of claim 46, further comprising transmitting, from the second electrical port of the electrical switch, the electrical signal to a first electrical port electrically coupled to the converter.

48. A method for transmitting a signal from an end point device to a host using an electrical-switch-over-optics (ESOO) device, the method comprising: receiving, at an optical port of the ESOO device, an optical signal from the end point device corresponding to the signal; converting, by a converter of the ESOO device coupled to the optical port, the optical signal to an electrical signal corresponding to the signal; receiving, at a first electrical port of an electrical switch in the ESOO device, the electrical signal; and transmitting, from a second electrical port of the electrical switch corresponding to the host, the electrical signal to the host, wherein the ESOO device includes a common semiconductor package in which the electrical switch and the converter are disposed.

49. The method of claim 48, further comprising transmitting, from a first electrical port electrically coupled to the converter, the electrical signal to the first electrical port of the electrical switch.

50. An electrical-switch-over-optics (ESOO) device comprising: an electric switch comprising: a switch fabric; a first plurality of electrical ports, each electrical port of the first plurality of electrical ports configured for electrical communication to a host; a second plurality of electrical ports; at least one processor communicatively coupled to the first and second pluralities of electrical ports; and memory; an optical communications device, comprising:an optical engine, electrically coupled to the second plurality of electrical ports of the electrical switch, to convert an electrical signal to an optical signal and / or an optical signal to an electrical signal; a first plurality of optical ports communicatively coupled to the optical engine; a second plurality of optical ports, each optical port of the second plurality of optical ports being configured for optical communication to a device; and an optical switch, directly coupled to the first plurality of optical ports and the second plurality of optical ports, to direct optical signals between the first plurality of optical ports and the second plurality of optical ports; and a common semiconductor package in which the electrical switch and the optical communications device are disposed.

51. The ESOO device of claim 50, wherein the electrical switch comprises a compute express link (CXL) switch, a peripheral component interconnect express (PCIe) switch, a Universal Chiplet Interconnect Express (UCIe) switch, a Non-Volatile Memory Express (NVMe) switch, or an Ethernet switch.

52. The ESOO device of claim 50 or 51, wherein the optical engine comprises a plurality of converters, each converter of the plurality of converters corresponding to one electrical port of the second plurality of electrical ports and configured to at least one of convert an electrical signal to an optical signal and / or an optical signal to an electrical signal.

53. The ESOO device according to any of claims 50-22, wherein the optical switch comprises: a plurality of switching devices, each switching device comprising: at least one input port to receive at least one optical signal; two or more output ports to transmit the at least one optical signal; and a switching element coupled to the at least one input port and the two or more output ports; and a microcontroller unit, communicatively coupled to the plurality of switching devices, to direct the at least one optical signal from the at least one input port to one output port of the two or more output ports via the switching element.

54. The ESOO device according to any of claims 50-53, wherein the microcontroller unit is integrated into the switch fabric.

55. The ESOO device according to any of claims 50-53, wherein the microcontroller unit is physically separate from the switch fabric and communicatively coupled to the switch fabric.

56. The ESOO device according to any of claims 50-55, wherein the first plurality of optical ports and the second plurality of optical ports differ in quantity.

57. The ESOO device according to any of claims 50-56, wherein the first plurality of optical ports comprises a plurality of waveguide optically coupled to the optical engine and the optical switch.

58. The ESOO device according to any of claims 50-57, further comprising a plurality of optical fibers, each optical fiber of the plurality of optical fibers being optically coupled to a corresponding optical port of the second plurality of optical ports via a pigtail type connection.

59. The ESOO device according to any claims 50-58, wherein the first and second pluralities of electrical ports are configured to transmit electrical signals that meet at least one of a compute express link (CXL) standard, a peripheral component interconnect express (PCIe) standard, a Universal Chiplet Interconnect Express (UCIe) standard, a Non-Volatile Memory Express (NVMe) standard, and / or an Ethernet standard.

60. A computing system, comprising: the ESOO device of claim 50; a host communicatively coupled to a first electrical port of the first plurality of electrical ports of the ESOO device; and a device communicatively coupled to an optical port of the second plurality of optical ports of the ESOO device.

61. The computing system of claim 60, wherein the computing system is not communicatively coupled to an Ethernet switch.

62. The computing system of claim 60 or 61, wherein the computing system is not communicatively coupled to an external optical switch.

63. The computing system according to any of claims 60-62, wherein the computing system does not include a retimer communicatively disposed between the ESOO device and the device.

64. The computing system according to any of claims 60-63, wherein: the computing system is configured for submersion in a coolant liquid; the ESOO device is communicatively coupled to the device via a fiber optic cable; and the ESOO device and the fiber optic cable are sealed such that the coolant liquid does not affect the optical signals carried by the optical communications device and the fiber optic cable when the computing system is submerged in the coolant liquid.

65. A method for transmitting a signal from a host to an end point device using an electrical-switch-over-optics (ESOO), the method comprising: receiving, at a first electrical port of an electrical switch in the ESOO device, an electrical signal from the host corresponding to the signal; routing, by a switch fabric of the electrical switch, the electrical signal to a second electrical port of the electrical switch; transmitting, from the second electrical port, the electrical signal to an optical engine of the ESOO device; converting, by the optical engine, the electrical signal to an optical signal corresponding to the signal; transmitting, from a first optical port coupled to the optical engine, the optical signal to an optical switch of the ESOO device; routing, by the optical switch, the optical signal to a second optical port coupled to the optical switch; and transmitting, from the second optical port, the optical signal to the end point device, wherein the ESOO device includes a common semiconductor package in which the electrical switch, the converter, the optical engine, and the optical switch are disposed.

66. The method of claim 65, further comprising transmitting, from the second electrical port of the electrical switch, the electrical signal to a first electrical port electrically coupled to the optical engine.

67. A method for transmitting a signal from an end point device to a host using an electrical-switch-over-optics (ESOO) device, the method comprising: receiving, at a first optical port of the ESOO device, an optical signal from the end point device corresponding to the signal; routing, by an optical switch of the ESOO device, the optical signal to a second optical port of the ESOO device; transmitting, from the second optical port, the optical signal to an optical engine of the ESOO device; converting, by the optical engine, the optical signal to an electrical signal corresponding to the signal; transmitting, from a first electrical port of the optical engine, the electrical signal to an electrical switch of the ESOO device; routing, by a switch fabric of the electrical switch, the electrical signal to a second electrical port of the electrical switch; and transmitting, from the second electrical port, the electrical signal to the host.

68. A semiconductor structure comprising: a substrate having electrical interconnection fabric defined in the substrate; a host mounted on and electrically coupled to a first side of the substrate; an electrical-switch-over-optics (ESOO) device mounted on and electrically coupled to the first side of the substrate, the ESOO device comprising: an electric switch comprising: a switch fabric; a first plurality of electrical ports, at least some of the plurality of first plurality of electrical ports electrically connected to the host through the electrical interconnection fabric in the substrate; a second plurality of electrical ports;at least one processor communicatively coupled to the first and second pluralities of electrical ports and configured to route electrical signals between the first and second pluralities of the electrical ports; and memory operatively coupled to the at least one processor; an optical device having an optical engine electrically coupled to the electric switch, the optical engine comprising: a plurality of converters, each converter of the plurality of converters corresponding to one electrical port of the second plurality of electrical ports and configured to at least one of convert an electrical signal to an optical signal and / or of an optical signal to an electrical signal; and a plurality of optical ports, each optical port of the plurality of optical ports corresponding to one converter of the plurality of converters and configured for optical communication to a device; and a common semiconductor package in which the electrical switch and the optical engine are disposed.

69. The semiconductor structure of claim 68, wherein the electrical switch comprises a compute express link (CXL) switch, a peripheral component interconnect express (PCIe) switch, a Universal Chiplet Interconnect Express (UCIe) switch, a Non-Volatile Memory Express (NVMe) switch, or an Ethernet switch.

70. The semiconductor structure of claim 68 or 69, further comprising a printed circuit board, the substrate mounted on and electrically coupled to the printed circuit board.

71. A semiconductor structure comprising: a substrate; an interposer mounted on and electrically coupled to the substrate, the interposer having electrical interconnection fabric defined in the interposer; a host mounted on and electrically coupled to a first side of the interposer; an electrical-switch-over-optics (ESOO) device mounted on and electrically coupled to the first side of the interposer, the ESOO device comprising: an electric switch comprising: a switch fabric;a first plurality of electrical ports, at least some of the plurality of first plurality of electrical ports electrically connected to the host through the electrical interconnection fabric in the interposer; a second plurality of electrical ports; at least one processor communicatively coupled to the first and second pluralities of electrical ports and configured to route electrical signals between the first and second pluralities of the electrical ports; and memory operatively coupled to the at least one processor; an optical engine electrically coupled to the electric switch, the optical engine comprising: a plurality of converters, each converter of the plurality of converters corresponding to one electrical port of the second plurality of electrical ports and configured to at least one of convert an electrical signal to an optical signal and / or of an optical signal to an electrical signal; and a plurality of optical ports, each optical port of the plurality of optical ports corresponding to one converter of the plurality of converters and configured for optical communication to a device; and a common semiconductor package in which the electrical switch and the optical engine are disposed.

72. The semiconductor structure of claim 71, wherein the electrical switch comprises a compute express link (CXL) switch, a peripheral component interconnect express (PCIe) switch, a Universal Chiplet Interconnect Express (UCIe) switch, a Non-Volatile Memory Express (NVMe) switch, or an Ethernet switch.

73. The semiconductor structure of claim 71 or 72, further comprising a printed circuit board, the substrate mounted on and electrically coupled to the printed circuit board.

74. A semiconductor structure comprising: a substrate; a host mounted on and electrically coupled to the substrate; an electrical-switch-over-optics (ESOO) device mounted on and electrically coupled to the host, the ESOO device comprising:an electric switch comprising: a switch fabric; a first plurality of electrical ports, at least some of the plurality of first plurality of electrical ports electrically connected to the host through electrical connections; a second plurality of electrical ports; at least one processor communicatively coupled to the first and second pluralities of electrical ports and configured to route electrical signals between the first and second pluralities of the electrical ports; and memory operatively coupled to the at least one processor; an optical engine electrically coupled to the electric switch, the optical engine comprising: a plurality of converters, each converter of the plurality of converters corresponding to one electrical port of the second plurality of electrical ports and configured to at least one of convert an electrical signal to an optical signal and / or of an optical signal to an electrical signal; and a plurality of optical ports, each optical port of the plurality of optical ports corresponding to one converter of the plurality of converters and configured for optical communication to a device; and a common semiconductor package in which the electrical switch and the optical engine are disposed.

75. The semiconductor structure of claim 74, wherein the electrical switch comprises a compute express link (CXL) switch, a peripheral component interconnect express (PCIe) switch, a Universal Chiplet Interconnect Express (UCIe) switch, a Non-Volatile Memory Express (NVMe) switch, or an Ethernet switch.

76. The semiconductor structure of claim 74 or 75, further comprising a printed circuit board, the substrate mounted on and electrically coupled to the printed circuit board.

77. The semiconductor structure according to any of claims 74-76, wherein the electrical connections comprise microbumps or hybrid bonds.

78. A semiconductor structure comprising: a substrate having electrical interconnection fabric defined in the substrate; a host mounted on and electrically coupled to a first side of the substrate; an electrical-switch-over-optics (ESOO) device mounted on and electrically coupled to the first side of the substrate, the ESOO device comprising: an electric switch comprising: a switch fabric; a first plurality of electrical ports, at least some of the plurality of first plurality of electrical ports electrically connected to the host through the electrical interconnection fabric in the substrate; a second plurality of electrical ports; at least one processor communicatively coupled to the first and second pluralities of electrical ports; and memory; an optical communications device, comprising: an optical engine, electrically coupled to the second plurality of electrical ports of the electrical switch, to convert an electrical signal to an optical signal and / or an optical signal to an electrical signal; a first plurality of optical ports communicatively coupled to the optical engine; a second plurality of optical ports, each optical port of the second plurality of optical ports being configured for optical communication to a device; and an optical switch, directly coupled to the first plurality of optical ports and the second plurality of optical ports, to direct optical signals between the first plurality of optical ports and the second plurality of optical ports; and a common semiconductor package in which the electrical switch and the optical communications device are disposed.

79. The semiconductor structure of claim 78, wherein the electrical switch comprises a compute express link (CXL) switch, a peripheral component interconnect express (PCIe) switch, a Universal Chiplet Interconnect Express (UCIe) switch, a Non-Volatile Memory Express (NVMe) switch, or an Ethernet switch.

80. The semiconductor structure of claim 78 or 79, further comprising a printed circuit board, the substrate mounted on and electrically coupled to the printed circuit board.

81. A semiconductor structure comprising: a substrate; an interposer mounted on and electrically coupled to the substrate, the interposer having electrical interconnection fabric defined in the interposer; a host mounted on and electrically coupled to a first side of the interposer; an electrical-switch-over-optics (ESOO) device mounted on and electrically coupled to the first side of the interposer, the ESOO device comprising: an electric switch comprising: a switch fabric; a first plurality of electrical ports, at least some of the plurality of first plurality of electrical ports electrically connected to the host through the electrical interconnection fabric in the interposer; a second plurality of electrical ports; at least one processor communicatively coupled to the first and second pluralities of electrical ports; and memory; an optical communications device, comprising: an optical engine, electrically coupled to the second plurality of electrical ports of the electrical switch, to convert an electrical signal to an optical signal and / or an optical signal to an electrical signal; a first plurality of optical ports communicatively coupled to the optical engine; a second plurality of optical ports, each optical port of the second plurality of optical ports being configured for optical communication to a device; and an optical switch, directly coupled to the first plurality of optical ports and the second plurality of optical ports, to direct optical signals between the first plurality of optical ports and the second plurality of optical ports; and a common semiconductor package in which the electrical switch and the optical communications device are disposed.

82. The semiconductor structure of claim 81, wherein the electrical switch comprises a compute express link (CXL) switch, a peripheral component interconnect express (PCIe) switch, a Universal Chiplet Interconnect Express (UCIe) switch, a Non-Volatile Memory Express (NVMe) switch, or an Ethernet switch.

83. The semiconductor structure of claim 81 or 82, further comprising a printed circuit board, the substrate mounted on and electrically coupled to the printed circuit board.

84. A semiconductor structure comprising: a substrate; a host mounted on and electrically coupled to the substrate; an electrical-switch-over-optics (ESOO) device mounted on and electrically coupled to the host, the ESOO device comprising: an electric switch comprising: a switch fabric; a first plurality of electrical ports, at least some of the plurality of first plurality of electrical ports electrically connected to the host through electrical connections; a second plurality of electrical ports; at least one processor communicatively coupled to the first and second pluralities of electrical ports; and memory; an optical communications device, comprising: an optical engine, electrically coupled to the second plurality of electrical ports of the electrical switch, to convert an electrical signal to an optical signal and / or an optical signal to an electrical signal; a first plurality of optical ports communicatively coupled to the optical engine; a second plurality of optical ports, each optical port of the second plurality of optical ports being configured for optical communication to a device; and an optical switch, directly coupled to the first plurality of optical ports and the second plurality of optical ports, to direct optical signals between the first plurality of optical ports and the second plurality of optical ports; anda common semiconductor package in which the electrical switch and the optical communications device are disposed.

85. The semiconductor structure of claim 84, wherein the electrical switch comprises a compute express link (CXL) switch, a peripheral component interconnect express (PCIe) switch, a Universal Chiplet Interconnect Express (UCIe) switch, a Non-Volatile Memory Express (NVMe) switch, or an Ethernet switch.

86. The semiconductor structure of claim 84 or 85, further comprising a printed circuit board, the substrate mounted on and electrically coupled to the printed circuit board.

87. The semiconductor structure according to any of claims 84-86, wherein the electrical connections comprise microbumps or hybrid bonds.

88. A method for coupling a host to a plurality of devices using electrical and optical connections, comprising: electrically integrating the electrical switch of the ESOO of claim 32 with the host using standard system-level or standard board-level integration; and optically coupling the plurality of optical ports in the ESOO of claim 32 to the plurality of devices, whereby: the host can transmit signals to each of the plurality of devices using a common optical interface and a common electrical interface, and each of the plurality of devices can transmit signals to the host using the common optical interface and the common electrical interface.

89. The method of claim 88, wherein: the host and the electrical switch are electrically integrated on a common substrate, and the electrically integrating step comprises customizing electrical interconnection fabric defined in the common substrate to electrically couple a plurality of electrical ports in the host and the first plurality of electrical ports in the electrical switch.

90. The method of claim 88, wherein: the host is a first host, and the method further comprises electrically integrating the electrical switch of the ESOO of claim 32 with a second host using standard system-level integration or board-level integration including customizing the electrical interconnection fabric defined in the common substrate to electrically couple a plurality of electrical ports in the second host and the first plurality of electrical ports in the electrical switch, wherein a configuration and / or a number of the plurality of electrical ports in the first host is / are different than the configuration and / or a number of plurality of the electrical ports in the second host, whereby: the first host and the second host can transmit signals to each of the plurality of devices using the common optical interface and the common electrical interface, and each of the plurality of devices can transmit signals to the first host and the second host using the common optical interface and the common electrical interface.

91. The method of claim 88, wherein: the host and the electrical switch are electrically integrated on a common interposer, and the electrically integrating step comprises customizing electrical interconnection fabric defined in the common interposer to electrically couple a plurality of electrical ports in the host and the first plurality of electrical ports in the electrical switch.

92. The method of claim 88, wherein: the host and the electrical switch are three-dimensionally electrically integrated, and the electrically integrating step comprises customizing electrical connections between a plurality of electrical ports in the host and the first plurality of electrical ports in the electrical switch.

93. The method according to any of claims 88-92, wherein the plurality of devices comprise at least one of a graphics processing unit, a network interface controller, a storage controller, volatile memory, non-volatile memory, a memory module, and / or a programmable switch.

94. The method according to any of claims 88-93, further comprising: optically coupling an optical transceiver to the optical ports of the ESOO device of claim 32; and electrically coupling the optical transceiver to one or more electrical ports of one or more of the plurality of devices.

95. The method according to any of claims 88-93, further comprising: optically a plurality of optical transceivers to the optical ports of the ESOO device of claim 32; and electrically coupling each optical transceiver to a respective one or more electrical ports of a respective device of the plurality of devices.

96. A method for coupling a host to a plurality of devices using electrical and optical connections, comprising: electrically integrating the electrical switch of the ESOO of claim 50 with the host using standard system-level or standard board-level integration; and optically coupling the second plurality of optical ports in the ESOO of claim 50 to the plurality of devices, whereby: the host can transmit signals to each of the plurality of devices using a common optical interface and a common electrical interface, and each of the plurality of devices can transmit signals to the host using the common optical interface and the common electrical interface.

97. The method of claim 96, wherein: the host and the electrical switch are electrically integrated on a common substrate, and the electrically integrating step comprises customizing electrical interconnection fabric defined in the common substrate to electrically couple a plurality of electrical ports in the host and the first plurality of electrical ports in the electrical switch.

98. The method of claim 96, wherein: the host is a first host, andthe method further comprises electrically integrating the electrical switch of the ESOO of claim 50 with a second host using standard system-level integration or board-level integration including customizing the electrical interconnection fabric defined in the common substrate to electrically couple a plurality of electrical ports in the second host and the first plurality of electrical ports in the electrical switch, wherein a configuration and / or a number of the plurality of electrical ports in the first host is / are different than the configuration and / or a number of plurality of the electrical ports in the second host, whereby: the first host and the second host can transmit signals to each of the plurality of devices using the common optical interface and the common electrical interface, and each of the plurality of devices can transmit signals to the first host and the second host using the common optical interface and the common electrical interface.

99. The method of claim 96, wherein: the host and the electrical switch are electrically integrated on a common interposer, and the electrically integrating step comprises customizing electrical interconnection fabric defined in the common interposer to electrically couple a plurality of electrical ports in the host and the first plurality of electrical ports in the electrical switch.

100. The method of claim 96, wherein: the host and the electrical switch are three-dimensionally electrically integrated, and the electrically integrating step comprises customizing electrical connections between a plurality of electrical ports in the host and the first plurality of electrical ports in the electrical switch.

101. The method according to any of claims 96-100, wherein the plurality of devices comprise at least one of a graphics processing unit, a network interface controller, a storage controller, volatile memory, non-volatile memory, a memory module, and / or a programmable switch.

102. The method according to any of claims 96-101, further comprising: optically coupling an optical transceiver to the second optical ports of the ESOO device of claim 50; andelectrically coupling the optical transceiver to one or more electrical ports of one or more of the plurality of devices.

103. The method according to any of claims 96-101, further comprising: optically a plurality of optical transceivers to the second optical ports of the ESOO device of claim 50; and electrically coupling each optical transceiver to a respective one or more electrical ports of a respective device of the plurality of devices.

Images