Display panel and display device

Abstract

The present application provides a display panel and a display device. According to the display panel, a first electrode of a first output transistor passes through a first connecting hole and is directly connected to a first active portion, and a second electrode of the first output transistor passes through the first connecting hole and is directly connected to the first active portion, so that the first electrode and the second electrode of the first output transistor are connected without using a second gate layer, the resolution is improved, and the electrical property of the display panel can be improved.

Description

Display panel and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display technology is a new type of display technology that is gaining attention for its unique advantages, including low power consumption, high saturation, fast response time, and wide viewing angle, and has established a significant position in the field of panel display technology. In related technologies, the pixel drive circuit of an OLED display panel is typically an 8T2C circuit. To address this pixel drive circuit, a complementary metal oxide semiconductor (CMOS) gate-on-array (GOA) circuit has been proposed to address the high power consumption of conventional gate drive circuits. In the gate drive circuit, metal oxide thin-film transistors (MTTs) are used as output transistors. To accommodate higher current requirements, the output transistors require a larger aspect ratio, resulting in an excessively wide output transistor and an increased bezel on the display panel. In order to solve the above problems, existing display devices will reduce the frame of the gate drive circuit by adopting stacked devices. Specifically, the metal oxide thin film transistor and the low-temperature polysilicon thin film transistor will be placed in the same vertical space. However, this solution requires drilling to be advanced before the preparation of the second gate layer. The corresponding advancement leads to a dehydrogenation process, which increases the electrical risk of the metal oxide semiconductor layer and the low-temperature polysilicon semiconductor layer. Moreover, when the connection hole of the oxide semiconductor layer is subsequently formed, the risk of over-etching the metal oxide semiconductor layer is high. Moreover, the source and drain need to be connected to the low-temperature polysilicon semiconductor layer after being transferred through the second gate layer, resulting in a decrease in resolution, an increase in contact resistance, and a deterioration in electrical properties.

[0003] Therefore, existing display devices have a problem in which the source and drain electrodes in the stacked gate driving circuit need to be connected to the low-temperature polysilicon semiconductor layer after being switched through the second gate layer, resulting in poor electrical performance of the display panel. SUMMARY OF THE INVENTION

[0004] The embodiments of the present application provide a display panel and a display device to solve the problem that the source and drain electrodes in the gate drive circuit of the stacked design of the existing display device need to be connected to the low-temperature polysilicon semiconductor layer after being transferred through the second gate layer, resulting in poor electrical properties of the display panel.

[0005] To solve the above problems, the technical solutions provided by this application are as follows:

[0006] An embodiment of the present application provides a display panel, comprising a display portion and a gate driving circuit located on one side of the display portion, wherein the gate driving circuit comprises N cascaded driving units, the N driving units being arranged along a first direction; wherein each of the driving units comprises a signal generating module and a first output module arranged along a second direction;

[0007] The first output module includes a first output transistor and a second output transistor, the first output transistor and the second output transistor are stacked in a third direction, the first output transistor includes a first active portion, a first electrode, and a second electrode, the second output transistor includes a second active portion, and in the third direction, the second active portion is arranged between the first active portion and the first electrode of the first output transistor;

[0008] In which, the display panel also includes a first connection hole, the first electrode of the first output transistor is directly connected to the first active part through the first connection hole, the second electrode of the first output transistor is directly connected to the first active part through the first connection hole, the third direction is perpendicular to the plane where the first direction and the second direction are located, the second direction is parallel to the scanning line of the display panel, the angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees, and N is a positive integer.

[0009] At the same time, an embodiment of the present application provides a display device, comprising a display panel, the display panel comprising a display portion and a gate drive circuit located on one side of the display portion, the gate drive circuit comprising N cascaded drive units, the N drive units being arranged along a first direction; wherein each of the drive units comprises a signal generation module and a first output module arranged along a second direction;

[0010] The first output module includes a first output transistor and a second output transistor, the first output transistor and the second output transistor are stacked in a third direction, the first output transistor includes a first active portion, a first electrode, and a second electrode, the second output transistor includes a second active portion, and in the third direction, the second active portion is arranged between the first active portion and the first electrode of the first output transistor;

[0011] In which, the display panel also includes a first connection hole, the first electrode of the first output transistor is directly connected to the first active part through the first connection hole, the second electrode of the first output transistor is directly connected to the first active part through the first connection hole, the third direction is perpendicular to the plane where the first direction and the second direction are located, the second direction is parallel to the scanning line of the display panel, the angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees, and N is a positive integer. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0013] FIG. 1 is a first schematic diagram of a conventional display device.

[0014] FIG. 2 is a second schematic diagram of a conventional display device.

[0015] FIG3 is a stacking diagram of various film layers in a region where a metal oxide thin film transistor and a low-temperature polysilicon thin film transistor are stacked in a conventional display device.

[0016] FIG4 is a first schematic diagram of a display panel provided in an embodiment of the present application.

[0017] FIG5 is a second schematic diagram of a display panel provided in an embodiment of the present application.

[0018] FIG6 is a circuit diagram of a gate driving circuit in a display panel provided in an embodiment of the present application.

[0019] FIG. 7 is a third schematic diagram of a display panel provided in an embodiment of the present application.

[0020] FIG8 is a fourth schematic diagram of a display panel provided in an embodiment of the present application.

[0021] FIG9 is a first stacking diagram of each film layer of the first output module corresponding to each step in the method for manufacturing a display panel provided in an embodiment of the present application.

[0022] FIG10 is a second stacking diagram of each film layer of the first output module corresponding to each step in the method for manufacturing a display panel provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0023] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0024] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0025] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0026] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0027] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0028] As shown in Figures 1 to 3, the display device includes a substrate 101, a light-shielding metal 121, a first insulating layer 102, a second insulating layer 103, a low-temperature polycrystalline silicon semiconductor layer 104, a third insulating layer 105, a first gate layer 106, a fourth insulating layer 107, a second gate layer 108, a fifth insulating layer 109, a metal oxide semiconductor layer 110, a sixth insulating layer 111, a third gate layer 112, a seventh insulating layer 113, a first source-drain metal layer 114, a first planarizing layer 115, a second source-drain metal layer 116, a second planarizing layer 117, an anode layer 122, and a pixel definition layer 118. As shown in FIG2 , in order to reduce the frame, existing display devices stack metal oxide thin film transistors and low-temperature polysilicon thin film transistors in the gate drive circuit setting area. As can be seen from FIG1 and FIG2 , in order to achieve the connection between the source and drain electrodes and the low-temperature polysilicon semiconductor layer 104, it is necessary to set a transfer line in the second gate layer 108, and connect the source and drain electrodes to the low-temperature polysilicon semiconductor layer 104 through the transfer line. This will result in an increase in the area occupied by the wiring of the display panel, a decrease in resolution, and an increase in the contact resistance between the source and drain electrodes and the low-temperature polysilicon semiconductor layer 104.

[0029] As shown in FIG3 , FIG3 is a stack diagram of each film layer in the region where the metal oxide thin film transistor and the low-temperature polycrystalline silicon thin film transistor are stacked. FIG3 (a) is a top view of the low-temperature polycrystalline silicon semiconductor layer 104, FIG3 (b) is a stack diagram of the low-temperature polycrystalline silicon semiconductor layer 104 and the first gate layer 106, FIG3 (c) is a stack diagram of a hole dug in the first gate layer 106, FIG3 (d) is a stack diagram of the film layer in FIG3 (c) and the second gate layer 108, and FIG3 (e) is a stack diagram of FIG3 (d). 3 is a stacking diagram of the film layer and the metal oxide semiconductor layer 110, (f) in FIG3 is a stacking diagram of the film layer of (e) in FIG3 and the third gate layer 112, (g) in FIG3 is a stacking diagram of a hole dug in the film layer of (f) in FIG3, (h) in FIG3 is a stacking diagram of the film layer of (g) in FIG3 and the first source-drain metal layer 114, (i) in FIG3 is a stacking diagram of a hole dug in the first flat layer 115 on (h) in FIG3, and (j) in FIG3 is a stacking diagram of (i) in FIG3 and the second source-drain metal layer 116.

[0030] It can be understood that, in the process of preparing the display device, the structure of the display device corresponding to each step is shown in (a) to (j) in FIG3 . In the process of preparing the display device, in order to connect the second gate layer 108 to the low-temperature polycrystalline silicon semiconductor layer 104, as shown in (c) in FIG3 , it is necessary to punch a hole in the display device to form a first through hole 131 before forming the second gate layer 108. The first through hole 131 is formed by one process. The first through hole 131 can be used as a through hole connecting the low-temperature polycrystalline silicon semiconductor layer 104 and the first gate layer 106, and dehydrogenation treatment is performed after the first drilling. The advance of the process sequence of the dehydrogenation process will cause the electrical properties of the metal oxide thin film transistor and the low-temperature polycrystalline silicon thin film transistor to deteriorate, and since the first drilling only needs to be completed from the fourth insulator, the first through hole 131 can be formed from the fourth insulator. The insulating layer 107 is drilled to the low-temperature polysilicon semiconductor layer 104. The etching amount of the first drilling is relatively small. To ensure that the seventh insulating layer 113 can be drilled to the light-shielding metal 121, the etching amount of the second drilling needs to be increased, that is, the etching amount during the formation of the second through-hole 132 needs to be increased. The second through-hole 132 is formed using a single process and can serve as a through-hole connected to the metal oxide semiconductor layer 110, the second gate layer 108, and the third gate layer 112. This will cause the metal oxide semiconductor layer 110 to be over-etched, affecting the electrical properties of the metal oxide thin film transistor. Specifically, in order to connect the second source and drain metal layer 116 to the first source and drain metal layer 114, as shown in (i) in Figure 3, the first planar layer 115 is also drilled to form a third through-hole 133. Therefore, the existing display device has a problem in which the source and drain electrodes in the gate drive circuit of the stacked design need to be connected to the low-temperature polysilicon semiconductor layer after being transferred through the second gate layer, resulting in poor electrical properties of the display panel.

[0031] In response to the above-mentioned technical problems, the embodiments of the present application provide a display panel and a display device to solve the problem that the source and drain electrodes in the gate drive circuit of the stacked design of the existing display device need to be connected to the low-temperature polysilicon semiconductor layer after being transferred through the second gate layer, resulting in poor electrical properties of the display panel.

[0032] Figure 4 is a first schematic diagram of a display panel provided in an embodiment of the present application. Figure 5 is a second schematic diagram of a display panel provided in an embodiment of the present application. Figure 6 is a circuit diagram of a gate drive circuit in a display panel provided in an embodiment of the present application. Figure 7 is a third schematic diagram of a display panel provided in an embodiment of the present application. Figure 8 is a fourth schematic diagram of a display panel provided in an embodiment of the present application. Figure 9 is a first stacking diagram of each film layer of a first output module corresponding to each step in the method for preparing a display panel provided in an embodiment of the present application. Figure 10 is a second stacking diagram of each film layer of a first output module corresponding to each step in the method for preparing a display panel provided in an embodiment of the present application.

[0033] As shown in Figures 4 to 10, an embodiment of the present application provides a display panel 2, which includes a display portion 31 and a gate driving circuit 32 located on one side of the display portion. The gate driving circuit 32 includes N cascaded driving units 321, and the N driving units 321 are arranged along a first direction X. Each of the driving units 321 includes a signal generating module 43 and a first output module 41 arranged along a second direction Y.

[0034] The first output module 41 includes a first output transistor T9 and a second output transistor T10. The first output transistor T9 and the second output transistor T10 are stacked in a third direction Z. The first output transistor T9 includes a first active portion 611, a first electrode 515c, and a second electrode 515a. The second output transistor T10 includes a second active portion 621. In the third direction Z, the second active portion 621 is disposed between the first active portion 611 and the first electrode 515c of the first output transistor T9.

[0035] In which, the display panel 2 also includes a first connection hole 614a, the first electrode 515c of the first output transistor T9 is directly connected to the first active portion 611 through the first connection hole 614a, and the second electrode 515a of the first output transistor T9 is directly connected to the first active portion 611 through the first connection hole 614a, the third direction Z is perpendicular to the plane where the first direction X and the second direction Y are located, the second direction Y is parallel to the scan line of the display panel 2, the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees, and N is a positive integer.

[0036] An embodiment of the present application provides a display panel, which directly connects the first electrode of the first output transistor T9 to the first active portion 611 through the first connection hole 614a, and directly connects the second electrode of the first output transistor T9 to the first active portion 611 through the first connection hole 614a, so that the first electrode and the second electrode of the first output transistor T9 do not need to be routed through the second gate layer, thereby improving the resolution and reducing the contact resistance between the first electrode and the second electrode and the first active portion 611. Accordingly, when punching the display panel, the punching can be performed after the preparation process of the two semiconductor film layers, reducing the electrical risk of the semiconductor film layers and the risk of over-etching the oxide semiconductor layer, thereby improving the electrical properties of the display panel.

[0037] It should be noted that the drawings in the embodiments of the present application respectively show the connections and structures of each component in the circuit, in the cross-section of the display panel, and in the stacking of the display panel. Therefore, some components may be marked with different numbers in different drawings. For example, the first output transistor T9 is marked as T9 in Figure 6 and as the first output transistor 61 in Figure 8. Similarly, the second output transistor T10 is marked as the second output transistor 62 in Figure 8.

[0038] It should be noted that the drawings in the embodiments of the present application may only show a partial structure of a certain film layer. Therefore, multiple numbers will be used to identify the same structure. It can be understood that the multiple numbers are identifications from different levels or different angles. For example, in Figure 8, the first active layer 505 and the first active part 611 identify the same structure. This is because Figure 8 only shows the first active part 611 in the first active layer 505. Similarly, in Figure 9, the number 611 (505) indicates that the structure is the first active part 611 in the first active layer 505. For other numbers, please refer to the above description.

[0039] Specifically, as shown in Figures 4 and 5, the display panel 2 includes a display area 21 and a non-display area 22. The non-display area 22 includes a gate drive circuit area 221 and a binding area 222. The display part 31 is arranged in the display area 21, and the gate drive circuit 32 is arranged in the gate drive circuit area 221.

[0040] Specifically, the non-display area 22 surrounds the display area 21, enclosing the display area 21. The display area 21 is the area within the display panel that performs the display function, and is internally provided with multiple display units that implement this display function. The non-display area 22 may be a border area of ​​the display panel 2, and may contain functional components that assist the display units within the display area 21 in performing display functions.

[0041] Referring to Figure 4 , a binding area 222 is provided below the display area 21. Binding terminals can be provided in this area. These terminals can be connected to external circuits and transmit signals input from these circuits to data traces, thereby driving the display panel to display images. For example, the binding terminals can be connected to a chip or chip-on-film to provide power and drive signals to the display panel.

[0042] In this embodiment, a plurality of light-emitting devices LED and sub-pixel circuits for driving the light-emitting devices LED may be arranged in an array in the display area 21. The sub-pixel circuits may be pixel driving circuits such as 7T1C, 7T2C, and 8T2C, and this application does not impose any specific restrictions.

[0043] In some embodiments, the display panel also includes a second output module 42; the first output module 41 is arranged on the side of the signal generating module 43 close to the display unit 31, and the first output module 41 is used to output a first gate drive signal; the second output module 42 is arranged on the side of the signal generating module 43 away from the display unit 31, and the second output module 42 is used to output a second gate drive signal, and the first gate drive signal and the second gate drive signal are different.

[0044] In the embodiment of the present application, the gate driving circuit 32 is disposed in the gate driving circuit area 221 , and the gate driving circuit 32 can be disposed on both sides of the display area 21 .

[0045] Specifically, taking the structure of FIG. 6 as an example, each driving unit 321 may include:

[0046] The stage transmission signal selection module 401 is electrically connected between the start signal line STV and the fourth node O.

[0047] The pull-up control module 402 controls the potential of the first node K according to the potential of the fourth node O and the potential of the second clock signal line XCK.

[0048] The first filter module 403 is electrically connected between the fifth node W and the first node K. The control end of the first filter module 403 is electrically connected to the reset signal line RST.

[0049] The second filtering module 404 is electrically connected between the fifth node W and the second node Q. The control terminal of the second filtering module 404 receives the first gate driving signal of the N-2th stage.

[0050] The first inverting module 405 is connected between the first node K and the third node P.

[0051] The feedback module 406 is connected between the first node K and the third node P.

[0052] The first output module 41 is connected between the first node K and the first signal output terminal Nout(n), and is configured to output a first gate driving signal.

[0053] The second output module 42 outputs a second gate driving signal according to the potential of the second node Q and the potential of the third node P.

[0054] The first storage capacitor C1 has a first plate connected to the second node Q, and a second plate connected to the second signal output terminal Pout(n).

[0055] a voltage regulating module 407, wherein a first terminal of the voltage regulating module 407 is electrically connected to the first low potential line NVGL, a second terminal of the voltage regulating module 407 is connected to the gate of the second output transistor T10, and a control terminal of the voltage regulating module 407 is electrically connected to the third node P;

[0056] The control transistor T15 has a gate connected to the control terminal Control, a first electrode connected to the second high potential line PVGH, and a second electrode connected to the first node K.

[0057] In some embodiments, the level transfer signal selection module 401 includes a first-level transfer transistor T13 and a second-level transfer transistor T12, and the first-level transfer transistor T13 is a dual-gate transistor; the two gates of the first-level transfer transistor T13 and the gate of the second-level transfer transistor T12 are connected to the start signal line STV, the source of the first-level transfer transistor T13 is connected to the second low-potential line PVGL, the drain of the first-level transfer transistor T13 and the source of the second-level transfer transistor T12 are connected to the fourth node O, and the drain of the second-level transfer transistor T12 is connected to the second high-potential line PVGH.

[0058] In some embodiments, the pull-up control module 402 includes a pull-up transistor T2 , a gate of the pull-up transistor T2 connected to the second clock signal line XCK, a source of the pull-up transistor T2 connected to the fourth node O, and a drain of the pull-up transistor T2 connected to the first node K.

[0059] In some embodiments, the first filtering module 403 includes a first filtering transistor T11 and a second storage capacitor C2, the gate of the first filtering transistor T11 and the first plate of the second storage capacitor C2 are connected to the reset signal line RST, the source of the first filtering transistor T11 is connected to the first node K, and the drain of the first filtering transistor T11 and the second plate of the second storage capacitor C2 are connected to the fifth node W.

[0060] In some embodiments, the second filtering module 404 includes a second filtering transistor T8, the gate of the second filtering transistor T8 is connected to the first signal output terminal Nout(n) of the N-2th stage driving unit 310, the source of the second filtering transistor T8 is connected to the fifth node W, and the drain of the second filtering transistor T8 is connected to the second node Q.

[0061] In some embodiments, the first inverting module 405 includes a first inverting transistor T3 and a second inverting transistor T1, and the second inverting transistor T1 is a dual-gate transistor; the gate of the first inverting transistor T3 and the two gates of the second inverting transistor T1 are connected to the first node K, the source of the first inverting transistor T3 is connected to the second high potential line PVGH, the drain of the first inverting transistor T3 and the source of the second inverting transistor T1 are connected to the third node P, and the drain of the second inverting transistor T1 is connected to the second low potential line PVGL.

[0062] In some embodiments, the feedback module 406 includes a first feedback transistor T4 and a second feedback transistor T5; wherein the gate of the first feedback transistor T4 is connected to the second clock signal line XCK, the source of the first feedback transistor T4 is connected to the first node K, the drain of the first feedback transistor T4 is connected to the source of the second feedback transistor T5, the gate of the second feedback transistor T5 is connected to the third node P, and the drain of the second feedback transistor T5 is connected to the second high potential line PVGH.

[0063] In some embodiments, the voltage regulation module 407 includes a regulation transistor T14, which is a dual-gate transistor; the two gates of the regulation transistor T14 are connected to the third node P, the source of the regulation transistor T14 is connected to the first node K, and the drain of the regulation transistor T14 is connected to the first low potential line NVGL.

[0064] In some embodiments, the first output module 41 includes a first output transistor T9 and a second output transistor T10, the second output transistor T10 is a dual-gate transistor, and the first output transistor T9 is a single-gate transistor; the second gate of the second output transistor T10 and the first gate of the first output transistor T9 are connected to the first node K of the signal generation module, the first electrode of the first output transistor T9 is connected to the first high potential line NVGH, the second electrode of the second output transistor T10 and the second electrode of the first output transistor T9 are connected to the first signal output terminal Nout (n), and the first electrode of the second output transistor T10 is connected to the first low potential line NVGL.

[0065] In some embodiments, the second output module 42 includes a third output transistor T6 and a fourth output transistor T7; the gate of the third output transistor T6 is connected to the second node Q of the signal generating module, the first electrode of the third output transistor T6 is connected to the first clock signal line CK, the second electrode of the third output transistor T6 and the second electrode of the fourth output transistor T7 are connected to the second signal output terminal Pout(n), the gate of the fourth output transistor T7 is connected to the third node P of the signal generating module, and the first electrode of the fourth output transistor T7 is connected to the second high potential line PVGH.

[0066] In some embodiments, the first-stage pass transistor T13, the second inverting transistor T1, the second output transistor T10, and the regulating transistor T14 are N-type transistors, and the second-stage pass transistor T12, the pull-up transistor T2, the first filter transistor T11, the second filter transistor T8, the first inverting transistor T3, the first output transistor T9, the third output transistor T6, the fourth output transistor T7, the first feedback transistor T4, and the second feedback transistor T5 are P-type transistors.

[0067] In some embodiments, the first active portion 611 is a silicon-containing semiconductor, and the second active portion 621 is a metal oxide semiconductor. By making the first active portion 611 a silicon-containing semiconductor and the second active portion 621 a metal oxide semiconductor, the first output transistor T9 and the second output transistor T10 can achieve both the high mobility of silicon-containing thin-film transistors and the low leakage current of metal oxide thin-film transistors, thereby improving the device performance of the first output module. Furthermore, since the first active portion 611 and the second active portion 621 are made of different materials and formed using different film layers, the first output transistor T9 and the second output transistor T10 can be stacked, reducing the width of the frame occupied by the first output module and thus the frame of the display panel.

[0068] Specifically, the silicon-containing semiconductor may be amorphous silicon, polycrystalline silicon, or single crystal silicon.

[0069] Specifically, since the second output transistor T10 is a metal oxide transistor, although the metal oxide transistor has a small leakage current, the mobility of the metal oxide transistor is low. Therefore, in order to improve the driving capability of the second output transistor T10, the present application increases the length of the second output transistor T10 in the second direction Y as much as possible within a limited space to improve the driving capability of the second output transistor T10; however, since the second output transistor T10 and the first output transistor T9 are stacked, the present application can make the length of the second output transistor T10 in the second direction Y equal to the length of the first output transistor T9 in the second direction Y, thereby increasing the driving capability of the first output transistor T9 as much as possible, thereby improving the load of the first output module.

[0070] In some embodiments, as shown in FIG8 , the first output transistor 61 is disposed away from the light-emitting side of the display panel, and the second output transistor 62 is disposed close to the light-emitting side of the display panel. Placing the first output transistor 61 away from the light-emitting side of the display panel and the second output transistor 62 close to the light-emitting side of the display panel can prevent the first active portion 611 of the first output transistor 61 from being affected by light and causing performance changes. However, embodiments of the present application are not limited thereto, and the first output transistor 61 can be disposed close to the light-emitting side of the display panel, while the second output transistor 62 can be disposed away from the light-emitting side of the display panel.

[0071] In some embodiments, as shown in Figures 4 to 10, the second output transistor T10 includes a first electrode and a second electrode, and the display panel further includes a second connection hole 614b. The first electrode 515b of the second output transistor T10 passes through the second connection hole 614b to connect to the second active portion 621. The second electrode of the second output transistor T10 passes through the second connection hole 614b to connect to the second active portion 621. The second electrode of the second output transistor T10 is connected to the second electrode 515a of the first output transistor T9. The aperture L1 of the first connection hole 614a is larger than the aperture L2 of the second connection hole 614b. By connecting the second electrode of the second output transistor T10 to the second electrode of the first output transistor T9, the second output transistor T10 and the first output transistor T9 can each output a signal. The larger the aperture of the first connection hole 614a than the aperture of the second connection hole 614b can avoid the problem of excessive depth of the first connection hole 614a, which could cause metal fracture within the first connection hole 614a, thereby improving the yield of the display panel.

[0072] Specifically, as shown in Figures 8 and 10, since the second electrode of the second output transistor is connected to the second electrode of the first output transistor, the second electrode of the second output transistor and the second electrode of the first output transistor are actually two parts of the same structure. Therefore, the second electrode of the second output transistor is not separately identified. It can be understood that the second electrode 515a of the first output transistor is the second electrode of the second output transistor.

[0073] Specifically, since the first active portion 611 is far away from the first electrode and the second electrode of the first output transistor relative to the second active portion 621, when the first electrode and the second electrode of the first output transistor are connected to the first active portion 611, the depth of the first connection hole 614a is greater than the depth of the second connection hole 614b. In order to avoid the first electrode and the second electrode of the first output transistor from being disconnected within the first connection hole 614a, the aperture of the first connection hole 614a can be increased so that the width of the part of the first electrode and the second electrode of the first output transistor located within the first connection hole 614a is larger, thereby avoiding disconnection and device failure.

[0074] In some embodiments, as shown in Figures 4 to 10, the first active portion 611 includes a first channel portion 505a and a first doped portion 505b, and the first doped portion 505b includes an active connection portion 611a disposed along the extension direction of the first channel portion. By having the first doped portion 505b include the active connection portion 611a disposed along the extension direction of the first channel portion 505a, the first electrode and the second electrode of the first output transistor T9 can be connected to the first active portion 611 through the active connection portion, preventing subsequent film layers from blocking the first active portion 611, allowing the thin film transistor to operate normally.

[0075] In some embodiments, as shown in Figures 4 to 9, the first output transistor T9 includes a first gate 612. The first gate 612 includes a first gate portion 507a arranged along the extension direction of the first channel portion 505a, a first gate input portion 507c, and a first gate connection portion 507b connected to the first gate portion 507a. The first gate connection portion 507b is arranged in a direction perpendicular to the first gate portion 507a. The distance between the first gate connection portion 507b and the first channel portion 505a is greater than the width of the active connection portion 611a. By having the first gate portion, the first gate input portion, and the first gate connection portion, a signal can be input through the first gate input portion. The first gate connection portion connects the first gate portions, allowing the first gate portion to control the first output transistor T9 to turn on or off, thereby ensuring normal operation of the first output transistor T9. The distance between the first gate connection portion and the first channel portion is greater than the width of the active connection portion, which can prevent the first gate from blocking the active connection portion, resulting in the subsequent first electrode being unable to connect to the active connection portion.

[0076] Specifically, since the first output transistor T9 and the second output transistor T10 are stacked, the first gate of the first output transistor T9 is also the first gate of the second output transistor T10.

[0077] Specifically, as shown in Figure 9, it can be seen that the active connection portion 611a is set beyond the first channel portion 505a. In order to avoid the active connection portion 611a being blocked by the first gate 612, the distance between the first gate connection portion 507b and the first channel portion 505a can be made greater than the width of the active connection portion 611a.

[0078] In some embodiments, as shown in Figures 4 to 10, the second active portion 621 includes a second channel portion 511a and a second doped portion 511b. The orthographic projection of the second channel portion 511a overlaps with the orthographic projection of the first channel portion 505a, and the active connection portion 611a is positioned beyond the second active portion 621. By aligning the orthographic projections of the second channel portion with the orthographic projections of the first channel portion, the first and second channel portions are stacked, eliminating the need for additional space. This reduces the space occupied by other electrodes and reduces the bezel of the display panel. Furthermore, the active connection portion is positioned beyond the second active portion 621, preventing the second active portion 621 from obstructing the active connection portion, thereby enabling the first and second electrodes of the first output transistor T9 to be connected to the active connection portion.

[0079] In some embodiments, as shown in Figures 4 to 9, the second output transistor T10 includes a second gate 613. The second gate 613 includes a second gate portion 513a arranged along the extension direction of the second channel portion 511a, a second gate input portion 513c, and a second gate connection portion 513b connected to the second gate portion 513a. The second gate connection portion 513b is arranged in a direction perpendicular to the second gate portion 513a. The orthographic projection of the second gate portion 513a coincides with the orthographic projection of the first gate portion 507a, the orthographic projection of the second gate connection portion 513b coincides with the orthographic projection of the first gate connection portion 507b, and there is a distance between the orthographic projection of the first gate input portion 507c and the orthographic projection of the second gate input portion 513c. By aligning the orthographic projections of the first gate portion and the second gate portion, and aligning the orthographic projections of the first and second gate connection portions, the space occupied by the first and second gates can be reduced. Furthermore, the distance between the first and second gate input portions allows signals to be input to the first and second gates, respectively, so that the first and second gates operate normally.

[0080] In some embodiments, as shown in Figures 9 and 10, the first connection hole 614a is provided corresponding to the active connection portion 611a, the second connection hole 614b is provided corresponding to the second doped portion 511b, and the display panel 2 further includes a third connection hole 614c and a fourth connection hole 614d. The third connection hole 614c is provided corresponding to the first gate input portion 507c, and the fourth connection hole 614d is provided corresponding to the second gate input portion 513c. By providing the first connection hole 614a corresponding to the active connection portion, the first and second electrodes of the first output transistor T9 can pass through the first connection hole 614a to connect to the active connection portion. By providing the second connection hole 614b corresponding to the second doped portion, the first and second electrodes of the second output transistor T10 can pass through the second connection hole 614b to connect to the second doped portion. The third connection hole is connected to the first gate input portion, and the fourth connection hole is connected to the second gate input portion. A signal input line can pass through the third and fourth connection holes to connect to the first and second gate connections, thereby inputting a signal to the first and second gates.

[0081] Specifically, since the first output transistor T9 and the second output transistor T10 are stacked, the first gate of the first output transistor T9 is also the first gate of the second output transistor T10. Therefore, the first output gate and the second gate can be connected together through a signal input line to input the same signal.

[0082] Specifically, as shown in FIG6 , it can be seen that although the first output transistor T9 and the second output transistor T10 share a common gate, the first output transistor T9 is turned on when the first gate is at a low potential, and the second output transistor is turned on when the first gate and / or the second gate is at a high potential. Therefore, the working processes of the two are not interfered.

[0083] In some embodiments, as shown in Figures 4 to 10, the second electrode 515a of the first output transistor T9 passes through the first connection hole 614a and the second connection hole 614b to respectively connect part of the active connection portion 611a and the second doped portion 511b, the first electrode 515c of the first output transistor T9 passes through the first connection hole 614a to connect part of the active connection portion 611a, and the first electrode 515b of the second output transistor T10 passes through the second connection hole 614b to the second doped portion 511b. By passing the second electrode of the first output transistor T9 through the first connection hole 614a and the second connection hole 614b to connect part of the active connection portion and the second doped portion respectively, the second electrode of the first output transistor T9 is connected to the first doped portion and the second doped portion. The second electrode of the first output transistor T9 can serve as the second electrode of the first output transistor T9 and the second output transistor T10 for signal output. The first electrode of the first output transistor T9 passes through the first connection hole 614a to connect the active connection portion, so that the first output transistor T9 can be connected to the first doped portion through the active connection portion for signal input. The first electrode of the second output transistor T10 passes through the second connection hole 614b to connect the second doped portion for signal input, so that the first output transistor T9 and the second output transistor T10 operate normally.

[0084] In some embodiments, as shown in FIG10 , the display panel 2 further includes a fifth connection hole 614e, which is disposed corresponding to the first electrode 515b of the second output transistor T10. By arranging the fifth connection hole corresponding to the first electrode of the second output transistor T10, the first electrode of the second output transistor T10 receives a signal through the signal adapter wire, thereby enabling normal operation of the second output transistor T10.

[0085] In some embodiments, as shown in Figures 9 and 10, the display panel 2 further includes a signal input line 515d. The signal input line 515d passes through the third connection hole 614c to connect to the first gate input portion 507c, and the signal input line 515d passes through the fourth connection hole 614d to connect to the second gate input portion 513c. The signal input line passes through the third connection hole and the fourth connection hole to connect to the first gate input portion and the second gate input portion, respectively, so that the first gate and the second gate can input signals, thereby controlling the normal operation of the first output transistor T9 and the second output transistor T10.

[0086] In some embodiments, as shown in FIG10 , the display panel 2 further includes a signal adapter line 517 a, which passes through the fifth connection hole 614 e and is connected to the first electrode 515 b of the second output transistor T10. By providing a signal adapter line so that the signal adapter line passes through the fifth via hole and is connected to the first electrode of the second output transistor T10, it is possible to avoid the signal lines being arranged on the same metal layer, which may result in too small spacing between the signal lines, too small a width of the signal lines, and thus causing line breakage, and to avoid the electrode being broken due to the excessive depth of the connection hole.

[0087] In some embodiments, as shown in FIG. 7 to FIG. 10 , the display panel 2 includes:

[0088] substrate 501;

[0089] A first active layer 505 is provided on one side of the substrate 501 and includes the first active portion 611;

[0090] a first gate insulating layer 506 , disposed on one side of the first active layer 505 ;

[0091] a first metal layer 507 disposed on a side of the first gate insulating layer 506 away from the first active layer 505 , the first metal layer 507 including the first gate 612 ;

[0092] A second gate insulating layer 508 is provided on a side of the first metal layer 507 away from the first gate insulating layer 506;

[0093] A second metal layer 509 is provided on a side of the second gate insulating layer 508 away from the first metal layer 507;

[0094] A first interlayer insulating layer 510 is provided on a side of the second metal layer 509 away from the second gate insulating layer 508;

[0095] a second active layer 511 disposed on a side of the first interlayer insulating layer 510 away from the second metal layer 509 , the second active layer 511 including a second active portion 621 ;

[0096] a third gate insulating layer 512 , disposed on a side of the second active layer 511 away from the first interlayer insulating layer 510 ;

[0097] a third metal layer 513 , disposed on a side of the third gate insulating layer 512 away from the second active layer 511 , and including the second gate 613 ;

[0098] A second interlayer insulating layer 514 is disposed on a side of the third metal layer 513 away from the third gate insulating layer 512;

[0099] A first source-drain layer 515 is provided on a side of the second interlayer insulating layer 514 away from the third metal layer 513 , and the first source-drain layer 515 includes a first electrode 515 c and a second electrode 515 a of the first output transistor T9 , a first electrode 515 b and a second electrode of the second output transistor T10 , and the signal input line 515 d ;

[0100] A first planarization layer 516 is disposed on a side of the first source / drain layer 515 away from the second interlayer insulating layer 514 ;

[0101] A second source-drain electrode layer 517 is disposed on a side of the first planarization layer 516 away from the first source-drain electrode layer 515 , and the second source-drain electrode layer 517 includes a signal transfer line 517 a;

[0102] The first connection hole 614a penetrates the second interlayer insulating layer 514, the third gate insulating layer 512, the first interlayer insulating layer 510, the second gate insulating layer 508, and the first gate insulating layer 506; the second connection hole 614b penetrates the second interlayer insulating layer 514 and the third gate insulating layer 512; the third connection hole 614c penetrates the second interlayer insulating layer 514, the third gate insulating layer 512, the first interlayer insulating layer 510, and the second gate insulating layer 508; the fourth connection hole 614d passes through the second interlayer insulating layer 514; and the fifth connection hole 614e penetrates the first planarizing layer 516. By having the first connection hole 614a penetrate the second interlayer insulating layer, the third gate insulating layer, the first interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer, the first electrode and the second electrode of the first output transistor T9 can be directly connected to the first active portion 611 without the need for switching through the second gate layer, thereby reducing the electrical risks of the thin film transistors of the display panel.

[0103] Specifically, the first electrode is a source electrode and the second electrode is a drain electrode; or the first electrode is a drain electrode and the second electrode is a source electrode.

[0104] Specifically, the display panel 2 further includes a light shielding layer 502 , a buffer layer 503 , a blocking layer 504 , a second planarization layer 518 , a pixel electrode layer 519 and a pixel definition layer 520 .

[0105] Specifically, the base substrate 501 supports the various layers provided on the base substrate 501. When the display panel 2 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent base substrate is used. When the display panel 2 is a top-emitting light-emitting display device, a semi-transparent or opaque base substrate or a transparent base substrate can be used.

[0106] Specifically, the base substrate 501 is used to support the various film layers provided on the base substrate 501. The base substrate 501 can be made of an insulating material such as glass, quartz, or a polymer resin. The base substrate 501 can be a rigid substrate or a flexible substrate that can be bent, folded, or rolled. Examples of flexible materials for the flexible substrate include, but are not limited to, polyimide (PI).

[0107] Specifically, the base substrate 501 may include a first flexible substrate, a first barrier layer, a second flexible substrate, and a second barrier layer that are stacked together. The first flexible substrate and the second flexible substrate may be formed of the same material such as polyimide, and the first barrier layer and the second barrier layer may be formed of an inorganic material including, for example, at least one of SiOx and SiNx.

[0108] Specifically, the thin film transistor in the embodiment of the present application can be an etch barrier type, a back channel etch type, or divided into a bottom gate thin film transistor, a top gate thin film transistor and other structures according to the position of the gate and the active layer, or divided into an N-type thin film transistor, a P-type thin film transistor according to the performance of the thin film transistor.

[0109] In some embodiments, thin film transistors are provided within the display portion 31, and the active portions of at least some of the thin film transistors are silicon-containing semiconductors. The first electrodes of the thin film transistors whose active portions are silicon-containing semiconductors are directly connected to the active portions, and the second electrodes of the thin film transistors whose active portions are silicon-containing semiconductors are directly connected to the active portions. By directly connecting the first and second electrodes of the thin film transistors whose active layers are silicon-containing semiconductors to the active portions, the first and second electrodes do not need to be connected via a second metal layer, thereby reducing the contact resistance between the first and second electrodes and the active portions. Accordingly, when punching holes in the display panel, the punching can be performed after the preparation of the two semiconductor film layers, thereby reducing the electrical risk of the semiconductor film layers and the risk of overetching the oxide semiconductor layer, thereby improving the electrical performance of the display panel.

[0110] Specifically, the above embodiment is described using the configuration of the first output transistor and the second output transistor as an example. For other thin film transistors whose active portions are silicon-containing semiconductors, the first electrode and the second electrode of the thin film transistor can also be connected to the active portion through the first connection hole. For example, the first filter transistor T11 can also have its first electrode and the second electrode directly connected to its active portion.

[0111] At the same time, an embodiment of the present application provides a method for manufacturing a display panel, the method for manufacturing a display panel comprising:

[0112] Providing a substrate, and sequentially forming a light shielding layer, a buffer layer, and a barrier layer on the substrate;

[0113] A first active layer is formed on the barrier layer; the stacked structure of each film layer of the first output module of the display panel corresponding to this step is shown in (a) of FIG9 ;

[0114] A first gate insulating layer and a first metal layer are sequentially formed on the first active layer; the stacked structure of the film layers of the first output module of the display panel corresponding to this step is shown in (b) of FIG9 ;

[0115] A second gate insulating layer, a second metal layer, a first interlayer insulating layer, and a second active layer are sequentially formed on the first metal layer. The stacked structure of the film layers of the first output module of the display panel corresponding to this step is shown in (c) of FIG. 9 ;

[0116] A third gate insulating layer and a third metal layer are sequentially formed on the second active layer; the stacked structure of the film layers of the first output module of the display panel corresponding to this step is shown in (d) of FIG9 ;

[0117] A second interlayer insulating layer is formed on the third metal layer, and the display panel is punched for the first time to form a first connection hole and a third connection hole, and then subjected to a dehydrogenation treatment and an oxide layer cleaning treatment. The stacked structure of the film layers of the first output module of the display panel corresponding to this step is shown in (e) of FIG. 9 ;

[0118] The display panel is punched a second time to form a second connection hole and a fourth connection hole. The laminated structure of each film layer of the first output module of the display panel corresponding to this step is shown in (a) of FIG10 .

[0119] A first source-drain electrode layer is formed on the second interlayer insulating layer; the stacked structure of the film layers of the first output module of the display panel corresponding to this step is shown in (b) of FIG10 ;

[0120] A first planarization layer is formed on the first source and drain electrode layer, and the first planarization layer is punched a third time to form a fifth connection hole. The stacked structure of the film layers of the first output module of the display panel corresponding to this step is shown in (c) of FIG. 10 .

[0121] A second source-drain electrode layer is formed on the first planarization layer. The stacked structure of the film layers of the first output module of the display panel corresponding to this step is shown in (d) of FIG10 .

[0122] An embodiment of the present application provides a method for preparing a display panel. After forming a second interlayer insulating layer, the method for preparing a display panel performs a first punching and a second punching on the display panel, delaying the punching process and the dehydrogenation process of the display panel, reducing the electrical risks of metal oxide thin film transistors and low-temperature polycrystalline silicon thin film transistors, and reducing the etching amount of the second punching, reducing the risk of over-etching of the metal oxide, and the first electrode and the second electrode are directly connected to the first active layer without the need for a second metal layer transfer, thereby reducing the contact resistance of the first electrode and the second electrode with the first active layer and improving the resolution.

[0123] Meanwhile, embodiments of the present application provide a display device comprising a display panel as described in any of the above embodiments. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0124] According to the above embodiments, it can be seen that:

[0125] Embodiments of the present application provide a display panel and a display device, the display panel including a display portion and a gate drive circuit located on one side of the display portion, the gate drive circuit including N cascaded drive units, the N drive units being arranged along a first direction, wherein each drive unit includes a signal generation module and a first output module arranged along a second direction, the first output module including a first output transistor and a second output transistor, the first output transistor and the second output transistor being stacked in a third direction, the first output transistor including a first active portion, a first electrode, and a second electrode, the second output transistor including a second active portion, and in the third direction, the second active portion being arranged between the first active portion and the first electrode of the first output transistor, wherein the display panel further includes a first connection hole, the first electrode of the first output transistor being directly connected to the first active portion through the first connection hole, and the second electrode of the first output transistor being directly connected to the first active portion through the first connection hole, the third direction being perpendicular to the plane in which the first and second directions lie, the second direction being parallel to a scan line of the display panel, the angle between the first and second directions being greater than 0 and less than or equal to 90 degrees, and N being a positive integer. In the present application, the first electrode of the first output transistor is directly connected to the first active portion through the first connection hole, and the second electrode of the first output transistor is directly connected to the first active portion through the first connection hole, so that the first electrode and the second electrode of the first output transistor do not need to be routed through the second gate layer, thereby improving the resolution and reducing the contact resistance between the first electrode and the second electrode and the first active portion. Accordingly, when punching the display panel, the punching can be performed after the preparation process of the two semiconductor film layers, reducing the electrical risk of the semiconductor film layer and the over-etching risk of the oxide semiconductor layer, thereby improving the electrical properties of the display panel.

[0126] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0127] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, comprising a display portion and a gate driving circuit located on one side of the display portion, wherein the gate driving circuit comprises N cascaded driving units, and the N driving units are arranged along a first direction; wherein: Each of the driving units includes a signal generating module and a first output module arranged along the second direction; The first output module includes a first output transistor and a second output transistor, the first output transistor and the second output transistor are stacked in a third direction, the first output transistor includes a first active portion, a first electrode, and a second electrode, the second output transistor includes a second active portion, and in the third direction, the second active portion is arranged between the first active portion and the first electrode of the first output transistor; Among them, the display panel also includes a first connection hole, the first electrode of the first output transistor is directly connected to the first active part through the first connection hole, the second electrode of the first output transistor is directly connected to the first active part through the first connection hole, the third direction is perpendicular to the plane where the first direction and the second direction are located, the second direction is parallel to the scanning line of the display panel, the angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees, and N is a positive integer.

2. The display panel according to claim 1, wherein: The first active portion is a semiconductor containing silicon, the second active portion is a metal oxide semiconductor, the first output transistor is arranged away from the light emitting side of the display panel, and the second output transistor is arranged close to the light emitting side of the display panel.

3. The display panel according to claim 1, wherein: The second output transistor includes a first electrode and a second electrode, and the display panel also includes a second connection hole, the first electrode of the second output transistor is connected to the second active part through the second connection hole, the second electrode of the second output transistor is connected to the second active part through the second connection hole, the second electrode of the second output transistor is connected to the second electrode of the first output transistor, and the aperture of the first connection hole is larger than the aperture of the second connection hole.

4. The display panel according to claim 3, wherein: The first active portion includes a first channel portion and a first doped portion, and the first doped portion includes an active connecting portion arranged along an extending direction of the first channel portion.

5. The display panel according to claim 4, wherein: The first output transistor includes a first gate, which includes a first gate portion arranged along an extension direction of the first channel portion, a first gate input portion, and a first gate connection portion connected to the first gate portion, the first gate connection portion is arranged in a direction perpendicular to the first gate portion, and a distance between the first gate connection portion and the first channel portion is greater than a width of the active connection portion.

6. The display panel according to claim 5, wherein: The second active portion includes a second channel portion and a second doped portion, an orthographic projection of the second channel portion overlaps with an orthographic projection of the first channel portion, and the active connecting portion is disposed beyond the second active portion.

7. The display panel according to claim 6, wherein: The second output transistor includes a second gate, which includes a second gate portion arranged along the extension direction of the second channel portion, a second gate input portion and a second gate connection portion connected to the second gate portion, the second gate connection portion is arranged in a direction perpendicular to the second gate portion, the orthographic projection of the second gate portion coincides with the orthographic projection of the first gate portion, the orthographic projection of the second gate connection portion coincides with the orthographic projection of the first gate connection portion, and there is a distance between the orthographic projection of the first gate input portion and the orthographic projection of the second gate output portion.

8. The display panel according to claim 7, wherein: The first connection hole is arranged corresponding to the active connection part, the second connection hole is arranged corresponding to the second doped part, and the display panel further includes a third connection hole and a fourth connection hole, the third connection hole is arranged corresponding to the first gate input part, and the fourth connection hole is arranged corresponding to the second gate input part.

9. The display panel according to claim 8, wherein: The second electrode of the first output transistor passes through the first connection hole and the second connection hole to respectively connect part of the active connection portion and the second doped portion, the first electrode of the first output transistor passes through the first connection hole to connect part of the active connection portion, and the first electrode of the second output transistor passes through the second connection hole to connect to the second doped portion.

10. The display panel according to claim 9, wherein: The display panel further includes a fifth connection hole, and the fifth connection hole is arranged corresponding to the first electrode of the second output transistor.

11. The display panel according to claim 10, wherein: The display panel further includes a signal input line, the signal input line passes through the third connection hole to be connected to the first gate input portion, and the signal input line passes through the fourth connection hole to be connected to the second gate input portion.

12. The display panel according to claim 11, wherein: The display panel further includes a signal switching line, and the signal switching line passes through the fifth connection hole and is connected to the first electrode of the second output transistor.

13. The display panel according to claim 12, wherein: The display panel comprises: substrate; A first active layer, disposed on one side of the substrate, comprising the first active portion; A first gate insulating layer, disposed on one side of the first active layer; A first metal layer is disposed on a side of the first gate insulating layer away from the first active layer, and the first metal layer includes the first gate; A second gate insulating layer is disposed on a side of the first metal layer away from the first gate insulating layer; A second metal layer is disposed on a side of the second gate insulating layer away from the first metal layer; A first interlayer insulating layer is disposed on a side of the second metal layer away from the second gate insulating layer; a second active layer, disposed on a side of the first interlayer insulating layer away from the second metal layer, the second active layer including the second active portion; a third gate insulating layer, disposed on a side of the second active layer away from the first interlayer insulating layer; A third metal layer is disposed on a side of the third gate insulating layer away from the second active layer, and the third metal layer includes the second gate; A second interlayer insulating layer is disposed on a side of the third metal layer away from the third gate insulating layer; A first source-drain layer is arranged on a side of the second interlayer insulating layer away from the third metal layer, the first source-drain layer includes a first electrode and a second electrode of the first output transistor, a first electrode and a second electrode of the second output transistor, and the signal input line; A first planarization layer is disposed on a side of the first source-drain electrode layer away from the second interlayer insulating layer; A second source-drain electrode layer is disposed on a side of the first planarization layer away from the first source-drain electrode layer, and the second source-drain electrode layer includes a signal transfer line; Among them, the first connection hole penetrates the second interlayer insulating layer, the third gate insulating layer, the first interlayer insulating layer, the second gate insulating layer and the first gate insulating layer, the second connection hole penetrates the second interlayer insulating layer and the third gate insulating layer, the third connection hole penetrates the second interlayer insulating layer, the third gate insulating layer, the first interlayer insulating layer and the second gate insulating layer, the fourth connection hole passes through the second interlayer insulating layer, and the fifth connection hole penetrates the first planarization layer.

14. The display panel according to claim 1, wherein: The display portion is provided with a thin film transistor, and the active portion of at least part of the thin film transistor is a silicon-containing semiconductor, the first electrode of the thin film transistor whose active portion is a silicon-containing semiconductor is directly connected to the active portion, and the second electrode of the thin film transistor whose active portion is a silicon-containing semiconductor is directly connected to the active portion.

15. A display device, comprising a display panel, wherein the display panel comprises a display portion and a gate driving circuit located on one side of the display portion, wherein the gate driving circuit comprises N cascaded driving units, wherein the N driving units are arranged along a first direction; wherein: Each of the driving units includes a signal generating module and a first output module arranged along the second direction; The first output module includes a first output transistor and a second output transistor, the first output transistor and the second output transistor are stacked in a third direction, the first output transistor includes a first active portion, a first electrode, and a second electrode, the second output transistor includes a second active portion, and in the third direction, the second active portion is arranged between the first active portion and the first electrode of the first output transistor; Among them, the display panel also includes a first connection hole, the first electrode of the first output transistor is directly connected to the first active part through the first connection hole, the second electrode of the first output transistor is directly connected to the first active part through the first connection hole, the third direction is perpendicular to the plane where the first direction and the second direction are located, the second direction is parallel to the scanning line of the display panel, the angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees, and N is a positive integer.

16. The display device according to claim 15, wherein: The first active portion is a semiconductor containing silicon, the second active portion is a metal oxide semiconductor, the first output transistor is arranged away from the light emitting side of the display panel, and the second output transistor is arranged close to the light emitting side of the display panel.

17. The display device according to claim 15, wherein: The second output transistor includes a first electrode and a second electrode, and the display panel also includes a second connection hole, the first electrode of the second output transistor is connected to the second active part through the second connection hole, the second electrode of the second output transistor is connected to the second active part through the second connection hole, the second electrode of the second output transistor is connected to the second electrode of the first output transistor, and the aperture of the first connection hole is larger than the aperture of the second connection hole.

18. The display device according to claim 17, wherein: The first active portion includes a first channel portion and a first doped portion, and the first doped portion includes an active connecting portion arranged along an extending direction of the first channel portion.

19. The display device according to claim 18, wherein: The first output transistor includes a first gate, which includes a first gate portion arranged along an extension direction of the first channel portion, a first gate input portion, and a first gate connection portion connected to the first gate portion, the first gate connection portion is arranged in a direction perpendicular to the first gate portion, and a distance between the first gate connection portion and the first channel portion is greater than a width of the active connection portion.

20. The display device according to claim 19, wherein: The second active portion includes a second channel portion and a second doped portion, an orthographic projection of the second channel portion overlaps with an orthographic projection of the first channel portion, and the active connecting portion is disposed beyond the second active portion.

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