Memory chip, logic chip, chip stack structure, and memory

Abstract

Provided are a memory chip, a logic chip, a chip stack structure, and a memory. A global signal region (20) of the memory chip (10) has n conductive via groups; an internal circuit of the memory chip (10) comprises n internal port groups, and each internal port group comprises four internal ports; four normal conductive vias in an ith conductive via group are electrically connected to four internal ports in an ith internal port group in a one-to-one correspondence manner, and the corresponding relationship between the four normal conductive vias and the four internal ports is determined on the basis of a selection signal.

Description

A memory chip, a logic chip, a chip stacking structure and a memory

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on December 6, 2023, with application number 202311693030.0 and application name “A memory chip, logic chip, chip stacking structure and memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a memory chip, a logic chip, a chip stacking structure, and a memory. Background Art

[0004] With the development of integrated circuit technology, the production process of semiconductor devices has made significant progress. However, in recent years, the development of two-dimensional semiconductor technology has encountered various challenges: physical limits, limits of existing development technology, and limits of storage electron density. In this context, in order to solve the difficulties encountered by two-dimensional semiconductor devices and pursue lower production costs per unit memory unit, bonding processes (such as hybrid bonding, bumping, and wire bonding) can be used to stack multiple chips to form three-dimensional semiconductor devices. However, for three-dimensional semiconductor devices, the connection structure between different chips still has problems such as large parasitic capacitance and large parasitic resistance, which affect the quality of signal transmission.

[0005] Summary of the Invention

[0006] Embodiments of the present disclosure provide a memory chip, a logic chip, a chip stacking structure, and a memory.

[0007] In a first aspect, an embodiment of the present disclosure provides a memory chip in which the center point of an active surface and an adjacent area thereof are defined as a global signal area, and the center point of the global signal area coincides with the center point of the active surface; the global signal area has a first axis and a second axis, the first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface, the first axis is parallel to a first side of the memory chip, and the second axis is parallel to a second side of the memory chip;

[0008] The global signal area is penetrated by n conductive via groups along a third direction, the third direction is perpendicular to the active surface, and n is a positive integer;

[0009] Each of the conductive via groups includes four normal conductive vias, and the first normal conductive via and the second normal conductive via are symmetrical about the first axis, the third normal conductive via and the fourth normal conductive via are symmetrical about the first axis, and the first normal conductive via and the fourth normal conductive via are symmetrical about the second axis;

[0010] The internal circuit of the memory chip includes n internal port groups, and each internal port group includes 4 internal ports;

[0011] The memory chip also includes n selection circuits; the i-th selection circuit is configured to receive and, based on a selection signal, electrically connect the four normal conductive through-holes in the i-th conductive through-hole group to the four internal ports in the i-th internal port group in a one-to-one correspondence; wherein the correspondence between the four normal conductive through-holes and the four internal ports is determined based on the selection signal, and i is a positive integer less than or equal to n.

[0012] In a second aspect, an embodiment of the present disclosure provides a logic chip, wherein a center point of an active surface of the logic chip and an adjacent area thereof are defined as a global signal area, and the center point of the global signal area coincides with the center point of the active surface; the global signal area has a first axis and a second axis, the first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface, the first axis is parallel to a first side of the logic chip, and the second axis is parallel to a second side of the logic chip;

[0013] The global signal area is penetrated by n conductive via groups along a third direction, the third direction is perpendicular to the active surface, and n is a positive integer;

[0014] Each of the conductive via groups includes four normal conductive vias, and the first normal conductive via and the second normal conductive via are symmetrical about the first axis, the third normal conductive via and the fourth normal conductive via are symmetrical about the first axis, and the first normal conductive via and the fourth normal conductive via are symmetrical about the second axis;

[0015] The logic chip further includes n control circuits, and the internal circuit of the logic chip includes n first signal ports, n second signal ports, n third signal ports, and n fourth signal ports;

[0016] The i-th control circuit is configured to electrically connect the first normal conductive via, the second normal conductive via, the third normal conductive via, and the fourth normal conductive via in the i-th conductive via group to the i-th first signal port, the i-th second signal port, the i-th third signal port, and the i-th fourth signal port one by one.

[0017] In a third aspect, an embodiment of the present disclosure provides a chip stacking structure, the chip stacking structure comprising the logic chip according to the second aspect and at least one stacking unit, wherein the logic chip and the at least one stacking unit are stacked sequentially along a third direction; each of the stacking units comprises a first memory chip, a second memory chip, a third memory chip, and a fourth memory chip stacked sequentially along the third direction, wherein the third direction is perpendicular to a top surface of each of the memory chips; the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip are all the memory chips according to the first aspect;

[0018] The first memory chip and the second memory chip are stacked face to face, the second memory chip and the third memory chip are stacked back to back, and the third memory chip and the fourth memory chip are stacked face to face;

[0019] The first memory chip and the logic chip in the first stacking unit are stacked in a back-to-back manner, or the first memory chip and the logic chip in the first stacking unit are stacked in a back-to-back manner.

[0020] In a fourth aspect, an embodiment of the present disclosure provides a memory comprising a chip stacking structure as described in any one of the third aspects.

[0021] The embodiments of the present disclosure provide a memory chip, a logic chip, a chip stacking structure and a memory, in which each conductive through-hole in the global signal area transmits a signal to the inside of the chip, thereby improving the signal transmission efficiency; at the same time, through the symmetrically arranged conductive through-holes, the chip stacking structure formed by the memory chip realizes a signal rotation transmission effect through the direct connection configuration of the conductive through-holes, and the parasitic resistance and parasitic capacitance are relatively small; at the same time, through the symmetrically arranged repair units, the redundant repair function of the above structure can be realized, thereby improving the stability of the memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG1 is a schematic diagram of the structure of a chip;

[0023] FIG2A is a schematic diagram showing the composition of a chip stacking structure;

[0024] FIG2B is a schematic diagram showing the composition of a chip stacking structure;

[0025] FIG3 is a schematic diagram of a memory chip provided in an embodiment of the present disclosure;

[0026] FIG4 is a first schematic diagram of a global signal region in a memory chip provided by an embodiment of the present disclosure;

[0027] FIG5A is a schematic diagram of a chip stack of a memory chip provided by an embodiment of the present disclosure;

[0028] FIG5B is a schematic diagram of another chip stack of memory chips provided by an embodiment of the present disclosure;

[0029] FIG6 is a second schematic diagram of a global signal region in a memory chip provided by an embodiment of the present disclosure;

[0030] FIG7 is a schematic diagram of a selection circuit in a memory chip provided by an embodiment of the present disclosure;

[0031] FIG8 is a schematic diagram of a partial structure of a first selection circuit provided in an embodiment of the present disclosure;

[0032] 9A to 9F are schematic diagrams of a repair process in a memory chip provided by an embodiment of the present disclosure;

[0033] FIG10 is a schematic diagram of a partial structure of a second selection circuit provided in an embodiment of the present disclosure;

[0034] FIG11 is a schematic diagram of a logic chip provided in an embodiment of the present disclosure;

[0035] FIG12 is a first schematic diagram of a global signal region in a logic chip provided by an embodiment of the present disclosure;

[0036] FIG13 is a schematic diagram of a selection circuit in a logic chip provided by an embodiment of the present disclosure;

[0037] FIG14 is a schematic diagram of a partial structure of a first control circuit provided in an embodiment of the present disclosure;

[0038] FIG15 is a schematic diagram of a partial structure of a second control circuit provided in an embodiment of the present disclosure;

[0039] FIG16 is a schematic diagram of the composition structure of a chip stacking structure provided by an embodiment of the present disclosure;

[0040] FIG17A / FIG17B are specific schematic diagrams of a first chip stacking structure provided by an embodiment of the present disclosure;

[0041] FIG18A / FIG18B are specific schematic diagrams of a second chip stacking structure provided by an embodiment of the present disclosure;

[0042] FIG19 is a schematic diagram of signal transmission of a chip stacking structure provided by an embodiment of the present disclosure;

[0043] FIG20A / FIG20B are schematic diagrams showing a repair method for a chip stacking structure according to an embodiment of the present disclosure;

[0044] FIG21A / FIG21B are specific schematic diagrams of a third chip stacking structure provided by an embodiment of the present disclosure;

[0045] FIG22A / FIG22B are specific schematic diagrams of a fourth chip stacking structure provided by an embodiment of the present disclosure;

[0046] FIG23 is a schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to explain the related applications and are not intended to limit the present disclosure. It should also be noted that for ease of description, only the portions relevant to the related applications are shown in the drawings.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0049] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0050] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0051] Before introducing the embodiments of the present disclosure, three directions that may be used to describe a three-dimensional structure in the plane involved in the following embodiments are defined. Taking the Cartesian coordinate system as an example, the three directions may include a first direction, a second direction, and a third direction.

[0052] Referring to Figure 1 , a semiconductor chip (specifically, a memory chip or a logic chip) may include a top surface on the front side and a bottom surface on the back side opposite the front side. Ignoring the flatness of the top and bottom surfaces, a direction intersecting (e.g., perpendicular to) the top and bottom surfaces of the semiconductor chip is defined as a third direction. Two mutually perpendicular directions, namely a first direction and a second direction, are defined on the top surface of the semiconductor chip. The first direction is perpendicular to one edge of the semiconductor chip, and the second direction is perpendicular to the other edge of the semiconductor chip.

[0053] Please refer to Figure 1. The semiconductor chip includes a substrate. The substrate has an active surface on one side used to make devices (such as transistors, capacitors, etc.). Multiple metal layers are distributed between the substrate and the top surface, such as M1, M2, M3... Figure 1 also shows two types of conductive vias (for example: silicon conductive vias), both of which are used to achieve signal connection between different stacked chips.

[0054] As shown in FIG. 1 , a type 1 conductive via penetrates the bottom surface and the top surface along a third direction, and is connected to an internal circuit of the chip through a metal layer.

[0055] As shown in Figure 1, Type 2 conductive vias only penetrate the substrate in the third direction and require a contact structure that penetrates the top surface in the third direction to achieve signal transmission. The contact structure and the conductive via are not directly electrically connected, but are indirectly electrically connected through the metal layer. For example, the contact structure in Figure 1 is connected to M4, which is then connected to M1 via M3 and M2, and M1 is connected to the conductive via. Of course, in other embodiments, the contact structure and the conductive via can also be designed to be directly electrically connected.

[0056] Meanwhile, the types of conductive vias are not limited to the two described above; the above are merely examples. In particular, the illustrations presented in this disclosure are not intended to be actual views of any particular microelectronic device or its components, but are merely idealized representations used to describe illustrative embodiments. Therefore, the drawings are not necessarily to scale.

[0057] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0058] In one embodiment, a memory chip and a logic chip are provided. Each memory chip and the logic chip include multiple conductive vias extending through the chip along a third direction. The conductive vias are used to transmit signals between different chips. All conductive vias can be located at any position. In particular, every four conductive vias can be functionally considered a conductive via group, but the positions of the four conductive vias are not limited.

[0059] In a specific embodiment, eight of the aforementioned memory chips and one logic chip are stacked to form a 3D memory device. The conductive vias of the eight memory chips are aligned along a third direction, and the nine conductive vias aligned along the third direction are connected to form an electrical path. Please refer to FIG2A , which shows a schematic diagram of signal transmission in a chip stacking structure. As shown in FIG2A , the chip stacking structure includes memory chips 0 to 7 and a logic chip. FIG2A shows only four conductive vias D0 to D3 for each memory chip, and these four conductive vias D0 to D3 belong to the same conductive via group. At this time, the conductive vias D0 in the eight memory chips and one logic chip are all aligned to form one electrical path, and the conductive vias D1 in the eight memory chips and one logic chip are all aligned to form one electrical path... The remaining conductive vias are similar.

[0060] At the same time, each memory chip and logic chip is also equipped with multiple drive circuits (only one of these drive circuits is shown in a dotted box in Figure 2A; the remaining drive circuits are not framed), and each conductive via is connected to a drive circuit. Each memory chip is also equipped with multiple data selectors (for example, mux0-7 in Figure 2A), with each conductive via group corresponding to one data selector. That is, all conductive vias in a conductive via group are connected to the data port of the data selector through their respective drive circuits. In other words, the data selector can select which conductive via transmits the signal to output to the memory chip or to which conductive via the signal output by the memory chip is output.

[0061] For the overall memory device, different areas in different memory chips will be divided into different channels (for example: CH0, CH1, CH4, CH5) for management. The signal Signal_CH0 of channel CH0 is transmitted through the electrical path formed by "the conductive through hole D0 in the logic chip, the conductive through hole D0 in memory chip 0 - the conductive through hole D0 in memory chip 1 - the conductive through hole D0 in memory chip 2 - the conductive through hole D0 in memory chip 3 - the conductive through hole D0 in memory chip 4 - the conductive through hole D0 in memory chip 5 - the conductive through hole D0 in memory chip 6 - the conductive through hole D0 in memory chip 7", and the selection signals of the data selector mux0 in memory chip 0 and the data selector mux4 in memory chip 4 are both SEL_C0, that is, the signal Signal_CH0 can enter the memory chip 0 and the memory chip 4 through the aforementioned electrical path; the signal output process can be understood similarly.

[0062] From the above, it can be seen that memory chip 0 only needs to obtain signals from conductive through-hole D0, and memory chip 1 only needs to obtain signals from conductive through-hole D1... That is, each memory chip only needs to obtain signals from one of the conductive through-holes in a conductive through-hole group. It is worth noting that different memory chips may need to obtain signals from different conductive through-holes. However, since all memory chips need to be designed into exactly the same structure during process manufacturing (so as to maximize cost and manpower savings), all conductive through-holes in the memory chip need to be designed with corresponding drive structures and data selectors to achieve structural consistency. Further, when the chip stacking structure shown in FIG2A is adopted, each conductive through-hole corresponds to a drive circuit; during the operation of the chip stacking structure, it is necessary to drive all drive circuits in all memory chips in the same channel, the load is large and the parasitic capacitance is large, which seriously affects the performance of the chips, restricts transmission efficiency and increases power consumption, and also restricts the number of chips stacked in the three-dimensional device.

[0063] In another embodiment, please refer to FIG2B , which shows a schematic diagram of signal transmission of another chip stacking structure. In particular, FIG2B only identifies some of the conductive through holes (D0 to D3), and omits the others. However, for FIG4 , the identification of the conductive through holes aligned along the third direction is the same. As shown in FIG2B , the chip stacking structure also includes 8 memory chips and 1 logic chip aligned along the third direction, but the conductive through holes in each memory chip are rotationally connected to another conductive through hole at a different position in another memory chip, and the whole realizes a spiral ascending connection, that is, the signal Signal_CH0 of channel CH0 is transmitted through "conductive through hole D0 in logic chip - conductive through hole D1 in memory chip 0 - conductive through hole D2 in memory chip 1 - conductive through hole D3 in memory chip 2 - conductive through hole D0 in memory chip 3 - conductive through hole D1 in memory chip 4 - conductive through hole D2 in memory chip 5 - conductive through hole D3 in memory chip 6 - conductive through hole D0 in memory chip 7", and the remaining signals are similar.

[0064] In this way, memory chip 0 can obtain signal Signal_CH0 through the output end of the conductive through hole D0 in the logic chip, memory chip 1 can obtain signal Signal_CH1 through the input end of the conductive through hole D0 in memory chip 0, memory chip 2 can obtain signal Signal_CH4 through the input end of the conductive through hole D0 in memory chip 1, and memory chip 3 can obtain signal Signal_CH5 through the input end of the conductive through hole D0 in memory chip 2... For each memory chip, only one conductive through hole in each conductive through hole group is required to connect to the driving circuit, and there is no need to set a data selector, which can reduce the number of devices and thus reduce parasitic capacitance. However, compared to the conductive via direct connection configuration of FIG2A , the process of the conductive via rotational connection in FIG2B is more complicated. Specifically, a horizontal interconnection structure needs to be set between adjacent conductive vias in each memory chip in FIG2B (only one of them is marked with a five-pointed star in FIG2B ). The signal interconnection structure can be a metal interconnection line, a conductive via, etc. In order to achieve the conductive via rotational connection, the input signal signal_CH0 must first be transmitted upward from the conductive via D0 of the logic chip to the interconnection structure below the conductive via D0 of the memory chip 0 (not connected to the conductive via D0 of the memory chip 0), and then horizontally transmitted from the interconnection structure below the conductive via D0 of the memory chip 0 to the conductive via D1 of the memory chip 0. That is, the structure shown in FIG2B also needs to pass through the interconnection structure in each memory chip during the signal process, and the output signal is similar. This will inevitably lead to an increase in parasitic resistance and also increase the complexity of the process.

[0065] In particular, in the chip stacking structure of Figures 2A and 2B, all chips are active-side up, that is, different memory chips are stacked back to back, and memory chips and logic chips are also stacked back to back, that is, the bottom surface of the upper chip is in contact with the top surface of the lower chip.

[0066] In summary, on the one hand, the chip stacking structure of Figure 2A requires more conductive vias to transmit the corresponding signals, and the corresponding drive circuit and data selector result in larger loads and parasitic capacitances. The chip stacking structure of Figure 2B has a larger parasitic resistance due to the rotational configuration. On the other hand, both the stacking structures of Figures 2A and 2B have certain problems and cannot be directly applied to face-to-face stacking structures. Specifically, if you want to further realize a face-to-face chip stacking structure, one way is to use two sets of masks to make two different chips as chips with the active surface facing up and the active surface facing down. This method has a high process complexity and uncontrollable costs. Another way is to make an extra set of conductive vias and connect both sets of conductive vias to the same drive circuit in the memory chip. However, this will make the internal wiring of the memory chip complicated, which will not only increase the process complexity but also increase power consumption.

[0067] In another embodiment of the present disclosure, referring to FIG11 , a schematic diagram of the structure of a memory chip 10 provided by an embodiment of the present disclosure is shown, which can be specifically understood as a cross-sectional schematic diagram of the active surface. As shown in FIG11 , the memory chip 10 includes m channels ( FIG11 takes m=4 as an example), the m channels are sequentially arranged along a first direction, and each channel includes a first memory array region, a channel signal region, and a second memory array region sequentially distributed along a second direction, and the center of each channel signal region coincides with the center of the corresponding channel.

[0068] The center of the active surface of the memory chip 10 and its adjacent area are defined as a global signal region 20, with the center point of the global signal region 20 coinciding with the center point of the active surface. The m channels are symmetrical about the global signal region 20. Both the global signal region 20 and the channel signal region are penetrated by numerous conductive vias along a third direction perpendicular to the active surface.

[0069] Here, the conductive via may be a through silicon via (TSV), specifically a vertical interconnect structure that penetrates a silicon wafer / chip, or, in other embodiments, may be other conductive vias having a conductive function, without specific limitation. Furthermore, the conductive via may be in the form of the aforementioned type 1 or the aforementioned type 2.

[0070] For the global signal area 20, each conductive through-hole is used to transmit a global signal, and the global signal is shared by all areas of the memory chip; specifically, the global signal includes but is not limited to: a reset signal, a power-on signal, a stack identification signal SID / CID, a power-related signal Voltage Monitor, and a timing-related signal Timing Aligner. In some cases, the global signal area 20 may also refer to a pad area. The global signal may be a test signal for Design For Test (DFT), through which the working status of the internal circuit of the chip and the transmission status of related signals can be known. In addition, because the pin pad (PAD) of the DFT in the logic chip is generally located in the middle of the chip, the conductive through-holes of global signals such as the DFT are preferably located in a narrow area in the middle of the chip, that is, the position of the global signal area 20 as shown in Figure 3. Conversely, for the channel signal area, each conductive through-hole is used to transmit a channel signal, and each channel signal will only be used by the corresponding channel.

[0071] Referring to Figure 3 , the active surface includes a first axis AA' and a second axis BB'. The first axis AA' is parallel to the first side of the memory chip 10 and intersects perpendicularly at the center of the active surface. In Figure 3 , the first axis AA' extends along the first direction, and the second axis BB' extends along the second direction. In other embodiments, the first axis AA' may extend along the second direction, and the second axis BB' may extend along the first direction.

[0072] For the global signal region 20, the multiple conductive vias therein are divided into multiple conductive via groups. That is, the global signal region 20 is penetrated by n conductive via groups along the third direction, where n is a positive integer. Referring to Figure 4, each conductive via group includes four normal conductive vias (D0, D1, D2, and D3). The first normal conductive via D0 and the second normal conductive via D1 are symmetrical about the first axis AA', the third normal conductive via D2 and the fourth normal conductive via D3 are symmetrical about the first axis AA', and the first normal conductive via D0 and the fourth normal conductive via D3 are symmetrical about the second axis BB'.

[0073] 4 , the memory chip 10 further includes n selection circuits 30 , and the internal circuit of the memory chip 10 includes n internal port groups ( In0 ˜ In2 ). Due to space constraints, FIG4 only shows one conductive through-hole group and one internal port group.

[0074] The i-th selection circuit 30 is configured to receive and, based on a selection signal, electrically connect the four normal conductive through-holes in the i-th conductive through-hole group to the four internal ports in the i-th internal port group one by one, and the correspondence between the four normal conductive through-holes and the four internal ports is determined based on the selection signal.

[0075] For convenience of description, the i-th internal port group includes the i-th first internal port In0, the i-th second internal port In1In0, the i-th third internal port In3In1 and the i-th fourth internal port In3In2.

[0076] Please refer to Table 1. The i-th selection circuit is configured as follows: (1) if the selection signal is the first preset value, the first normal conductive via D0, the second normal conductive via D1, the third normal conductive via D2, and the fourth normal conductive via D3 in the i-th conductive via group are electrically connected one-to-one with the i-th fourth internal port In3, the i-th third internal port In3, the i-th second internal port In1, and the i-th first internal port In0, i.e., Case 1 in Table 1; (2) if the selection signal is the second preset value, the first normal conductive via D0, the second normal conductive via D1, the third normal conductive via D2, and the fourth normal conductive via D3 in the i-th conductive via group are electrically connected one-to-one with the i-th second internal port In1, the i-th first internal port In0, the i-th fourth internal port In3, and the i-th third internal port In3, i.e., Case 1 in Table 1. 1; (3) if the selection signal is the third preset value, the first normal conductive through hole D0, the second normal conductive through hole D1, the third normal conductive through hole D2, and the fourth normal conductive through hole D3 in the i-th conductive through hole group are electrically connected one by one with the i-th third internal port In3, the i-th fourth internal port In3, the i-th first internal port In0, and the i-th second internal port In1, that is, case 3 in Table 1; (4) if the selection signal meets the fourth preset value, the first normal conductive through hole D0, the second normal conductive through hole D1, the third normal conductive through hole D2, and the fourth normal conductive through hole D3 in the i-th conductive through hole group are electrically connected one by one with the i-th fourth internal port In3, the i-th third internal port In3, the i-th second internal port In1, and the i-th first internal port In0, that is, case 4 in Table 1.

[0077] Table 1

[0078] Referring to FIG. 2A or FIG. 2B , a logic chip and multiple memory chips 10 are stacked along a third direction to form a chip stack structure. In the chip stack structure, four memory chips 10 form a stacking unit. Each memory chip 10 also has a chip location identification code (CID) and a chip location identification code (SID). The chip location identification code (CID) indicates the location of the memory chip 10 within the stacking unit to which it belongs, while the stacking location identification code (SID) indicates the location of the stacking unit to which the memory chip 10 belongs within the chip stack structure.

[0079] Taking a chip stacking unit formed by stacking one logic chip and eight memory chips 10 (each four memory chips 10 constitutes a stacking unit, for a total of two stacking units) as an example, the CID has a two-bit sub-signal CID[1:0], the SID has a two-bit sub-signal SID[1:0], and the chip location identification code CID[1:0] is decoded from the chip location identification signal group CID0[3:0]. In particular, during the normal operation phase of the memory chip 10, the chips are numbered from the side of the logic chip (i.e., from bottom to top). At this time, the CID[1:0] and SID[1:0] of each chip are as shown in Table 2. During the initialization phase of the memory chip 10, the chips are numbered from the side away from the logic chip (i.e., from top to bottom). This situation is not shown yet, but can be understood accordingly.

[0080] Table 2

[0081] In particular, in the embodiment of the present disclosure, different memory chips 10 are placed in different positions in the chip stacking structure. For the convenience of explanation, the active surface of each memory chip 10 (the plane where the first direction and the second direction are located) is divided into a low-order transmission area and a high-order transmission area. Please refer to Figure 5A. The arrow direction of each chip is the high-order transmission area.

[0082] In the embodiment of the present disclosure, the positions of the memory chips 10 are divided into four categories: the top surfaces of the memory chips in the first and third positions are facing upward along the third direction, and the top surfaces of the memory chips in the second and fourth positions are facing downward along the third direction; the active surface of each memory chip is divided into a low-order transmission area and a high-order transmission area, and the low-order transmission area in the memory chip in the first position, the high-order transmission area in the memory chip in the second position, the high-order transmission area in the memory chip in the third position, and the low-order transmission area in the memory chip in the fourth position are aligned along the third direction.

[0083] In one stacking manner, see FIG5A , (1) the first memory chip 11 is in a first position, the second memory chip 12 is in a second position, the third memory chip 13 is in a third position, and the fourth memory chip 14 is in a fourth position;

[0084] In another stacking method, see FIG5B , (1) the first memory chip 11 is in the first position, the second memory chip 12 is in the fourth position, the third memory chip 13 is in the third position, and the fourth memory chip 14 is in the second position.

[0085] The memory chip 10 also includes: a decoding circuit 21, configured to receive a chip position identification code CID[1:0], and if the chip position identification code CID[1:0] indicates a first type of position, output a selection signal of a first preset value; if the chip position identification code CID[1:0] indicates a second type of position, output a selection signal of a second preset value; if the chip position identification code CID[1:0] indicates a third type of position, output a selection signal of a third preset value; if the chip position identification code CID[1:0] indicates a fourth type of position, output a selection signal that meets the fourth preset value.

[0086] In some other embodiments, the decoding circuit 21 may also generate a selection signal according to CID0[3:0].

[0087] In some embodiments, referring to FIG. 6 , each conductive via group further includes a first redundant conductive via R0, a second redundant conductive via R1, a third redundant conductive via R2, and a fourth redundant conductive via R3. FIG. 6 temporarily uses a = 1 as an example, but a can be any other positive integer. As shown in FIG. 6 , the a first redundant conductive via R0 and the a second redundant conductive via R1 are symmetrical about the first axis AA', the a third redundant conductive via R2 and the a fourth redundant conductive via R3 are symmetrical about the first axis AA', and the a first redundant conductive via R0 and the a fourth redundant conductive via R3 are symmetrical about the second axis BB'.

[0088] For each conductive via group, a first redundant conductive via R0, a second redundant conductive via R1, a first normal conductive via D0 and a second normal conductive via D1 constitute a repair unit, and a third redundant conductive via R2, a fourth redundant conductive via R3, a third normal conductive via D2 and a fourth normal conductive via D3 constitute another repair unit;

[0089] The selection circuit 30 is further configured to, when any normal conductive via fails, replace the failed normal conductive via with another conductive via in the same repair unit and electrically connect it to the corresponding internal port. For example, assuming the selection signal is a first preset value, if the first normal conductive via D0 is not failed, the selection circuit 30 electrically connects the first normal conductive via D0 to the first internal port In0. If the first normal conductive via D0 fails, the selection circuit 30 electrically connects the other conductive vias in the same repair unit to the first internal port In0.

[0090] It should be noted that the failure of a conductive through-hole refers to the failure of the signal transmission channel formed by the conductive through-hole and other conductive through-holes aligned along the third direction (belonging to other memory chips). In other words, for multiple conductive through-holes aligned along the third direction, damage to any conductive through-hole will cause the signal transmission channel to fail, and at the same time, the other multiple conductive through-holes will enter a failure state even if they are not damaged.

[0091] Here, a normal conductive via refers to a conductive via that is used to transmit valid signals at the beginning of the design, and a redundant conductive via refers to a conductive via that is not used to transmit any signal at the beginning of the design. However, when any normal conductive via fails, the redundant conductive via can be changed to a normal conductive via to transmit valid signals, so that the memory can still operate normally. That is, for the same repair unit, when any normal conductive via fails, the valid signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along the preset signal switching direction. Specifically: (1) If the next conductive via switched is a redundant conductive via, the repair is completed, and the redundant conductive via becomes the new normal conductive via; (2) If the next conductive via switched is another normal conductive via, the signal originally transmitted by the switched normal conductive via continues to be switched to its next conductive via along the preset switching direction.

[0092] In this way, through the selection circuit 30, any conductive via in any repair unit is electrically connected to the internal circuit of the logic chip 10 when used to transmit a valid signal, and any conductive via in any repair unit is electrically isolated from the internal circuit of the logic chip 10 when not transmitting a valid signal.

[0093] The following example of redundant repair logic uses a=1 as an example to facilitate understanding of the preceding description. However, the following example is not the only solution. In this specific embodiment, each normal conductive via can be repaired via two other conductive vias; however, this is merely an example. In other embodiments, more redundant conductive vias may be provided, or each normal conductive via may be repaired via a different number of other conductive vias.

[0094] In some embodiments, referring to FIG6 , the selection circuit 30 is specifically configured such that if the first normal conductive via D0 fails, the first redundant conductive via R0 or the fourth normal conductive via D3 is used to replace the first normal conductive via D0 to be electrically connected to the corresponding internal port; if the fourth normal conductive via D3 fails, the fourth redundant conductive via R3 or the first normal conductive via D0 is used to replace the fourth normal conductive via D3 to be electrically connected to the corresponding internal port; and, if the second normal conductive via D1 fails, the second redundant conductive via R1 or the third normal conductive via D2 is used to replace the second normal conductive via D1 to be electrically connected to the corresponding internal port; and, if the third normal conductive via D2 fails, the third redundant conductive via R2 or the second normal conductive via D1 is used to replace the third normal conductive via D2 to be electrically connected to the corresponding internal port.

[0095] It should be noted that if a normal conductive via is used to replace another failed normal conductive via, another redundant conductive via is required to replace the fourth normal conductive via D3 and electrically connect to the corresponding internal port until a redundant conductive via is enabled. For example, if the fourth normal conductive via D3 replaces the first normal conductive via D0 and electrically connects to the corresponding internal port, the fourth redundant conductive via R3 may also need to be enabled to replace the fourth normal conductive via D3 and electrically connect to the corresponding internal port.

[0096] In this way, the repair units in the logic chip 10 have a four-quadrant symmetrical relationship, and the normal conductive through-holes therein also have a four-quadrant symmetrical relationship, so that the chip stacking structure formed by the logic chip and the memory chip 10 (which also has this feature) can achieve a signal rotation transmission effect through the direct connection configuration of the conductive through-holes, and the parasitic resistance and parasitic capacitance are relatively small. For details, please refer to the subsequent description; at the same time, through the four-quadrant symmetrical arrangement of the repair units, the redundant repair function of the above structure can also be realized, thereby improving the stability of the chip.

[0097] In a specific embodiment, referring to FIG7 , the selection signal includes a first selection signal Ch0 and a second selection signal Ch1, and the i-th selection circuit 30 includes an i-th first selection circuit 31, an i-th second selection circuit 32, an i-th first signal output circuit 33, and an i-th second signal output circuit 34;

[0098] For the i-th first selection circuit 31, one side thereof is coupled to the first normal conductive via D0, the fourth normal conductive via D3, the first redundant conductive via R0, and the fourth redundant conductive via R3 in the i-th conductive via group, and the other side thereof is coupled to the i-th first secondary node Sec0 and the i-th fourth secondary node Sec3;

[0099] an i-th first selection circuit 31 configured to receive and, based on the first via state parameter set and the first selection signal Ch0, electrically connect one of the coupled conductive vias to the i-th first secondary node Sec0 and electrically connect the other coupled conductive via to the i-th fourth secondary node Sec3;

[0100] For the i-th second selection circuit 32, one side thereof is coupled to the second normal conductive via D1, the third normal conductive via D2, the second redundant conductive via R1, and the third redundant conductive via R2 in the i-th conductive via group, and the other side thereof is coupled to the i-th second secondary node Sec1 and the i-th third secondary node Sec2;

[0101] an i-th second selection circuit 32 configured to receive and, based on the second via state parameter set and the first selection signal Ch0, electrically connect one of the coupled conductive vias to the i-th second secondary node Sec1 and electrically connect the other coupled conductive via to the i-th third secondary node Sec2;

[0102] The i-th first signal output circuit 33 is configured to receive and, based on the second selection signal Ch1, electrically connect the i-th first secondary node Sec0 to the i-th first internal port In0, and electrically connect the i-th fourth secondary node Sec3 to the i-th fourth internal port In3; or, electrically connect the i-th second primary node Sec1 to the i-th first internal port In0, and electrically connect the i-th third secondary node Sec2 to the i-th fourth internal port In3.

[0103] The i-th second signal output circuit 34 is configured to receive and, based on the second selection signal Ch1, electrically connect the i-th second secondary node Sec1 to the i-th second internal port In1, and electrically connect the i-th third secondary node Sec2 to the i-th third internal port In2; or, electrically connect the i-th first secondary node Sec0 to the i-th second internal port In1, and electrically connect the i-th fourth secondary node Sec3 to the i-th third internal port In3.

[0104] Assuming that when each normal conductive via fails, another redundant conductive via is preferentially used for repair; if both the normal conductive via and the corresponding redundant conductive via fail, another normal conductive via is used for repair. A specific selection circuit is provided below.

[0105] 7 , the i-th first selection circuit 31 includes an i-th first repair circuit 311 , an i-th second repair circuit 312 , and an i-th first selection output circuit 313 ;

[0106] For the i-th first repair circuit 311, one side of the repair circuit 311 is respectively coupled to the first redundant conductive via R0, the first normal conductive via D0, and the fourth normal conductive via D3 in the i-th conductive via group, and the other side of the repair circuit 311 is coupled to the i-th first primary node Middle0. The first repair circuit 311 is configured to receive and, based on the i-th first via state parameter set, electrically connect one of the coupled first normal conductive via D0, the first redundant conductive via R0, and the fourth normal conductive via D3 to the i-th first primary node Middle0.

[0107] For the i-th second repair circuit 312, one side of the second repair circuit 312 is respectively coupled to the first normal conductive via D0, the fourth normal conductive via D3, and the fourth redundant conductive via R3 in the i-th conductive via group, and the other side of the second repair circuit 312 is coupled to the i-th fourth primary node Middle3. The second repair circuit 312 is configured to receive and, based on the i-th first via state parameter set, connect one of the coupled first normal conductive via D0, the fourth normal conductive via D3, and the fourth redundant conductive via R3 to the i-th fourth primary node Middle3.

[0108] The i-th first selection output circuit 313 is configured to receive and output the first selection signal Ch0, and electrically connect the i-th first primary node Middle0 to the i-th first secondary node Sec0, and electrically connect the i-th fourth primary node Middle3 to the i-th fourth secondary node Sec3; or, electrically connect the i-th fourth primary node Middle3 to the i-th first secondary node Sec0, and electrically connect the i-th first primary node Middle0 to the i-th fourth secondary node Sec3.

[0109] In a specific embodiment, the first preset value is the selection signal Ch[1:0] = 00, the second preset value is the selection signal Ch[1:0] = 10, the third preset value is the selection signal Ch[1:0] = 11, and the fourth preset value is the selection signal Ch[1:0] = 01. A feasible structure of the first selection output circuit 313 is shown in FIG8 .

[0110] As shown in FIG8 , each selection output circuit 313 may include four enable transmission gates, wherein the first enable transmission gate is coupled between the first primary node Middle0 and the first secondary node Sec0, the second enable transmission gate is coupled between the first primary node Middle0 and the fourth secondary node Sec3, and the enable terminal of the first enable transmission gate receives the inverted signal of the first selection signal Ch0, and the enable terminal of the second enable transmission gate receives the first selection signal Ch0; the third enable transmission gate is coupled between the fourth primary node Middle3 and the first secondary node Sec0, and the fourth enable transmission gate is coupled between the fourth primary node Middle3 and the fourth secondary node Sec3, and the enable terminal of the third enable transmission gate receives the first selection signal Ch0, and the enable terminal of the fourth enable transmission gate receives the inverted signal of the first selection signal Ch0. The structures of the first signal output unit 33 and the second signal output unit 34 are similar.

[0111] In a specific embodiment, the i-th first via state parameter group includes a first state parameter R0E, a second state parameter D0E, a third state parameter D3E, and a fourth state parameter R3E, and indicates one by one whether the first redundant conductive via R0, the first normal conductive via D0, the fourth normal conductive via D3, and the fourth redundant conductive via R3 in the i-th conductive via group are failed; when any state parameter is in an enabled state, it indicates that the corresponding conductive via is not failed; when any state parameter is in a disabled state, it indicates that the corresponding conductive via is failed;

[0112] 8 , the i-th first repair circuit 311 includes a first switching unit 412 , a second switching unit 422 , a third switching unit 432 , a first logic unit 411 , a second logic unit 421 , and a third logic unit 431 ;

[0113] The first logic unit 411 is configured to output the first control signal Ctr1 in the enabled state only when the i-th first through-hole state parameter group meets the first preset condition; wherein the first preset condition refers to that the first state parameter R0E is in the enabled state and the second state parameter D0E is in the disabled state, or that the first state parameter R0E and the second state parameter D0E are both in the enabled state and the third state parameter D3E and the fourth state parameter R3E are both in the disabled state; the first switching unit 412 is configured to control the i-th first redundant conductive through-hole R0 to be electrically connected to the i-th first primary node Middle0 only when the first control signal Ctr1 is in the enabled state.

[0114] In this way, R0 replaces D0 to work (R0 is electrically connected to the first primary node Middle0) in the following two situations: (1) R0 is not failed and D0 is failed, see Figure 9A and Figure 9E; (2) R0 and D0 are not failed and D3 and R3 are both failed. At this time, the surviving D0 needs to replace the failed D3 and be electrically connected to the corresponding internal port, so R0 also needs to replace D0 to work, see Figure 9B.

[0115] The second logic unit 421 is configured to output the second control signal Ctr2 in the enabled state only when the i-th first through-hole state parameter group meets the second preset condition; wherein the second preset condition refers to the second state parameter D0E being in the enabled state, and at least one of the third state parameter D3E and the fourth state parameter R3E being in the enabled state; the second switching unit 422 is configured to control the i-th first normal conductive through-hole D0 to be electrically connected to the i-th first primary node Middle0 only when the second control signal Ctr2 is in the enabled state.

[0116] 9C or 9F , the normal operation of D0 (D0 is electrically connected to the first primary node Middle0) occurs under the following circumstances: (1) D0 is not failed, and at least one of D3 and R3 is not failed.

[0117] The third logic unit 431 is configured to output the third control signal Ctr3 of the enable state only when the i-th first through-hole state parameter group meets the third preset condition; wherein the third preset condition means that the first state parameter R0E and the second state parameter D0E are both in the disabled state, and the third state parameter D3E is in the enabled state; the third switching unit 432 is configured to control the i-th fourth normal conductive through-hole D3 to be electrically connected to the i-th first primary node Middle0 only when the third control signal Ctr3 is in the enabled state.

[0118] Thus, referring to FIG. 9D , D3 works instead of D0 (D3 is electrically connected to the first primary node Middle0 ) and the following situations exist: (1) D0 and R0 both fail, but D3 does not fail.

[0119] Similarly, the i-th second repair circuit 312 includes a fourth switching unit 442 , a fifth switching unit 452 , a sixth switching unit 462 , a fourth logic unit 441 , a fifth logic unit 451 and a sixth logic unit 461 ;

[0120] The fourth logic unit 441 is configured to output the fourth control signal Ctr4 in the enabled state only when the i-th first through-hole state parameter group meets the fourth preset condition; wherein the fourth preset condition refers to when the fourth state parameter R3E is in the enabled state and the third state parameter D3E is in the disabled state, or when the fourth state parameter R3E and the third state parameter D3E are both in the enabled state and the second state parameter D0E and the first state parameter R0E are both in the disabled state; the fourth switching unit 442 is configured to control the i-th fourth redundant conductive through-hole R3 to be electrically connected to the i-th fourth primary node Middle3 only when the fourth control signal Ctr4 is in the enabled state.

[0121] In this way, R3 replaces D3 to work (R3 is electrically connected to the fourth primary node Middle3) in the following two situations: (1) R3 is not failed and D3 is failed, see Figure 9F; (2) R3 and D3 are not failed and D0 and R0 are both failed. At this time, the surviving D3 needs to replace the failed D0 and be electrically connected to the corresponding internal port, so R3 also needs to replace D3 to work.

[0122] The fifth logic unit 451 is configured to output the fifth control signal Ctr5 in the enabled state only when the i-th first through-hole state parameter group meets the fifth preset condition; wherein the fifth preset condition refers to the third state parameter D3E being in the enabled state, and at least one of the second state parameter D0E and the first state parameter R0E being in the enabled state; the fifth switching unit 452 is configured to control the i-th fourth normal conductive through-hole D3 to be electrically connected to the i-th fourth primary node Middle3 only when the fifth control signal Ctr5 is in the enabled state.

[0123] Thus, normal operation of D3 (D3 is electrically connected to the fourth primary node Middle3) occurs in the following situations: (1) D3 is not failed, and at least one of D0 and R0 is not failed, see FIG. 9C and FIG. 9E .

[0124] The sixth switching unit 462 is configured to output the sixth control signal Ctr6 in the enabled state only when the i-th first through-hole state parameter group meets the sixth preset condition; wherein the sixth preset condition means that the fourth state parameter R3E and the third state parameter D3E are both in the disabled state, and the second state parameter D0E is in the enabled state; the sixth switching unit 462 is configured to control the i-th first normal conductive through-hole D0 to be electrically connected to the i-th fourth primary node Middle3 only when the sixth control signal Ctr6 is in the enabled state.

[0125] Thus, D0 replaces D3 to be electrically connected to the corresponding internal port in the following situation (D0 is electrically connected to the fourth primary node Middle3) when D3 and R3 are both failed and D0 is not failed, see FIG9B.

[0126] For the following circuit settings: the enabled state is a high level, and the disabled state is a low level, a feasible structure of each of the above circuit units is provided, but it is not the only structure.

[0127] As shown in Figure 8, the first logic unit 411 includes a first NOT gate 501, a first AND gate 502 and a first OR gate 503; the second logic unit 421 includes a second AND gate 511 and a second OR gate 512; the third logic unit 431 includes a third NOT gate 521 and a third AND gate 522; the fourth logic unit 441 includes a fourth NOT gate 531, a fourth AND gate 532 and a fourth OR gate 533; the fifth logic unit 451 includes a fifth AND gate 541 and a fifth OR gate 542; and the sixth logic unit 461 includes a sixth NOT gate 551 and a sixth AND gate 552.

[0128] An input of the first NOT gate 501 receives the second state parameter D0E. An output of the first NOT gate 501 is connected to an input of the first AND gate 502. The other input of the first AND gate 502 receives the first state parameter R0E. The output of the first AND gate 502 and the output of the sixth AND gate 552 are respectively connected to two inputs of the first OR gate 503. The first OR gate 503 outputs a first control signal Ctr1. Two inputs of the second OR gate 512 respectively receive the third state parameter D3E and the fourth state parameter R3E. An output of the second OR gate 512 is connected to one input of the second AND gate 511. The other input of the second AND gate 511 receives the second state parameter D0E. The second AND gate 511 outputs a second control signal Ctr2. An input of the third NOT gate 521 is connected to the output of the fifth OR gate 542. An output of the third NOT gate 521 is connected to one input of the third AND gate 522. The other input of the third AND gate 522 receives the third state parameter D3E. The third AND gate 522 outputs a third control signal Ctr3.

[0129] An input of the fourth NOT gate 531 receives the third state parameter D3E. An output of the fourth NOT gate 531 is connected to one input of a fourth AND gate 532. The other input of the fourth AND gate 532 receives the fourth state parameter R3E. The output of the fourth AND gate 532 and the output of the third AND gate 522 are respectively connected to two inputs of a fourth OR gate 533. The fourth OR gate 533 outputs a fourth control signal Ctr4. Two inputs of the fifth OR gate 542 receive the first state parameter R0E and the second state parameter D0E, respectively. An output of the fifth OR gate 542 is connected to one input of a fifth AND gate 541. The other input of the fifth AND gate 541 receives the third state parameter D3E. The fifth AND gate 541 outputs a fifth control signal Ctr5. An input of the sixth NOT gate 551 is connected to the output of the second OR gate 512. An output of the sixth NOT gate 551 is connected to one input of a sixth AND gate 552. The other input of the sixth AND gate 552 receives the second state parameter D0E. The sixth AND gate 552 outputs a sixth control signal Ctr6.

[0130] The second selection circuit 32 has a similar structure to the first selection circuit 31 , and their working principles can be understood accordingly.

[0131] In some specific embodiments, as shown in FIG10 , the i-th second selection circuit 32 includes an i-th third repair unit 321 , an i-th fourth repair unit 322 , and an i-th second selection output circuit 323 ;

[0132] For the i-th third repair unit 321, one side thereof is coupled to the second redundant conductive via R1, the first normal conductive via D0, and the second normal conductive via D1 in the i-th conductive via group, and the other side thereof is coupled to the i-th second primary node Middle1; the third repair unit 321 is configured to receive and, based on the i-th second via state parameter group, electrically connect one of the coupled second normal conductive via D1, the second redundant conductive via R1, and the third normal conductive via D2 to the i-th second primary node Middle1;

[0133] For the i-th fourth repair unit 322, one side thereof is coupled to the second normal conductive via D1, the normal conductive via, and the third redundant conductive via R2 in the i-th conductive via group, and the other side thereof is coupled to the i-th third primary node Middle3. The fourth repair unit 322 is configured to receive and, based on the i-th second via state parameter group, electrically connect one of the coupled second normal conductive via D1, the third normal conductive via D2, and the third redundant conductive via R2 to the i-th third primary node Middle3.

[0134] The i-th second selection output circuit 323 is configured to receive and transmit the first selection signal Ch0, electrically connect the i-th second primary node Middle1 to the i-th second secondary node Sec1, and electrically connect the i-th third primary node Middle2 to the i-th third secondary node Sec2; or, electrically connect the i-th third primary node Middle2 to the i-th second secondary node Sec1, and electrically connect the i-th second primary node Middle1 to the i-th third secondary node Sec2.

[0135] Similarly, the second selection output circuit 323 is also composed of four enable transmission gates. The principle thereof can be found in the description of the first selection output circuit 313 .

[0136] In some embodiments, the i-th second via state parameter group includes a fifth state parameter R1E, ​​a sixth state parameter D1E, a seventh state parameter D2E, and an eighth state parameter R2E, and indicates one by one whether the second redundant conductive via R1, the second normal conductive via D1, the third normal conductive via D2, and the third redundant conductive via R2 in the i-th corresponding conductive via group are failed; when any state parameter is in an enabled state, it indicates that the corresponding conductive via is not failed; when any state parameter is in a disabled state, it indicates that the corresponding conductive via is failed.

[0137] 10 , the i-th third repair unit 321 includes a seventh switching unit 612 , an eighth switching unit 622 , a ninth switching unit 632 , a seventh logic unit 611 , an eighth logic unit 621 , and a ninth logic unit 631 ;

[0138] Please refer to Figure 10. The seventh logic unit 611 is configured to output the seventh control signal Ctr7 of the enable state only when the i-th second through-hole state parameter group meets the seventh preset condition; wherein the seventh preset condition refers to the fifth state parameter R1E is in the enable state and the sixth state parameter D1E is in the disable state, or the fifth state parameter R1E and the sixth state parameter D1E are both in the enable state and the seventh state parameter D2E and the eighth state parameter R2E are both in the disable state; the i-th seventh switching unit 612 is configured to control the i-th second redundant conductive through-hole R1 to be electrically connected to the i-th third primary node Middle2 only when the seventh control signal Ctr7 is in the enable state.

[0139] In this way, R1 replaces D1 to work (R1 is electrically connected to the second primary node Middle1) in the following two situations: (1) R1 is not failed and D1 is failed; (2) R1 and D1 are not failed and D2 and R2 are both failed. At this time, the surviving D1 needs to replace the failed D2 and be electrically connected to the corresponding internal port, so R1 also needs to replace D1 to work.

[0140] Please refer to Figure 10. The eighth logic unit 621 is configured to output the eighth control signal Ctr8 in the enabled state only when the i-th second through-hole state parameter group meets the eighth preset condition; wherein the eighth preset condition refers to the sixth state parameter D1E being in the enabled state, and at least one of the seventh state parameter D2E and the eighth state parameter R2E being in the enabled state; the eighth switching unit 622 is configured to control the i-th second normal conductive through-hole D1 to be electrically connected to the i-th third primary node Middle2 only when the eighth control signal Ctr8 is in the enabled state.

[0141] Thus, normal operation of D1 (D1 being electrically connected to the second primary node Middle1) occurs under the following circumstances: (1) D1 is not failed, and at least one of D2 and R2 is not failed.

[0142] Please refer to Figure 10. The ninth logic unit 631 is configured to output the ninth control signal Ctr9 in the enabled state only when the i-th second through-hole state parameter group meets the ninth preset condition; wherein the ninth preset condition means that the fifth state parameter R1E and the sixth state parameter D1E are both in the disabled state, and the seventh state parameter D2E is in the enabled state; the ninth switching unit 632 is configured to control the i-th third normal conductive through-hole D2 to be electrically connected to the i-th third primary node Middle2 only when the ninth control signal Ctr9 is in the enabled state.

[0143] Thus, D2 replaces D1 and is electrically connected to the corresponding internal port in the following situation (D2 is electrically connected to the second primary node Middle1) when the following conditions exist: (1) D1 and R1 are both failed, but D2 is not failed.

[0144] In a specific embodiment, referring to FIG10 , the fourth repair unit 322 includes a tenth switching unit 642 , an eleventh switching unit 652 , a twelfth switching unit 662 , a tenth logic unit 641 , an eleventh logic unit 651 , and a twelfth logic unit 661 ;

[0145] Please refer to Figure 10. The tenth logic unit 641 is configured to output the seventh control signal Ctr7 in the enabled state only when the i-th second through-hole state parameter group meets the tenth preset condition; wherein the fourth preset condition refers to when the eighth state parameter R2E is in the enabled state and the seventh state parameter D2E is in the disabled state, or when the eighth state parameter R2E and the seventh state parameter D2E are both in the enabled state and the sixth state parameter D1E and the fifth state parameter R1E are both in the disabled state; the tenth switching unit 642 is configured to control the i-th third redundant conductive through-hole R2 to be electrically connected to the i-th fourth primary node only when the tenth control signal Ctr10 is in the enabled state.

[0146] In this way, R2 replaces D2 to work (R2 is electrically connected to the third primary node Middle2) in the following two situations: (1) R2 is not failed and D2 is failed; (2) R2 and D2 are not failed and D1 and R1 are both failed. At this time, the surviving D2 needs to replace the failed D1 and be electrically connected to the corresponding internal port, so R2 also needs to replace D2 to work.

[0147] Please refer to Figure 10. The eleventh logic unit 651 is configured to output the eleventh control signal Ctr11 in the enable state only under the eleventh preset condition of the i-th second through-hole state parameter group; wherein the eleventh preset condition refers to the seventh state parameter D2E being in the enable state, and at least one of the sixth state parameter D1E and the fourth state parameter R3E being in the enable state; the eleventh switching unit 652 is configured to control the i-th third normal conductive through-hole D2 to be electrically connected to the i-th fourth primary node only when the eleventh control signal Ctr11 is in the enable state.

[0148] Thus, normal operation of D2 (D2 is electrically connected to the third primary node Middle2) occurs in the following situations: (1) D2 is not failed, and at least one of D1 and R1 is not failed.

[0149] Please refer to Figure 10. The twelfth logic unit 661 is configured to output the twelfth control signal Ctr12 in the enabled state only under the twelfth preset condition of the i-th second through-hole state parameter group; wherein the twelfth preset condition means that the eighth state parameter R2E and the seventh state parameter D2E are both in the disabled state, and the sixth state parameter D1E is in the enabled state; the twelfth switching unit 662 is configured to control the i-th second normal conductive through-hole D1 to be electrically connected to the i-th fourth primary node only when the twelfth control signal Ctr12 is in the enabled state.

[0150] Thus, D1 replaces D2 in electrical connection with the corresponding internal port in the following situation (D1 is electrically connected to the third primary node Middle2) when the following conditions exist: D1 and R1 are both failed and D2 is not failed.

[0151] In a specific embodiment, referring to FIG9 , when the enable state is a high level and the disable state is a low level, the seventh logic unit 611 includes a seventh NOT gate 701, a seventh AND gate 702, and a seventh OR gate 703; the eighth logic unit 621 includes an eighth AND gate 711 and an eighth OR gate 712; the ninth logic unit 631 includes a ninth NOT gate 721 and a ninth AND gate 722; the tenth logic unit 641 includes a tenth NOT gate 731, a tenth AND gate 732, and a tenth OR gate 733; the eleventh logic unit 651 includes an eleventh AND gate 741 and an eleventh OR gate 742; and the twelfth logic unit 631 includes a twelfth NOT gate 751 and a twelfth AND gate 752.

[0152] The input end of the seventh NOT gate 701 receives the sixth state parameter D1E, the output end of the seventh NOT gate 701 is connected to one input end of the seventh AND gate 702, the other input end of the seventh AND gate 702 receives the fifth state parameter R1E, ​​the output end of the seventh AND gate 702 and the output end of the twelfth AND gate 752 are respectively connected to the two input ends of the seventh OR gate 703; the two input ends of the eighth OR gate 712 receive the seventh state parameter D2E and the eighth state parameter R2E respectively, and the output end of the eighth OR gate 712 is connected to the eighth AND gate 711 , the other input terminal of the eighth AND gate 711 receives the sixth state parameter D1E; the input terminal of the ninth NOT gate 721 is connected to the output terminal of the eleventh OR gate 742, the output terminal of the ninth NOT gate 721 is connected to one input terminal of the ninth AND gate 722, and the other input terminal of the ninth AND gate 722 receives the seventh state parameter D2E; the seventh OR gate 703 outputs a seventh control signal Ctr7, the eighth AND gate 711 outputs an eighth control signal Ctr8, and the ninth AND gate 722 outputs a ninth control signal Ctr9;

[0153] The input end of the tenth NOT gate 731 receives the seventh state parameter D2E, the output end of the tenth NOT gate 731 is connected to one input end of the tenth AND gate 732, the other input end of the tenth AND gate 732 receives the eighth state parameter R2E, the output end of the tenth AND gate 732 and the output end of the ninth AND gate 722 are respectively connected to the two input ends of the tenth OR gate 733, and the tenth OR gate 733 outputs the tenth control signal Ctr10; the two input ends of the eleventh OR gate 742 respectively receive the fifth state parameter R1E and the sixth state parameter D1E, and the eleventh OR gate 743 outputs the tenth control signal Ctr10. The output end of the gate 742 is connected to one input end of the eleventh AND gate 741, the other input end of the eleventh AND gate 741 receives the seventh state parameter D2E, and the eleventh AND gate 741 outputs the eleventh control signal Ctr11; the input end of the twelfth NOT gate 751 is connected to the output end of the eighth OR gate 712, the output end of the twelfth NOT gate 751 is connected to one input end of the twelfth AND gate 752, the other input end of the twelfth AND gate 752 receives the sixth state parameter D1E, and the twelfth AND gate 752 outputs the twelfth control signal Ctr12.

[0154] It should also be noted that the conductive vias mentioned above can at least be embodied as through silicon vias (TSVs), specifically a vertical interconnect structure that penetrates the silicon wafer / memory chip 10, such as type 1 in FIG. 1 ; of course, the conductive vias can also be type 2 in FIG. 1 , which together with the contact structure realize signal transmission. In other embodiments, other electrical connection structures can also be selected as the conductive vias.

[0155] Conductive vias can be fabricated using one or more of the following processes: via-first, via-mid, via-last, and via-back. A via-first process involves fabricating the via structure before manufacturing the device structure, such as a metal oxide semiconductor field effect transistor (MOSFET). A via-mid process involves forming the via structure during the manufacturing process, often after the device is formed but before the stack is fabricated. A via-last process involves forming the via from the front side of the wafer after the back-end of line (BEOL) processing is complete. A via-back process involves forming the via structure from the back side of the wafer after the BEOL processing is complete. In other words, a via-first process can involve fabricating the via first, followed by the circuit; a via-mid process can involve fabricating the circuit and some metal layers first, then the via, and finally the remaining via. Both a via-last and via-back process involve fabricating the circuit and metal layers first, followed by the via.

[0156] In summary, the embodiments of the present disclosure provide a memory chip that transmits four different global signals through four different normal conductive vias, with high signal transmission efficiency; at the same time, every four different normal conductive vias also correspond to 4a redundant conductive vias, and a redundant repair function can also be realized; the chip stacking structure formed by the memory chip and the logic chip (which also has this feature) can achieve a signal rotation transmission effect through the direct connection configuration of the conductive vias, and the parasitic resistance and parasitic capacitance are relatively small.

[0157] In another embodiment of the present disclosure, see Figure 11, which illustrates a schematic structural diagram of a logic chip 70 provided by an embodiment of the present disclosure, specifically a cross-sectional diagram of an active surface. As shown in Figure 11, the logic chip 70 includes m channel signal regions (Figure 10 illustrates m = 4 as an example) arranged sequentially along a first direction, with the center of each channel signal region coinciding with the center of the corresponding channel.

[0158] The center of the active surface of the logic chip 70 and its adjacent area are defined as the global signal region 20, with the center point of the global signal region 20 coinciding with the center point of the active surface. The m channel signal regions are symmetrical about the global signal region 20. Both the global signal region 20 and the channel signal region are penetrated by numerous conductive vias along a third direction perpendicular to the active surface. In the global signal region 20, each conductive via is used to transmit a global signal, which is shared by all regions of the memory chip 10. In the channel signal region, each conductive via is used to transmit a channel signal, and each channel signal is used only by the corresponding channel.

[0159] Specifically, the global signal regions 20 of the logic chip 70 and the memory chip 10 have the same area, but the active area of ​​the logic chip 70 may be greater than or equal to the active area of ​​the memory chip 10 .

[0160] Referring to Figure 11 , the global signal region 20 has a first axis AA' and a second axis BB'. The first axis AA' is parallel to the first side of the logic chip 70 and intersects perpendicularly at the center of the active surface. In Figure 11 , the first axis AA' extends along a first direction, and the second axis BB' extends along a second direction. This is merely an example and does not constitute a limitation.

[0161] The logic chip 70 also has a conductive via group similar to the aforementioned logic chip 70 , which is described in detail below.

[0162] Referring to Figure 12 , the global signal region 20 is penetrated by n conductive via groups along the third direction. Each conductive via group includes four normal conductive vias (D0, D1, D2, and D3), with the first normal conductive via D0 and the second normal conductive via D1 being symmetrical about the first axis AA', the third normal conductive via D2 and the fourth normal conductive via D3 being symmetrical about the first axis AA', and the first normal conductive via D0 and the fourth normal conductive via D3 being symmetrical about the second axis BB'.

[0163] 12 , the logic chip 70 further includes n control circuits 80 , and the internal circuit of the logic chip 70 includes n first signal ports TA0 , n second signal ports TA1 , n third signal ports TA2 , and n fourth signal ports TA3 .

[0164] The i-th control circuit 80 is configured to electrically connect the first normal conductive through hole D0, the second normal conductive through hole D1, the third normal conductive through hole D2, and the fourth normal conductive through hole D3 in the i-th conductive through hole group to the i-th first signal port TA1, the i-th second signal port TA2, the i-th third signal port TA4, and the i-th fourth signal port TA4 in a one-to-one correspondence.

[0165] In some embodiments, referring to FIG. 12 , each conductive via group further includes 4a redundant conductive vias ( FIG. 12 illustrates a=1 as an example), wherein 4a first redundant conductive via R0 and 4a second redundant conductive via R1 are symmetrical about a first axis AA', 4a third redundant conductive via R2 and 4a fourth redundant conductive via R3 are symmetrical about the first axis AA', and 4a first redundant conductive via R0 and 4a fourth redundant conductive via R3 are symmetrical about a second axis BB'. a first redundant conductive via R0, a second redundant conductive via R1, a first normal conductive via D0, and a second normal conductive via D1 constitute a repair unit, and a third redundant conductive via R2, a fourth redundant conductive via R3, a third normal conductive via D2, and a fourth normal conductive via D3 constitute another repair unit.

[0166] The control circuit 80 is further configured to utilize other conductive vias of the same repair unit to replace the failed normal conductive vias and electrically connect to the corresponding signal port when any normal conductive via fails.

[0167] In a specific embodiment, the control circuit 80 is specifically configured such that if the first normal conductive via D0 fails, the first redundant conductive via R0 or the fourth normal conductive via D3 is used to replace the first normal conductive via D0 to be electrically connected to the corresponding signal port (i.e., connected to the first signal port TA1); and, if the fourth normal conductive via D3 fails, the fourth redundant conductive via R3 or the first normal conductive via D0 is used to replace the fourth normal conductive via D3 to be electrically connected to the corresponding signal port (i.e., connected to the fourth signal port TA3); and if the second normal conductive via D1 fails, the second redundant conductive via R1 or the third normal conductive via D2 is used to replace the second normal conductive via D1 to be electrically connected to the corresponding signal port (i.e., connected to the second signal port TA2); and, if the third normal conductive via D2 fails, the third redundant conductive via R2 or the second normal conductive via D1 is used to replace the third normal conductive via D2 to be electrically connected to the corresponding signal port (i.e., connected to the third signal port TA3).

[0168] In a specific embodiment, referring to FIG12 , the i-th control circuit 80 includes an i-th first control circuit 81 and an i-th second control circuit 82 ;

[0169] For the i-th first control circuit 81, one side of the first control circuit 81 is coupled to the first normal conductive via D0, the fourth normal conductive via D3, the first redundant conductive via R0, and the fourth redundant conductive via R3 in the i-th conductive via group, and the other side of the first control circuit 81 is coupled to the i-th first signal port TA1 and the i-th fourth signal port TA4; the i-th first control circuit 81 is configured to receive the i-th first via state parameter group, and based on the first via state parameter group and the selection signal, electrically connect one of the coupled conductive vias to the i-th first signal port TA1, and electrically connect the other coupled conductive via to the i-th fourth signal port TA4;

[0170] For the i-th second control circuit 82, one side thereof is coupled to the second normal conductive via D1, the third normal conductive via D2, the second redundant conductive via R1 and the third redundant conductive via R2 in the i-th conductive via group, and the other side thereof is coupled to the i-th second signal port TA2 and the i-th third signal port TA3; the i-th second control circuit 82 is configured to receive the i-th second via state parameter group, and based on the second via state parameter group and the selection signal, electrically connect one of the coupled conductive vias to the second signal port TA2, and electrically connect the other coupled conductive via to the third signal port TA3.

[0171] In a specific embodiment, referring to FIG13 , the i-th first control circuit 81 includes an i-th first repair circuit 311 and an i-th second repair circuit 312 ;

[0172] For the i-th first repair circuit 311, one side of the repair circuit 311 is respectively coupled to the first redundant conductive via R0, the first normal conductive via D0, and the second normal conductive via D1 in the i-th conductive via group, and the other side of the repair circuit 311 is coupled to the first signal port TA1; the first repair circuit 311 is configured to receive and, based on the first via state parameter set, electrically connect one of the coupled first normal conductive via D0, the first redundant conductive via R0, and the fourth normal conductive via D3 to the i-th first signal port TA0;

[0173] For the i-th second repair circuit 312, one side thereof is coupled to the first normal conductive via D0, the normal conductive via and the fourth redundant conductive via R3 in the i-th conductive via group, and the other side thereof is coupled to the third signal port TA2; the second repair circuit 312 is configured to receive the i-th first via state parameter group, and is electrically connected to the i-th third signal port TA2 based on one of the first normal conductive via D0, the fourth normal conductive via D3 and the fourth redundant conductive via R3.

[0174] In some embodiments, the i-th first through-hole state parameter group includes a first state parameter R0E, a second state parameter D0E, a third state parameter D3E and a fourth state parameter R3E, and indicates one by one whether the first redundant conductive through-hole R0, the first normal conductive through-hole D0, the fourth normal conductive through-hole D3 and the fourth redundant conductive through-hole R3 in the i-th conductive through-hole group are failed; when any state parameter is in an enabled state, it indicates that the corresponding conductive through-hole is not failed; when any state parameter is in a disabled state, it indicates that the corresponding conductive through-hole is failed.

[0175] 14 , the i-th first repair circuit 311 includes a first switching unit 412 , a second switching unit 422 , a third switching unit 432 , a first logic unit 411 , a second logic unit 421 , and a third logic unit 431 ;

[0176] The first logic unit 411 is configured to output the first control signal Ctr1 in the enabled state only when the i-th first through-hole state parameter group meets the first preset condition; wherein the first preset condition refers to that the first state parameter R0E is in the enabled state and the second state parameter D0E is in the disabled state, or that the first state parameter R0E and the second state parameter D0E are both in the enabled state and the third state parameter D3E and the fourth state parameter R3E are both in the disabled state; the first switching unit 412 is configured to control the i-th first redundant conductive through-hole R0 to be electrically connected to the i-th first signal port TA0 only when the first control signal Ctr1 is in the enabled state.

[0177] The second logic unit 421 is configured to output the second control signal Ctr2 in the enabled state only when the i-th first through-hole state parameter group meets the second preset condition; wherein the second preset condition refers to the second state parameter D0E being in the enabled state, and at least one of the third state parameter D3E and the fourth state parameter R3E being in the enabled state; the second switching unit 422 is configured to control the i-th first normal conductive through-hole D0 to be electrically connected to the i-th first signal port TA0 only when the second control signal Ctr2 is in the enabled state.

[0178] The third switching unit 432 is configured to output the third control signal Ctr3 of the enable state only when the i-th first through-hole state parameter group meets the third preset condition; wherein the third preset condition means that the first state parameter R0E and the second state parameter D0E are both in the disabled state, and the third state parameter D3E is in the enabled state; the third switching unit 432 is configured to control the i-th fourth normal conductive through-hole D3 to be electrically connected to the i-th first signal port TA0 only when the third control signal Ctr3 is in the enabled state.

[0179] In some embodiments, referring to FIG. 14 , the i-th second repair circuit 312 includes a fourth switching unit 442 , a fifth switching unit 452 , a sixth switching unit 462 , a fourth logic unit 441 , a fifth logic unit 451 , and a sixth logic unit 461 ;

[0180] The fourth logic unit 441 is configured to output a fourth control signal Ctr4 in an enabled state only when the i-th first via state parameter group meets a fourth preset condition; wherein the fourth preset condition is that the fourth state parameter R3E is in an enabled state and the third state parameter D3E is in a disabled state, or that the fourth state parameter R3E and the third state parameter D3E are both in an enabled state and the second state parameter D0E and the first state parameter R0E are both in a disabled state; and the fourth switching unit 442 is configured to control the i-th fourth redundant conductive via R3 to be electrically connected to the i-th fourth signal port TA3 only when the fourth control signal Ctr4 is in an enabled state.

[0181] The fifth logic unit 451 is configured to output a fifth control signal Ctr5 in an enabled state only when the i-th first via state parameter group meets a fifth preset condition; wherein the fifth preset condition is that the third state parameter D3E is in an enabled state and at least one of the second state parameter D0E and the first state parameter R0E is in an enabled state; and the fifth switching unit 452 is configured to control the i-th fourth normal conductive via D3 to be electrically connected to the i-th fourth signal port TA3 only when the fifth control signal Ctr5 is in an enabled state.

[0182] The sixth switching unit 462 is configured to output the sixth control signal Ctr6 in the enabled state only when the i-th first through-hole state parameter group meets the sixth preset condition; wherein the sixth preset condition means that the fourth state parameter R3E and the third state parameter D3E are both in the disabled state, and the second state parameter D0E is in the enabled state; the sixth switching unit 462 is configured to control the i-th first normal conductive through-hole D0 to be electrically connected to the i-th fourth signal port TA3 only when the sixth control signal Ctr6 is in the enabled state.

[0183] In some embodiments, referring to FIG. 14 , when the enabled state is at a high level and the disabled state is at a low level, the first logic unit 411 includes a first NOT gate 501, a first AND gate 502, and a first OR gate 503; the second logic unit 421 includes a second AND gate 511 and a second OR gate 512; the third logic unit 431 includes a third NOT gate 521 and a third AND gate 522; the fourth logic unit 441 includes a fourth NOT gate 531, a fourth AND gate 532, and a fourth OR gate 533; the fifth logic unit 451 includes a fifth AND gate 541 and a fifth OR gate 542; the sixth logic unit 431 includes a sixth NOT gate 551 and a sixth AND gate 552;

[0184] An input of the first NOT gate 501 receives the second state parameter D0E. An output of the first NOT gate 501 is connected to an input of the first AND gate 502, the other input of which receives the first state parameter R0E. The output of the first AND gate 502 and the output of the sixth AND gate 552 are respectively connected to two inputs of the first OR gate 503. Two inputs of the second OR gate 512 receive the third state parameter D3E and the fourth state parameter R3E, respectively. An output of the second OR gate 512 is connected to an input of the second AND gate 511, the other input of which receives the second state parameter D0E. An input of the third NOT gate 521 is connected to the output of the fifth OR gate 542. An output of the third NOT gate 521 is connected to an input of the third AND gate 522, the other input of which receives the third state parameter D3E. The first OR gate 503 outputs the first control signal Crt1. The second AND gate 511 outputs the second control signal Crt2, and the third AND gate 522 outputs the third control signal Crt3.

[0185] An input of the fourth NOT gate 531 receives the third state parameter D3E. An output of the fourth NOT gate 531 is connected to one input of a fourth AND gate 532. The other input of the fourth AND gate 532 receives the fourth state parameter R3E. The output of the fourth AND gate 532 and the output of the third AND gate 522 are respectively connected to two inputs of a fourth OR gate 533. Two inputs of the fifth OR gate 542 receive the first state parameter R0E and the second state parameter D0E, respectively. The output of the fifth OR gate 542 is connected to one input of the fifth AND gate 541. The other input of the fifth AND gate 541 receives the third state parameter D3E. An input of the sixth NOT gate 551 is connected to the output of the second OR gate 512. An output of the sixth NOT gate 551 is connected to one input of a sixth AND gate 552. The other input of the sixth AND gate 552 receives the second state parameter D0E. The fourth OR gate 533 outputs a fourth control signal Crt4. The fifth AND gate 541 outputs a fifth control signal Crt5. The sixth AND gate 552 outputs a sixth control signal Crt6.

[0186] In some embodiments, referring to FIG15 , the i-th second selection circuit 32 includes a third repair unit 321 and a fourth repair unit 322 ;

[0187] The third repair unit 321 has one side coupled to the second redundant conductive via R1, the first normal conductive via D0, and the second normal first state parameter R0E via in the i-th conductive via group, and the other side coupled to the second signal port TA1. The third repair unit 321 is configured to receive and, based on the second via state parameter group, electrically connect one of the coupled second normal conductive via D1, the second redundant conductive via R1, and the third normal conductive via D2 to the i-th second signal port TA1.

[0188] For the fourth repair unit 322, one side thereof is coupled to the second normal conductive via D1, the normal conductive via and the third redundant conductive via R2 in the i-th conductive via group, and the other side thereof is coupled to the fourth signal port TA2; the fourth repair unit 322 is configured to receive and, based on the second via state parameter group, electrically connect one of the second normal conductive via D1, the third normal conductive via D2 and the third redundant conductive via R2 to the i-th third signal port TA2.

[0189] In some embodiments, the i-th second through-hole state parameter group includes 4 state parameters, and the fifth state parameter R1E, ​​the sixth state parameter D1E, the seventh state parameter D2E and the eighth state parameter R2E correspond one to one to indicate whether the second redundant conductive through-hole R1, the second normal conductive through-hole D1, the third normal conductive through-hole D2 and the third redundant conductive through-hole R2 in the i-th conductive through-hole group are failed; when any state parameter is in the enabled state, it indicates that the corresponding conductive through-hole is not failed; when any state parameter is in the disabled state, it indicates that the corresponding conductive through-hole is failed.

[0190] 15 , the i-th third repair unit 321 includes a seventh switching unit 612 , an eighth switching unit 622 , a ninth switching unit 632 , a seventh logic unit 611 , an eighth logic unit 621 , and a ninth logic unit 631 ;

[0191] The seventh logic unit 611 is configured to output a seventh control signal Ctr7 in an enabled state only when the i-th second via state parameter group meets a seventh preset condition; wherein the seventh preset condition is that the fifth state parameter R1E is in an enabled state and the sixth state parameter D1E is in a disabled state, or that the fifth state parameter R1E and the sixth state parameter D1E are both in an enabled state and the seventh state parameter D2E and the eighth state parameter R2E are both in a disabled state; and the seventh switching unit 612 is configured to control the i-th second redundant conductive via R1 to be electrically connected to the i-th second signal port TA1 only when the seventh control signal Ctr7 is in an enabled state.

[0192] The eighth logic unit 621 is configured to output an eighth control signal Ctr8 in an enabled state only when the i-th second via state parameter group meets an eighth preset condition; wherein the eighth preset condition is that the sixth state parameter D1E is in an enabled state, and at least one of the seventh state parameter D2E and the eighth state parameter R2E is in an enabled state; and the eighth switching unit 622 is configured to control the i-th second normal conductive via D1 to be electrically connected to the i-th second signal port TA1 only when the eighth control signal Ctr8 is in an enabled state.

[0193] The ninth switching unit 632 is configured to output a ninth control signal Ctr9 in an enabled state only when the i-th second via state parameter group meets a ninth preset condition; wherein the ninth preset condition is that the fifth state parameter R1E and the sixth state parameter D1E are both in a disabled state, and the seventh state parameter D2E is in an enabled state; the ninth switching unit 632 is configured to control the third normal conductive via D2 to be electrically connected to the second signal port TA1 only when the ninth control signal Ctr9 is in the enabled state;

[0194] In some embodiments, referring to FIG. 15 , the fourth repair unit 322 includes a tenth switching unit 642 , an eleventh switching unit 652 , a twelfth switching unit 662 , a tenth logic unit 641 , an eleventh logic unit 651 , and a twelfth logic unit 661 ;

[0195] The tenth logic unit 641 is configured to output a tenth control signal Ctr10 in an enabled state only when the i-th second via state parameter group meets a tenth preset condition; wherein the tenth preset condition is when the eighth state parameter R2E is in an enabled state and the seventh state parameter D2E is in a disabled state, or when the eighth state parameter R2E and the seventh state parameter D2E are both in an enabled state and the sixth state parameter D1E and the fifth state parameter R1E are both in a disabled state; and the tenth switching unit 642 is configured to control the i-th third redundant conductive via R2 to be electrically connected to the i-th third signal port TA2 only when the tenth control signal Ctr10 is in an enabled state.

[0196] The eleventh logic unit 651 is configured to output an eleventh control signal Ctr11 in an enabled state only when the i-th second via state parameter group meets an eleventh preset condition; wherein the eleventh preset condition is that the seventh state parameter D2E is in an enabled state, and at least one of the fifth state parameter R1E and the sixth state parameter D1E is in an enabled state; and the eleventh switching unit 652 is configured to control the i-th third normal conductive via D2 to be electrically connected to the i-th third signal port TA2 only when the eleventh control signal Ctr11 is in an enabled state.

[0197] The twelfth switching unit 662 is configured to output the twelfth control signal Ctr12 in the enabled state only when the i-th second through-hole state parameter group meets the twelfth preset condition; wherein the twelfth preset condition means that the eighth state parameter R2E and the seventh state parameter D2E are both in the disabled state, and the sixth state parameter D1E is in the enabled state; the twelfth switching unit 662 is configured to control the i-th second normal conductive through-hole D1 to be electrically connected to the i-th third signal port TA2 only when the twelfth control signal Ctr12 is in the enabled state.

[0198] In a specific embodiment, when the enabled state is at a high level and the disabled state is at a low level, the seventh logic unit 611 includes a seventh NOT gate 701, a seventh AND gate 702, and a seventh OR gate 703; the eighth logic unit 621 includes an eighth AND gate 711 and an eighth OR gate 712; the ninth logic unit 631 includes a ninth NOT gate 721 and a ninth AND gate 722; the tenth logic unit 641 includes a tenth NOT gate 731, a tenth AND gate 732, and a tenth OR gate 733; the eleventh logic unit 651 includes an eleventh AND gate 741 and an eleventh OR gate 742; the twelfth logic unit 631 includes a twelfth NOT gate 751 and a twelfth AND gate 752;

[0199] The input end of the seventh NOT gate 701 receives the sixth state parameter D1E, the output end of the seventh NOT gate 701 is connected to one input end of the seventh AND gate 702, the other input end of the seventh AND gate 702 receives the fifth state parameter R1E, ​​the output end of the seventh AND gate 702 and the output end of the twelfth AND gate 752 are respectively connected to the two input ends of the seventh OR gate 703; the two input ends of the eighth OR gate 712 receive the seventh state parameter D2E and the eighth state parameter R2E respectively, and the output end of the eighth OR gate 712 is connected to the eighth AND gate 711 , the other input terminal of the eighth AND gate 711 receives the sixth state parameter D1E; the input terminal of the ninth NOT gate 721 is connected to the output terminal of the eleventh OR gate 742, the output terminal of the ninth NOT gate 721 is connected to one input terminal of the ninth AND gate 722, and the other input terminal of the ninth AND gate 722 receives the seventh state parameter D2E; the seventh OR gate 703 outputs a seventh control signal Ctr7, the eighth AND gate 711 outputs an eighth control signal Ctr8, and the ninth AND gate 722 outputs a ninth control signal Ctr9;

[0200] The input end of the tenth NOT gate 731 receives the seventh state parameter D2E, the output end of the tenth NOT gate 731 is connected to one input end of the tenth AND gate 732, the other input end of the tenth AND gate 732 receives the eighth state parameter R2E, the output end of the tenth AND gate 732 and the output end of the ninth AND gate 722 are respectively connected to the two input ends of the tenth OR gate 733, and the tenth OR gate 733 outputs the tenth control signal Ctr10; the two input ends of the eleventh OR gate 742 respectively receive the fifth state parameter R1E and the sixth state parameter D1E, and the eleventh OR gate 743 outputs the tenth control signal Ctr10. The output end of the gate 742 is connected to one input end of the eleventh AND gate 741, the other input end of the eleventh AND gate 741 receives the seventh state parameter D2E, and the eleventh AND gate 741 outputs the eleventh control signal Ctr11; the input end of the twelfth NOT gate 751 is connected to the output end of the eighth OR gate 712, the output end of the twelfth NOT gate 751 is connected to one input end of the twelfth AND gate 752, the other input end of the twelfth AND gate 752 receives the sixth state parameter D1E, and the twelfth AND gate 752 outputs the twelfth control signal Ctr12.

[0201] The embodiment of the present disclosure provides a logic chip 70 that transmits four different global signals through four different normal conductive vias, with high signal transmission efficiency. At the same time, every four different normal conductive vias also correspond to 4a redundant conductive vias, which can also realize a redundant repair function. The chip stacking structure formed by the memory chip and the logic chip (which also has this feature) can achieve a signal rotation transmission effect through the direct connection configuration of the conductive vias, and the parasitic resistance and parasitic capacitance are relatively small.

[0202] In another embodiment of the present disclosure, see FIG16 , which illustrates a schematic diagram of the composition of a chip stacking structure 90 provided in an embodiment of the present disclosure. As shown in FIG16 , the chip stacking structure 90 includes the aforementioned logic chip 70 and at least one stacking unit, wherein the logic chip 70 and the at least one stacking unit are stacked sequentially along a third direction. Each stacking unit includes a first memory chip 11, a second memory chip 12, a third memory chip 13, and a fourth memory chip 14 stacked along the third direction. The logic chip 70, and the structures of the first memory chip 11, the second memory chip 12, the third memory chip 13, and the fourth memory chip 14 are all the aforementioned memory chips 10.

[0203] For each stacking unit, the first memory chip 11 and the second memory chip 12 are stacked face to face, the second memory chip 12 and the third memory chip 13 are stacked back to back, and the third memory chip 13 and the fourth memory chip 14 are stacked face to face; the first memory chip 11 and the logic chip 70 in the first stacking unit are stacked back to back, or the first memory chip 11 and the logic chip 70 in the first stacking unit are stacked back to back.

[0204] In the embodiment of the present disclosure, face-to-face stacking means that the top surfaces of the two chips are approximately aligned along the third direction; back-to-back stacking means that the top surfaces of the two chips are approximately aligned along the third direction; and face-to-back stacking means that the top surface of one chip is approximately aligned with the bottom surface of another chip along the third direction. When a logic chip or a memory chip is not specified, "chip" can refer to both a logic chip and a memory chip. In the chip stacking structure 90, the center points of all chips, the first axis AA' and the second axis BB' of the top surface are aligned along the third direction,

[0205] It should be noted that, in one possibility, for two chips connected face to face, the bonding surfaces of the two (the positions where the conductive through holes are aligned along the third direction) are electrically connected through a hybrid bonding structure (Hyperbonding, also known as bonding columns); for two chips connected back to back or back to face, the bonding surfaces of the two (the positions where the conductive through holes are aligned along the third direction) are electrically connected through conductive bumps (UBumps, also known as microbumps).

[0206] In another possibility, for two chips connected face to face or for two chips connected back to back or for two chips connected back to face, both bonding surfaces (positions where conductive vias are aligned along the third direction) are connected through a hybrid bonding structure.

[0207] In another possibility, for two chips connected face to face or for two chips connected back to back or for back to face connection, both bonding surfaces (where the conductive vias are aligned along the third direction) are connected via conductive bumps.

[0208] Here, the above chip may refer to a logic chip 70 or a memory chip 10 .

[0209] It should be noted that, compared to the conductive bump process, the face-to-face connection using the hybrid bonding process can make adjacent memory chips fit more closely together, with essentially no gaps, thereby significantly reducing the height of the chip stacking structure. This is also one of the advantages of face-to-face stacking. Of course, two memory chips connected back to back can also be connected using a hybrid bonding structure, but its connection performance is weaker than when connected using the conductive bump process. Thus, in the embodiment of the present disclosure, the chip stacking structure 90 supports face-to-face stacking and has better performance.

[0210] As previously mentioned, logic chip 70 or each memory chip can be divided into a high-order transmission region and a low-order transmission region. Arrows for each chip in subsequent figures are uniformly positioned within the high-order transmission region of the chip. In particular, the high-order transmission region and the low-order transmission region in the disclosed embodiments merely distinguish two regions of the memory chip and do not impose any additional limitations. They have no relation to the high-order data and low-order data commonly used in data transmission.

[0211] When the logic chip 30 and the first memory chip 11 are stacked back-to-back and the logic chip 30 is placed in the same manner as the fourth memory chip 14, a first specific implementation method and a second specific embodiment method are provided; when the logic chip 30 and the first memory chip 11 are stacked back-to-back and the logic chip 30 is placed in the same manner as the second memory chip 12, a third specific implementation method and a fourth specific embodiment method are provided, as described in detail below.

[0212] In a first specific embodiment, as shown in FIG17A , assuming that the first axis AA' of the logic chip 70 and each memory chip divides the corresponding chip into a high-order transmission area and a low-order transmission area (i.e., the first axis AA' extends along the first direction), the high-order transmission area of ​​the logic chip 70, the high-order transmission area of ​​the first memory chip 11, the low-order transmission area of ​​the second memory chip 12, the low-order transmission area of ​​the third memory chip 13, and the high-order transmission area of ​​the fourth memory chip 14 are aligned along the third direction; the low-order transmission area of ​​the logic chip 70, the low-order transmission area of ​​the first memory chip 11, the high-order transmission area of ​​the second memory chip 12, the high-order transmission area of ​​the third memory chip 13, and the low-order transmission area of ​​the fourth memory chip 14 are aligned along the third direction.

[0213] At this time, according to the aforementioned classification rules: the top surfaces of the memory chips in the first and third positions are facing upward along the third direction, and the top surfaces of the memory chips in the second and fourth positions are facing downward along the third direction; the active surface of each memory chip is divided into a low-order transmission area and a high-order transmission area, and the low-order transmission area in the memory chip in the first position, the high-order transmission area in the memory chip in the second position, the high-order transmission area in the memory chip in the third position, and the low-order transmission area in the memory chip in the fourth position are aligned along the third direction.

[0214] At this time, the first storage chip 11 is in the first position, the second storage chip 12 is in the second position, the third storage chip 13 is in the third position, and the fourth storage chip 14 is in the fourth position.

[0215] In a second specific embodiment, as shown in FIG18A , assuming that the second axis BB' of the logic chip 70 and each memory chip divides the corresponding chip into a high-order transmission area and a low-order transmission area (i.e., the second axis BB' extends along the first direction), the high-order transmission area of ​​the logic chip 70, the low-order transmission area of ​​the first memory chip 11, the low-order transmission area of ​​the second memory chip 12, the high-order transmission area of ​​the third memory chip 13, and the high-order transmission area of ​​the fourth memory chip 14 are aligned along the third direction; the low-order transmission area of ​​the logic chip 70, the high-order transmission area of ​​the first memory chip 11, the high-order transmission area of ​​the second memory chip 12, the low-order transmission area of ​​the third memory chip 13, and the low-order transmission area of ​​the fourth memory chip 14 are aligned along the third direction.

[0216] Similarly, the first storage chip 11 is a first type of position, the second storage chip 12 is a second type of position, the third storage chip 13 is a third type of position, and the fourth storage chip 14 is a fourth type of position.

[0217] Referring to FIG. 17B or FIG. 18B , for the first and second specific embodiments, each through hole has the following alignment relationship:

[0218] The fourth normal conductive via D3 in the i-th conductive via group in the logic chip 70, the first normal conductive via D0 in the i-th conductive via group in each first memory chip 11, the second normal conductive via D1 in the i-th conductive via group in each second memory chip 12, the third normal conductive via D2 in the i-th conductive via group in each third memory chip 13, and the fourth normal conductive via D3 in the i-th conductive via group in each fourth memory chip 14 are aligned along the third direction and constitute a normal signal transmission channel, assuming that it is used to transmit Signal A;

[0219] The third normal conductive via D2 in the i-th conductive via group in the logic chip 70, the second normal conductive via D1 in the i-th conductive via group in each first memory chip 11, the first normal conductive via D0 in the i-th conductive via group in each second memory chip 12, the fourth normal conductive via D3 in the i-th conductive via group in each third memory chip 13, and the third normal conductive via D2 in the i-th conductive via group in each fourth memory chip 14 are aligned along the third direction and constitute a normal signal transmission channel, assuming that it is used to transmit Signal B.

[0220] The second normal conductive via D1 in the i-th conductive via group in the logic chip 70, the third normal conductive via D2 in the i-th conductive via group in each first memory chip 11, the fourth normal conductive via D3 in the i-th conductive via group in each second memory chip 12, the first normal conductive via D0 in the i-th conductive via group in each third memory chip 13, and the second normal conductive via D1 in the i-th conductive via group in each fourth memory chip 14 are aligned along a third direction and constitute a normal signal transmission channel; assuming that it is used to transmit Signal C;

[0221] The first normal conductive through-hole D0 in the i-th conductive through-hole group in the logic chip 70, the fourth normal conductive through-hole D3 in the i-th conductive through-hole group in each first storage chip 11, the third normal conductive through-hole D2 in the i-th conductive through-hole group in each second storage chip 12, the second normal conductive through-hole D1 in the i-th conductive through-hole group in each third storage chip 13, and the first normal conductive through-hole D0 in the i-th conductive through-hole group in each fourth storage chip 14 are aligned along the third direction and constitute a normal signal transmission channel, which is assumed to be used for transmitting Signal D.

[0222] For the chip stacking structure of Figures 17A / B, its signal transmission schematic is shown in Figure 19. In the chip stacking structure of Figures 18A / B, only the connection relationship between the internal ports and conductive vias in the logic chip 70 is different. That is, whether in Figures 17A / B or 18A / B, the correspondence between the four internal ports, conductive vias, and specific signals in each chip can be found in Table 3 below. Although the first to fourth memory chips 11 to 14 are arranged in different ways, the first internal port In0 of each chip receives the same signal SignalA, the second internal port In1 of each chip receives the same signal SignalB, the third internal port In2 of each chip receives the same signal SignalC, and the fourth internal port In3 of each chip receives the same signal SignalD. In particular, in Figure 19, the internal ports / signal ports and the corresponding conductive vias are coupled rather than directly electrically connected. For example, the first internal port In0 of the first memory chip 11 is coupled to the first conductive via D0, and the rest are similar.

[0223] Table 3

[0224] 17B or 18B , the fourth redundant conductive via R3 in the i-th conductive via group in the logic chip 70, the first redundant conductive via R0 in the i-th conductive via group in each first memory chip 11, the second redundant conductive via R1 in the i-th conductive via group in each second memory chip 12, the third redundant conductive via R2 in the i-th conductive via group in each third memory chip 13, and the fourth redundant conductive via R3 in the i-th conductive via group in each fourth memory chip 14 are aligned along the third direction and constitute a redundant signal transmission channel.

[0225] The third redundant conductive via R2 in the i-th conductive via group in the logic chip 70, the second redundant conductive via R1 in the i-th conductive via group in each first memory chip 11, the first redundant conductive via R0 in the i-th conductive via group in each second memory chip 12, the fourth redundant conductive via R3 in the i-th conductive via group in each third memory chip 13, and the third redundant conductive via R2 in the i-th conductive via group in each fourth memory chip 14 are aligned along the third direction and constitute a redundant signal transmission channel;

[0226] The second redundant conductive via R1 in the i-th conductive via group in the logic chip 70, the third redundant conductive via R2 in the i-th conductive via group in each first memory chip 11, the fourth redundant conductive via R3 in the i-th conductive via group in each second memory chip 12, the first redundant conductive via R0 in the i-th conductive via group in each third memory chip 13, and the second redundant conductive via R1 in the i-th conductive via group in each fourth memory chip 14 are aligned along the third direction and constitute a redundant signal transmission channel;

[0227] The first redundant conductive via R0 in the i-th conductive via group in the logic chip 70, the fourth redundant conductive via R3 in the i-th conductive via group in each first memory chip 11, the third redundant conductive via R2 in the i-th conductive via group in each second memory chip 12, the second redundant conductive via R1 in the i-th conductive via group in each third memory chip 13, and the first redundant conductive via R0 in the i-th conductive via group in each fourth memory chip 14 are aligned along the third direction and constitute a redundant signal transmission channel.

[0228] It should be noted that when the normal signal transmission channel of each chip fails, the redundant signal transmission channel will be enabled to work instead of the normal signal transmission channel. Taking the chip stacking structure provided in FIG. 17A / B as an example, refer to FIG. 20A and FIG. 20B . Assume that the normal signal transmission channel (assuming it is originally used to transmit Signal A) formed by D3 in the logic chip 70, D0 in the first memory chip 12, D1 in the second memory chip 11, D2 in the third memory chip 13, and D3 in the fourth memory chip 14 fails (for example, any conductive through-hole or junction therein is damaged). Then, R3 in the logic chip 70 replaces D3, R0 in the first memory chip 12 replaces D0, R1 in the second memory chip 11 replaces D1, R2 in the third memory chip 13 replaces D2, and R3 in the fourth memory chip 14 replaces D3. At this time, the redundant signal transmission channel formed by R3 in the logic chip 70, R0 in the first memory chip 12, R1 in the second memory chip 11, R2 in the third memory chip 13, and R3 in the fourth memory chip 14 will be used to transmit Signal A. For other reasons, please refer to the working principles of the selection circuit 30 in the memory chip / the control circuit 80 in the logic chip.

[0229] In a third specific embodiment, as shown in FIG21A , assuming that the logic chip 70 and each memory chip are each divided by their respective first axes AA' into a high-order transmission region and a low-order transmission region (i.e., the first axes AA' extend along the first direction), the low-order transmission region of the logic chip 70, the high-order transmission region of the first memory chip 11, the low-order transmission region of the second memory chip 12, the low-order transmission region of the third memory chip 13, and the high-order transmission region of the fourth memory chip 14 are aligned along a third direction; the high-order transmission region of the logic chip 70, the low-order transmission region of the first memory chip 11, the high-order transmission region of the second memory chip 12, the high-order transmission region of the third memory chip 13, and the low-order transmission region of the fourth memory chip 14 are aligned along the third direction. In this case, the first memory chip 11 is in the first position, the second memory chip 12 is in the fourth position, the third memory chip 13 is in the third position, and the fourth memory chip 14 is in the second position.

[0230] In a fourth specific embodiment, as shown in FIG22A , assuming that the second axis BB' of the logic chip 70 and each memory chip divides the respective chips into a high-order transmission region and a low-order transmission region (i.e., the second axis BB' extends along the first direction), the low-order transmission region of the logic chip 70, the low-order transmission region of the first memory chip 11, the low-order transmission region of the second memory chip 12, the high-order transmission region of the third memory chip 13, and the high-order transmission region of the fourth memory chip 14 are aligned along a third direction; the high-order transmission region of the logic chip 70, the high-order transmission region of the first memory chip 11, the high-order transmission region of the second memory chip 12, the low-order transmission region of the third memory chip 13, and the low-order transmission region of the fourth memory chip 14 are aligned along the third direction. In this case, the first memory chip 11 is in the first position, the second memory chip 12 is in the fourth position, the third memory chip 13 is in the third position, and the fourth memory chip 14 is in the second position.

[0231] Referring to FIG. 21B or FIG. 22B , for the third and fourth specific embodiments, each signal region has the following alignment relationship:

[0232] The second normal conductive via D1 in the i-th conductive via group in the logic chip 70, the first normal conductive via D0 in the i-th conductive via group in each first memory chip 11, the second normal conductive via D1 in the i-th conductive via group in each second memory chip 12, the third normal conductive via D2 in the i-th conductive via group in each third memory chip 13, and the fourth normal conductive via D3 in the i-th conductive via group in each fourth memory chip 14 are aligned along the third direction and constitute a normal signal transmission channel;

[0233] The first normal conductive via D0 in the i-th conductive via group in the logic chip 70, the second normal conductive via D1 in the i-th conductive via group in each first memory chip 11, the first normal conductive via D0 in the i-th conductive via group in each second memory chip 12, the fourth normal conductive via D3 in the i-th conductive via group in each third memory chip 13, and the third normal conductive via D2 in the i-th conductive via group in each fourth memory chip 14 are aligned along the third direction and constitute a normal signal transmission channel;

[0234] The fourth normal conductive via D3 in the i-th conductive via group in the logic chip 70, the third normal conductive via D2 in the i-th conductive via group in each first memory chip 11, the fourth normal conductive via D3 in the i-th conductive via group in each second memory chip 12, the first normal conductive via D0 in the i-th conductive via group in each third memory chip 13, and the second normal conductive via D1 in the i-th conductive via group in each fourth memory chip 14 are aligned along the third direction and constitute a normal signal transmission channel;

[0235] The third normal conductive through-hole D2 in the i-th conductive through-hole group in the logic chip 70, the fourth normal conductive through-hole D3 in the i-th conductive through-hole group in each first storage chip 11, the third normal conductive through-hole D2 in the i-th conductive through-hole group in each second storage chip 12, the second normal conductive through-hole D1 in the i-th conductive through-hole group in each third storage chip 13, and the first normal conductive through-hole D0 in the i-th conductive through-hole group in each fourth storage chip 14 are aligned along the third direction and constitute a normal signal transmission channel.

[0236] Similarly, the first memory chip 11 is in the first type of position, the second memory chip 12 is in the second type of position, the memory chip 13 is in the third type of position, and the memory chip 14 is in the fourth type of position, so the same internal ports all receive the same signal.

[0237] Meanwhile, referring to FIG. 21B and FIG. 22B , the alignment relationship of the redundant conductive vias is as follows:

[0238] The second redundant conductive via R1 in the i-th conductive via group in the logic chip 70, the first redundant conductive via R0 in the i-th conductive via group in each first memory chip 11, the second redundant conductive via R1 in the i-th conductive via group in each second memory chip 12, the third redundant conductive via R2 in the i-th conductive via group in each third memory chip 13, and the fourth redundant conductive via R3 in the i-th conductive via group in each fourth memory chip 14 are aligned along the third direction and constitute a redundant signal transmission channel;

[0239] The first redundant conductive via R0 in the i-th conductive via group in the logic chip 70, the second redundant conductive via R1 in the i-th conductive via group in each first memory chip 11, the first redundant conductive via R0 in the i-th conductive via group in each second memory chip 12, the fourth redundant conductive via R3 in the i-th conductive via group in each third memory chip 13, and the third redundant conductive via R2 in the i-th conductive via group in each fourth memory chip 14 are aligned along the third direction and constitute a redundant signal transmission channel;

[0240] The fourth redundant conductive via R3 in the i-th conductive via group in the logic chip 70, the third redundant conductive via R2 in the i-th conductive via group in each first memory chip 11, the fourth redundant conductive via R3 in the i-th conductive via group in each second memory chip 12, the first redundant conductive via R0 in the i-th conductive via group in each third memory chip 13, and the second redundant conductive via R1 in the i-th conductive via group in each fourth memory chip 14 are aligned along the third direction and constitute a redundant signal transmission channel;

[0241] The third redundant conductive via R2 in the i-th conductive via group in the logic chip 70, the fourth redundant conductive via R3 in the i-th conductive via group in each first memory chip 11, the third redundant conductive via R2 in the i-th conductive via group in each second memory chip 12, the second redundant conductive via R1 in the i-th conductive via group in each third memory chip 13, and the first redundant conductive via R0 in the i-th conductive via group in each fourth memory chip 14 are aligned along the third direction and constitute a redundant signal transmission channel.

[0242] At the same time, for repairs when the normal signal transmission channel fails, please refer to the above content.

[0243] Regardless of FIG. 21A / B or FIG. 22A / B , the correspondence between the four internal ports, conductive vias, and specific signals in each chip can be found in Table 4 below.

[0244] Table 4

[0245] At the same time, it can be seen from Figures 17A to 22B that for the chip stacking structure 90, the bottom-up signal transmission path will be similar to the following form: the fourth conductive through hole D3 in the logic chip 70 - the first conductive through hole D0 in the first memory chip 11 - the second conductive through hole D1 in the second memory chip 12 - the third conductive through hole D2 in the third memory chip 13 - the fourth conductive through hole D3 in the fourth memory chip 14..." for transmission. That is to say, for the chip stacking structure 90, from a physical point of view, the conductive through holes therein are still directly connected, but from the perspective of the conductive through holes in the active In terms of absolute position on the surface, the conductive vias therein can be considered as a functional rotational configuration, that is, a signal transmission effect similar to that of Figure 2 is achieved through a physical direct connection configuration (i.e., a rotational transmission effect such as conductive via D0-conductive via D1-conductive via D2-conductive via D3...). Simply put, the chip stacking structure 90 in Figure 2B requires a physical spiral structure, which necessarily has a horizontal interconnection structure. However, the chip stacking structure 90 in the embodiment of the present disclosure is physically a direct connection structure, which does not require a horizontal interconnection structure, greatly reducing parasitic resistance and significantly improving transmission speed and transmission performance.

[0246] In another embodiment of the present disclosure, referring to Figure 23, a schematic diagram of the composition structure of a memory 100 provided by an embodiment of the present disclosure is shown. As shown in Figure 23, the memory 100 includes the chip stacking structure 90 of the aforementioned embodiment.

[0247] In some embodiments, the memory 100 may be a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc., and no specific limitation is given here.

[0248] In the embodiment of the present disclosure, for the memory 100, the chip area can be reduced and the chip manufacturing cost can be reduced.

[0249] Details not disclosed in the embodiments of the present disclosure may be understood by referring to the description of the aforementioned embodiments.

[0250] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure.

[0251] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0252] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0253] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0254] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0255] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0256] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory chip (10), wherein the center point of an active surface of the memory chip (10) and an adjacent area thereof are defined as a global signal area (20), and the center point of the global signal area (20) coincides with the center point of the active surface; the global signal area (20) has a first axis and a second axis, the first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface, the first axis is parallel to a first side of the memory chip (10), and the second axis is parallel to a second side of the memory chip (10); The global signal area (20) is penetrated by n conductive through-hole groups along a third direction, the third direction is perpendicular to the active surface, and n is a positive integer; Each of the conductive through-hole groups includes four normal conductive through-holes, and the first normal conductive through-hole (D0) and the second normal conductive through-hole (D1) are symmetrical about the first axis, the third normal conductive through-hole (D2) and the fourth normal conductive through-hole (D3) are symmetrical about the first axis, and the first normal conductive through-hole (D0) and the fourth normal conductive through-hole (D3) are symmetrical about the second axis; The internal circuit of the memory chip (10) comprises n internal port groups, and each internal port group comprises 4 internal ports; The memory chip (10) further comprises n selection circuits (30); the i-th selection circuit (30) is configured to receive and, based on a selection signal, electrically connect four normal conductive vias in the i-th conductive via group to four internal ports in the i-th internal port group in a one-to-one correspondence; wherein: The corresponding relationship between the four normal conductive through holes and the four internal ports is determined based on the selection signal, and i is a positive integer less than or equal to n.

2. The memory chip (10) according to claim 1, wherein: The internal port group includes a first internal port (In0), a second internal port (In1), a third internal port (In2) and a fourth internal port (In3); The selection circuit (30) is specifically configured to electrically connect the first normal conductive via (D0), the second normal conductive via (D1), the third normal conductive via (D2), and the fourth normal conductive via (D3) to the first internal port (In0), the second internal port (In1), the third internal port (In2), and the i-th fourth internal port (In3) in a one-to-one correspondence if the selection signal is a first preset value; If the selection signal is a second preset value, the first normal conductive via (D0), the second normal conductive via (D1), the third normal conductive via (D2), and the fourth normal conductive via (D3) are electrically connected to the second internal port (In1), the first internal port (In0), the fourth internal port (In3), and the third internal port (In2) in a one-to-one correspondence; If the selection signal is a third preset value, the first normal conductive via (D0), the second normal conductive via (D1), the third normal conductive via (D2), and the fourth normal conductive via (D3) are connected to the The third internal port (In2), the fourth internal port (In3), the first internal port (In0), and the second internal port (In1) are electrically connected; If the selection signal meets the fourth preset value, the first normal conductive via (D0), the second normal conductive via (D1), the third normal conductive via (D2), and the fourth normal conductive via (D3) are electrically connected one by one to the fourth internal port (In3), the third internal port (In2), the second internal port (In1), and the first internal port (In0).

3. The memory chip (10) according to claim 2, wherein: Every four of the memory chips (10) are stacked along a third direction to form a stacking unit, and the chip position identification code of each of the memory chips (10) indicates the position of the memory chip (10) in the corresponding stacking unit; The memory chip (10) further comprises: A decoding circuit (21) is configured to receive the chip position identification code, and if the chip position identification code indicates that the memory chip (10) is in a first type of position, output the selection signal of a first preset value; if the chip position identification signal group indicates that the memory chip (10) is in a second type of position, output the selection signal of a second preset value; if the chip position identification signal group indicates that the memory chip (10) is in a third type of position, output the selection signal of a third preset value; if the chip position identification signal group indicates that the memory chip (10) is in a fourth type of position, output the selection signal that conforms to a fourth preset value; The top surface of the memory chip (10) in the first and third positions faces upward along the third direction, and the top surface of the memory chip (10) in the second and fourth positions faces downward along the third direction; the active surface of each memory chip (10) is divided into a low-order transmission area and a high-order transmission area, and the low-order transmission area in the memory chip (10) in the first position, the high-order transmission area in the memory chip (10) in the second position, the high-order transmission area in the memory chip (10) in the third position, and the low-order transmission area in the memory chip (10) in the fourth position are aligned along the third direction.

4. The memory chip (10) according to claim 2 or 3, wherein: Each of the conductive via groups further comprises a first redundant conductive via (R0), a second redundant conductive via (R1), a third redundant conductive via (R2) and a fourth redundant conductive via (R3); a first redundant conductive via (R0) and a second redundant conductive via (R1) are symmetrical about a first axis, a third redundant conductive via (R2) and a fourth redundant conductive via (R3) are symmetrical about the first axis, a first redundant conductive via (R0) and a fourth redundant conductive via (R3) are symmetrical about the second axis; a is a positive integer; For each of the conductive via groups, a of the first redundant conductive vias (R0), a of the second redundant conductive vias (R1), the first normal conductive via (D0) and the second normal conductive via (D1) constitute a repair unit, a of the third redundant conductive vias (R2), a of the fourth redundant conductive vias (R3), the first The three normal conductive vias (D2) and the fourth normal conductive via (D3) constitute another repair unit; The selection circuit (30) is further configured to, when any of the normal conductive vias fails, use other conductive vias of the same repair unit to replace the failed normal conductive via and electrically connect to the corresponding internal port.

5. The memory chip (10) according to claim 4, wherein: When a=1, The selection circuit (30) is specifically configured to use the first redundant conductive via (R0) or the fourth normal conductive via (D3) to replace the first normal conductive via (D0) to electrically connect to the corresponding internal port if the first normal conductive via (D0) fails; If the fourth normal conductive via (D3) fails, the fourth redundant conductive via (R3) or the first normal conductive via (D0) is used to replace the fourth normal conductive via (D3) to be electrically connected to the corresponding internal port; If the second normal conductive via (D1) fails, the second redundant conductive via (R1) or the third normal conductive via (D2) is used to replace the second normal conductive via (D1) to be electrically connected to the corresponding internal port; If the third normal conductive via (D2) fails, the third redundant conductive via (R2) or the second normal conductive via (D1) is used to replace the third normal conductive via (D2) to be electrically connected to the corresponding internal port.

6. The memory chip (10) according to claim 5, wherein: The selection signal includes a first selection signal and a second selection signal; the i-th selection circuit (30) includes an i-th first selection circuit (31), an i-th second selection circuit (32), an i-th first signal output circuit (33) and an i-th second signal output circuit (34); For the i-th first selection circuit (31), one side of the first selection circuit (31) is coupled to the first normal conductive via (D0), the fourth normal conductive via (D3), the first redundant conductive via (R0) and the fourth redundant conductive via (R3) in the i-th conductive via group, and the other side of the first selection circuit (31) is coupled to the i-th first secondary node and the i-th fourth secondary node; the first selection circuit (31) is configured to receive and, based on the i-th first via state parameter group and the first selection signal, electrically connect one of the coupled conductive vias to the i-th first secondary node, and electrically connect the other coupled conductive via to the i-th fourth secondary node; For the i-th second selection circuit (32), one side of the second selection circuit (32) is coupled to the second normal conductive via (D1), the third normal conductive via (D2), the second redundant conductive via (R1) and the third redundant conductive via (R2) in the i-th conductive via group, and the other side of the second selection circuit (32) is coupled to the i-th second secondary node and the i-th third secondary node; the second selection circuit (32) is configured to receive and, based on the i-th second via state parameter group and the first selection signal, electrically connect one of the coupled conductive vias to the i-th second secondary node, and electrically connect the other coupled conductive via to the i-th third secondary node; The i-th first signal output circuit (33) is configured to receive and, based on the second selection signal, electrically connect the i-th first secondary node to the i-th first internal port (In0), and electrically connect the i-th fourth secondary node to the i-th fourth internal port (In3); or, electrically connect the i-th second secondary node to the i-th The first internal port (In0) is electrically connected, and the i-th third secondary node is electrically connected to the i-th fourth internal port (In3); The i-th second signal output circuit (34) is configured to receive and, based on the second selection signal, electrically connect the i-th second secondary node to the i-th second internal port (In1), and electrically connect the i-th third secondary node to the i-th third internal port (In2); or, electrically connect the i-th first secondary node to the i-th second internal port (In1), and electrically connect the i-th fourth secondary node to the i-th third internal port (In2).

7. The memory chip (10) according to claim 6, wherein: The i-th first selection circuit (31) comprises an i-th first repair circuit (311), an i-th second repair circuit (312) and an i-th first selection output circuit (313); For the i-th first repair circuit (311), one side of the first repair circuit (311) is respectively coupled to the first redundant conductive via (R0), the first normal conductive via (D0) and the fourth normal conductive via (D3) in the i-th conductive via group, and the other side of the first repair circuit (311) is coupled to the i-th first primary node; the first repair circuit (311) is configured to receive and electrically connect one of the coupled conductive vias to the i-th first primary node based on the i-th first via state parameter group; For the i-th second repair circuit (312), one side of the second repair circuit (312) is respectively coupled to the first normal conductive via (D0), the fourth normal conductive via (D3) and the fourth redundant conductive via (R3) in the i-th conductive via group, and the other side of the second repair circuit (312) is coupled to the i-th fourth primary node; the second repair circuit (312) is configured to receive and electrically connect one of the coupled conductive vias to the i-th fourth primary node based on the i-th first via state parameter group; The i-th first selection output circuit (313) is configured to receive and, based on the first selection signal, electrically connect the i-th first primary node with the i-th first secondary node, and electrically connect the i-th fourth primary node with the i-th fourth secondary node; Alternatively, the i-th first primary node is electrically connected to the i-th fourth secondary node, and the i-th fourth primary node is electrically connected to the i-th first secondary node.

8. The memory chip (10) according to claim 7, wherein: The i-th first through-hole state parameter group includes a first state parameter, a second state parameter, a third state parameter and a fourth state parameter, and indicates one by one whether the first redundant conductive through-hole (R0), the first normal conductive through-hole (D0), the fourth normal conductive through-hole (D3) and the fourth redundant conductive through-hole (R3) in the i-th conductive through-hole group are failed; The i-th first repair circuit (311) comprises a first switching unit (412), a second switching unit (422), a third switching unit (432), a first logic unit (411), a second logic unit (421) and a third logic unit (431); The first logic unit (411) is configured to output a first control signal of an enabled state only when the i-th first through-hole state parameter group meets a first preset condition; wherein the first preset condition refers to that the first state parameter is in an enabled state and the second state parameter is in a disabled state, or that the first state parameter and the second state parameter are both in an enabled state and the third state parameter and the fourth state parameter are both in a disabled state; The first switching unit (412) is configured to control the i-th first redundant conductive via (R0) to be electrically connected to the i-th first primary node only when the first control signal is in an enabled state; The second logic unit (421) is configured to output a second control signal of an enabled state only when the i-th first through-hole state parameter group meets a second preset condition; wherein the second preset condition refers to that the second state parameter is in an enabled state, and at least one of the third state parameter and the fourth state parameter is in an enabled state; The second switching unit (422) is configured to control the i-th first normal conductive via (D0) to be electrically connected to the i-th first primary node only when the second control signal is in an enabled state; The third logic unit (431) is configured to output a third control signal of an enabled state only when the i-th first through-hole state parameter group meets a third preset condition; wherein the third preset condition means that both the first state parameter and the second state parameter are in a disabled state, and the third state parameter is in an enabled state; The third switching unit (432) is configured to control the i-th fourth normal conductive via (D3) to be electrically connected to the i-th first primary node only when the third control signal is in an enabled state; When any state parameter is in an enabled state, it indicates that the corresponding conductive via is not failed; when any state parameter is in a disabled state, it indicates that the corresponding conductive via is failed.

9. The memory chip (10) according to claim 8, wherein: The i-th second repair circuit (312) comprises a fourth switching unit (442), a fifth switching unit (452), a sixth switching unit (462), a fourth logic unit (441), a fifth logic unit (451) and a sixth logic unit (461); The fourth logic unit (441) is configured to output a fourth control signal of an enabled state only when the i-th first through hole state parameter group meets a fourth preset condition; wherein the fourth preset condition refers to that the fourth state parameter is in an enabled state and the third state parameter is in a disabled state, or that the fourth state parameter and the third state parameter are both in an enabled state and the second state parameter and the first state parameter are both in a disabled state; The fourth switching unit (442) is configured to control the i-th fourth redundant conductive via (R3) to be electrically connected to the i-th fourth primary node only when the fourth control signal is in an enabled state; The fifth logic unit (451) is configured to output a fifth control signal of an enabled state only when the i-th group of the first through-hole state parameters meets a fifth preset condition; wherein the fifth preset condition refers to that the third state parameter is in an enabled state, and at least one of the second state parameter and the first state parameter is in an enabled state; The fifth switching unit (452) is configured to control the i-th fourth normal conductive via (D3) to be electrically connected to the i-th fourth primary node only when the fifth control signal is in an enabled state; The sixth logic unit (461) is configured to output a sixth control signal of an enabled state only when the i-th first through-hole state parameter group meets a sixth preset condition; wherein the sixth preset condition means that the fourth state parameter and the third state parameter are both in a disabled state, and the second state parameter is in an enabled state; The sixth switching unit (462) is configured to control the i-th first normal conductive via (D0) to be electrically connected to the i-th fourth primary node only when the sixth control signal is in an enabled state.

10. The memory chip (10) according to claim 9, wherein: When the enabling state is at a high level and the disabling state is at a low level, the first logic unit (411) includes a first NOT gate (501), a first AND gate (502) and a first OR gate (503); the second logic unit (421) includes a second AND gate (511) and a second OR gate (512); the third logic unit (431) includes a third NOT gate (521) and a third AND gate (522); the fourth logic unit (441) includes a fourth NOT gate (531), a fourth AND gate (532) and a fourth OR gate (533); the fifth logic unit (451) includes a fifth AND gate (541) and a fifth OR gate (542); the sixth logic unit (461) includes a sixth NOT gate (551) and a sixth AND gate (552); The input end of the first NOT gate (501) receives the second state parameter, the output end of the first NOT gate (501) is connected to an input end of the first AND gate (502), the other input end of the first AND gate (502) receives the first state parameter, the output end of the first AND gate (502) and the output end of the sixth AND gate (552) are respectively connected to two input ends of the first OR gate (503), and the first OR gate (503) outputs the first control signal; Two input ends of the second OR gate (512) receive the third state parameter and the fourth state parameter respectively, an output end of the second OR gate (512) is connected to an input end of the second AND gate (511), another input end of the second AND gate (511) receives the second state parameter, and the second AND gate (511) outputs the second control signal; The input end of the third NOT gate (521) is connected to the output end of the fifth OR gate (542), the output end of the third NOT gate (521) is connected to an input end of the third AND gate (522), the other input end of the third AND gate (522) receives the third state parameter, and the third AND gate (522) outputs the third control signal; The input end of the fourth NOT gate (531) receives the third state parameter, the output end of the fourth NOT gate (531) is connected to one input end of the fourth AND gate (532), the other input end of the fourth AND gate (532) receives the fourth state parameter, the output end of the fourth AND gate (532) and the output end of the third AND gate (522) are respectively connected to two input ends of the fourth OR gate (533), and the fourth OR gate (533) outputs the fourth control signal; Two input ends of the fifth OR gate (542) receive the first state parameter and the second state parameter respectively, an output end of the fifth OR gate (542) is connected to an input end of the fifth AND gate (541), another input end of the fifth AND gate (541) receives the third state parameter, and the fifth AND gate (541) outputs the fifth control signal; The input end of the sixth NOT gate (551) is connected to the output end of the second OR gate (512), the output end of the sixth NOT gate (551) is connected to an input end of the sixth AND gate (552), the other input end of the sixth AND gate (552) receives the second state parameter, and the sixth AND gate (552) outputs the sixth control signal.

11. The memory chip (10) according to claim 6, wherein: The i-th second selection circuit (32) comprises an i-th third repair unit (321), an i-th fourth repair unit (322), and an i-th second selection output circuit (323); For the i-th third repair unit (321), one side thereof is respectively coupled to the second redundant conductive via (R1), the first normal conductive via (D0) and the second normal conductive via (D1) in the i-th conductive via group, and the other side thereof is coupled to the i-th second primary node; the third repair unit (321) is configured to receive and electrically connect one of the coupled conductive vias to the i-th second primary node based on the i-th second via state parameter group; For the i-th fourth repair unit (322), one side thereof is respectively coupled to the second normal conductive via (D1), the normal conductive via and the third redundant conductive via (R2) in the i-th conductive via group, and the other side thereof is coupled to the i-th third primary node; the fourth repair unit (322) is configured to receive and electrically connect one of the coupled conductive vias to the i-th third primary node based on the i-th second via state parameter group; The i-th second selection output circuit (323) is configured to receive and, based on the first selection signal, electrically connect the i-th second primary node with the i-th second secondary node, and electrically connect the i-th third primary node with the i-th third secondary node; Alternatively, the i-th third primary node is electrically connected to the i-th second secondary node, and the i-th second primary node is electrically connected to the i-th third secondary node.

12. The memory chip (10) according to claim 11, wherein: The i-th group of state parameters of the second through-hole comprises a fifth state parameter, a sixth state parameter, a seventh state parameter and an eighth state parameter, and indicates one by one whether the second redundant conductive through-hole (R1), the second normal conductive through-hole (D1), the third normal conductive through-hole (D2) and the third redundant conductive through-hole (R2) in the i-th corresponding conductive through-hole group are failed; The i-th third repair unit (321) comprises a seventh switching unit (612), an eighth switching unit (622), a ninth switching unit (632), a seventh logic unit (611), an eighth logic unit (621) and a ninth logic unit (631); The seventh logic unit (611) is configured to output a seventh control signal of an enable state only when the i-th second through hole state parameter group meets a seventh preset condition; wherein the seventh preset condition means that the fifth state parameter is in an enable state and the sixth state parameter is in a disable state, or the fifth state parameter and the sixth state parameter are both in an enable state and the seventh state parameter and the eighth state parameter are both in a disable state; The seventh switching unit (612) is configured to control the i-th second redundant conductive via (R1) to be electrically connected to the i-th second primary node only when the seventh control signal is in an enabled state; The eighth logic unit (621) is configured to output an eighth control signal of an enabled state only when the i-th second through-hole state parameter group meets an eighth preset condition; wherein the eighth preset condition refers to that the sixth state parameter is in an enabled state, and at least one of the seventh state parameter and the eighth state parameter is in an enabled state; The eighth switching unit (622) is configured to control the i-th second normal conductive via (D1) to be electrically connected to the i-th second primary node only when the eighth control signal is in an enabled state; The ninth switching unit (632) is configured to output a ninth control signal of the enabling state only when the i-th second through hole state parameter group meets the ninth preset condition; wherein the ninth preset condition refers to the fifth state parameter and the The sixth state parameters are all in a disabled state, and the seventh state parameters are in an enabled state; The ninth switching unit (632) is configured to control the i-th third normal conductive via (D2) to be electrically connected to the i-th second primary node only when the ninth control signal is in an enabled state; When any state parameter is in an enabled state, it indicates that the corresponding conductive via is not failed; when any state parameter is in a disabled state, it indicates that the corresponding conductive via is failed.

13. The memory chip (10) according to claim 12, wherein: The i-th fourth repair unit (322) includes a tenth switching unit (642), an eleventh switching unit (652), a twelfth switching unit (662), a tenth logic unit (641), an eleventh logic unit (651) and a twelfth logic unit (661); The tenth logic unit (641) is configured to output a tenth control signal of an enabled state only when the i-th second through hole state parameter group meets a tenth preset condition; wherein the tenth preset condition refers to that the eighth state parameter is in an enabled state and the seventh state parameter is in a disabled state, or that the seventh state parameter and the eighth state parameter are both in an enabled state and the fifth state parameter and the sixth state parameter are both in a disabled state; The tenth switching unit (642) is configured to control the i-th third redundant conductive via (R2) to be electrically connected to the i-th third primary node only when the tenth control signal is in an enabled state; The eleventh logic unit (651) is configured to output an eleventh control signal of an enabling state only when the i-th group of the second through-hole state parameters meets an eleventh preset condition; wherein the eleventh preset condition refers to that the seventh state parameter is in an enabling state, and at least one of the sixth state parameter and the fifth state parameter is in an enabling state; The eleventh switching unit (652) is configured to control the i-th third normal conductive via (D2) to be electrically connected to the i-th third primary node only when the eleventh control signal is in an enabled state; The twelfth logic unit (661) is configured to output a twelfth control signal of an enabled state only when the i-th second through hole state parameter group meets a twelfth preset condition; wherein the twelfth preset condition means that the eighth state parameter and the seventh state parameter are both in a disabled state, and the sixth state parameter is in an enabled state; The twelfth switching unit (662) is configured to control the i-th second normal conductive via (D1) to be electrically connected to the i-th third primary node only when the twelfth control signal is in an enabled state.

14. The memory chip (10) according to claim 13, wherein: When the enabling state is at a high level and the disabling state is at a low level, the seventh logic unit (611) includes a seventh NOT gate (701), a seventh AND gate (702) and a seventh OR gate (703); the eighth logic unit (621) includes an eighth AND gate (711) and an eighth OR gate (712); the ninth logic unit (631) includes a ninth NOT gate (721) and a ninth AND gate (722); the tenth logic unit (641) includes a tenth NOT gate (731), a tenth AND gate (732) and a tenth OR gate (733); the eleventh logic unit (651) includes an eleventh AND gate (741) and an eleventh OR gate (742); the twelfth logic unit (661) includes a twelfth NOT gate (751) and a twelfth AND gate (752); The input end of the seventh NOT gate (701) receives the sixth state parameter, the output end of the seventh NOT gate (701) is connected to one input end of the seventh AND gate (702), the other input end of the seventh AND gate (702) receives the fifth state parameter, the output end of the seventh AND gate (702) and the output end of the twelfth AND gate (752) are respectively connected to two input ends of the seventh OR gate (703), and the seventh OR gate (703) outputs the seventh control signal; Two input ends of the eighth OR gate (712) receive the seventh state parameter and the eighth state parameter respectively, an output end of the eighth OR gate (712) is connected to an input end of the eighth AND gate (711), another input end of the eighth AND gate (711) receives the sixth state parameter, and the eighth AND gate (711) outputs the eighth control signal; The input end of the ninth NOT gate (721) is connected to the output end of the eleventh OR gate (742), the output end of the ninth NOT gate (721) is connected to an input end of the ninth AND gate (722), the other input end of the ninth AND gate (722) receives the seventh state parameter, and the ninth AND gate (722) outputs the ninth control signal; The input end of the tenth NOT gate (731) receives the seventh state parameter, the output end of the tenth NOT gate (731) is connected to one input end of the tenth AND gate (732), the other input end of the tenth AND gate (732) receives the sixth state parameter, the output end of the tenth AND gate (732) and the output end of the ninth AND gate (722) are respectively connected to two input ends of the tenth OR gate (733), and the tenth OR gate (733) outputs the tenth control signal; Two input ends of the eleventh OR gate (742) receive the fifth state parameter and the sixth state parameter respectively, an output end of the eleventh OR gate (742) is connected to an input end of the eleventh AND gate (741), another input end of the eleventh AND gate (741) receives the seventh state parameter, and the eleventh AND gate (741) outputs the eleventh control signal; The input end of the twelfth NOT gate (751) is connected to the output end of the eighth OR gate (712), the output end of the twelfth NOT gate (751) is connected to an input end of the twelfth AND gate (752), the other input end of the twelfth AND gate (752) receives the sixth state parameter, and the twelfth AND gate (752) outputs the twelfth control signal.

15. The memory chip (10) according to any one of claims 1 to 3 and 5 to 14, wherein: The conductive vias are prepared by any one or more of the following processes: via-first, via-middle, via-last, and back side via-last, and different conductive vias in the same memory chip (10) are electrically isolated from each other.

16. A logic chip (70), wherein the center point of the active surface of the logic chip (70) and its adjacent area are defined as a global signal area (20), and the center point of the global signal area (20) coincides with the center point of the active surface; the global signal area (20) has a first axis and a second axis, the first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface, the first axis is parallel to a first side of the logic chip (70), and the second axis is parallel to a second side of the logic chip (70); The global signal area (20) is penetrated by n conductive through-hole groups along a third direction, and the third direction is perpendicular to the Active surface, n is a positive integer; Each of the conductive through-hole groups includes four normal conductive through-holes, and the first normal conductive through-hole (D0) and the second normal conductive through-hole (D1) are symmetrical about the first axis, the third normal conductive through-hole (D2) and the fourth normal conductive through-hole (D3) are symmetrical about the first axis, and the first normal conductive through-hole (D0) and the fourth normal conductive through-hole (D3) are symmetrical about the second axis; The logic chip (70) further comprises n control circuits (80), and the internal circuit of the logic chip (70) comprises n first signal ports, n second signal ports, n third signal ports and n fourth signal ports; The i-th control circuit (80) is configured to electrically connect the first normal conductive via (D0), the second normal conductive via (D1), the third normal conductive via (D2), and the fourth normal conductive via (D3) in the i-th conductive via group to the i-th first signal port, the i-th second signal port, the i-th third signal port, and the i-th fourth signal port in a one-to-one correspondence.

17. The logic chip (70) according to claim 16, wherein: Each of the conductive via groups further comprises 4a redundant conductive vias, and a first redundant conductive via (R0) and a second redundant conductive via (R1) are symmetrical about a first axis, a third redundant conductive via (R2) and a fourth redundant conductive via (R3) are symmetrical about the first axis, and a first redundant conductive via (R0) and a fourth redundant conductive via (R3) are symmetrical about a second axis; a of the first redundant conductive vias (R0), a of the second redundant conductive vias (R1), the first normal conductive via (D0) and the second normal conductive via (D1) constitute a repair unit, and a of the third redundant conductive vias (R2), a of the fourth redundant conductive vias (R3), the third normal conductive via (D2) and the fourth normal conductive via (D3) constitute another repair unit; The i-th control circuit (80) is further configured to, when any of the normal conductive vias fails, utilize other conductive vias of the same repair unit to replace the failed normal conductive via and electrically connect to the corresponding signal port.

18. The logic chip (70) according to claim 17, wherein: When a=1, The control circuit (80) is specifically configured to use the first redundant conductive via (R0) or the fourth normal conductive via (D3) to replace the first normal conductive via (D0) to electrically connect to the corresponding signal port if the first normal conductive via (D0) fails; If the fourth normal conductive via (D3) fails, the fourth redundant conductive via (R3) or the first normal conductive via (D0) is used to replace the fourth normal conductive via (D3) to be electrically connected to the corresponding signal port; If the second normal conductive via (D1) fails, the second redundant conductive via (R1) or the third normal conductive via (D2) is used to replace the second normal conductive via (D1) to be electrically connected to the corresponding signal port; If the third normal conductive via (D2) fails, the third redundant conductive via (R2) or the The second normal conductive via (D1) replaces the third normal conductive via (D2) and is electrically connected to the corresponding signal port.

19. The logic chip (70) according to claim 18, wherein: The i-th control circuit (80) comprises an i-th first control circuit (81) and an i-th second control circuit (82); For the i-th first control circuit (81), one side of the first control circuit (81) is coupled to the first normal conductive via (D0), the fourth normal conductive via (D3), the first redundant conductive via (R0) and the fourth redundant conductive via (R3) in the i-th conductive via group, and the other side of the first control circuit (81) is coupled to the i-th first signal port and the i-th fourth signal port; the i-th first control circuit (81) is configured to receive and, based on the i-th first via state parameter group, electrically connect one of the coupled conductive vias to the i-th first signal port, and electrically connect another coupled conductive via to the i-th fourth signal port; For the i-th second control circuit (82), one side thereof is coupled to the second normal conductive via (D1), the third normal conductive via (D2), the second redundant conductive via (R1) and the third redundant conductive via (R2) in the i-th conductive via group, and the other side thereof is coupled to the i-th second signal port and the i-th third signal port; the i-th second control circuit (82) is configured to receive and, based on the i-th second via state parameter group, electrically connect one of the coupled conductive vias to the i-th second signal port, and electrically connect the other coupled conductive via to the i-th third signal port.

20. The logic chip (70) according to claim 19, wherein: The i-th first control circuit (81) comprises an i-th first repair circuit (311) and an i-th second repair circuit (312); For the i-th first repair circuit (311), one side thereof is respectively coupled to the first redundant conductive via (R0), the first normal conductive via (D0) and the fourth normal conductive via (D3) in the i-th conductive via group, and the other side thereof is coupled to the i-th first signal port; the first repair circuit (311) is configured to receive and electrically connect one of the coupled conductive vias to the i-th first signal port based on the i-th first via state parameter group; For the i-th second repair circuit (312), one side thereof is respectively coupled to the first normal conductive via (D0), the fourth normal conductive via (D3) and the fourth redundant conductive via (R3) in the i-th conductive via group, and the other side thereof is coupled to the i-th four signal ports; the second repair circuit (312) is configured to receive and electrically connect one of the coupled conductive vias to the i-th fourth signal port based on the i-th first via state parameter group.

21. The logic chip (70) according to claim 20, wherein: The i-th first through-hole state parameter group includes a first state parameter, a second state parameter, a third state parameter and a fourth state parameter, which indicate whether the first redundant conductive through-hole (R0), the first normal conductive through-hole (D0), the fourth normal conductive through-hole (D3) and the fourth redundant conductive through-hole (R3) in the i-th conductive through-hole group are failed in a one-to-one correspondence; The i-th first repair circuit (311) includes a first switching unit (412), a second switching unit (422), three switching units (432), a first logic unit (411), a second logic unit (421) and a third logic unit (431); The first logic unit (411) is configured to output a first control signal of an enabled state only when the i-th first through-hole state parameter group meets a first preset condition; wherein the first preset condition refers to the first state parameter being in an enabled state and the second state parameter being in a disabled state, or the first state parameter and the second state parameter are both in an enabled state and the third state parameter and the fourth state parameter are both in a disabled state; The first switching unit (412) is configured to control the i-th first redundant conductive via (R0) to be electrically connected to the i-th first signal port only when the first control signal is in an enabled state; The second logic unit (421) is configured to output a second control signal of an enabled state only when the i-th first through-hole state parameter group meets a second preset condition; wherein the second preset condition refers to that the second state parameter is in an enabled state, and at least one of the third state parameter and the fourth state parameter is in an enabled state; The second switching unit (422) is configured to control the i-th first normal conductive through hole (D0) to be electrically connected to the i-th first signal port only when the second control signal is in an enabled state; The third logic unit (431) is configured to output a third control signal of an enabled state only when the i-th first through-hole state parameter group meets a third preset condition; wherein the third preset condition means that both the first state parameter and the second state parameter are in a disabled state, and the third state parameter is in an enabled state; The third switching unit (432) is configured to control the i-th fourth normal conductive via (D3) to be electrically connected to the i-th first signal port only when the third control signal is in an enabled state; When any state parameter is in an enabled state, it indicates that the corresponding conductive via is not failed; when any state parameter is in a disabled state, it indicates that the corresponding conductive via is failed.

22. The logic chip (70) according to claim 21, wherein: The i-th second repair circuit (312) comprises a fourth switching unit (442), a fifth switching unit (452), a sixth switching unit (462), a fourth logic unit (441), a fifth logic unit (451) and a sixth logic unit (461); The fourth logic unit (441) is configured to output a fourth control signal of an enabled state only when the i-th first through hole state parameter group meets a fourth preset condition; wherein the fourth preset condition refers to that the fourth state parameter is in an enabled state and the third state parameter is in a disabled state, or that the fourth state parameter and the third state parameter are both in an enabled state and the second state parameter and the first state parameter are both in a disabled state; The fourth switching unit (442) is configured to control the i-th fourth redundant conductive via (R3) to be electrically connected to the i-th fourth signal port only when the fourth control signal is in an enabled state; The fifth logic unit (451) is configured to output a fifth control signal of an enabled state only when the i-th group of the first through-hole state parameters meets a fifth preset condition; wherein the fifth preset condition refers to that the third state parameter is in an enabled state, and at least one of the second state parameter and the first state parameter is in an enabled state; The fifth switching unit (452) is configured to control the i-th fourth normal conductive via (D3) to be electrically connected to the i-th fourth signal port only when the fifth control signal is in an enabled state; The sixth switching unit (462) is configured to output a sixth control signal of an enabled state only when the i-th first through hole state parameter group meets a sixth preset condition; wherein the sixth preset condition means that the fourth state parameter and the third state parameter are both in a disabled state, and the second state parameter is in an enabled state; The sixth switching unit (462) is configured to control the i-th first normal conductive via (D0) to be electrically connected to the i-th fourth signal port only when the sixth control signal is in an enabled state.

23. The logic chip (70) according to claim 22, wherein: When the enabling state is at a high level and the disabling state is at a low level, the first logic unit (411) includes a first NOT gate (501), a first AND gate (502) and a first OR gate (503); the second logic unit (421) includes a second AND gate (511) and a second OR gate (512); the third logic unit (431) includes a third NOT gate (521) and a third AND gate (522); the fourth logic unit (441) includes a fourth NOT gate (531), a fourth AND gate (532) and a fourth OR gate (533); the fifth logic unit (451) includes a fifth AND gate (541) and a fifth OR gate (542); the sixth logic unit (461) includes a sixth NOT gate (551) and a sixth AND gate (552); The input end of the first NOT gate (501) receives the second state parameter, the output end of the first NOT gate (501) is connected to an input end of the first AND gate (502), the other input end of the first AND gate (502) receives the first state parameter, the output end of the first AND gate (502) and the output end of the sixth AND gate (552) are respectively connected to two input ends of the first OR gate (503), and the first OR gate (503) outputs the first control signal; Two input ends of the second OR gate (512) receive the third state parameter and the fourth state parameter respectively, an output end of the second OR gate (512) is connected to an input end of the second AND gate (511), another input end of the second AND gate (511) receives the second state parameter, and the second AND gate (511) outputs the second control signal; The input end of the third NOT gate (521) is connected to the output end of the fifth OR gate (542), the output end of the third NOT gate (521) is connected to an input end of the third AND gate (522), the other input end of the third AND gate (522) receives the third state parameter, and the third AND gate (522) outputs the third control signal; The input end of the fourth NOT gate (531) receives the third state parameter, the output end of the fourth NOT gate (531) is connected to one input end of the fourth AND gate (532), the other input end of the fourth AND gate (532) receives the fourth state parameter, the output end of the fourth AND gate (532) and the output end of the third AND gate (522) are respectively connected to two input ends of the fourth OR gate (533), and the fourth OR gate (533) outputs the fourth control signal; Two input ends of the fifth OR gate (542) receive the first state parameter and the second state parameter respectively, an output end of the fifth OR gate (542) is connected to an input end of the fifth AND gate (541), another input end of the fifth AND gate (541) receives the third state parameter, and the fifth AND gate (541) outputs the fifth control signal; The input end of the sixth NOT gate (551) is connected to the output end of the second OR gate (512), the output end of the sixth NOT gate (551) is connected to an input end of the sixth AND gate (552), the other input end of the sixth AND gate (552) receives the second state parameter, and the sixth AND gate (552) outputs the sixth control signal.

24. The logic chip (70) according to claim 19, wherein: The i-th second control circuit (82) comprises an i-th third repair unit (321) and an i-th fourth repair unit (322); For the i-th third repair unit (321), one side thereof is respectively coupled to the second redundant conductive via (R1), the first normal conductive via (D0) and the second normal first state parameter via in the i-th conductive via group, and the other side thereof is coupled to the i-th second signal port; the third repair unit (321) is configured to receive and electrically connect one of the coupled conductive vias to the i-th second signal port based on the second via state parameter group; For the i-th fourth repair unit (322), one side thereof is respectively coupled to the second normal conductive via (D1), the normal conductive via and the third redundant conductive via (R2) in the i-th conductive via group, and the other side thereof is coupled to the i-th third signal port; the fourth repair unit (322) is configured to receive and electrically connect one of the coupled conductive vias to the i-th third signal port based on the second via state parameter group.

25. The logic chip (70) according to claim 24, wherein: The i-th group of state parameters of the second through-hole comprises a fifth state parameter, a sixth state parameter, a seventh state parameter and an eighth state parameter, and is used to indicate, in a one-to-one correspondence, whether the second redundant conductive through-hole (R1), the second normal conductive through-hole (D1), the third normal conductive through-hole (D2) and the third redundant conductive through-hole (R2) in the i-th group of conductive through-holes are failed; The i-th third repair unit (321) comprises a seventh switching unit (612), an eighth switching unit (622), a ninth switching unit (632), a seventh logic unit (611), an eighth logic unit (621) and a ninth logic unit (631); The seventh logic unit (611) is configured to output a seventh control signal of an enable state only when the i-th second through hole state parameter group meets a seventh preset condition; wherein the seventh preset condition means that the fifth state parameter is in an enable state and the sixth state parameter is in a disable state, or the fifth state parameter and the sixth state parameter are both in an enable state and the seventh state parameter and the eighth state parameter are both in a disable state; The seventh switching unit (612) is configured to control the i-th second redundant conductive via (R1) to be electrically connected to the i-th second signal port only when the seventh control signal is in an enabled state; The eighth logic unit (621) is configured to output an eighth control signal of an enabled state only when the i-th second through-hole state parameter group meets an eighth preset condition; wherein the eighth preset condition refers to that the sixth state parameter is in an enabled state, and at least one of the seventh state parameter and the eighth state parameter is in an enabled state; The eighth switching unit (622) is configured to control the i-th second normal conductive through hole (D1) to be electrically connected to the i-th second signal port only when the eighth control signal is in an enabled state; The ninth logic unit (631) is configured to generate a logic signal only when the second through hole state parameter group meets the ninth preset condition. Under the condition, a ninth control signal of the enabled state is output; wherein the ninth preset condition means that the fifth state parameter and the sixth state parameter are both in the disabled state, and the seventh state parameter is in the enabled state; The ninth switching unit (632) is configured to control the third normal conductive via (D2) to be electrically connected to the i-th second signal port only when the ninth control signal is in an enabled state; When any state parameter is in an enabled state, it indicates that the corresponding conductive via is not failed; when any state parameter is in a disabled state, it indicates that the corresponding conductive via is failed.

26. The logic chip (70) according to claim 25, wherein: The fourth repair unit (322) includes a tenth switching unit (642), an eleventh switching unit (652), a twelfth switching unit (662), a tenth logic unit (641), an eleventh logic unit (651) and a twelfth logic unit (661); The tenth logic unit (641) is configured to output a tenth control signal of an enabled state only when the i-th second through hole state parameter group meets a tenth preset condition; wherein the tenth preset condition refers to when the eighth state parameter is in an enabled state and the seventh state parameter is in a disabled state, or when the eighth state parameter and the seventh state parameter are both in an enabled state and the sixth state parameter and the fifth state parameter are both in a disabled state; The tenth switching unit (642) is configured to control the i-th third redundant conductive via (R2) to be electrically connected to the i-th third signal port only when the tenth control signal is in an enabled state; The eleventh logic unit (651) is configured to output an eleventh control signal of an enabling state only when the i-th group of the second through-hole state parameters meets an eleventh preset condition; wherein the eleventh preset condition refers to that the seventh state parameter is in an enabling state, and at least one of the sixth state parameter and the fifth state parameter is in an enabling state; The eleventh switching unit (652) is configured to control the i-th third normal conductive via (D2) to be electrically connected to the i-th third signal port only when the eleventh control signal is in an enabled state; The twelfth logic unit (661) is configured to output a twelfth control signal of an enabled state only when the i-th second through hole state parameter group meets a twelfth preset condition; wherein the twelfth preset condition means that the eighth state parameter and the seventh state parameter are both in a disabled state, and the sixth state parameter is in an enabled state; The twelfth switching unit (662) is configured to control the i-th second normal conductive via (D1) to be electrically connected to the i-th third signal port only when the twelfth control signal is in an enabled state.

27. The logic chip (70) according to claim 26, wherein: When the enabling state is at a high level and the disabling state is at a low level, the seventh logic unit (611) includes a seventh NOT gate (701), a seventh AND gate (702) and a seventh OR gate (703); the eighth logic unit (621) includes an eighth AND gate (711) and an eighth OR gate (712); the ninth logic unit (631) includes a ninth NOT gate (721) and a ninth AND gate (722); the tenth logic unit (641) includes a tenth NOT gate (731), a tenth AND gate (732) and a tenth OR gate (733); the eleventh logic unit (651) includes an eleventh AND gate (741) and an eleventh OR gate (742); the twelfth logic unit (661) includes a twelfth NOT gate (751) and a twelfth AND gate (752); The input end of the seventh NOT gate (701) receives the sixth state parameter, the output end of the seventh NOT gate (701) is connected to one input end of the seventh AND gate (702), the other input end of the seventh AND gate (702) receives the fifth state parameter, the output end of the seventh AND gate (702) and the output end of the twelfth AND gate (752) are respectively connected to the two input ends of the seventh OR gate (703), and the seventh OR gate (703) outputs a seventh control signal; the two input ends of the eighth OR gate (712) respectively receive the seventh state parameter and the eighth state parameter, and the The output end of the eighth OR gate (712) is connected to an input end of the eighth AND gate (711), the other input end of the eighth AND gate (711) receives the sixth state parameter, and the eighth AND gate (711) outputs the eighth control signal; the input end of the ninth NOT gate (721) is connected to the output end of the eleventh OR gate (742), the output end of the ninth NOT gate (721) is connected to an input end of the ninth AND gate (722), the other input end of the ninth AND gate (722) receives the seventh state parameter, and the ninth AND gate (722) outputs the ninth control signal; The input end of the tenth NOT gate (731) receives the seventh state parameter, the output end of the tenth NOT gate (731) is connected to one input end of the tenth AND gate (732), the other input end of the tenth AND gate (732) receives the sixth state parameter, the output end of the tenth AND gate (732) and the output end of the ninth AND gate (722) are respectively connected to the two input ends of the tenth OR gate (733), and the tenth OR gate (733) outputs the tenth control signal; the two input ends of the eleventh OR gate (742) respectively receive the fifth state parameter and the sixth state parameter, and the eleventh OR gate (742) receives the sixth state parameter. The output end of the OR gate (742) is connected to an input end of the eleventh AND gate (741), the other input end of the eleventh AND gate (741) receives the seventh state parameter, and the eleventh AND gate (741) outputs the eleventh control signal; the input end of the twelfth NOT gate (751) is connected to the output end of the eighth OR gate (712), the output end of the twelfth NOT gate (751) is connected to an input end of the twelfth AND gate (752), the other input end of the twelfth AND gate (752) receives the sixth state parameter, and the twelfth AND gate (752) outputs the twelfth control signal.

28. A chip stacking structure (90), comprising a logic chip (70) as claimed in any one of claims 16 to 27 and at least one stacking unit, wherein the logic chip (70) and the at least one stacking unit are stacked in sequence along a third direction; each of the stacking units comprises a first memory chip (11), a second memory chip (12), a third memory chip (13) and a fourth memory chip (14) stacked in sequence along the third direction, wherein the third direction is perpendicular to a top surface of each of the memory chips (10); the first memory chip (11), the second memory chip (12), the third memory chip (13) and the fourth memory chip (14) are all memory chips (10) as claimed in any one of claims 1 to 15; The first memory chip (11) and the second memory chip (12) are stacked face to face, the second memory chip (12) and the third memory chip (13) are stacked back to back, and the third memory chip (13) and the fourth memory chip (14) are stacked face to face; The first memory chip (11) and the logic chip (70) in the first stacking unit are stacked in a back-to-back manner, or the first memory chip (11) and the logic chip (70) in the first stacking unit are stacked in a back-to-back manner.

29. The chip stacking structure (90) according to claim 28, wherein: The chip position identification code of the first storage chip (11) indicates a first type of position, the chip position identification code of the second storage chip (12) indicates a second type of position, the chip position identification code of the third storage chip (13) indicates a third type of position, and the chip position identification code of the fourth storage chip (14) indicates a fourth type of position; or, The chip position identification code of the first storage chip (11) indicates a first type of position, the chip position identification code of the second storage chip (12) indicates a fourth type of position, the chip position identification code of the third storage chip (13) indicates a third type of position, and the chip position identification code of the fourth storage chip (14) indicates a second type of position.

30. The chip stacking structure (90) according to claim 29, wherein: When the logic chip (70) and the first memory chip (11) are stacked in a back-to-back manner, The fourth normal conductive through hole (D3) in the i-th conductive through hole group in the logic chip (70), the first normal conductive through hole (D0) in the i-th conductive through hole group in each of the first memory chips (11), the second normal conductive through hole (D1) in the i-th conductive through hole group in each of the second memory chips (12), the third normal conductive through hole (D2) in the i-th conductive through hole group in each of the third memory chips (13), and the fourth normal conductive through hole (D3) in the i-th conductive through hole group in each of the fourth memory chips (14) are aligned along the third direction and form a normal signal transmission channel; The third normal conductive through hole (D2) in the i-th conductive through hole group in the logic chip (70), the second normal conductive through hole (D1) in the i-th conductive through hole group in each of the first memory chips (11), the first normal conductive through hole (D0) in the i-th conductive through hole group in each of the second memory chips (12), the fourth normal conductive through hole (D3) in the i-th conductive through hole group in each of the third memory chips (13), and the third normal conductive through hole (D2) in the i-th conductive through hole group in each of the fourth memory chips (14) are aligned along the third direction and form a normal signal transmission channel; The second normal conductive through hole (D1) in the i-th conductive through hole group in the logic chip (70), the third normal conductive through hole (D2) in the i-th conductive through hole group in each of the first memory chips (11), the fourth normal conductive through hole (D3) in the i-th conductive through hole group in each of the second memory chips (12), the first normal conductive through hole (D0) in the i-th conductive through hole group in each of the third memory chips (13), and the second normal conductive through hole (D1) in the i-th conductive through hole group in each of the fourth memory chips (14) are aligned along the third direction and form a normal signal transmission channel; The first normal conductive through hole (D0) in the i-th conductive through hole group in the logic chip (70), the fourth normal conductive through hole (D3) in the i-th conductive through hole group in each of the first memory chips (11), the third normal conductive through hole (D2) in the i-th conductive through hole group in each of the second memory chips (12), and the third normal conductive through hole (D3) in each of the third memory chips (13). The second normal conductive through hole (D1) in the i-th conductive through hole group and the first normal conductive through hole (D0) in the i-th conductive through hole group in each of the fourth memory chips (14) are aligned along the third direction and form a normal signal transmission channel; Here, i is a positive integer less than or equal to n.

31. The chip stacking structure (90) according to claim 30, wherein: The fourth redundant conductive through hole (R3) in the i-th conductive through hole group in the logic chip (70), the first redundant conductive through hole (R0) in the i-th conductive through hole group in each of the first memory chips (11), the second redundant conductive through hole (R1) in the i-th conductive through hole group in each of the second memory chips (12), the third redundant conductive through hole (R2) in the i-th conductive through hole group in each of the third memory chips (13), and the fourth redundant conductive through hole (R3) in the i-th conductive through hole group in each of the fourth memory chips (14) are aligned along the third direction and form a redundant signal transmission channel; The third redundant conductive through hole (R2) in the i-th conductive through hole group in the logic chip (70), the second redundant conductive through hole (R1) in the i-th conductive through hole group in each of the first memory chips (11), the first redundant conductive through hole (R0) in the i-th conductive through hole group in each of the second memory chips (12), the fourth redundant conductive through hole (R3) in the i-th conductive through hole group in each of the third memory chips (13), and the third redundant conductive through hole (R2) in the i-th conductive through hole group in each of the fourth memory chips (14) are aligned along the third direction and form a redundant signal transmission channel; The second redundant conductive via (R1) in the i-th conductive via group in the logic chip (70), the third redundant conductive via (R2) in the i-th conductive via group in each of the first memory chips (11), the fourth redundant conductive via (R3) in the i-th conductive via group in each of the second memory chips (12), the first redundant conductive via (R0) in the i-th conductive via group in each of the third memory chips (13), and the second redundant conductive via (R1) in the i-th conductive via group in each of the fourth memory chips (14) are aligned along the third direction and form a redundant signal transmission channel; The first redundant conductive through hole (R0) in the i-th conductive through hole group in the logic chip (70), the fourth redundant conductive through hole (R3) in the i-th conductive through hole group in each of the first memory chips (11), the third redundant conductive through hole (R2) in the i-th conductive through hole group in each of the second memory chips (12), the second redundant conductive through hole (R1) in the i-th conductive through hole group in each of the third memory chips (13), and the first redundant conductive through hole (R0) in the i-th conductive through hole group in each of the fourth memory chips (14) are aligned along the third direction and constitute a redundant signal transmission channel.

32. The chip stacking structure (90) according to claim 29, wherein: When the logic chip (70) and the first memory chip (11) are stacked in a back-to-back manner, The second normal conductive through hole (D1) in the i-th conductive through hole group in the logic chip (70), the first normal conductive through hole (D0) in the i-th conductive through hole group in each of the first memory chips (11), the second normal conductive through hole (D1) in the i-th conductive through hole group in each of the second memory chips (12), the third normal conductive through hole (D2) in the i-th conductive through hole group in each of the third memory chips (13), and the fourth normal conductive through hole (D3) in the i-th conductive through hole group in each of the fourth memory chips (14) are aligned along the third direction and form a normal signal transmission channel; The first normal conductive through hole (D0) in the i-th conductive through hole group in the logic chip (70), the second normal conductive through hole (D1) in the i-th conductive through hole group in each of the first memory chips (11), the first normal conductive through hole (D0) in the i-th conductive through hole group in each of the second memory chips (12), the fourth normal conductive through hole (D3) in the i-th conductive through hole group in each of the third memory chips (13), and the third normal conductive through hole (D2) in the i-th conductive through hole group in each of the fourth memory chips (14) are aligned along the third direction and form a normal signal transmission channel; The fourth normal conductive through hole (D3) in the i-th conductive through hole group in the logic chip (70), the third normal conductive through hole (D2) in the i-th conductive through hole group in each of the first memory chips (11), the fourth normal conductive through hole (D3) in the i-th conductive through hole group in each of the second memory chips (12), the first normal conductive through hole (D0) in the i-th conductive through hole group in each of the third memory chips (13), and the second normal conductive through hole (D1) in the i-th conductive through hole group in each of the fourth memory chips (14) are aligned along the third direction and form a normal signal transmission channel; The third normal conductive through hole (D2) in the i-th conductive through hole group in the logic chip (70), the fourth normal conductive through hole (D3) in the i-th conductive through hole group in each of the first memory chips (11), the third normal conductive through hole (D2) in the i-th conductive through hole group in each of the second memory chips (12), the second normal conductive through hole (D1) in the i-th conductive through hole group in each of the third memory chips (13), and the first normal conductive through hole (D0) in the i-th conductive through hole group in each of the fourth memory chips (14) are aligned along the third direction and constitute a normal signal transmission channel.

33. The chip stacking structure (90) according to claim 32, wherein: The second redundant conductive via (R1) in the i-th conductive via group in the logic chip (70), the first redundant conductive via (R0) in the i-th conductive via group in each of the first memory chips (11), the second redundant conductive via (R1) in the i-th conductive via group in each of the second memory chips (12), the third redundant conductive via (R2) in the i-th conductive via group in each of the third memory chips (13), and the fourth redundant conductive via (R3) in the i-th conductive via group in each of the fourth memory chips (14) are aligned along the third direction and form a redundant signal transmission channel; The first redundant conductive through hole (R0) in the i-th conductive through hole group in the logic chip (70), the second redundant conductive through hole (R1) in the i-th conductive through hole group in each of the first memory chips (11), the first redundant conductive through hole (R0) in the i-th conductive through hole group in each of the second memory chips (12), the fourth redundant conductive through hole (R3) in the i-th conductive through hole group in each of the third memory chips (13), and the third redundant conductive through hole (R2) in the i-th conductive through hole group in each of the fourth memory chips (14) are aligned along the third direction and form a redundant signal transmission channel; The fourth redundant conductive through hole (R3) in the i-th conductive through hole group in the logic chip (70), the third redundant conductive through hole (R2) in the i-th conductive through hole group in each of the first memory chips (11), the fourth redundant conductive through hole (R3) in the i-th conductive through hole group in each of the second memory chips (12), the first redundant conductive through hole (R0) in the i-th conductive through hole group in each of the third memory chips (13), and the second redundant conductive through hole (R1) in the i-th conductive through hole group in each of the fourth memory chips (14) are aligned along the third direction and form a redundant signal transmission channel; The third redundant conductive through hole (R2) in the i-th conductive through hole group in the logic chip (70), the fourth redundant conductive through hole (R3) in the i-th conductive through hole group in each of the first memory chips (11), the third redundant conductive through hole (R2) in the i-th conductive through hole group in each of the second memory chips (12), the second redundant conductive through hole (R1) in the i-th conductive through hole group in each of the third memory chips (13), and the first redundant conductive through hole (R0) in the i-th conductive through hole group in each of the fourth memory chips (14) are aligned along the third direction and form a redundant signal transmission channel.

34. The chip stacking structure (90) according to any one of claims 28 to 33, wherein: For two chips connected face to face, the positions where the conductive vias are aligned along the third direction are electrically connected by a hybrid bonding process; for two chips connected back to back or two chips connected back to face, the positions where the conductive vias are aligned along the third direction are electrically connected by a conductive bump bonding process; or, For two chips connected face to face or two chips connected back to back or two chips connected back to face, the positions of the conductive through holes aligned along the third direction in both chips are electrically connected by the hybrid bonding process; or, For two chips connected face to face or two chips connected back to back or two chips connected back to face, the positions of the conductive through holes aligned along the third direction in both chips are electrically connected through the conductive bump bonding process.

35. A memory (100), comprising the chip stacking structure (90) according to any one of claims 28 to 34.

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