Cache data replacement method and related device

Abstract

Disclosed in embodiments of the present application are a cache data replacement method and related device, used for determining a CL on which data replacement is preferentially performed. In the present application, during the operation of a second process, a second access request for second data, which is sent by a target application, is received; if none of CLs in a cache stores the second data, a plurality of CLs to be replaced in the cache are determined, wherein the plurality of CLs comprise a first CL; and if a first hint status information carried by the first CL among the plurality of CLs is a first hint id, and a hint status mapped by the first hint id in a second hint mapping table is eviction, first data in the first CL is replaced with the second data, and the second data is accessed from the first CL, the first data being data accessed by a first process, and the first process being a process before the second process in the target application.

Description

A cache data replacement method and related device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on December 8, 2023, with application number 202311685153.X and application name “A Cache Data Replacement Method and Related Devices”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of data storage, and in particular to a cache data replacement method and related equipment. Background Art

[0003] Cache is the memory within the central processing unit (CPU). When the CPU accesses a piece of data, it first checks whether the data is stored in the cache. If so, the CPU accesses the data directly from the cache. Otherwise, the CPU accesses the data from another storage module and stores it in the cache.

[0004] The smallest unit of data stored in a cache is a cache line (CL). This means the entire cache's storage capacity is divided into multiple CLs of equal size (e.g., 64 bytes). Each CL can be used as a whole for state maintenance and data loading. Due to the limited cache capacity, when new data is stored in the cache, there are often no free CLs left. In this case, a cache replacement algorithm must be used to select a CL, evict the data from it, and store the new data in that CL. This is called replacing the CL. In current cache replacement algorithms, each CL has a retention priority. When selecting a CL to be replaced by data, the CL with the lowest retention priority is chosen.

[0005] However, in many applications, execution occurs in multiple distinct phases, each accessing different data. With existing cache replacement algorithms, when one phase ends and the next begins, the CL containing frequently accessed data from the previous phase still has a higher retention priority, making it less likely to be selected for data replacement. This results in the CL containing the most frequently accessed data in the current phase being more likely to be selected for data replacement, resulting in performance degradation. Summary of the Invention

[0006] Embodiments of the present application provide a cache data replacement method and related devices for determining a CL for priority data replacement.

[0007] The first aspect of the present application provides a cache data replacement method. In the present application, before the second process runs, a second hint mapping table is received, the second hint mapping table includes a hint id and a mapped hint state, and the second process is the process of the target application. During the running of the second process, a second access request for the second data sent by the target application is received. If none of the CLs in the cache store the second data, multiple CLs to be replaced in the cache are determined, and the multiple CLs include a first CL. If the first hint state information carried by the first CL among the multiple CLs is a first hint id, and the hint state mapped by the first hint id in the second hint mapping table is eviction, the first data in the first CL is replaced by the second data, and the second data is accessed from the first CL. The first data is the data accessed by the first process, and the first process is the process before the second process in the target application.

[0008] In an embodiment of the present application, by writing a second hint mapping table during the second process, data replacement is performed preferentially on the first CL where the first data that does not need to be accessed in the second process is located, thereby overcoming the process change of the target application and the fact that the originally accessed data does not need to be accessed in the current process. These data can be evicted as soon as possible, thereby avoiding the situation where these data are retained for a long time, thereby improving performance.

[0009] In some possible implementations, before the first process runs, a first replacement configuration is received. The first replacement configuration includes a first address range and a first hint mapping table. The first hint mapping table includes the hint ID and the mapped hint state. In the first hint mapping table, the hint state mapped to the first hint ID is "collecting." During the execution of the first process, a first access request for the first data is received from the target application, and the first data is accessed from the first CL. If the address of the first data falls within the first address range, the first hint state information is set to the first hint ID. This allows the first CL containing the currently accessed first data to be marked, facilitating subsequent data replacement in the first CL.

[0010] In some possible implementations, while the first process is running, a request for access to the shared data sent by the target application is received, and the shared data is accessed from the shared CL. The shared data is data accessed by both the first process and the second process. If the address of the shared data does not fall within the first address range, the shared hint status information carried by the shared CL is set to unconfigured. This avoids marking the shared CL and distinguishes the first CL from the shared CL.

[0011] In some possible implementations, in the first hint mapping table, the hint status mapped to other hint IDs except the first hint ID is eviction, thereby achieving the goal of marking only the first CL at present.

[0012] In some possible implementations, the second hint mapping table is obtained by receiving a second replacement configuration, where the second replacement configuration includes the second hint mapping table, in which the hint status mapped to the first hint ID is eviction.

[0013] In some possible implementations, the second replacement configuration also includes a second address range, and the hint state mapped by the second hint id in the second hint mapping table is collecting. After accessing the second data from the first CL, if the address of the second data belongs to the second address range, the first hint state information carried by the first CL is set to the second hint id, thereby achieving the marking of the second CL while replacing the data of the first CL.

[0014] In some possible implementations, the hint status information is carried in the tag information of the CL.

[0015] A second aspect of the present application provides a processor, which is configured to execute any one of the methods described in the first aspect.

[0016] A third aspect of the present application provides a computer-readable storage medium, which stores instructions. When the computer-readable storage medium is run on a computer, it enables the computer to execute the method provided by the first aspect or any possible implementation of the first aspect.

[0017] A fourth aspect of the present application provides a computer program product, which includes computer-executable instructions, which are stored in a computer-readable storage medium; at least one processor of a device can read the computer-executable instructions from the computer-readable storage medium, and at least one processor executes the computer-executable instructions so that the device implements the method provided by the above-mentioned first aspect or any possible implementation of the first aspect.

[0018] In a fifth aspect, the present application provides a chip system, which includes a processor for supporting the implementation of the functions involved in the above-mentioned first aspect or any possible implementation method of the first aspect.

[0019] In a possible design, the chip system may further include a memory for storing necessary program instructions and data. The chip system may be composed of a chip or may include a chip and other discrete devices.

[0020] Among them, the technical effects brought about by the second to fifth aspects or any possible implementation methods thereof can refer to the technical effects brought about by the first aspect or different possible implementation methods of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG1-1 is a schematic diagram of the composition structure of a storage system provided in an embodiment of the present application;

[0022] Figures 1-2 are schematic diagrams of accessing data based on a storage system according to an embodiment of the present application;

[0023] FIG2-1 is a flow chart of a cache data replacement method provided in an embodiment of the present application;

[0024] FIG2-2 is another schematic diagram of accessing data based on a storage system according to an embodiment of the present application;

[0025] 2-3 is another schematic diagram of accessing data based on a storage system according to an embodiment of the present application;

[0026] Figures 2-4 are schematic diagrams of the address arrangement of data provided in embodiments of the present application;

[0027] Figures 2-5 are schematic diagrams of the sequential execution of multiple processes provided in the embodiments of the present application;

[0028] FIG3-1 is a flow chart of a cache data replacement method provided in an embodiment of the present application;

[0029] FIG3-2 is a schematic diagram of the address arrangement of data provided in an embodiment of the present application;

[0030] FIG3-3 is a schematic diagram of the sequential execution of multiple processes provided in an embodiment of the present application;

[0031] FIG4 is a schematic diagram of the structure of a processor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] Embodiments of the present application provide a cache data replacement method and related devices for determining a CL for priority data replacement.

[0033] The embodiments of the present application are described below with reference to the accompanying drawings.

[0034] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, and this is merely a way of distinguishing the objects of the same attributes when describing them in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0035] The present application can be applied to a storage system. Please refer to FIG1-1 , which is a schematic diagram of the structure of a storage system 100. As shown in FIG1-1 , the storage system 100 includes a cache 110 and a memory 120.

[0036] In some possible implementations, the storage system 100 may be applied to a server or a user device, etc., which is not limited here.

[0037] Among them, the server is a device that provides computing services and / or storage services. Since the server needs to respond to service requests and process them to provide reliable services, generally speaking, the server should have the ability to undertake and guarantee services. The server needs to have strong processing power, high stability, high reliability, high security, scalability and manageability. In the embodiment of the present application, the server can be an x86 server, which is also called a complex instruction set computer (CISC) architecture server, that is, a personal computer (PC) server commonly referred to. It is a server based on the PC architecture and uses an Intel (Intel) or other x86 instruction set compatible processor chip and a Windows operating system.

[0038] Among them, the user equipment can be a terminal, a mobile station (MS), a mobile terminal (MT), etc. Among them, the terminal can be a mobile phone, a tablet computer (Pad), a computer with wireless transceiver function, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, etc. The embodiments of this application do not limit the specific technology and specific device form adopted by the user equipment. The user equipment and the server can be directly or indirectly connected through wired or wireless communication, and this application does not limit this.

[0039] In the embodiments of the present application, cache 110 is part of the processor and can be considered its internal memory. Cache 110 is highly readable and writable at any time, and typically serves as a temporary data storage medium for the operating system or other running programs. While cache 110 improves the read and write speeds of storage system 100, it is expensive and has a relatively small capacity (typically tens of kilobytes (KB) to several megabytes (MB), far less than the capacity of RAM or a hard drive).

[0040] In some possible implementations, the processor may be a single-core processor or a multi-core processor, which is not limited here. In some possible implementations, the processor may be a general-purpose processor, such as a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor or a coprocessor, etc., which is not limited here. In some possible implementations, the processor may also be a special-purpose processor, such as a digital signal processor (DSP), a neural processing unit (NPU), an application-specific integrated circuit (ASIC) and a field programmable gate array (FPGA), etc., which are not limited here.

[0041] Memory 120 is a memory device outside the processor, used to temporarily store processor data and exchange data with other external memories. Memory 120 acts as a bridge between the hard drive and the processor, and all programs in the device run in memory 120. As soon as the device starts running, the operating system transfers data required for calculation from memory 120 to the processor for processing. The capacity of memory 120 is much larger than cache 110, and its data access speed is much faster than that of a hard drive. Solid-state drives (SSDs) are typically used as memory 120.

[0042] In the storage system 100, when accessing data, the system first checks whether the data exists in cache 110. If so, the data is directly accessed from cache 110. Otherwise, the data is retrieved from memory 120 and stored in cache 110. Based on this mechanism, as the storage system 110 operates, data can be gradually stored in cache 110, allowing faster access to the data and improving execution performance.

[0043] In some possible implementations, a multi-level caching mechanism exists between cache 110 and memory 120. Specifically, multiple levels of cache exist between cache 110 and memory 120. "Retrieving the data from memory 120" includes retrieving the data from any level of the multi-level cache. If the data is not stored in any level of cache between cache 110 and memory 120, the data is retrieved from memory 120.

[0044] The smallest unit of data stored in the cache is a cache lock (CL). This means the entire cache's storage capacity is divided into multiple CLs of equal size (e.g., 64 bytes). Each CL can be used as a whole for state maintenance and data loading. Due to the limited cache capacity, when new data is stored in the cache, there are often no free CLs left. In this case, a cache replacement algorithm is used to select a CL, evict the data from it, and store the new data in that CL. This is called data replacement for the CL. In the current cache replacement algorithm, each CL has a retention priority. When selecting a CL to be replaced by data, the CL with the lowest retention priority is chosen.

[0045] The design goal of a cache replacement algorithm is to try to identify or predict data that will not be frequently used in the future. Current mainstream cache replacement algorithms include: 1. First Input First Output (FIFO), which evicts the data written to the cache earliest; 2. Least Recently Used (LRU), which evicts the data that has not been accessed in the longest; 3. Least Frequently Used (LFU), which evicts the data accessed the least frequently; and 4. Re-Reference Interval Prediction (RRIP), which maintains a re-reference prediction value (RRPV) for each cache lock. The RRPV represents the predicted time interval when the cache lock will be accessed next. The cache lock with the largest RRPV is replaced first.

[0046] However, in many applications, execution occurs in multiple distinct phases, each accessing different data. In existing cache replacement algorithms, when one phase ends and the next begins, the CL containing frequently accessed data from the previous phase still has a higher retention priority, making it less likely to be selected for data replacement. This results in the CL containing the most frequently accessed data in the current phase being more likely to be selected for data replacement, resulting in performance degradation.

[0047] For example, the target application includes a first process and a second process. The first process is executed first, and after the first process is completed, the second process begins to execute. Among them, when the first process is running, it needs to access the first data and shared data, and when the second process is running, it needs to access the second data and shared data. Then, when the first process ends and the second process is running, since the first data is no longer accessed, the better cache replacement strategy should be to select the CL corresponding to the first data, thereby expelling the first data from the cache. However, the existing cache replacement algorithm cannot recognize changes in access habits. Then, when the first process is running, as the first data is accessed, the cache replacement algorithm will give a higher retention priority to the CL where the first data is located, making it less likely to be replaced. After the second process is running, the retention priority of the first data will still generally be higher than that of the shared data, resulting in some shared data being more easily replaced than the CL where the first data is located, which will lead to cache failure when these shared data are subsequently accessed, causing performance degradation.

[0048] To this end, the present application proposes a cache data replacement method and related devices for determining a CL for priority data replacement.

[0049] During the execution of the second process, a second access request for the second data sent by the target application is received. If the second data is not stored in any CL in the cache, multiple CLs to be replaced in the cache are determined, and the multiple CLs include the first CL. If the first hint status information carried by the first CL among the multiple CLs is the first hint id, and the hint status mapped by the first hint id in the second hint mapping table is eviction, the first data in the first CL is replaced by the second data, and the second data is accessed from the first CL, the first data is the data accessed by the first process, and the first process is the process before the second process in the target application.

[0050] In an embodiment of the present application, by writing a second hint mapping table during the second process, data replacement is performed preferentially on the first CL where the first data that does not need to be accessed in the second process is located, thereby overcoming the process change of the target application and the fact that the originally accessed data does not need to be accessed in the current process. These data can be evicted as soon as possible, thereby avoiding the situation where these data are retained for a long time, thereby improving performance.

[0051] In an embodiment of the present application, a configuration interface and a configuration storage module may be provided in the processor. Then, the cache management program may configure the storage module to write a replacement configuration (for example, a first replacement configuration and a second replacement configuration) based on the configuration interface. In addition, a control circuit may be built into the processor, which may be used to receive and process access requests to data in the CL, and may also execute a cache replacement algorithm. In some possible implementations, the control circuit may include a cache control circuit and a replacement control circuit, wherein the cache control circuit is used to receive and process access requests to data in the CL, and the replacement control circuit is used to execute a cache replacement algorithm.

[0052] In some possible implementations, the cache management program can be a software entity running on a processor. Exemplarily, the program file of the storage management program can be stored in a hard disk, and the processor reads the program file from the hard disk, thereby running the cache management program. In some possible implementations, the cache management program can provide an interactive interface, and the user can operate the cache management program through the interactive interface, thereby implementing the above-mentioned cache data replacement method. In some possible implementations, the cache management program can be an independent program on the device, and through interaction with the target application, it obtains the running time period of the first process, thereby executing the above-mentioned cache data replacement method; in some possible implementations, the cache management program can also be a part of the target application, and the cache management program can be used as one of the functions of the target application to execute the above-mentioned cache data replacement method, which is not limited here.

[0053] Exemplarily, as shown in Figure 1-2, the control circuit includes a cache control circuit and a replacement control circuit, wherein the cache control circuit is used to receive access requests for data sent by the target application, and the replacement control circuit is used to execute the cache replacement algorithm according to the replacement configuration (for example, the first replacement configuration or the second replacement configuration) written by the cache management program.

[0054] Referring to FIG. 2-1 , a cache data replacement method provided in the first embodiment of the present application mainly includes the following steps:

[0055] 201. Before a first process is executed, a cache management program writes a first replacement configuration into a control circuit. The first replacement configuration includes a first address range and a first hint mapping table. The first hint mapping table includes the hint ID and a mapped hint state.

[0056] It should be noted that the first address range includes one or more address value intervals in the memory, and the one or more address values ​​may be continuous or discontinuous, which is not limited here.

[0057] It should be noted that, as shown in Figure 2-2, each CL can carry a hint status information. The value of the hint status information can be unconfigured or hint id. The hint id is used to determine the mapped hint status according to the replacement configuration. The hint status can be collecting or evicting. In a hint mapping table, if the hint status mapped by a hint id is collecting, it means that the CL whose hint status information is the hint id is marked, and the CL needs to replace data in the next process; in a hint mapping table, if the hint status mapped by a hint id is evicting, it means that the CL whose hint status information is the hint id needs to replace data in the current process. If the hint status information of a CL is unconfigured, no processing is required for the CL.

[0058] In some possible implementations, in the first hint mapping table, the hint state mapped to the first hint ID is collection, and the hint states mapped to other hint IDs except the first hint ID are all eviction.

[0059] Exemplarily, the one or more hint IDs include three hint IDs, namely a first hint ID, a second hint ID, and a third hint ID. Exemplarily, as shown in Table 1, the first hint ID is 1, the second hint ID is 2, and the third hint ID is 3. In the first hint mapping table, a first hint ID value of 1 maps to a hint state of "collect," a second hint ID value of 2 maps to a hint state of "evict," and a third hint ID value of 3 maps to a hint state of "evict."

[0060] Table 1

[0061] In some possible implementations, at the same time, in the first hint mapping table, at most one hint ID may be mapped to the "collect" state, while all other hint IDs may be mapped to the "eviction" state. In some possible implementations, at the same time, two or more hint IDs may be mapped to the "collect" state, while all other hint IDs may be mapped to the "eviction" state. This is not a limitation here. In some possible implementations, at the same time, all hint IDs may be mapped to the "eviction" state. This is not a limitation here.

[0062] It should be noted that executing the target application requires executing multiple processes, including a first process and a second process. The first process is used to access first data and perform calculations to obtain a first calculation result; the second process is used to access second data and perform calculations to obtain a second calculation result. In some possible implementations, the first process and / or the second process can be processes or other types of execution processes, which are not limited here.

[0063] In some possible implementations, the first data is a portion of data to be accessed by the first process, and the second data is a portion of data to be accessed by the second process. For example, the first process needs to access data 1a, data 1b, data 1c, and data d, and the second process needs to access data 2a, data 2b, data 2c, and data d, where the first data is data 1a, the second data is data 2a, and the shared data is data d.

[0064] In some possible implementations, the second data may also be a portion of the data that the second process needs to access, rather than a portion of the accessed data, which is not limited here. In the following examples, the second data is taken as an example of a portion of the data accessed by the second process.

[0065] In an embodiment of the present application, after the first process ends, in order to expel the first data that is only accessed by the first process as soon as possible and retain the shared data that both the first process and the second process need to access, it is necessary to mark the first CL that stores the first data. To this end, before executing the first process, it is necessary to first define a first address range that includes the first data. Since the first replacement configuration includes the first address range where the first data is located, when the first process accesses the first data, the address of the first data is obtained, and based on the first replacement configuration, it is determined that the address of the first data belongs to the first address range, then the first CL where the first data is located can be marked based on the first hint mapping table, that is, the first hint state information of the first CL is set to the first hint id, and the hint state of the first hint id in the first hint mapping table is collecting.

[0066] In some possible implementations, the cache management program can obtain the running time period of the first process and then write the first replacement configuration to the control circuit before the first process runs. In some possible implementations, the cache management program can communicate with the target application to obtain the target application's currently running process and the process to be run, which is not limited here.

[0067] Exemplarily, as shown in FIG2-3 , the target application includes a first process and a second process that are executed successively, wherein the first process needs to access first data and shared data when running, and the second process needs to access second data and shared data when running.

[0068] As shown in Figure 2-3, before the first process runs, the cache management program can write a first replacement configuration in the control circuit. The first address range in the first replacement configuration includes the address of the first data but does not include the address of the shared data. Then, the control circuit can mark the first CL where the first data accessed by the first process is located, so that the value of the first hint status information of the first CL is set to the first hint id.

[0069] In some possible implementations, based on prior knowledge of the target application's software design, the shared data, first data, and second data are identified in advance during the software design phase or before the first process is executed, and are arranged within different address ranges in memory. In some possible implementations, as shown in Figures 2-4, the first address range includes the first data but does not include the shared data or the second data, which is not a limitation herein.

[0070] 202. During the execution of the first process, the control circuit receives a first access request for first data sent by a target application.

[0071] In some possible implementations, when the first process is running, the first process needs to access the first data, then the target application can send a first access request for the first data to the control circuit, and the first access request can carry the address of the first data in the memory.

[0072] 203. The control circuit accesses first data from the first CL based on the first access request.

[0073] In some possible implementations, when a first process accesses first data, it first queries the cache based on the address of the first data indicated in the first access request to determine which CL stores the first data. If the first CL stores the first data, the first process can access the first data from the first CL. In some possible implementations, if the first data is not stored in any CL, the first process can retrieve the first data from memory, store it in the first CL, and then access the first data from the first CL. This is not limited here.

[0074] Exemplarily, the process of the first process accessing the first data may be as shown in the following steps S1 to S7:

[0075] S1. The control circuit traverses each CL of the cache to determine whether there is a CL storing the first data.

[0076] Exemplarily, the cache includes a first CL, a second CL, and a third CL, and the control circuit traverses the first CL, the second CL, and the third CL to determine whether the first data is stored in the first CL, the second CL, or the third CL.

[0077] S2. If the first data is stored in the first CL of the cache, the control circuit accesses the first data from the first CL.

[0078] S3. If the first data is not stored in any CL of the cache, the control circuit obtains the first data from the memory.

[0079] S4. If there is an idle first CL in the cache, the control circuit stores the first data in the first CL and accesses the first data from the first CL.

[0080] S5. If there is no idle CL in the cache, the control circuit determines multiple CLs to be replaced based on the current cache replacement algorithm.

[0081] S6. If a first CL among the multiple CLs carries first hint status information, and the value of the first hint status information is a second hint ID, and the hint status mapped by the second hint ID in the first hint mapping table is eviction, the control circuit replaces the data in the first CL with the first data.

[0082] S7. The control circuit updates the retention priorities of multiple CLs.

[0083] 204. If the address of the first data belongs to the first address range, the control circuit sets the first hint state information as a first hint ID.

[0084] In some possible implementations, each CL in the cache carries corresponding tag information, and the tag information also includes hint status information of the CL, which is not limited here.

[0085] In some possible implementations, the value of the hint status information carried by a CL can be a hint ID or unconfigured. The hint ID is used to determine the mapped hint status based on a hint mapping table, where the hint status is either collect or evict. For example, when accessing first data from a first CL, the control circuit determines that the address of the first data in the first CL falls within a first address range. The control circuit then sets the first hint status information carried by the first CL to a first hint ID. The first hint ID is the hint ID mapped in the first hint mapping table to a collect status, thereby marking the first CL.

[0086] It should be noted that, since the control circuit needs to set the first hint status information carried by the first CL to the hint ID mapped in the first hint mapping table as collected, it is also necessary to determine whether the hint ID mapped in the first hint mapping table as collected exists.

[0087] For example, during the execution of the first process, the value of the first hint status information carried in the first CL is 2, that is, the second hint ID, and the hint status mapped in the first hint mapping table is eviction. Since the address of the first data belongs to the first address range, and the hint status mapped by the first hint ID in the first hint mapping table is collection, the control circuit can set the first hint status information carried by the first CL to 1, that is, the first hint ID, and the hint status mapped by the first hint ID in the first hint mapping table is collection, thereby marking the first CL, that is, collecting the first data in the first CL that needs to be evicted in the next process.

[0088] 205. During the execution of the first process, the control circuit receives an access request for shared data sent by the target application, and accesses the shared data from the shared CL. The shared data is data accessed by both the first process and the second process.

[0089] In some possible implementations, when a first process accesses shared data, it first queries the cache to determine which CL stores the shared data. If a shared CL stores the shared data, the first process can access the shared data from the shared CL. In some possible implementations, if the shared data is not stored in any CL, the first process can retrieve the shared data from memory, store it in the shared CL, and then access the shared data from the shared CL. This is not a limitation here.

[0090] 206. If the address of the shared data does not belong to the first address range, the control circuit sets the shared hint status information carried by the shared CL to unconfigured.

[0091] In some possible implementations, when the first process accesses other data that does not fall within the first address range from the CL, the hint state information of the CL may be set to unconfigured. For example, when the first process accesses shared data from a shared CL, and the shared data stored in the shared CL does not fall within the first address range, the control circuit sets the shared hint state information corresponding to the shared CL to 0, i.e., unconfigured.

[0092] 207. Before the second process is executed, the cache management program writes a second replacement configuration into the control circuit. The second replacement configuration includes a second address range and a second hint mapping table. The second hint mapping table includes a hint ID and a mapped hint state.

[0093] In an embodiment of the present application, the cache management program may first obtain the running time period of the second process, and then, before the second process runs, the second replacement configuration may be written into the control circuit.

[0094] In some possible implementations, when the first process is finished, the second process can be run immediately. In some possible implementations, before the second process is run, the cache management program can modify the first replacement configuration to a second replacement configuration. The second replacement configuration includes a second hint mapping table. Compared with the first hint mapping table, the hint state mapped by the first hint id in the second hint mapping table is eviction, and the hint state mapped by the second hint id in the second hint mapping table is collection. Then, the hint state corresponding to the first CL is eviction, and when the second process is running, the control circuit can quickly replace the data of the first CL.

[0095] In some possible implementations, in the second hint mapping table, the hint state mapped to the second hint ID is collection, and the hint states mapped to other hint IDs except the second hint ID are all eviction.

[0096] For example, the second hint mapping table is shown in Table 2, where the first hint id is 1, the second hint id is 2, and the third hint id is 3. In the second mapping table, the first hint id value of 1 maps to the hint state of Eviction, the second hint id value of 2 maps to the hint state of Collection, and the third hint id value of 3 maps to the hint state of Eviction. Therefore, since the value of the first hint state information carried in the first CL is 1, the hint state mapped in the first hint mapping table is Collection, while the hint state mapped in the second hint mapping table is Eviction.

[0097] Table 2

[0098] In some possible implementations, at any given moment in the second hint mapping table, at most one hint ID may be mapped to the collect state, while all other hint IDs may be mapped to the evict state. In some possible implementations, at any given moment in the second hint mapping table, two or more hint IDs may be mapped to the collect state, while all other hint IDs may be mapped to the evict state. This is not a limitation here.

[0099] In an embodiment of the present application, after the second process ends, in order to expel the second data that is only accessed by the second process as soon as possible and retain the shared data that both the first process and the second process need to access, the CL storing the second data needs to be marked. To this end, before executing the second process, it is necessary to first define a second address range including the second data. Since the second replacement configuration includes the second address range where the second data is located, when the second process accesses the second data, the address of the second data is obtained, and based on the second replacement configuration, it is determined that the address of the second data belongs to the second address range, then the CL where the second data is located can be marked based on the second hint mapping table, that is, the hint status information of the CL where the second data is located is set to the second hint id, and the hint status of the second hint id in the second hint mapping table is collected.

[0100] Therefore, in some possible implementations, the second replacement configuration also includes a second address range to replace the first address range. The second data belongs to the second address range, and the hint state mapped by the second hint id (value is 2) in the second hint mapping table is collecting. Then, when the second process is running, when the second process accesses the second data, the control circuit can mark the CL where the second data is located, and give priority to replacing the second data in the CL after the second process ends. It should be noted that the second address range includes one or more address value intervals in the memory, and the one or more address values ​​can be continuous or discontinuous, which is not limited here.

[0101] 208. During the execution of the second process, the control circuit receives a second access request for second data sent by the target application.

[0102] In some possible implementations, when the second process accesses the second data, it first queries the cache to determine which CL stores the second data. If the second CL stores the second data, the second process can access the second data from the second CL. In some possible implementations, if the second data is not stored in any CL, step 209 is executed.

[0103] 209. If none of the CLs in the cache stores the second data, the control circuit determines multiple CLs in the cache to be replaced, where the multiple CLs include the first CL.

[0104] It should be noted that during the second process, by executing any cache replacement algorithm, multiple CLs to be replaced can be determined. Exemplarily, the multiple CLs include a first CL, a second CL, and a third CL. Based on the current cache replacement algorithm, the first CL, the second CL, and the third CL are determined to have lower retention priorities.

[0105] 210. If the first hint status information carried by the first CL among the multiple CLs is the first hint id, and the hint status mapped by the first hint id in the second hint mapping table is eviction, the control circuit replaces the first data in the first CL with the second data and accesses the second data from the first CL.

[0106] In some possible implementations, the control circuit can traverse each CL in the multiple CLs to be replaced, obtain the hint status information corresponding to each CL, and obtain the mapped hint status from the second hint mapping table based on the hint status information, and perform data replacement for the CL whose hint status is eviction.

[0107] For example, before the second process is executed, the first hint state information of the first CL is a first hint ID (e.g., a value of 1). Based on the first hint mapping table, the hint state mapped to the first hint ID is collect. During the execution of the second process, the hint state mapped to the first hint ID (e.g., a value of 1) based on the second hint mapping table is evict. Therefore, the control circuit can preferentially replace data on the first CL during the execution of the second process.

[0108] Furthermore, if the multiple CLs include a shared CL containing shared data, the shared hint status information for that shared CL is unconfigured (its value is 0) before the second process runs. During the second process, the shared hint status information for that shared CL remains unconfigured (its value is 0). Therefore, the shared data is not replaced first during the second process, achieving the goal of replacing the first data in the first CL as quickly as possible. At the same time, the shared data is retained, and subsequent access to this shared data will not result in cache invalidation, thus avoiding performance degradation.

[0109] 211. If the address of the second data belongs to the second address range, the control circuit sets the first hint state information carried by the first CL as a second hint ID.

[0110] In some possible implementations, the second replacement configuration also includes a second address range, which includes the address of the second data but does not include the address of the shared data. Then, the control circuit can mark the first CL where the second data accessed by the second process is located. Then, after the subsequent second process ends, the second data can be expelled first, that is, the data of the first CL is replaced.

[0111] In some possible implementations, when the second process accesses the second data, it first queries the cache to determine which CL stores the second data. If the first CL stores the second data, the second process can access the second data from the first CL. In some possible implementations, if the first data is not stored in any CL, the second process can retrieve the second data from memory, store it in the first CL, and then access the second data from the first CL. This is not a limitation here.

[0112] In some possible implementations, when accessing the second data from the first CL, the control circuit determines that the address of the second data belongs to the second address range, then the control circuit sets the first hint status information carried by the first CL to the hint state mapped in the second hint mapping table as the collected hint id, that is, the second hint id (for example, the value is 2), thereby realizing the marking of the first CL.

[0113] Exemplarily, the value of the first hint state information carried in the first CL is 1, that is, the hint state corresponding to the first hint state information is eviction. When accessing the second data from the first CL, the control circuit determines that the address of the second data in the first CL belongs to the second address range, and the hint state mapped by the second hint ID in the second hint mapping table is collection. Then, the control circuit sets the first hint state information carried by the first CL to 2, that is, the second hint ID. The hint state mapped by the second hint ID in the second hint mapping table is collection, thereby marking the first CL so that after the second process ends, the data of the first CL can be replaced first, that is, the second data in the first CL can be evicted first.

[0114] In some possible implementations, when the second process accesses other data that does not fall within the second address range from the CL, the hint state information of the CL may be set to unconfigured. For example, when the second process accesses shared data from the shared CL, and the shared data stored in the shared CL does not fall within the second address range, the control circuit sets the shared hint state information corresponding to the shared CL to 0, i.e., unconfigured.

[0115] Based on steps 201-211 above, by reusing different hint states mapped to several hint IDs, different hint mapping tables and corresponding replacement configurations can be obtained. Different replacement configurations also include different address ranges. Using different replacement configurations in different processes can achieve marking or data replacement for different CLs in different processes. The following example illustrates this.

[0116] For example, as shown in Figures 2-5, the target application includes multiple processes, and the multiple processes include process 1, process 2, process 3, process 4 and process 5 that run in sequence, where process 1 needs to access data 1 and shared data, process 2 needs to access data 2 and shared data, process 3 needs to access data 3 and shared data, process 4 needs to access data 4 and shared data, and process 5 needs to access data 5 and shared data.

[0117] Before process 1 is executed, the cache management program writes replacement configuration 1 on the control circuit. Replacement configuration 1 includes address range 1 and hint mapping table 1. Address range 1 includes data 1 but does not include shared data. Hint mapping table 1 is shown in Table 1.

[0118] Then, during the execution of process 1, when accessing data 1 from CL 1, since the address of data 1 in CL 1 belongs to address range 1 and the hint state mapped to the first hint ID in hint mapping table 1 is collecting, the value of hint state information 1 carried by CL 1 can be set to 1 (first hint ID). However, since the shared data is not in address range 1, no processing will be performed on the shared CL where the shared data is located. The value of the shared hint state information of the shared CL remains 0, that is, the corresponding hint state is unconfigured. The control circuit then marks CL 1 without marking the shared CL.

[0119] After process 1 completes and before process 2 begins, the cache management program writes replacement configuration 2 to the control circuit to replace replacement configuration 1. Replacement configuration 2 includes address range 2 and hint mapping table 2. Address range 2 includes data 2 but excludes shared data. Hint mapping table 2 is shown in Table 2.

[0120] Then, during the execution of process 2, when multiple CLs to be replaced are determined, if the multiple CLs to be replaced include CL 1 and the shared CL, since the value of hint status information 1 carried by CL 1 is 1, that is, the first hint ID, the hint status mapped in hint mapping table 2 is eviction. However, the value of the shared hint status information of the shared CL is 0, that is, the corresponding hint status is unconfigured. Therefore, the control circuit can prioritize data replacement for CL 1 rather than the shared CL.

[0121] Furthermore, during the execution of process 2, when accessing data 2 from CL 2, since the address of data 2 in CL 2 falls within address range 2 and the hint state mapped to the second hint ID in hint mapping table 2 is "collect," the value of hint state information 2 carried by CL 2 can be set to 2 (the second hint ID). However, since the shared data is not within address range 2, no processing is performed on the shared CL containing the shared data. The value of the shared hint state information of the shared CL remains 0, indicating that the corresponding hint state is "unconfigured." The control circuit then marks CL 2 without marking the shared CL.

[0122] After process 2 completes and before process 3 begins, the cache management program writes replacement configuration 3 to the control circuit to replace replacement configuration 2. Replacement configuration 3 includes address range 3 and hint mapping table 3. Address range 3 includes data 3 but excludes shared data. Hint mapping table 3 is shown in Table 3.

[0123] Table 3

[0124] Then, during the execution of process 3, when determining multiple CLs to be replaced, if the multiple CLs to be replaced include CL 1, CL 2, and the shared CL, since the value of the hint state information 2 carried by CL 2 is 2, i.e., the second hint ID, the hint state mapped in hint mapping table 3 is Evicted; the value of the hint state information 1 carried by CL 1 is 1, i.e., the first hint ID, and the hint state mapped in hint mapping table 3 is Evicted. The value of the shared hint state information of the shared CL is 0, i.e., the corresponding hint state is Unconfigured. Therefore, the control circuit can prioritize data replacement for CL 1 and CL 2 rather than the shared CL.

[0125] Furthermore, during the execution of process 3, when accessing data 3 from CL 3, since the address of data 3 in CL 3 falls within address range 3 and the hint state mapped to the third hint ID in hint mapping table 3 is "collect," the value of hint state information 3 carried by CL 3 can be set to 3, the third hint ID. However, since the shared data is not within address range 3, no processing is performed on the shared CL containing the shared data. Therefore, the value of the shared hint state information of the shared CL remains 0, indicating that the corresponding hint state is "unconfigured." Therefore, the control circuit marks CL 3 without marking the shared CL.

[0126] After process 3 completes and before process 4 begins, the cache management program writes replacement configuration 4 to the control circuit to replace replacement configuration 3. Replacement configuration 4 includes address range 4 and hint mapping table 4. Address range 4 includes data 4 but excludes shared data. Hint mapping table 4 is shown in Table 4.

[0127] Table 4

[0128] Then, during the execution of process 4, when determining multiple CLs to be replaced, if the multiple CLs to be replaced include CL 2, CL 3, and the shared CL, since the value of the hint state information 2 carried by CL 2 is 2, i.e., the second hint ID, the hint state mapped in hint mapping table 4 is Evicted; the value of the hint state information 3 carried by CL 3 is 3, i.e., the third hint ID, the hint state mapped in hint mapping table 4 is Evicted. Since the value of the shared hint state information of the shared CL is 0, i.e., the corresponding hint state is Unconfigured, the control circuit can prioritize data replacement for CL 2 and CL 3 rather than the shared CL.

[0129] It should be noted that although the value of hint status information 1 carried by CL 1 is still 1, that is, the first hint ID, and the hint status mapped in hint mapping table 4 is collecting, since CL 1 has been replaced by sufficient data and the data in CL 1 is not data that needs to be accessed in process 4, data 1 may not be accessed from CL 1, that is, CL 1 may not be marked.

[0130] Furthermore, during the execution of process 4, when accessing data 4 from CL 4, since the address of data 4 in CL 4 falls within address range 4 and the hint state mapped to the first hint ID in hint mapping table 4 is "collect," the value of hint state information 4 carried by CL 4 can be set to 1. However, since the shared data is not within address range 4, no processing will be performed on the shared CL containing the shared data. Therefore, the value of the shared hint state information of the shared CL remains 0, indicating that the corresponding hint state is "unconfigured." The control circuit then marks CL 4 without marking the shared CL.

[0131] After process 4 is completed and before process 5 is executed, the cache management program writes replacement configuration 5 to the control circuit to replace replacement configuration 4. Replacement configuration 5 includes address range 5 and hint mapping table 5, where address range 5 includes data 5 but does not include shared data. Hint mapping table 5 is shown in Table 5.

[0132] Table 5

[0133] Then, during the execution of process 5, when determining multiple CLs to be replaced, if the multiple CLs to be replaced include CL 3, CL 4, and the shared CL, since the value of hint status information 3 carried by CL 3 is 3, i.e., the third hint ID, the hint status mapped in hint mapping table 5 is Evicted; the value of hint status information 4 carried by CL 4 is 1, i.e., the first hint ID, and the hint status mapped in hint mapping table 5 is Evicted. The value of the shared hint status information of the shared CL is 0, i.e., the corresponding hint status is Unconfigured. Therefore, the control circuit can prioritize data replacement for CLs 3 and 4 over data replacement for the shared CL.

[0134] It should be noted that although the value of hint status information 2 carried by CL 2 is still 2, that is, the second hint ID, and the hint status mapped in hint mapping table 5 is collecting, since CL 2 has been replaced by sufficient data and the data in CL 2 is not data that needs to be accessed in process 5, data 2 may not be accessed from CL 2, that is, CL 2 may not be marked.

[0135] Furthermore, during the execution of process 5, when accessing data 5 from CL 5, since the address of data 5 in CL 5 falls within address range 5 and the hint state mapped by the second hint ID in hint mapping table 5 is "collect," the value of hint state information 5 carried by CL 5 can be set to 2 (the second hint ID). However, since the shared data is not within address range 5, no processing is performed on the shared CL containing the shared data. Therefore, the value of the shared hint state information of the shared CL remains 0, indicating that the corresponding hint state is "unconfigured." Therefore, the control circuit marks CL 5 without marking the shared CL.

[0136] By using different replacement configurations in different processes as described above, it is possible to reuse several hint IDs to mark and replace data for different CLs in different processes, so that the CL where the data accessed by the previous process is located is given priority for data replacement in the current process, and the shared data that the current process needs to continue to access can continue to remain in the cache.

[0137] In the present application, during the operation of the second process, a second access request for the second data sent by the target application is received, and the second data is the data accessed by the second process. If the second data is not stored in each CL in the cache, multiple CLs to be replaced in the cache are determined, and the multiple CLs include the first CL. If the first hint status information carried by the first CL among the multiple CLs is the first hint id, and the hint status mapped by the first hint id in the second hint mapping table is eviction, the first data in the first CL is replaced by the second data, and the second data is accessed from the first CL, the first data is the data accessed by the first process, and the first process is the process before the second process in the target application.

[0138] In an embodiment of the present application, by writing a second hint mapping table during the second process, data replacement is performed preferentially on the first CL where the first data that does not need to be accessed in the second process is located, thereby overcoming the process change of the target application and the fact that the originally accessed data does not need to be accessed in the current process. These data can be evicted as soon as possible, thereby avoiding the situation where these data are retained for a long time, thereby improving performance.

[0139] In the above embodiment 1, a hint mapping table may have multiple hint id values. In some possible implementations, a hint mapping table may have only one hint id, and the hint state mapped to the hint id is collection or eviction. For an example, please refer to the following embodiment 2.

[0140] Referring to FIG3-1 , a cache data replacement method provided in the second embodiment of the present application mainly includes the following steps:

[0141] 301. Before the first process is executed, the cache management program writes a first replacement configuration into the control circuit. The first replacement configuration includes a first address range and a first hint mapping table. The first hint mapping table includes the hint ID and the mapped hint state.

[0142] It should be noted that the first address range includes one or more address value intervals in the memory, and the one or more address values ​​may be continuous or discontinuous, which is not limited here.

[0143] It should be noted that, as shown in Figure 2-2, each CL can carry a hint status information. The value of the hint status information can be unconfigured or hint id. The hint id is used to determine the mapped hint status according to the replacement configuration. The hint status can be collecting or evicting. In a hint mapping table, if the hint status mapped by a hint id is collecting, it means that the CL whose hint status information is the hint id is marked, and the CL needs to replace data in the next process; in a hint mapping table, if the hint status mapped by a hint id is evicting, it means that the CL whose hint status information is the hint id needs to replace data in the current process. If the hint status information of a CL is unconfigured, no processing is required for the CL.

[0144] In some possible implementations, in the first hint mapping table, the hint state mapped to the first hint ID is collection, and the hint states mapped to other hint IDs except the first hint ID are all eviction.

[0145] Exemplarily, the one or more hint ids include one hint id, namely the first hint id. Exemplarily, as shown in Table 6, the first hint id = 1. In the first hint mapping table, the first hint id having a value of 1 maps the hint state to collecting.

[0146] Table 6

[0147] It should be noted that executing the target application requires executing multiple processes, including a first process and a second process. The first process is used to access first data and perform calculations to obtain a first calculation result; the second process is used to access second data and perform calculations to obtain a second calculation result. In some possible implementations, the first process and / or the second process can be processes or other types of execution processes, which are not limited here.

[0148] It should be noted that the first data is part of the data to be accessed by the first process, and the second data is part of the data to be accessed by the second process. For example, the first process wants to access data 1a, data 1b, data 1c, and data d, and the first process wants to access data 2a, data 2b, data 2c, and data d, wherein the first data is data 1a, the second data is data 2a, and the shared data is data d. The first data is stored in the first CL (or the first data is not stored in any CL. When the first data is accessed, the first data can be obtained from the memory and stored in the first CL), the second data is stored in the second CL (or the second data is not stored in any CL. When the second data is accessed, the second data can be obtained from the memory and stored in the second CL), and the shared data is stored in the shared CL (or the shared data is not stored in any CL. When the shared data is accessed, the shared data can be obtained from the memory and stored in the shared CL).

[0149] In an embodiment of the present application, after the first process ends, in order to expel the first data that is only accessed by the first process as soon as possible and retain the shared data that both the first process and the second process need to access, it is necessary to mark the first CL that stores the first data. To this end, before executing the first process, it is necessary to first define a first address range that includes the first data. Since the first replacement configuration includes the first address range where the first data is located, when the first process accesses the first data, the address of the first data is obtained, and based on the first replacement configuration, it is determined that the address of the first data belongs to the first address range, then the first CL where the first data is located can be marked based on the first hint mapping table, that is, the first hint state information of the first CL is set to the first hint id, and the hint state of the first hint id in the first hint mapping table is collecting.

[0150] In some possible implementations, the cache management program can obtain the running time period of the first process and then write the first replacement configuration to the control circuit before the first process runs. In some possible implementations, the cache management program can communicate with the target application to obtain the target application's currently running process and the process to be run, which is not limited here.

[0151] Exemplarily, as shown in FIG2-3 , the target application includes a first process and a second process that are executed successively, wherein the first process needs to access first data and shared data when running, and the second process needs to access second data and shared data when running.

[0152] As shown in Figure 2-3, before the first process runs, the cache management program can write a first replacement configuration in the control circuit. The first address range in the first replacement configuration includes the address of the first data but does not include the address of the shared data. Then, the control circuit can mark the first CL where the first data accessed by the first process is located, so that the value of the first hint status information of the first CL is set to the first hint id.

[0153] In some possible implementations, based on prior knowledge of the target application's software design, the shared data, first data, and second data are identified in advance during the software design phase or before the first process is executed, and are arranged within different address ranges in memory. In some possible implementations, as shown in Figures 2-4, the first address range includes the first data but does not include the shared data or the second data, which is not a limitation herein.

[0154] In some possible implementations, the address range does not necessarily distinguish the first data from the second data. For example, as shown in FIG3-2 , the first address range includes the first data and the second data, but does not include shared data. This is not limited here.

[0155] 302. During the execution of the first process, the control circuit receives a first access request for first data sent by a target application, and accesses the first data from the first CL.

[0156] Please refer to step 202, which will not be described in detail here.

[0157] 303. The control circuit accesses first data from the first CL based on the first access request.

[0158] Please refer to step 203, which will not be described in detail here.

[0159] 304. If the address of the first data belongs to the first address range, the control circuit sets the first hint state information as a first hint ID.

[0160] In some possible implementations, each CL in the cache carries corresponding tag information, and the tag information also includes hint status information of the CL, which is not limited here.

[0161] In some possible implementations, the value of the hint status information carried by a CL can be a hint ID or unconfigured. The hint ID is used to determine the mapped hint status based on a hint mapping table, where the hint status is either collect or evict. For example, when accessing first data from a first CL, the control circuit determines that the address of the first data in the first CL falls within a first address range. The control circuit then sets the first hint status information carried by the first CL to a first hint ID. The first hint ID is the hint ID mapped in the first hint mapping table to a collect status, thereby marking the first CL.

[0162] It should be noted that, since the control circuit needs to set the first hint status information carried by the first CL to the hint ID mapped in the first hint mapping table as collected, it is also necessary to determine whether the hint ID mapped in the first hint mapping table as collected exists.

[0163] For example, during the execution of the first process, the value of the first hint status information carried in the first CL is 0, i.e., not configured. Since the address of the first data belongs to the first address range, and the hint status mapped by the first hint ID in the first hint mapping table is collecting, the control circuit can set the first hint status information carried by the first CL to 1, i.e., the first hint ID, and the hint status mapped by the first hint ID in the first hint mapping table is collecting, thereby marking the first CL, i.e., collecting the first data in the first CL that needs to be evicted in the next process.

[0164] 305. During the execution of the first process, the control circuit receives an access request for shared data sent by the target application, and accesses the shared data from the shared CL. The shared data is data accessed by both the first process and the second process.

[0165] Please refer to step 205, which will not be described in detail here.

[0166] 306. If the address of the shared data does not belong to the first address range, the control circuit sets the shared hint status information carried by the shared CL to unconfigured.

[0167] Please refer to step 206, which will not be described in detail here.

[0168] 307. Before the second process is executed, the cache management program writes a second replacement configuration into the control circuit. The second replacement configuration includes a second hint mapping table. The second hint mapping table includes a hint ID and a mapped hint state.

[0169] In an embodiment of the present application, the cache management program may first obtain the running time period of the second process, and then, before the second process runs, the second replacement configuration may be written into the control circuit.

[0170] In some possible implementations, after the first process completes, the second process can be run immediately. In some possible implementations, before the second process runs, the cache management program can modify the first replacement configuration to a second replacement configuration. The second replacement configuration includes a second hint mapping table. Compared with the first hint mapping table, the hint state mapped to the first hint ID in the second hint mapping table is eviction. Then, the hint state corresponding to the first CL is eviction. When the second process runs, the control circuit can quickly replace the data of the first CL.

[0171] For example, the second hint mapping table is shown in Table 7, where the first hint ID is 1. In the second mapping table, the hint state mapped to the first hint ID value of 1 is eviction. Since the first hint state information carried in the first CL has a value of 1, the hint state mapped in the first hint mapping table is collection, while the hint state mapped in the second hint mapping table is changed to eviction.

[0172] Table 7

[0173] 308. During the execution of the second process, the control circuit receives a second access request for second data sent by the target application.

[0174] Please refer to step 208, which will not be described in detail here.

[0175] 309. If none of the CLs in the cache stores the second data, the control circuit determines multiple CLs to be replaced in the cache, where the multiple CLs include the first CL.

[0176] Please refer to step 209, which will not be described here in detail.

[0177] 310. If the first hint status information carried by a first CL among the multiple CLs is a first hint id, and the hint status mapped by the first hint id in the second hint mapping table is eviction, the control circuit replaces the first data in the first CL with second data and accesses the second data from the first CL.

[0178] Please refer to step 210, which will not be described in detail here.

[0179] Since the cache capacity is small and the price is high, by reducing the number of hint IDs, the capacity required for the first hint mapping table is reduced, thereby reducing the capacity of the first replacement configuration, thereby reducing the storage demand in the cache. It is also possible to replace the data in the CL where the data accessed by the previous process is located, achieving a balance between performance and cost.

[0180] Through steps 301-310, different hint states mapped to a single hint ID can be used to generate different hint mapping tables and corresponding replacement configurations. Different replacement configurations also include different address ranges. Using different replacement configurations in different processes allows for marking or data replacement for different CLs in different processes. The following example illustrates this.

[0181] For example, as shown in Figure 3-3, the target application includes multiple processes, and the multiple processes include process 1, process 2, process 3 and process 4 that run in sequence, where process 1 needs to access data 1 and shared data, process 2 needs to access data 2 and shared data, process 3 needs to access data 3 and shared data, and process 4 needs to access data 4 and shared data.

[0182] Before process 1 is executed, the cache management program writes replacement configuration 1 to the control circuit. Replacement configuration 1 includes address range 1 and hint mapping table 1. Address range 1 includes data 1 but does not include shared data. Hint mapping table 1 is shown in Table 6.

[0183] Then, during the execution of process 1, when accessing data 1 from CL 1, since the address of data 1 in CL 1 belongs to address range 1 and the hint state mapped to the first hint ID in hint mapping table 1 is collecting, the value of hint state information 1 carried by CL 1 can be set to 1 (first hint ID). However, since the shared data is not in address range 1, no processing will be performed on the shared CL where the shared data is located. The value of the shared hint state information of the shared CL remains 0, that is, the corresponding hint state is unconfigured. The control circuit then marks CL 1 without marking the shared CL.

[0184] After process 1 is finished and before process 2 is executed, the cache management program writes replacement configuration 2 on the control circuit to replace replacement configuration 1. Replacement configuration 2 includes hint mapping table 2, as shown in Table 7.

[0185] Then, during the execution of process 2, when multiple CLs to be replaced are determined, if the multiple CLs to be replaced include CL 1 and the shared CL, since the value of hint status information 1 carried by CL 1 is 1, that is, the first hint ID, the hint status mapped in hint mapping table 2 is eviction. However, the value of the shared hint status information of the shared CL is 0, that is, the corresponding hint status is unconfigured. Therefore, the control circuit can prioritize data replacement for CL 1 rather than the shared CL.

[0186] After process 2 completes and before process 3 begins, the cache management program writes replacement configuration 3 to the control circuit to replace replacement configuration 2. Replacement configuration 3 includes address range 3 and hint mapping table 3. Address range 3 includes data 3 but excludes shared data. Hint mapping table 3 is shown in Table 6.

[0187] Then, during the execution of process 3, when accessing data 3 from CL 3, since the address of data 3 in CL 3 falls within address range 3 and the hint state mapped to the third hint ID in hint mapping table 3 is "collecting," the value of hint state information 3 carried by CL 3 can be set to 1 (the first hint ID). However, since the shared data is not within address range 3, no processing will be performed on the shared CL containing the shared data. Therefore, the value of the shared hint state information of the shared CL remains 0, indicating that the corresponding hint state is "unconfigured." Therefore, the control circuit marks CL 3 but does not mark the shared CL.

[0188] After process 3 is finished and before process 4 is executed, the cache management program writes replacement configuration 4 into the control circuit to replace replacement configuration 3. Replacement configuration 4 includes hint mapping table 4, as shown in Table 7.

[0189] Then, during the execution of process 4, when determining multiple CLs to be replaced, if the multiple CLs to be replaced include CL 4 and a shared CL, since the value of hint status information 4 carried by CL 4 is 1, i.e., the first hint ID, the hint status mapped in hint mapping table 4 is eviction. However, the value of the shared hint status information of the shared CL is 0, i.e., the corresponding hint status is unconfigured. Therefore, the control circuit can prioritize data replacement for CL 4 over data replacement for the shared CL.

[0190] Compared with the first embodiment, in the technical solution of the second embodiment, the amount of storage required in the cache is minimal. By using the second process as an interval process, the control circuit has enough time to evict the first data accessed by the first process, without having to change the replacement configuration in the gap between the two processes, which is low-cost and easy to implement. Moreover, the second embodiment does not need to be too precise in distinguishing the address range of the data. For example, the first data and the second data can be arranged in the same address range without having to distinguish and arrange them. The data in the address range accessed during the operation of the first process is naturally identified as the first data, and the same applies to the second process, which can reduce the difficulty of modifying the software and expand the application scenarios.

[0191] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0192] In order to better implement the above-mentioned solutions of the embodiments of the present application, relevant devices for implementing the above-mentioned solutions are also provided below.

[0193] Referring to FIG. 4 , a processor 400 provided in an embodiment of the present application may include:

[0194] The receiving module 401 is used to receive a second hint mapping table before the second process runs, the second hint mapping table including a hint id and a mapped hint status, and the second process is the process of the target application; the receiving module 401 is also used to receive a second access request for the second data sent by the target application during the running of the second process; the processing module 402 is used to determine multiple CLs to be replaced in the cache if none of the CLs in the cache stores the second data, the multiple CLs including the first CL; the processing module 402 is also used to replace the first data in the first CL with the second data if the first hint status information carried by the first CL in the multiple CLs is the first hint id and the hint status mapped by the first hint id in the second hint mapping table is eviction, the first data is the data accessed by the first process, and the first process is the process before the second process in the target application; the processing module 402 is also used to access the second data from the first CL.

[0195] In some possible implementations, the receiving module 401 is further used to receive a first replacement configuration before the first process is run, the first replacement configuration including a first address range and a first hint mapping table, the first hint mapping table including the hint id and the mapped hint state, and in the first hint mapping table, the hint state mapped to the first hint id is collecting; the receiving module 401 is further used to receive a first access request for the first data sent by the target application during the running of the first process, and access the first data from the first CL; the processing module 402 is further used to set the first hint state information to the first hint id if the address of the first data belongs to the first address range.

[0196] In some possible implementations, the receiving module 401 is further used to receive an access request for the shared data sent by the target application during the running of the first process, and access the shared data from the shared CL, where the shared data is the data accessed by the first process and the second process respectively; the processing module 402 is further used to set the shared hint status information carried by the shared CL to unconfigured if the address of the shared data does not belong to the first address range.

[0197] In some possible implementations, the receiving module 401 is specifically configured to receive a second replacement configuration, where the second replacement configuration includes the second hint mapping table, and in the second hint mapping table, the hint status mapped to the first hint ID is eviction.

[0198] In some possible implementations, the second replacement configuration also includes a second address range, the hint status mapped by the second hint id in the second hint mapping table is collecting, and the receiving module 401 is further used to set the first hint status information carried by the first CL to the second hint id if the address of the second data belongs to the second address range.

[0199] It should be noted that the information interaction, execution process, etc. between the modules / units of the above-mentioned device are based on the same concept as the method embodiment of the present application, and the technical effects they bring are the same as those of the method embodiment of the present application. For specific contents, please refer to the description in the method embodiment shown above in the present application, and no further details will be given here.

[0200] An embodiment of the present application further provides a computer storage medium, wherein the computer storage medium stores a program, and the program executes some or all of the steps recorded in the above method embodiment.

[0201] In another possible design, when the processor 400 includes: a processing unit and a communication unit, the processing unit may be, for example, a processor, and the communication unit may be, for example, an input / output interface, a pin, or a circuit. The processing unit may execute computer-executable instructions stored in the storage unit to cause the chip in the terminal to perform the method for sending wireless report information of any one of the first aspects described above.

[0202] The processor mentioned in any of the above may be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the program of the above method.

[0203] It should also be noted that the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed across multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. In addition, in the drawings of the device embodiments provided in this application, the connection relationship between the modules indicates that there is a communication connection between them, which can be specifically implemented as one or more communication buses or signal lines.

[0204] Through the description of the above embodiments, it is clear to those skilled in the art that the present application can be implemented by means of software plus necessary general-purpose hardware, and of course it can also be implemented by means of dedicated hardware including application-specific integrated circuits, dedicated CPUs, dedicated memories, dedicated components, etc. In general, all functions performed by computer programs can be easily implemented with corresponding hardware, and the specific hardware structures used to implement the same function can also be various, such as analog circuits, digital circuits, or dedicated circuits, etc. However, for the present application, software program implementation is a better implementation method in most cases. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer's floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0205] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0206] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, a computer, a server, or a data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode to another website, a computer, a server, or a data center. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a server or a data center that includes one or more available media integrations. The available medium can be a magnetic medium, (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid-state drive (SSD)).

Claims

1. A cache data replacement method, characterized in that: include: Before the second process is run, a second hint mapping table is received, wherein the second hint mapping table includes a hint id and a mapped hint state, and the second process is a process of a target application; During the execution of the second process, receiving a second access request for the second data sent by the target application; If all CLs in the cache do not store the second data, determining a plurality of CLs to be replaced in the cache, where the plurality of CLs include the first CL; If the first hint state information carried by the first CL among the multiple CLs is a first hint id, and the hint state mapped by the first hint id in the second hint mapping table is eviction, then replacing the first data in the first CL with the second data, the first data being data accessed by a first process, and the first process being a process before the second process in the target application; The second data is accessed from the first CL.

2. The method according to claim 1, characterized in that: The method further comprises: Before the first process is executed, a first replacement configuration is received, wherein the first replacement configuration includes a first address range and a first hint mapping table, wherein the first hint mapping table includes the hint id and a mapped hint state, and in the first hint mapping table, the hint state mapped to the first hint id is collecting; During the execution of the first process, receiving a first access request for the first data sent by the target application, and accessing the first data from the first CL; If the address of the first data belongs to the first address range, the first hint state information is set to the first hint id.

3. The method according to claim 2, characterized in that: The method further comprises: During the running of the first process, receiving an access request for the shared data sent by the target application, and accessing the shared data from the shared CL, the shared data being data accessed by both the first process and the second process; If the address of the shared data does not belong to the first address range, the shared hint state information carried by the shared CL is set to unconfigured.

4. The method according to claim 2 or 3, characterized in that: In the first hint mapping table, the hint status mapped to other hint IDs except the first hint ID is eviction.

5. The method according to any one of claims 1 to 4, characterized in that: The receiving the second hint mapping table includes: A second replacement configuration is received, where the second replacement configuration includes the second hint mapping table, in which the hint state mapped to the first hint id is eviction.

6. The method according to claim 5, characterized in that: The second replacement configuration further includes a second address range, the hint state mapped by the second hint id in the second hint mapping table is collection, and after accessing the second data from the first CL, the method further includes: If the address of the second data belongs to the second address range, the first hint state information carried by the first CL is set to the second hint id.

7. The method according to any one of claims 1 to 6, characterized in that: The hint status information is carried in the label information of the CL.

8. A processor, characterized in that: include: A receiving module, used for receiving a second hint mapping table before the second process is run, wherein the second hint mapping table includes a hint id and a mapped hint state, and the second process is a process of a target application; The receiving module is further configured to receive a second access request for the second data sent by the target application during the execution of the second process; a processing module, configured to determine a plurality of CLs to be replaced in the cache if none of the CLs in the cache stores the second data, wherein the plurality of CLs include the first CL; The processing module is further configured to replace first data in the first CL with the second data if the first hint state information carried by the first CL among the multiple CLs is a first hint id and the hint state mapped by the first hint id in the second hint mapping table is eviction, wherein the first data is data accessed by a first process, and the first process is a process before the second process in the target application; The processing module is further used to access the second data from the first CL.

9. The processor according to claim 8, characterized in that: The receiving module is further configured to receive a first replacement configuration before the first process is executed, wherein the first replacement configuration includes a first address range and a first hint mapping table, wherein the first hint mapping table includes the hint id and a mapped hint state, and in the first hint mapping table, the hint state mapped by the first hint id is collection; The receiving module is further configured to receive a first access request for the first data sent by the target application during the running of the first process, and access the first data from the first CL; The processing module is further configured to set the first hint state information as the first hint id if the address of the first data belongs to the first address range.

10. The processor according to claim 9, characterized in that: The receiving module is further used to receive, during the running of the first process, an access request for the shared data sent by the target application, and access the shared data from the shared CL, wherein the shared data is the data accessed by the first process and the second process respectively; The processing module is further configured to set the shared hint status information carried by the shared CL to unconfigured if the address of the shared data does not belong to the first address range.

11. The processor according to any one of claims 8 to 10, characterized in that: The receiving module is specifically used for: A second replacement configuration is received, where the second replacement configuration includes the second hint mapping table, in which the hint state mapped to the first hint id is eviction.

12. The processor according to claim 11, characterized in that: The second replacement configuration further includes a second address range, the hint state mapped by the second hint id in the second hint mapping table is collection, The receiving module is further configured to set the first hint state information carried by the first CL as the second hint id if the address of the second data belongs to the second address range.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a program, and the program causes a computer device to execute the method according to any one of claims 1 to 7.

14. A computer program product, characterized in that The computer program product includes computer-executable instructions, which are stored in a computer-readable storage medium; at least one processor of a device reads the computer-executable instructions from the computer-readable storage medium, and the at least one processor executes the computer-executable instructions so that the device performs the method as described in any one of claims 1-7.

15. A communication device, characterized in that: The communication device includes at least one processor, a memory and a communication interface; The at least one processor is coupled to the memory and the communication interface; The memory is used to store instructions, the processor is used to execute the instructions, and the communication interface is used to communicate with other communication devices under the control of the at least one processor; When the instructions are executed by the at least one processor, the at least one processor is caused to perform the method according to any one of claims 1 to 7.

16. A chip system, characterized in that: The chip system includes a processor and a memory, the memory and the processor are interconnected via a line, instructions are stored in the memory, and the processor is used to execute the method as described in any one of claims 1-7.

Images