Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor capable of ensuring high moisture resistance reliability even in a case where moisture intrudes into the multilayer ceramic capacitor. In a multilayer ceramic capacitor 1, a laminate 2 includes: an inner layer part 60 in which first internal electrodes 30 and second internal electrodes 31 are alternately laminated with a dielectric layer 20 interposed therebetween; outer layer parts 61 which are arranged so as to sandwich the inner layer part 60 in a lamination direction 102 and which are composed of a ceramic material; and side gap parts which are arranged so as to sandwich the inner layer part 60 and the outer layer parts 61 in a width direction 101. A glass region 80 in which glass is segregated is present in at least either the side gap parts or the outer layer parts 61.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors are electronic components that include a laminate in which dielectric layers and internal electrodes are alternately stacked, and external electrodes electrically connected to the internal electrodes. Multilayer ceramic capacitors are used in a wide range of fields, including communications, IoT, automotive, and medical. In particular, in recent years, multilayer ceramic capacitors have been installed in devices used to protect people's safety, increasing the demand for improved quality of multilayer ceramic capacitors. In particular, the moisture-resistant reliability of multilayer ceramic capacitors is one of the factors that significantly influences the likelihood of device failure, so improving the moisture-resistant reliability of multilayer ceramic capacitors is an urgent need. For example, Patent Document 1 discloses a technology for improving reliability by adjusting the indium and tin content in internal electrodes.

[0003] JP 2023-124814 A

[0004] However, with conventional multilayer ceramic capacitors, if moisture penetrates the interior of the multilayer ceramic capacitor, the moisture easily reaches the inner layer portion consisting of the internal electrodes and dielectric layers, making it impossible to ensure high moisture resistance reliability.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor that can ensure high moisture resistance reliability even when moisture penetrates into the interior of the multilayer ceramic capacitor.

[0006] The multilayer ceramic capacitor of the present invention comprises a laminate having a plurality of laminated dielectric layers and a plurality of internal electrodes laminated on the dielectric layers, the laminate having first and second main faces opposing each other in a lamination direction, first and second side faces opposing each other in a width direction perpendicular to the lamination direction, and first and second end faces opposing each other in a length direction perpendicular to the lamination direction and the width direction, and the plurality of internal electrodes having a first internal electrode extended to the first end face and a second internal electrode extended to the second end face, the first internal electrode being connected to the first internal electrode, and the second internal electrode being connected to the first internal electrode. The laminate comprises a first external electrode covering the end face, and a second external electrode connected to the second internal electrode and covering the second end face, and the laminate has an inner layer portion in which the first internal electrodes and the second internal electrodes are alternately stacked with the dielectric layer interposed therebetween, outer layer portions made of a ceramic material and arranged to sandwich the inner layer portion in the stacking direction, and side gap portions arranged to sandwich the inner layer portion and the outer layer portion in the width direction, and a glass region in which glass is segregated is present in at least either the side gap portion or the outer layer portion.

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can ensure high moisture resistance reliability even when moisture penetrates into the interior of the multilayer ceramic capacitor.

[0008] FIG. 1 is a diagram showing a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 2 is a diagram showing a laminate according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view taken along line 201-201 of FIG. 1. FIG. 4 is a cross-sectional view taken along line 202-202 of FIG. 1. FIG. 5 is a cross-sectional view taken along line 203-203 of FIG. 1. FIG. 6 is a cross-sectional view taken along line 204-204 of FIG. 1. FIG. 7 is a diagram illustrating a method for manufacturing a multilayer ceramic capacitor according to an embodiment of the present invention, showing ceramic green sheets on which conductive films have been formed. FIG. 8 is a diagram illustrating a method for manufacturing a multilayer ceramic capacitor according to an embodiment of the present invention, showing how ceramic green sheets on which conductive films have been formed are laminated. FIG. 9 is a diagram illustrating a method for manufacturing a multilayer ceramic capacitor according to an embodiment of the present invention, showing the appearance of a laminate chip. FIG. 10 is a cross-sectional view of a multilayer ceramic capacitor according to a second embodiment of the present invention. FIG. 11 is a cross-sectional view of a multilayer ceramic capacitor according to a third embodiment of the present invention. FIG. 12 is a cross-sectional view of a modified example of the multilayer ceramic capacitor according to the third embodiment of the present invention.

[0009] First Embodiment (Multilayer Ceramic Capacitor) An embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a diagram showing a multilayer ceramic capacitor 1 according to a first embodiment of the present invention. As shown in Fig. 1, the multilayer ceramic capacitor 1 includes a laminate 2 and external electrodes. The external electrodes include a first external electrode 40 and a second external electrode 41.

[0010] (Laminate 2) Fig. 2 is a diagram showing the laminate 2. Fig. 3 is a cross-sectional view taken along line 201-201 in Fig. 1. As shown in Fig. 2, the laminate 2 is formed in a substantially rectangular parallelepiped shape. As shown in Fig. 3, the laminate 2 includes a plurality of stacked dielectric layers 20 and a plurality of internal electrodes stacked on the dielectric layers 20. The internal electrodes include a first internal electrode 30 and a second internal electrode 31.

[0011] The laminate 2 has a first main surface 10 and a second main surface 11 facing in the stacking direction 102, a first side surface 12 and a second side surface 13 facing in the width direction 101 perpendicular to the stacking direction 102, and a first end surface 14 and a second end surface 15 facing in the length direction 100 perpendicular to the stacking direction 102 and the width direction 101.

[0012] A portion where two surfaces of the laminate 2 intersect is called a ridge 5. A portion where three surfaces of the laminate 2 intersect is called a corner 6. The ridge 5 and the corner 6 are preferably rounded or the like.

[0013] (Inner layer portion 60) In the laminate 2, an internal electrode is disposed at the interface between two dielectric layers 20, and the dielectric layers 20 and the internal electrodes are alternately stacked. By stacking a large number of dielectric layers 20 and internal electrodes in this manner, the inner layer portion 60 is formed. In the laminate 2, the portion where the first internal electrodes 30 and the second internal electrodes 31 are alternately stacked with the dielectric layers 20 interposed therebetween is called the inner layer portion 60.

[0014] (Inner layer portion 60 and side gap portion) The portions arranged to sandwich the inner layer portion 60 in the stacking direction 102 and made of ceramic material are called outer layer portions 61. As shown in Figure 2, the outer layer portions 61 are located on both sides of the inner layer portion 60 in the stacking direction 102.

[0015] (Side Gap Portion) Figure 5 is a cross-sectional view taken along line 203-203 in Figure 1. As shown in Figures 2 and 5, the portions arranged to sandwich the inner layer portion 60 and the outer layer portion 61 in the width direction 101 are called side gap portions 70. The side gap portions 70 are mainly made of a ceramic material. The side gap portions 70 are located on both sides of the inner layer portion 60 in the width direction 101.

[0016] (Dielectric Layer 20) The dielectric layer 20 is disposed so as to be sandwiched between the first internal electrode 30 and the second internal electrode 31. The dielectric layer 20 is composed of dielectric ceramic particles having a perovskite structure, with a perovskite-type compound containing barium and titanium as the main component, for example. At least one of silicon, magnesium, and barium may also be added as an additive to these main components. The additive is usually distributed between the ceramic particles. The thickness of the dielectric layer 20 is, for example, 0.2 μm or more and 10 μm or less.

[0017] (Internal Electrodes) The internal electrodes include a first internal electrode 30 and a second internal electrode 31. The first internal electrode 30 is an internal electrode that is extended to the first end face 14 of the laminate 2. The second internal electrode 31 is an internal electrode that is extended to the second end face 15 of the laminate 2. FIG. 4 is a cross-sectional view taken along line 202-202 in FIG. 1. As shown in FIG. 4, the internal electrodes extend in the length direction 100 and have a rectangular shape when viewed from the stacking direction 102. FIG. 4 shows the second internal electrode 31 as an internal electrode.

[0018] The first internal electrode 30 and the second internal electrode 31 are disposed on different dielectric layers 20 .

[0019] The internal electrodes are formed by sintering a conductive paste containing metal powder as a conductor, an organic solvent, a binder, and a dispersant on the dielectric layer 20. The internal electrodes and the dielectric layers 20 are alternately stacked to form the inner layer portion 60 described above.

[0020] The material of the internal electrodes may be, for example, nickel, copper, silver, palladium, a silver-palladium alloy, gold, etc. These metals may also be compounds containing these metal elements or alloys with other metals.

[0021] The thickness of the internal electrodes is not particularly limited, but may be, for example, about 0.3 μm to 1.5 μm.

[0022] The inner layer portion 60, outer layer portion 61, side gap portion 70, and glass region 80 in the multilayer ceramic capacitor 1 of this embodiment will be described below with further reference to Figure 6. Figure 6 is a cross-sectional view taken along line 204-204 in Figure 1. (Inner layer portion 60) As shown in Figure 6, in the inner layer portion 60, first inner electrodes 30 and second inner electrodes 31 are alternately stacked with dielectric layers 20 interposed therebetween. The inner layer portion 60 enables the multilayer ceramic capacitor 1 to ensure sufficient capacitance.

[0023] On the first side surface 12 side and the second side surface 13 side of the inner layer portion 60, the first side surface side end portion 32 of the first internal electrode 30 and the second side surface side end portion 33 of the second internal electrode 31 are exposed.

[0024] 3 , on the first end face 14 side of the inner layer portion 60, the first end face side end portion 34 of the first inner electrode 30 is exposed and is covered by the first outer electrode 40. On the second end face 15 side of the inner layer portion 60, the second end face side end portion 35 of the second inner electrode 31 is exposed and is covered by the second outer electrode 41.

[0025] (Outer layer portion 61) The outer layer portions 61 are arranged above and below (on both sides of) the inner layer portion 60 in the stacking direction 102. The outer layer portions 61 are made of a dielectric ceramic material whose main component is, for example, barium titanate, calcium titanate, strontium titanate, calcium zirconate, or the like.

[0026] The outer layer portion 61 contains a glass component. The main component of the glass contained in the outer layer portion 61 is, for example, silicon dioxide, but is not limited to this.

[0027] The dimension (thickness) of the outer layer portion 61 in the stacking direction 102 is, for example, not less than 10 μm and not more than 80 μm, but is not limited to this.

[0028] (Glass Region) As shown in Fig. 6, at least one of the side gap portion 70 and the outer layer portion 61 has a glass region 80 in which glass is segregated in a layered form. The glass region 80 refers to a portion where the glass concentration (wt %, etc.) is significantly higher than in other portions. Specifically, elemental analysis of silicon (WDX, FE-WDX, etc.) was performed on a cross section of the glass region 80 at a position halfway along the length direction 100, in a plane parallel to the width direction 101 and the stacking direction 102. The glass region 80 was determined to be a portion where the silicon content was significantly higher than in the side gap portion 70 or the outer layer portion 61 where the glass region 80 was not formed.

[0029] (Inner Layer and Outer Layer) The innermost layer in the width direction 101 of the side gap portion 70 is called the inner layer 71. The outermost layer in the width direction 101 of the side gap portion 70 is called the outer layer 72.

[0030] (Method for observing the inner layer and the outer layer) The inner layer 71 and the outer layer 72 differ in the content and type of sintering-promoting elements and sintering-suppressing elements described below, and therefore the inner layer 71 and the outer layer 72 can be distinguished by elemental analysis.

[0031] In the multilayer ceramic capacitor 1 of this embodiment, the side gap portion 70 is configured from the outer layer 72 and the inner layer 71, but is not limited to this. For example, the side gap portion 70 may have an additional ceramic layer between the outer layer 72 and the inner layer 71.

[0032] In the multilayer ceramic capacitor 1 of this embodiment, the glass region 80 is disposed on the inner layer side 73 of the outer layer 72 in the width direction 101. Note that the arrangement of the glass region 80 is not limited to the inner layer 71 side of the outer layer 72.

[0033] (Inner Layer) The inner layer 71 is made of a dielectric ceramic material containing, as a main component, for example, barium titanate, calcium titanate, strontium titanate, calcium zirconate, etc. The inner layer 71 may also contain glass containing, as a main component, silicon dioxide.

[0034] The inner layer 71 may contain a sintering aid element. Examples of sintering aid elements include dysprosium, nickel, barium, boron, lithium, potassium, sodium, manganese, magnesium, holmium, calcium, and vanadium. The sintering aid element may be one type or two or more types.

[0035] The thickness of the inner layer 71 in the width direction 101 is preferably 0.1 μm or more and 10 μm or less.

[0036] (Outer Layer) The outer layer 72 is made of a dielectric ceramic material whose main component is, for example, barium titanate, calcium titanate, strontium titanate, calcium zirconate, etc. The outer layer 72 may also contain, for example, silicon dioxide as a glass component.

[0037] The thickness of the outer layer 72 in the width direction 101 is preferably 0.1 μm or more and 10 μm or less.

[0038] The outer layer 72 may contain a sintering promoting element, such as dysprosium, nickel, barium, boron, lithium, potassium, sodium, manganese, magnesium, holmium, calcium, or vanadium. The outer layer 72 may contain one or more sintering promoting elements.

[0039] (Comparison between outer layer and inner layer) The outer layer 72 has a higher content of sintering promoting elements than the inner layer 71. The content of the sintering promoting elements in the outer layer 72 is preferably 1.5 to 2.5 times the content of the sintering promoting elements in the inner layer 71.

[0040] The outer layer 72 having a higher content of sintering-promoting elements than the inner layer 71 has the following effect. That is, due to the difference in concentration of the sintering-promoting elements between the outer layer 72 and the inner layer 71, the sintering-promoting elements diffuse from the higher concentration to the lower concentration during firing. This creates a concentration gradient of the sintering-promoting elements or sintering-suppressing elements between the outer layer 72 near the surface of the laminate 2 and the inner layer 71 side of the outer layer 72, resulting in a difference in sinterability between the outer layer 72 near the surface of the laminate 2 and the inner layer 71 side of the outer layer 72. Glass has fluidity and flows to unsintered portions. As a result, the glass component can collect in areas that are difficult to sinter, forming glass regions 80.

[0041] In the multilayer ceramic capacitor 1 of this embodiment, by creating a difference in sinterability between the inner layer 71 and the outer layer 72, the outer layer 72 densifies before the inner layer 71, and the glass component of the outer layer 72 is expelled to the inner layer 71 side, forming a glass region 80 on the inner layer side 73 of the outer layer 72. This glass region 80 can trap moisture that penetrates through the side gap portion 70, preventing moisture from penetrating into the inner layer portion 60. In other words, moisture resistance reliability can be improved.

[0042] In addition to including the sintering-promoting element described above in the outer layer 72, the glass region 80 can also be formed by the following method (1) or (2). (1) Particle size of the outer layer (1) is a method of reducing the particle size of the outer layer 72. The particle size of the dielectric material in the outer layer 72 is preferably smaller than the particle size of the dielectric material in the inner layer 71. Specifically, the average particle size of the inner layer 71 relative to the average particle size of the outer layer 72 is preferably 1.2 times or more and 2 times or less.

[0043] The grain size comparison can be performed as follows: An SEM image of the laminate 2 is obtained in a cross section parallel to the width direction 101 and the stacking direction 102, so that the grain boundaries are visible. Then, the maximum grain size and the average grain size are measured, thereby measuring the grain sizes of the inner layer 71 and the outer layer 72 and allowing a comparison of the grain sizes.

[0044] In the multilayer ceramic capacitor 1 of this embodiment, the grain size of the outer layer 72 is further made smaller than that of the inner layer 71, thereby creating a difference in sinterability between the inner layer 71 and the outer layer 72, causing the outer layer 72 to densify before the inner layer 71, and the glass component of the outer layer 72 to be expelled to the inner layer 71 side, making it easier to form a glass region 80 on the inner layer side 73 of the outer layer 72. This glass region 80 can trap moisture that penetrates through the side gap portion 70, preventing moisture from penetrating into the inner layer portion 60. In other words, moisture resistance reliability can be improved.

[0045] (2) Effective Molar Ratio of Outer Layer (2) is a method of making the effective molar ratio of the outer layer 72 smaller than the effective molar ratio of the inner layer 71. The effective molar ratio of the outer layer 72 is preferably smaller than the effective molar ratio of the inner layer 71. The effective molar ratio can be calculated using the following formula: Effective Molar Ratio = (Calcium Molar Ratio + Barium Molar Ratio) / (Titanium Molar Ratio + Zirconium Molar Ratio) Calcium, barium, titanium, and zirconium can be measured by elemental analysis.

[0046] In the multilayer ceramic capacitor 1 of this embodiment, by further setting the effective molar ratio of the outer layer 72 smaller than the effective molar ratio of the inner layer 71, it is possible to easily form a glass region 80 on the inner layer 71 side 74 of the outer layer 72 by a process similar to that of the grain size of the outer layer 72 described above in (1). This glass region 80 can trap moisture that penetrates through the side gap portion 70, thereby suppressing moisture penetration into the inner layer portion 60. In other words, it is possible to improve moisture resistance reliability.

[0047] (Glass Region) In the multilayer ceramic capacitor 1 of this embodiment, the glass region 80 is a segregation of glass that is disposed on the inner layer side 73 of the outer layer 72 and extends in the stacking direction 102, and has a higher silicon content than the side gap portion 70 and the outer layer portion 61 where the glass region 80 is not disposed.

[0048] In the multilayer ceramic capacitor 1 of this embodiment, the glass region 80 is disposed on the inner layer side 73 of the outer layer 72 in the width direction 101 .

[0049] (Inner layer side of outer layer) The inner layer side 73 of the outer layer 72 refers to the region from the boundary between the outer layer 72 and the inner layer 71 toward the surface of the laminate 2 in the width direction 101, which is 0 μm or more and 10 μm or less, but is not necessarily limited to this range.

[0050] The glass region 80 is formed by creating a difference in sinterability between the inner layer 71 and the outer layer 72. More specifically, the difference in sinterability causes a difference in firing rate, so that the fluid glass flows to the unsintered portions, and as a result, the glass components gather in the portions that are difficult to sinter, forming the glass region 80. In the multilayer ceramic capacitor 1 of this embodiment, by creating a difference in sinterability between the inner layer 71 and the outer layer 72, the outer layer 72 densifies before the inner layer 71, and the glass components of the outer layer 72 are expelled to the inner layer 71 side, forming the glass region 80 on the inner layer 71 side of the outer layer 72.

[0051] As a result, in the multilayer ceramic capacitor 1 of this embodiment, the glass region 80 is disposed on the inner layer side 73 of the outer layer 72 .

[0052] When elemental analysis using a wavelength dispersive X-ray fluorescence analyzer (WDX) or the like is performed on a cross section in a plane parallel to the width direction 101 and stacking direction 102 at a position in the length direction 100, i.e., at a position halfway along the length direction 100, the inner layer 71 and the outer layer 72 can be distinguished from each other based on the type and content of the sintering-promoting element in the side gap portion 70. This makes it possible to confirm through elemental analysis that silicon derived from the glass region 80 is present in the observed outer layer 72 in a portion close to the inner layer 71, i.e., on the inner layer side 73 of the outer layer 72.

[0053] In outer layer 72, glass region 80 is disposed within the widely distributed sintering promoting elements, so that silicon derived from glass region 80 and the sintering promoting elements of outer layer 72 are distributed in an overlapping manner on inner layer side 73 of outer layer 72. This makes it possible to more reliably ensure moisture resistance reliability.

[0054] The thickness of glass region 80 may be 0.1 μm or more and 10 μm or less. The total dimension of glass region 80 in width direction 101 may be 50% or more of the dimension of laminate 2 in width direction 101. The total dimension of glass region 80 in width direction 101 means the sum of the dimension of glass region 80 located on the first side surface 12 side of inner layer portion 60 and the dimension of glass region 80 located on the second side surface 13 side.

[0055] The glass component of glass region 80 may be the same as the glass component contained in outer layer 72. In other words, elemental components specific to outer layer 72 may be confirmed from the region where glass region 80 is observed. Specifically, at least one or more types of sintering-promoting elements added to outer layer 72 may be detected from the same location as glass region 80.

[0056] These can be detected by performing elemental analysis such as WDX on a cross section parallel to the width direction 101 and stacking direction 102 at a position half the length of the length direction 100.

[0057] The formation of the glass region 80 can prevent moisture from entering through the side gap portion 70, improving the moisture resistance reliability.

[0058] The glass region 80 on the inner layer side 73 of the outer layer 72 may be continuous or partially interrupted, but is more preferably continuous in the stacking direction 102. In other words, it is preferable that the glass region 80 is continuous in the stacking direction 102 without any interruptions.

[0059] Since the glass region 80 is continuous, the glass region 80 can trap moisture regardless of which part of the side gap portion 70 the moisture has entered from, thereby ensuring higher moisture resistance reliability.

[0060] The glass region 80 contains a larger amount of glass components than the side gap portion 70 and the outer layer portion 61 where the glass region 80 is not disposed.

[0061] (Method for detecting boundary between inner layer and outer layer) A method for detecting the boundary between the inner layer 71 and the outer layer 72 will be described. Because the type and content of the sintering-promoting element differ between the inner layer 71 and the outer layer 72, the boundary between the inner layer 71 and the outer layer 72 can be confirmed at a position where the difference in the type and content of the sintering-promoting element is significant in a cross section at a position half the length of the length direction 100, parallel to the width direction 101 and the stacking direction 102.

[0062] (Method for detecting glass region) Glass region 80 was subjected to elemental analysis of silicon (WDX, FE-WDX, etc.) in a cross section in a plane parallel to width direction 101 and stacking direction 102 at a position half the dimension in length direction 100, and the portion where the silicon content was significantly higher than that of side gap portion 70 or outer layer portion 61 where glass region 80 was not formed was detected as glass region 80.

[0063] (External Electrode) The external electrode includes a first external electrode 40 connected to the first internal electrode 30 and covering the first end face 14, and a second external electrode 41 connected to the second internal electrode 31 and covering the second end face 15.

[0064] The first external electrode 40 is disposed so as to cover the first end face 14 of the laminate 2 and to be connected to the internal electrode extended to the first end face 14. Specifically, the first external electrode 40 is preferably disposed so as to extend to parts of the first main face 10 and the second main face 11, and parts of the first side face 12 and the second side face 13. However, the first external electrode 40 may be disposed only on the first end face 14.

[0065] The first external electrode 40 has a first base electrode layer 42 disposed on the first end face 14 and a plating layer covering the first base electrode layer 42 .

[0066] The first base electrode layer 42 includes at least one selected from a baked layer, a resin layer, and a thin film layer. The first base electrode layer 42 covers the first end face 14 of the laminate 2 and is arranged so as to be connected to the internal electrode extended to the first end face 14. Specifically, the first base electrode layer 42 is preferably provided so as to extend to a part of the first main face 10, a part of the second main face 11, and a part of the first side face 12 and a part of the second side face 13, but may be arranged only on the first end face 14.

[0067] The second external electrode 41 is disposed so as to cover the second end face 15 of the laminate 2 and to be connected to the internal electrode extended to the second end face 15. Specifically, it is preferable that the second external electrode 41 be disposed so as to extend to parts of the first main face 10 and the second main face 11, and parts of the first side face 12 and the second side face 13. However, the second external electrode 41 may be disposed only on the second end face 15.

[0068] The second external electrode 41 has a second base electrode layer 45 disposed on the second end face 15 and a plating layer covering the second base electrode layer 45 .

[0069] The second base electrode layer 45 includes at least one selected from a baked layer, a resin layer, and a thin film layer. The second base electrode layer 45 covers the second end face 15 of the laminate 2 and is arranged so as to be connected to the internal electrode extended to the second end face 15. Specifically, the second base electrode layer 45 is preferably provided so as to extend to a part of the first main face 10, a part of the second main face 11, a part of the first side face 12, and a part of the second side face 13, but may be arranged only on the second end face 15.

[0070] (When the first and second base electrode layers are baking layers) A case where the first and second base electrode layers 42 and 45 are baking layers will be described. The baking layer contains glass and metal. The glass contains at least one selected from boron, silicon, barium, magnesium, aluminum, lithium, and the like. The metal of the baking layer contains at least one selected from copper, nickel, silver, palladium, a silver-palladium alloy, gold, and the like, for example.

[0071] The baked layer may be formed of multiple layers. The baked layer is formed by applying a conductive paste containing glass and metal to the laminate 2 and baking it. The baked layer may be baked simultaneously with the internal electrodes or may be baked after the internal electrodes are baked. The thickness of the baked layer (at its thickest point) is preferably 10 μm or more and 50 μm or less.

[0072] (When the First Base Electrode Layer and the Second Base Electrode Layer are Resin Layers) A case where the first base electrode layer 42 and the second base electrode layer 45 are resin layers will be described. The resin layer contains, for example, conductive particles and a thermosetting resin. When forming a resin layer, the resin layer may be formed directly on the laminate 2 without forming a baking layer, or the resin layer may be formed so as to cover the baking layer. For example, the resin layer may be formed on the surface of the baking layer, or may be formed directly on the surface of the first end face 14 or the second end face 15 without forming a baking layer. The resin layer may be formed in multiple layers. The thickness of the resin layer (at its thickest point) is preferably 10 μm or more and 150 μm or less.

[0073] (When the first and second base electrode layers are thin film layers) A case where the first and second base electrode layers 42 and 45 are thin film layers will be described. The thin film layer is formed by a thin film formation method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness where metal particles are deposited.

[0074] (Plating Layer) The plating layer includes a first plating layer and a second plating layer. The first plating layer is disposed so as to cover the first base electrode layer 42. The second plating layer is disposed so as to cover the second base electrode layer 45.

[0075] The plating layer contains, for example, at least one selected from copper, nickel, silver, palladium, a silver-palladium alloy, gold, and the like.

[0076] The plating layer may be formed of multiple layers. Preferably, it has a two-layer structure of nickel plating and tin plating. In the multilayer ceramic capacitor 1 of this embodiment, the first plating layer includes a first nickel plating layer 43 and a first tin plating layer 44. The second plating layer includes a second nickel plating layer 46 and a second tin plating layer 47.

[0077] The nickel plating layer can prevent the base electrode layer from being eroded by solder when mounting the multilayer ceramic capacitor, and the tin plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor, facilitating mounting. For example, the thickness of each nickel plating layer or tin plating layer is preferably 0.5 μm or more and 10 μm or less.

[0078] (Size of Multilayer Ceramic Capacitor) The multilayer ceramic capacitor 1 is composed of a laminate 2 and external electrodes covering end faces of the laminate 2. The size of the multilayer ceramic capacitor 1 of this embodiment, that is, the size of the multilayer ceramic capacitor 1 including the external electrodes, is, for example, as follows: When expressed as "dimension in the length direction 100 × dimension in the width direction 101 × dimension in the stacking direction 102," it is generally expected that the size will be, for example, "1.6 mm × 0.8 mm × 0.8 mm," "1.0 mm × 0.5 mm × 0.5 mm," "0.6 mm × 0.3 mm × 0.3 mm," "0.4 mm × 0.2 mm × 0.2 mm," or "0.2 mm × 0.1 mm × 0.1 mm," but is not limited to the above sizes.

[0079] (Method of Manufacturing Multilayer Ceramic Capacitor) A method of manufacturing the multilayer ceramic capacitor 1 will be described with reference to FIGS. 7 to 9. FIGS. 7 to 9 are all diagrams for explaining the method of manufacturing the multilayer ceramic capacitor 1. FIG. 7 is a diagram showing ceramic green sheets on which conductive films are formed. FIG. 8 is a diagram showing how the ceramic green sheets on which conductive films are formed are stacked. FIG. 9 is a diagram showing the appearance of the laminate chip 210. (1) Mixing First, a perovskite-type compound containing barium and titanium is prepared as a dielectric material. A dielectric powder obtained from this dielectric material is mixed with silicon and magnesium as additives, as well as an organic binder, an organic solvent, a plasticizer, and a dispersant in predetermined proportions to prepare a ceramic slurry.

[0080] (2) Sheet Forming Next, the prepared ceramic slurry is applied to the surfaces of a plurality of resin films to prepare a first ceramic green sheet 200 and a second ceramic green sheet 201. The second ceramic green sheet 201 is laminated alternately with the first ceramic green sheet 200. The first ceramic green sheet 200 and the second ceramic green sheet 201 can be prepared using, for example, a die coater, a gravure coater, a microgravure coater, or the like.

[0081] (3) Internal Electrode Printing Next, as shown in FIG. 7 , a conductive paste for internal electrodes is printed in stripes on the surfaces of the first ceramic green sheet 200 and the second ceramic green sheet 201 and then dried. FIG. 7 shows only the first ceramic green sheet 200. The second ceramic green sheet 201 has the same configuration as the first ceramic green sheet 200. The conductive paste for internal electrodes contains, for example, nickel. Here, the direction in which the conductive paste for internal electrodes extends in stripes is defined as a first direction 110, and the direction perpendicular to the first direction 110 on the ceramic green sheet is defined as a second direction 111. In this manner, a first conductive film 202 that will become the first internal electrode 30 and a second conductive film 203 that will become the second internal electrode 31 are formed. Various printing methods, such as screen printing, inkjet printing, and gravure printing, can be used.

[0082] (4) Lamination Next, the produced ceramic green sheets are laminated as shown in Fig. 8. Specifically, after laminating a predetermined number of ceramic green sheets that do not have a conductive film formed thereon and that will become the outer layer portion 61, a plurality of first ceramic green sheets 200 and second ceramic green sheets 201 that have a first conductive film 202 and a second conductive film 203 formed thereon are laminated while being shifted from each other in the second direction 111. Then, a predetermined number of ceramic green sheets that do not have a conductive film formed thereon and that will become the outer layer portion 61 are laminated thereon to obtain a mother laminate.

[0083] (5) Pressing and Cutting Next, the mother laminate is pressed using a method such as a rigid press or a hydrostatic press. The pressed mother laminate is then cut into a chip shape to obtain a laminate chip 210. As shown in FIG. 9 , only the first conductive film 202 of the first ceramic green sheet 200 is exposed on one end surface of the laminate chip 210, and only the second conductive film 203 of the second ceramic green sheet 201 is exposed on the other end surface. Furthermore, the first conductive film 202 of the first ceramic green sheet 200 and the second conductive film 203 of the second ceramic green sheet 201 are exposed on both side surfaces of the laminate chip 210.

[0084] (6) Formation of Side Gap Section Sheets Next, ceramic green sheets for the side gap section 70 are prepared. A perovskite-type compound containing barium and titanium is prepared as a dielectric material for preparing the ceramic green sheets for the side gap section 70. A dielectric powder obtained from this dielectric material is mixed with an additive containing silicon and magnesium, an organic binder, an organic solvent, a plasticizer, and a dispersant in predetermined proportions to prepare a ceramic slurry. Then, using the prepared ceramic slurry, ceramic green sheets for forming the outer layer 72 and ceramic green sheets for forming the inner layer 71 are prepared. Next, a ceramic green sheet for the inner layer 71 is laminated and bonded onto the ceramic green sheet for the outer layer 72 to obtain a two-layer ceramic green sheet for the side margin section.

[0085] (7) Formation of Side Gap Portion Next, among the ceramic green sheets for the side gap portion 70, the ceramic green sheet for the inner layer 71 is placed opposite the side surface of the laminate chip 210 where the first conductive film 202 and the second conductive film 203 are exposed, and the ceramic green sheet is pressed against the side surface and punched out to form a layer that will become the side gap portion 70. A layer that will become the side gap portion 70 is also formed on the opposite side surface using a similar method. Here, in the multilayer ceramic capacitor 1 of this embodiment, ceramic green sheets for the inner layer 71 and the outer layer 72 are used, in which the outer layer 72 contains a larger amount of sintering-promoting elements than the inner layer 71.

[0086] (8) Barrel Polishing and Firing Next, the laminate chip 210 on which the layer that will become the side gap portion 70 is formed is subjected to barrel polishing. The laminate chip 210 is then degreased under predetermined conditions in a nitrogen atmosphere, and then fired at a predetermined temperature in a nitrogen-hydrogen-water vapor mixed atmosphere. This results in a sintered laminate 2.

[0087] (9) Formation of External Electrodes Next, an external electrode paste containing copper as a main component is applied to each of the end faces of the sintered laminate 2 and baked to form a first base electrode layer 42 connected to the first internal electrode 30 and a second base electrode layer 45 connected to the second internal electrode 31.

[0088] Next, a first nickel plating layer 43 is formed by nickel plating on the surface of the first base electrode layer 42, and a first tin plating layer 44 is formed by tin plating on the surface of the first nickel plating layer 43, thereby forming the first external electrode 40. In a similar manner, a second nickel plating layer 46 is formed on the surface of the second base electrode layer 45, and a second tin plating layer 47 is formed on the surface of the second nickel plating layer 46, thereby forming the second external electrode 41.

[0089] However, in the above description, the laminated chip 210 and the external electrode paste may be fired simultaneously.

[0090] Second Embodiment A multilayer ceramic capacitor 1 according to a second embodiment will be described with reference to FIG. 10 . FIG. 10 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the second embodiment, taken along a plane parallel to the width direction 101 and the lamination direction 102. FIG. 10 corresponds to FIG. 6 for the first embodiment. FIG. 10 is a cross-sectional view taken at a position halfway along the length direction 100. The following description will focus on differences between the second embodiment and the first embodiment. Items not specifically mentioned in the following description are the same as those in the first embodiment.

[0091] (Side Gap Portion) The side gap portion 70 includes an inner layer 71 and an outer layer 72. The inner layer 71 may include a sintering promoting element. Examples of the sintering promoting element include the same elements as those in the first embodiment. The sintering promoting element may be one type or two or more types.

[0092] The content of the sintering promoting element in the inner layer 71 is greater than the content of the sintering promoting element in the dielectric layer 20. The content of the sintering promoting element in the inner layer 71 is preferably 1.5 to 2.5 times the content of the sintering promoting element in the dielectric layer 20.

[0093] The difference in the concentration of the sintering-promoting element between the dielectric layer 20 and the inner layer 71 causes the sintering-promoting element to diffuse from the higher concentration to the lower concentration during firing. This creates a concentration gradient of the sintering-promoting element between the outer layer side 75 of the inner layer 71 and the inner layer side 74 of the inner layer 71, resulting in a difference in sinterability between the outer layer side 75 of the inner layer 71 and the inner layer side 74 of the inner layer 71. Glass has fluidity and flows to unsintered portions. As a result, the glass component can concentrate in areas that are difficult to sinter, forming a glass region 80. In the multilayer ceramic capacitor 1 of this embodiment, the difference in sinterability between the inner layer 71 and the dielectric layer 20 causes the inner layer 71 to densify before the dielectric layer 20. The glass component of the inner layer 71 is expelled to the inner layer side 60, forming a glass region 80 on the inner layer side 60 of the inner layer 71. This glass region 80 can trap moisture that penetrates through the side gap portion 70, preventing moisture from penetrating into the inner layer portion 60. That is, the moisture resistance reliability can be improved.

[0094] In addition to including the sintering promoting element in the inner layer 71, the glass region 80 can also be formed by the following method (1) or (2).

[0095] (1) Particle size of the inner layer (1) is a method that uses the difference in particle size of the inner layer 71. The particle size of the inner layer 71 will be explained. The particle size of the dielectric material of the inner layer 71 is preferably smaller than the particle size of the dielectric material of the dielectric layer 20. Specifically, the average particle size of the dielectric material of the inner layer 71 is preferably 1.2 times or more and 2 times or less.

[0096] By obtaining an SEM image of a plane parallel to the width direction 101 and stacking direction 102 so that the grain boundaries are visible, measuring the maximum grain size of the grains, and measuring the average grain size, it is possible to measure the grain sizes of the inner layer 71 and the dielectric layer 20 and compare the grain sizes.

[0097] In the multilayer ceramic capacitor 1 of this embodiment, the grain size of the inner layer 71 is further made smaller than the grain size of the dielectric layer 20, thereby creating a difference in sinterability between the inner layer 71 and the inner layer portion 60. This causes the inner layer 71 to densify before the dielectric layer 20, and the glass component of the inner layer 71 is expelled to the inner layer portion 60 side, making it easier to form a glass region 80 on the inner layer portion side 74 of the inner layer 71. This glass region 80 can trap moisture that penetrates from the side gap portion 70, preventing moisture from penetrating into the inner layer portion 60. In other words, moisture resistance reliability can be improved.

[0098] (2) Effective Molar Ratio of Inner Layer (2) is a method that uses the effective molar ratio of the inner layer 71. The effective molar ratio of the inner layer 71 will be explained. The effective molar ratio of the inner layer 71 is preferably smaller than the effective molar ratio of the dielectric layer 20. The effective molar ratio can be calculated by the following formula: Effective molar ratio = (calcium molar ratio + barium molar ratio) / (titanium molar ratio + zirconium molar ratio)

[0099] In the multilayer ceramic capacitor 1 of this embodiment, by further setting the effective molar ratio of the inner layer 71 smaller than the effective molar ratio of the dielectric layer 20, it is possible to easily form a glass region 80 on the inner layer portion side 74 of the inner layer 71 by a process similar to that of (1) above, i.e., adjusting the grain size of the inner layer 71. This glass region 80 can trap moisture that penetrates from the side gap portion 70, thereby suppressing moisture penetration into the inner layer portion 60. In other words, it is possible to improve moisture resistance reliability.

[0100] (Outer Layer) The outer layer 72 is made of a dielectric ceramic material whose main component is, for example, barium titanate, calcium titanate, strontium titanate, calcium zirconate, etc. The main component of the glass contained in the outer layer 72 is, for example, silicon dioxide, but is not limited to this.

[0101] The outer layer 72 may contain a sintering promoting element or a sintering inhibiting element. The sintering promoting element may be the same as that in the first embodiment. The sintering promoting element may be one type or two or more types. The thickness of the outer layer 72 is preferably 0.1 μm or more and 10 μm or less.

[0102] (Glass Region) In this embodiment, the glass region 80 is a segregation of glass that is disposed near the boundary between the inner layer 71 and the inner layer portion 60 and extends in the stacking direction 102, and has a higher silicon content than the side gap portion 70 and the outer layer portion 61 where the glass region 80 is not disposed.

[0103] In the multilayer ceramic capacitor 1 of this embodiment, the glass region 80 is disposed on the inner layer portion side 74 of the inner layer 71 in the width direction 101 .

[0104] The inner layer side 74 of the inner layer 71 refers to the region from the boundary between the inner layer 71 and the inner layer 60 toward the surface of the laminate 2 in the width direction 101, which is 0 μm or more and 10 μm or less, but is not necessarily limited to this range.

[0105] The glass region 80 is formed by creating a difference in sinterability between the inner layer 71 and the dielectric layer 20. More specifically, the difference in sinterability causes a difference in firing rate, so that the fluid glass flows to the unsintered portions, and as a result, the glass component gathers in the portions that are difficult to sinter, forming the glass region 80. In the multilayer ceramic capacitor 1 of this embodiment, by creating a difference in sinterability between the inner layer 71 and the dielectric layer 20, the inner layer 71 densifies before the dielectric layer 20, and the glass component of the inner layer 71 is expelled to the inner layer portion 60 side, forming the glass region 80 on the inner layer portion 60 side of the inner layer 71.

[0106] In the multilayer ceramic capacitor 1 of this embodiment, a glass region 80 is disposed on the inner layer portion side 74 of the inner layer 71. The glass region 80 can be confirmed as follows. When elemental analysis such as WDX is performed on a cross section in a plane parallel to the width direction 101 and the stacking direction 102 at a position halfway along the length direction 100, the inner layer 71 and the dielectric layer 20 can be distinguished from each other based on the difference in the type and content of the sintering-promoting element in the side gap portion 70. This makes it possible to confirm through elemental analysis that silicon derived from the glass region 80 is present in the observed inner layer 71 in a portion close to the inner layer 71.

[0107] In the inner layer 71, the sintering-promoting elements are distributed in a larger amount than in the inner layer portion 60, and the glass region 80 is arranged therein. Therefore, on the inner layer side 74 of the inner layer 71, silicon derived from the glass region 80 and the sintering-promoting elements of the inner layer 71 are distributed in an overlapping manner.

[0108] This ensures reliable moisture resistance. The multilayer ceramic capacitor 1 of the second embodiment also achieves improved moisture resistance reliability similar to that of the multilayer ceramic capacitor 1 of the first embodiment.

[0109] The thickness of glass region 80 may be 0.1 μm or more and 10 μm or less. The total dimension of glass region 80 in width direction 101 may be 50% or more of the dimension of laminate 2 in width direction 101. The total dimension of glass region 80 in width direction 101 means the sum of the dimension of glass region 80 located on the first side surface 12 side of inner layer portion 60 and the dimension of glass region 80 located on the second side surface 13 side.

[0110] The glass component of glass region 80 may be the same as the glass component contained in inner layer 71. In other words, elemental components specific to inner layer 71 may be confirmed from the region where glass region 80 is observed. Specifically, at least one or more types of sintering promoting elements added to inner layer 71 may be detected from the same location as glass region 80.

[0111] As a detection method, it can be confirmed by performing elemental analysis such as WDX on a cross section in a plane parallel to the width direction 101 and the stacking direction 102 at a position half the size in the length direction 100.

[0112] The formation of the glass region 80 can prevent moisture from entering through the side gap portion 70, improving the moisture resistance reliability.

[0113] The glass region 80 on the inner layer portion side 74 of the inner layer 71 may be continuous or partially interrupted, but is more preferably continuous in the stacking direction 102. In other words, it is preferable that the glass region 80 is continuous in the stacking direction 102 without any interruptions.

[0114] This allows the glass region 80 to trap moisture regardless of which part of the side gap portion 70 the moisture has entered from, thereby ensuring higher moisture resistance reliability.

[0115] (Manufacturing Method) The manufacturing method of the multilayer ceramic capacitor 1 of the second embodiment differs from the manufacturing method of the multilayer ceramic capacitor 1 of the first embodiment in the following points. The manufacturing method of the first embodiment can be used for matters not specifically described below. (7) Formation of Side Gap Portion The manufacturing method of the multilayer ceramic capacitor 1 of the second embodiment differs from the manufacturing method of the multilayer ceramic capacitor 1 of the first embodiment in the process of forming the side gap portion. To form the side gap portion, a ceramic green sheet for the inner layer 71, one of the ceramic green sheets for the side gap portion 70, is placed opposite the side surface of the laminate chip 210 on which the first conductive film 202 and the second conductive film 203 are exposed, and the ceramic green sheet is pressed against the side surface and punched out to form the layer that will become the side gap portion 70. A layer that will become the side gap portion 70 is also formed on the opposite side surface in a similar manner.

[0116] Here, in the multilayer ceramic capacitor 1 of this embodiment, ceramic green sheets for the inner layer 71 and the outer layer 72 are used, in which the inner layer 71 contains a larger amount of sintering-promoting elements than the dielectric layer 20. This allows a glass region 80 to be formed on the inner layer side 74 of the inner layer 71.

[0117] Third Embodiment A multilayer ceramic capacitor 1 according to a third embodiment will be described with reference to FIG. 11 . FIG. 11 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the third embodiment, taken along a plane parallel to the width direction 101 and the lamination direction 102. FIG. 11 corresponds to FIG. 6 for the first embodiment. FIG. 11 is a cross-sectional view taken at a position halfway along the length direction 100. The following description of the first embodiment will focus on differences from the first or second embodiment. Items not specifically mentioned in the following description are the same as those in the first or second embodiment.

[0118] In the multilayer ceramic capacitor 1 of the third embodiment, a glass region 80 is formed on the inner layer portion side 76 (dielectric layer 20 side) of the outer layer portion 61. (Outer Layer Portion) The outer layer portion 61 may contain a sintering promoting element. Examples of sintering promoting elements include dysprosium, nickel, barium, boron, lithium, potassium, sodium, manganese, magnesium, holmium, calcium, and vanadium. The sintering promoting element may be one type or two or more types. The outer layer portion 61 has a higher content of the sintering promoting element than the dielectric layer 20. The content of the sintering promoting element in the outer layer portion 61 is preferably 1.5 to 2.5 times the content of the sintering promoting element in the dielectric layer 20.

[0119] The difference in sintering-promoting element concentration between the dielectric layer 20 and the outer layer portion 61 causes the sintering-promoting element to diffuse from the higher concentration to the lower concentration during firing. This creates a concentration gradient of the sintering-promoting element between the surface side 77 of the laminate 2 of the outer layer portion 61 and the inner layer portion side 76 of the outer layer portion 61, resulting in a difference in sinterability between the surface side 77 of the laminate 2 of the outer layer portion 61 and the inner layer portion side 76 of the outer layer portion 61. Glass has fluidity and flows to unsintered portions, resulting in the glass component concentrating in the difficult-to-sinter portion, forming a glass region 80. In the multilayer ceramic capacitor 1 of this embodiment, the difference in sinterability between the outer layer portion 61 and the dielectric layer 20 causes the outer layer portion 61 to densify before the dielectric layer 20, and the glass component of the outer layer portion 61 is expelled to the inner layer portion 60, forming a glass region 80 on the inner layer portion side 76 of the outer layer portion 61. The glass region 80 can trap moisture that penetrates from the main surface or the side gap portion 70, thereby suppressing moisture penetration into the inner layer portion 60. In other words, moisture resistance reliability can be improved.

[0120] In addition to including the above-described sintering-promoting element in the outer layer portion 61 in a larger amount than in the dielectric layer 20, the glass region 80 can also be formed by the following method (1) or (2). (1) Adjusting the Grain Size of the Outer Layer Portion The formation of the glass region 80 by adjusting the grain size of the outer layer portion 61 will be described. The grain size of the outer layer portion 61 is preferably smaller than that of the dielectric layer 20. Specifically, the average grain size of the dielectric layer 20 relative to that of the outer layer portion 61 is preferably 1.2 times or more and 2 times or less.

[0121] The grain size can be confirmed as follows: An SEM image of a plane parallel to the width direction 101 and the stacking direction 102 is obtained, in which the grain boundaries are visible, and the maximum grain size and the average grain size are measured, thereby measuring the grain sizes of the outer layer portion 61 and the dielectric layer 20 and comparing the grain sizes.

[0122] In the multilayer ceramic capacitor 1 of this embodiment, the grain size of the outer layer portion 61 is further made smaller than the grain size of the dielectric layer 20, thereby creating a difference in sinterability between the outer layer portion 61 and the inner layer portion 60. This causes the outer layer portion 61 to densify before the dielectric layer 20, and the glass component of the outer layer portion 61 is expelled to the inner layer portion 60 side, making it easier to form a glass region 80 on the inner layer portion side 76 of the outer layer portion 61. This glass region 80 can trap moisture that penetrates through the side gap portion 70, preventing moisture from penetrating into the inner layer portion 60. In other words, moisture resistance reliability can be improved.

[0123] (2) Adjustment of Effective Molar Ratio of Outer Layer Portion The formation of the glass region 80 by adjusting the effective molar ratio of the outer layer portion 61 will be described. The effective molar ratio of the outer layer portion 61 is preferably smaller than the effective molar ratio of the dielectric layer 20. The effective molar ratio can be calculated by the following formula: Effective molar ratio = (calcium molar ratio + barium molar ratio) / (titanium molar ratio + zirconium molar ratio)

[0124] In the multilayer ceramic capacitor 1 of this embodiment, by further making the effective molar ratio of the outer layer portion 61 smaller than the effective molar ratio of the dielectric layer 20, it is possible to easily form a glass region 80 on the inner layer portion side 76 of the outer layer portion 61 by a process similar to the adjustment of the grain size of the outer layer portion 61 in (1) above. This glass region 80 can trap moisture that penetrates through the side gap portion 70, thereby suppressing moisture penetration into the inner layer portion 60. In other words, it is possible to improve moisture resistance reliability.

[0125] (When a Glass Region is Formed Other Than on the Dielectric Layer Side) In the multilayer ceramic capacitor 1 of this embodiment, as a modified example, the glass region 80 can be formed on a portion other than the inner layer portion side 76 (dielectric layer 20 side) of the outer layer portion 61. That is, the glass region 80 may be disposed in a position other than the inner layer portion 60 side of the outer layer portion 61. This will be described with reference to FIG. 12. FIG. 12 is a cross-sectional view of a modified example of the multilayer ceramic capacitor 1. As shown in FIG. 12, the glass region 80 may be disposed in a portion that is half the dimension of the outer layer portion 61 in the stacking direction 102 (a central portion 78 of the outer layer portion 61 in the stacking direction). Such a configuration can be achieved by stacking and firing two or more types of ceramic green sheets having different contents of sintering-promoting elements for the outer layer.

[0126] (Glass Region) The glass region 80 of this embodiment is a segregation of glass disposed in the outer layer portion 61 and extending in the width direction 101, and contains a higher silicon content than the side gap portion 70 and the outer layer portion 61 where the glass region 80 is not disposed. In the multilayer ceramic capacitor 1 of this embodiment, the glass region 80 is disposed in the outer layer portion 61. Specifically, the glass region 80 is disposed on the inner layer portion side 76 of the outer layer portion 61, but the location where the glass region 80 is disposed may be any location in the outer layer portion 61, such as near a position halfway along the stacking direction 102 of the outer layer portion 61.

[0127] When the glass region 80 is positioned at any position in the outer layer portion 61, a multilayer ceramic capacitor having the glass region 80 formed at any position in the outer layer portion 61 can be manufactured by stacking any number of ceramic green sheets for the outer layer having different types or contents of sintering-promoting elements.

[0128] In the multilayer ceramic capacitor 1 of this embodiment, the inner layer side 76 of the outer layer portion 61 refers to the region extending from the boundary between the outer layer portion 61 and the inner layer portion 60 toward the surface of the laminate 2 in the stacking direction 102, which is 0 μm or more and 10 μm or less, but is not necessarily limited to this range.

[0129] The glass region 80 is formed by creating a difference in sinterability between the outer layer portion 61 and the dielectric layer 20, or between the outer layer portions 61 themselves. More specifically, the difference in sinterability causes a difference in firing rate, so that fluid glass flows to unsintered portions, and as a result, the glass component gathers in areas that are difficult to sinter, forming the glass region 80. In the multilayer ceramic capacitor 1 of this embodiment, by creating a difference in sinterability between the outer layer portion 61 and the dielectric layer 20, the outer layer portion 61 densifies before the dielectric layer 20, and the glass component of the outer layer portion 61 is expelled to the inner layer portion 60 side, forming the glass region 80 on the inner layer portion side 76 of the outer layer portion 61.

[0130] In the multilayer ceramic capacitor 1 of this embodiment, as described above, the glass region 80 is disposed on the inner layer portion side 76 of the outer layer portion 61. The glass region 80 can be confirmed as follows. That is, when elemental analysis such as WDX is performed on a cross section in a plane parallel to the width direction 101 and the stacking direction 102 at a position halfway along the length direction 100, the outer layer portion 61 and the dielectric layer 20 can be distinguished from each other based on the difference in the type and content of the sintering-promoting element in the side gap portion 70. This makes it possible to confirm through elemental analysis that silicon derived from the glass region 80 is present in the observed outer layer portion 61 in a portion close to the inner layer portion 60.

[0131] In outer layer portion 61, the sintering promoting elements are distributed more widely than in inner layer portion 60, and glass region 80 is disposed therein, so that silicon derived from glass region 80 and the sintering promoting elements of inner layer 71 are distributed in an overlapping manner on inner layer portion side 76 of outer layer portion 61. This ensures more reliable moisture resistance.

[0132] The thickness of glass region 80 may be 0.1 μm or more and 10 μm or less. The total dimension of glass region 80 in stacking direction 102 may be 50% or more of the dimension of stack 2 in stacking direction 102. The total dimension of glass region 80 in stacking direction 102 means the sum of the dimension of glass region 80 located on the first main surface 10 side and the dimension of glass region 80 located on the second main surface 11 side with respect to inner layer portion 60.

[0133] The glass component of glass region 80 may be the same as the glass component contained in outer layer portion 61. In other words, elemental components specific to outer layer portion 61 may be confirmed from the region where glass region 80 is observed. Specifically, at least one or more types of sintering-promoting elements added to outer layer portion 61 may be detected from the same location as glass region 80.

[0134] As a detection method, it can be confirmed by performing elemental analysis such as WDX on a cross section in a plane parallel to the width direction 101 and the stacking direction 102 at a position half the size in the length direction 100.

[0135] By forming the glass region 80 in the outer layer portion 61, it is possible to prevent moisture from entering from the main surface, thereby improving the moisture resistance reliability.

[0136] The glass region 80 on the inner layer portion side 76 of the outer layer portion 61 may be continuous or partially interrupted, but is more preferably continuous in the width direction 101. This is also true even if the glass region 80 is disposed at any position in the outer layer portion 61. In other words, it is preferable that the glass region 80 is continuous in the width direction 101 without any interruptions.

[0137] With this configuration, regardless of which part of first main surface 10 or second main surface 11 the moisture has penetrated from, or even for moisture that has penetrated from side gap portion 70, glass region 80 can easily trap the moisture, thereby ensuring higher moisture resistance reliability. This is because glass region 80 contains a larger amount of glass components than side gap portion 70 and outer layer portion 61 where glass region 80 is not disposed.

[0138] (Manufacturing Method) The manufacturing method of the multilayer ceramic capacitor 1 of the third embodiment will be described below in terms of differences from the manufacturing methods of the multilayer ceramic capacitor 1 of the first and second embodiments. For matters not specifically described below, the manufacturing methods of the first and second embodiments can be used.

[0139] The manufacturing method of the multilayer ceramic capacitor 1 of the third embodiment differs from the manufacturing methods of the multilayer ceramic capacitor 1 of the first and second embodiments in the lamination step. In the lamination step, the prepared ceramic green sheets are laminated. Specifically, after a predetermined number of ceramic green sheets that do not have a conductive film formed thereon and that will become the outer layer portion 61 are laminated, a plurality of first ceramic green sheets 200 that have a first conductive film 202 formed thereon and a plurality of second ceramic green sheets 201 that have a second conductive film 203 formed thereon are laminated while being shifted from each other in the second direction 111. Then, a predetermined number of ceramic green sheets that do not have a conductive film formed thereon and that will become the outer layer portion 61 are laminated on top of the first ceramic green sheets to obtain a mother laminate.

[0140] In the multilayer ceramic capacitor 1 of this embodiment, the ceramic green sheets that form the outer layer portions 61 and that have no conductive film formed thereon contain a larger amount of sintering-promoting elements than the ceramic green sheets that form the dielectric layers 20 of the inner layer portions 60. When forming the glass region 80 at a desired position in the outer layer portions 61, two or more types of ceramic green sheets that form the outer layers and have no conductive film formed thereon and that differ in the type and content of the sintering-promoting elements are prepared, and these are laminated as the ceramic green sheets that form the outer layer portions 61, thereby making it possible to manufacture the multilayer ceramic capacitor 1 in which the glass region 80 is formed at a desired position.

[0141] Although the present invention has been described above as an embodiment, it is not limited to the above-described embodiment, and various changes, modifications, and combinations are possible.

[0142] For example, the glass region 80 of the first embodiment and the glass region 80 of the third embodiment may be formed simultaneously. Similarly, the glass region 80 of the second embodiment and the glass region 80 of the third embodiment may be formed simultaneously. These configurations can more reliably ensure high moisture resistance reliability.

[0143] As described above, in the multilayer ceramic capacitor 1 according to each embodiment of the present invention, the glass region 80 is present in at least one of the side gap portion 70 and the outer layer portion 61, and therefore moisture that has penetrated from the outside can be trapped by the glass (glass region 80). In other words, moisture penetration is restricted to the portion where the glass region 80 is present, and therefore moisture penetration into the inner layer portion 60 can be restricted. This makes it possible to suppress problems caused by moisture penetration and ensure high moisture resistance reliability.

[0144] <1> A laminate having a plurality of laminated dielectric layers and a plurality of internal electrodes laminated on the dielectric layers, the laminate having first and second main surfaces opposing each other in a lamination direction, first and second side surfaces opposing each other in a width direction perpendicular to the lamination direction, and first and second end surfaces opposing each other in a length direction perpendicular to the lamination direction and the width direction, the plurality of internal electrodes having first internal electrodes extended to the first end surfaces and second internal electrodes extended to the second end surfaces, a first external electrode connected to the first internal electrodes and covering the first end surfaces, and a second external electrode connected to the second internal electrodes and covering the second end surfaces, the laminate comprising: an inner layer portion in which the first internal electrodes and the second internal electrodes are alternately laminated with the dielectric layers interposed therebetween; and outer layer portions arranged to sandwich the inner layer portion in the lamination direction and made of a ceramic material. and side gap portions arranged to sandwich the inner layer portions and the outer layer portions in the width direction, wherein a glass region in which glass is segregated exists in at least one of the side gap portions or the outer layer portions.

[0145] <2> The multilayer ceramic capacitor according to <1>, wherein the side gap portion has an inner layer that is an innermost layer in the width direction and an outer layer that is an outermost layer in the width direction, and the glass region is disposed on the inner layer side of the outer layer in the width direction.

[0146] <3> The multilayer ceramic capacitor according to <2>, wherein the outer layer contains at least one sintering-promoting element selected from dysprosium, nickel, barium, boron, lithium, potassium, sodium, manganese, magnesium, holmium, calcium, and vanadium in a larger amount than the inner layer, and a distribution position of the glass region and a distribution position of the sintering-promoting element contained in the outer layer at least partially overlap with each other.

[0147] <4> The multilayer ceramic capacitor according to <2> or <3>, wherein the glass region is disposed on the inner layer portion side of the inner layer in the width direction.

[0148] <5> The multilayer ceramic capacitor according to <3> or <4>, wherein the inner layer contains a larger amount of the sintering promoting element than the dielectric layer, and a distribution position of the glass region and a distribution position of the sintering promoting element contained in the inner layer at least partially overlap with each other.

[0149] <6> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein the glass region is disposed in the outer layer portion.

[0150] <7> The multilayer ceramic capacitor according to <6>, wherein the outer layer portion contains a sintering promoting element in a larger amount than the dielectric layer, and a distribution position of the glass region and a distribution position of the sintering promoting element contained in the outer layer portion at least partially overlap with each other.

[0151] <8> The multilayer ceramic capacitor according to any one of <1> to <7>, wherein the glass region contains a larger amount of glass component than the side gap portion and the outer layer portion where the glass region is not disposed.

[0152] REFERENCE SIGNS LIST 1 multilayer ceramic capacitor 2 laminate 20 dielectric layer 30 first internal electrode 31 second internal electrode 60 inner layer portion 61 outer layer portion 70 side gap portion 80 glass region 100 length direction 101 width direction 102 lamination direction

Claims

1. A laminate having a plurality of laminated dielectric layers and a plurality of internal electrodes laminated on the dielectric layers, the laminate having a first main surface and a second main surface opposing each other in a lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction; the plurality of internal electrodes having a first internal electrode extended to the first end surface and a second internal electrode extended to the second end surface, a first external electrode connected to the first internal electrode and covering the first end surface, and a second external electrode connected to the second internal electrode and covering the second end surface; the laminate comprising: an inner layer portion in which the first internal electrodes and the second internal electrodes are alternately laminated with the dielectric layers interposed therebetween; and outer layer portions arranged to sandwich the inner layer portion in the lamination direction and made of a ceramic material. and a side gap portion disposed so as to sandwich the inner layer portion and the outer layer portion in the width direction, wherein a glass region in which glass is segregated is present in at least one of the side gap portion and the outer layer portion.

2. The multilayer ceramic capacitor according to claim 1, wherein the side gap portion has an inner layer that is an innermost layer in the width direction and an outer layer that is an outermost layer in the width direction, and the glass region is disposed on a side of the outer layer facing the inner layer in the width direction.

3. The multilayer ceramic capacitor according to claim 2, wherein the outer layer contains at least one sintering-promoting element selected from dysprosium, nickel, barium, boron, lithium, potassium, sodium, manganese, magnesium, holmium, calcium, and vanadium in a greater amount than the inner layer, and the distribution position of the glass region and the distribution position of the sintering-promoting element contained in the outer layer at least partially overlap.

4. The multilayer ceramic capacitor according to claim 2 or 3, wherein the glass region is disposed on the inner layer portion side of the inner layer in the width direction.

5. The multilayer ceramic capacitor according to claim 3 or 4, wherein the inner layer contains a larger amount of the sintering-promoting element than the dielectric layer, and the distribution positions of the glass regions and the distribution positions of the sintering-promoting element contained in the inner layer at least partially overlap.

6. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein the glass region is disposed in the outer layer portion.

7. The multilayer ceramic capacitor according to claim 6, wherein the outer layer portion contains a larger amount of a sintering promoting element than the dielectric layer, and a distribution position of the glass region and a distribution position of the sintering promoting element contained in the outer layer portion at least partially overlap each other.

8. The multilayer ceramic capacitor according to claim 1, wherein the glass region contains a larger amount of glass component than the side gap portion and the outer layer portion in which the glass region is not disposed.

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