Test apparatus and test method

Abstract

Provided is a test apparatus comprising an input unit that is connected to a device under test and receives a signal to be tested from the device under test, and a function test unit that tests a function of the device under test on the basis of the signal to be tested, the function test unit having a timing measurement unit that measures the timing of an edge of the input signal, the input unit having a current measurement unit that outputs a current measurement signal corresponding to the current value of the signal to be tested, and a first input switching unit that switches whether or not to input the current measurement signal to the function test unit, and the timing measurement unit measuring the pulse width of the current measurement signal on the basis of the timing of the edge of the current measurement signal that is input to the function test unit.

Description

Testing equipment and testing method

[0001] The present invention relates to a testing device and a testing method.

[0002] Patent Documents 1 and 2 describe LED display driver circuits and the like. [Prior Art Documents] [Patent Documents] Patent Document 1: U.S. Patent Application Publication No. 2022 / 0208076 Patent Document 2: U.S. Patent No. 11,302,248 General disclosure

[0003] In a first aspect of the present invention, a test apparatus is provided which comprises an input section connected to a device under test and which receives a signal under test from the device under test, and a functional testing section which performs a functional test of the device under test based on the signal under test, wherein the functional testing section has a timing measurement section which measures the timing of the edge of the input signal, and the input section has a current measurement section which outputs a current measurement signal corresponding to the current value of the signal under test, and a first input switching section which switches whether the current measurement signal is input to the functional testing section, and wherein the timing measurement section measures the pulse width of the current measurement signal based on the timing of the edge of the current measurement signal input to the functional testing section.

[0004] In the above-mentioned test apparatus, the input section may further include a voltage measurement section that outputs a voltage measurement signal corresponding to the voltage value of the signal under test, and the first input switching section may select either the voltage measurement signal or the current measurement signal and input it to the functional testing section.

[0005] In the above test apparatus, the input section may further include a level comparison circuit that inputs a signal according to a result of comparison between the signal level of the signal selected by the first input switching section and a reference value to the functional test section.

[0006] Any of the above test apparatuses may further comprise a DC test section that performs a DC test on the device under test based on at least one of the voltage measurement signal and the current measurement signal.

[0007] In any of the above test devices, the input section may further include a second input switching section that selects either the voltage measurement signal or the current measurement signal and inputs it to the DC test section.

[0008] In any of the above test apparatuses, the input section may receive the signal under test from a probe card that contacts the device under test.

[0009] In any of the above test devices, the functional testing unit may further include a digital comparison unit that determines whether a logic pattern corresponding to the input signal matches an expected value pattern, and when measuring the pulse width of the current measurement signal, the digital comparison unit may receive the current measurement signal, and the timing measurement unit may measure the pulse width of the current measurement signal based on the timing of the edge of the current measurement signal in response to the digital comparison unit determining that the logic pattern corresponding to the current measurement signal matches the expected value pattern.

[0010] Any of the above test apparatuses may further comprise a control section that sets different reference values ​​in the level comparison circuit when a functional test of the device under test is performed and when the pulse width of the current measurement signal is measured.

[0011] The above test apparatus may further include a DC test unit that measures the signal level of the current measurement signal, the level comparison circuit compares each of the first reference value and the second reference value with the signal level of the signal selected by the first input switching unit, and the control unit, when measuring the pulse width of the current measurement signal, may set the first reference value larger than the signal level measured by the DC test unit and the second reference value smaller than the signal level measured by the DC test unit.

[0012] In any of the above test devices, the timing measurement section may measure at least one of the jitter, frequency, and slew rate of the current measurement signal based on the timing of an edge of the current measurement signal input to the functional test section.

[0013] In a second aspect of the present invention, there is provided a test method executed by a test apparatus, the test method comprising the steps of receiving a signal under test from a device under test, outputting a current measurement signal corresponding to the current value of the signal under test, switching whether or not to input the current measurement signal to a functional testing section of the test apparatus, and measuring the pulse width of the current measurement signal based on the timing of the edge of the current measurement signal input to the functional testing section.

[0014] In the above test method, the step of measuring the pulse width of the current measurement signal may include a step of determining whether a logic pattern corresponding to the current measurement signal input to the functional testing section matches an expected value pattern, and a step of measuring the pulse width of the current measurement signal based on the timing of the edges of the current measurement signal in response to determining that the logic pattern matches the expected value pattern.

[0015] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions.

[0016] 1 shows a test apparatus 10 according to the present embodiment; FIG. 2 is a diagram for explaining an example of a signal under test tested by the test apparatus 10; FIG. 3 shows an example of the operation of the test apparatus 10 according to the present embodiment; FIG. 4 shows another example of the operation of the test apparatus 10 according to the present embodiment; and FIG. 5 shows an example of the relationship between signals in the test apparatus 10.

[0017] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0018] FIG. 1 shows a test apparatus 10 according to the present embodiment. The test apparatus 10 transmits and receives electrical signals to and from a device under test (DUT) 20 to test the DUT. The test apparatus 10 performs a functional test and a DC test on the DUT 20. In the functional test, the test apparatus 10 may determine whether the DUT 20 is functioning normally based on a signal under test Sout output by the DUT 20. The test apparatus 10 may perform a functional test on the DUT 20 based on the waveform of the signal under test Sout over time. More specifically, the test apparatus 10 may perform a functional test based on the pattern (logic pattern) of digital values ​​indicated by the signal under test Sout, or may perform a functional test based on AC characteristics such as edge timing of the signal under test Sout. In the DC test, the test apparatus 10 may determine whether the DC levels of the input / output currents or the DC levels of the input / output voltages of the DUT 20 are within a predetermined range. The test apparatus 10 may perform a DC test on the device under test 20 based on the DC level of the power supply current or power supply voltage applied to the device under test 20. The test apparatus 10 may be, for example, automatic test equipment (ATE).

[0019] The test apparatus 10 according to the present embodiment tests the device under test 20 based on the pulse width of the signal under test Sout output by the device under test 20. The test apparatus 10 may test a display driver (for example, a micro LED driver) as the device under test 20. The display driver may output a current signal having a duty ratio (i.e., pulse width) according to the brightness of the display to be driven. The test apparatus 10 may determine whether the device under test 20 is good or bad based on the pulse width of the current signal.

[0020] The test apparatus 10 includes a probe card 100, an input section 200, a DC test section 300, a functional test section 400, and a control section 500. During testing, the probe card 100 electrically connects the input section 200 and the device under test 20, enabling transmission and reception of signals between the test apparatus 10 and the device under test 20. The probe card 100 has a plurality of probe pins that contact a plurality of pins under test of the device under test 20, and a substrate on which the plurality of probe pins are provided. The substrate is provided with wiring that electrically connects each probe pin to the input section 200. The probe card 100 may be replaceable by a user of the test apparatus 10, for example. For example, the probe card 100 is replaced for each type of device under test 20.

[0021] The input section 200 is connected to the device under test 20 and receives the signal under test Sout from the device under test 20. The input section 200 may receive the signal under test Sout from a probe card 100 that is in contact with the device under test 20. The input section 200 includes a connection switching section 210, a voltage measuring section 220, a current measuring section 230, a current output section 240, a second input switching section 250, an AD conversion section 260, a first input switching section 270, and a level comparison circuit 280. The test apparatus 10 may include a plurality of input sections 200 corresponding to a plurality of pins under test of the device under test 20.

[0022] The connection switching section 210 is connected to the device under test 20, the current measuring section 230, and the voltage measuring section 220. The connection switching section 210 connects the device under test 20 to one of the current measuring section 230 and the voltage measuring section 220. The connection switching section 210 has a first switch 212 and a second switch 214. One end of the first switch 212 is connected to the device under test 20, and the other end is connected to the voltage measuring section 220. When the first switch 212 is turned on, it connects the device under test 20 to the voltage measuring section 220. One end of the second switch 214 is connected to a node between the first switch 212 and the device under test 20, and the other end is connected to the current measuring section 230. When the second switch 214 is turned on, it connects the device under test 20 to the current measuring section 230.

[0023] The output terminal of the voltage measurement section 220 is connected to the first input switching section 270 and the second input switching section 250. The voltage measurement section 220 outputs a voltage measurement signal Svm corresponding to the voltage value of the signal under test Sout. The voltage measurement section 220 may output the voltage measurement signal Svm at the same signal level (voltage level) as the signal under test Sout, or may output the voltage measurement signal Svm by amplifying the signal level (voltage level) of the signal under test Sout. The voltage measurement section 220 may include an operational amplifier.

[0024] The output terminal of the current measuring section 230 is connected to the first input switching section 270 and the second input switching section 250. The current measuring section 230 outputs a current measurement signal Sim corresponding to the current value of the signal under test Sout. The current measuring section 230 may convert the signal under test Sout into a voltage signal and output the current measurement signal Sim. The current measuring section 230 of this example outputs a current measurement signal Sim with a higher signal level (voltage level) as the current value of the signal under test Sout increases. The current measuring section 230 may include an operational amplifier.

[0025] The current output section 240 is connected to a node between the second switch 214 and the current measuring section 230. In a DC test, the current output section 240 outputs a DC signal for the test to the device under test 20. The current output section 240 may output a DC signal of a predetermined current value to the device under test 20 via the connection switching section 210.

[0026] The output terminal of the second input switching unit 250 is connected to the AD conversion unit 260. The second input switching unit 250 selects either the voltage measurement signal Svm output by the voltage measurement unit 220 or the current measurement signal Sim output by the current measurement unit 230. The second input switching unit 250 inputs the selected signal to the DC testing unit 300 via the AD conversion unit 260.

[0027] The output terminal of the AD conversion unit 260 is connected to the DC testing unit 300. The AD conversion unit 260 converts an input analog signal into a digital signal and outputs the digital signal. The AD conversion unit 260 may convert the signal selected by the second input switching unit 250 from the voltage measurement signal Svm and the current measurement signal Sim into a digital signal. The AD conversion unit 260 outputs the converted digital signal to the DC testing unit 300.

[0028] The first input switching unit 270 is connected to the level comparison circuit 280. The first input switching unit 270 selects either the voltage measurement signal Svm or the current measurement signal Sim, and switches whether or not to input it to the functional testing unit 400. The first input switching unit 270 has a third switch 272. One side of the third switch 272 is connected to the voltage measurement unit 220 and the current measurement unit 230, and the other side is connected to the level comparison circuit 280. The third switch 272 switches the connection between the voltage measurement unit 220 and the level comparison circuit 280 and the connection between the current measurement unit 230 and the level comparison circuit 280, and inputs either the voltage measurement signal Svm or the current measurement signal Sim to the level comparison circuit 280.

[0029] The level comparison circuit 280 is connected to the functional testing section 400. The level comparison circuit 280 inputs to the functional testing section 400 a signal corresponding to the comparison result between the signal level (amplitude) of the signal selected by the first input switching section 270 and a reference value. The level comparison circuit 280 may compare the signal level of the signal output by the first input switching section 270 with a first reference value and a second reference value, and output a first comparison result signal Sc1 and a second comparison result signal Sc2 corresponding to the comparison result to the functional testing section 400 via different lines. The first reference value may be greater than the second reference value. The level comparison circuit 280 includes a first reference value setting section 282, a first comparing section 284, a second reference value setting section 286, and a second comparing section 288.

[0030] The first reference value setting section 282 is connected to one input of the first comparing section 284 and sets the first reference value to the first comparing section 284. The first reference value setting section 282 may be a DA converter that converts an input digital signal into an analog signal. The first reference value setting section 282 may receive a digital signal indicative of the first reference value and output an analog signal corresponding to the digital signal to the first comparing section 284. As a result, a voltage corresponding to the first reference value is applied to one input of the first comparing section 284.

[0031] The first comparing section 284 has the other input connected to the first input switching section 270 and the output connected to the functional testing section 400. The first comparing section 284 compares the signal level of the signal output by the first input switching section 270 with a voltage corresponding to a first reference value applied to the other input. The first comparing section 284 may output a first comparison result signal Sc1 that changes to a first logic (for example, H) when the signal level of the signal output by the first input switching section 270 changes to or exceeds the first reference value, and that changes to a second logic (for example, L) when the signal level changes to or falls below the first reference value.

[0032] The second reference value setting section 286 is connected to one input of the second comparing section 288 and sets the second reference value to the second comparing section 288. The second reference value setting section 286 may be a DA converter that converts an input digital signal into an analog signal. The second reference value setting section 286 may receive a digital signal indicative of the second reference value and output an analog signal corresponding to the digital signal to the second comparing section 288. As a result, a voltage corresponding to the second reference value is applied to one input of the second comparing section 288.

[0033] The second comparing section 288 has the other input connected to the first input switching section 270 and the output connected to the functional testing section 400. The second comparing section 288 compares the signal level of the signal output by the first input switching section 270 with a voltage corresponding to a second reference value applied to the other input. The second comparing section 288 may output a second comparison result signal Sc2 that changes to a first logic (for example, H) when the signal level of the signal output by the first input switching section 270 changes to or exceeds the second reference value, and that changes to a second logic (for example, L) when the signal level changes to or falls below the second reference value.

[0034] The DC testing section 300 performs a DC test on the device under test 20 based on at least one of the voltage measurement signal Svm and the current measurement signal Sim. When a digital signal corresponding to the voltage measurement signal Svm is input to the DC testing section 300, the DC testing section 300 may measure the voltage value of the signal output by the device under test 20. When a digital signal corresponding to the current measurement signal Sim is input to the DC testing section 300, the DC testing section 300 may measure the current value of the signal output by the device under test 20. When a current is output to the device under test 20 by the current output section 240, the DC testing section 300 can measure the load current, etc. of the device under test 20. The DC testing section 300 may form a digitizer together with the AD conversion section 260. The DC testing section 300 may include a digital computing unit that processes digital data, a memory that stores the digital data, a communication unit that communicates with the control section 500, etc.

[0035] The functional testing section 400 performs a functional test of the device under test 20 based on the signal under test Sout. The functional testing section 400 may perform a functional test of the device under test 20 based on at least one of the voltage measurement signal Svm and the current measurement signal Sim. The test apparatus 10 performs pulse width measurement of the signal under test Sout using at least a portion of the configuration of the functional testing section 400. By using the functional testing section 400 for pulse width measurement in addition to functional testing, it is possible to perform pulse width measurement while suppressing an increase in the device size of the test apparatus 10. The functional testing section 400 performs pulse width measurement of the signal under test Sout based on the current measurement signal Sim. The functional testing section 400 includes a digital comparing section 410 and a timing measuring section 420.

[0036] The digital comparing section 410 performs a functional test of the device under test 20 based on at least one of the voltage measurement signal Svm and the current measurement signal Sim. The digital comparing section 410 determines whether a logic pattern corresponding to the input signal matches an expected value pattern. For example, when a functional test of a semiconductor memory is performed as the device under test 20, the digital comparing section 410 determines whether the logic pattern of digital data read from the device under test 20 matches an expected value pattern. When the digital comparing section 410 receives at least one of a first comparison result signal Sc1 and a second comparison result signal Sc2 corresponding to the voltage measurement signal Svm or the current measurement signal Sim from the level comparing circuit 280, the digital comparing section 410 may compare the logic pattern of the received signal with the expected value pattern to determine whether they match.

[0037] The digital comparator 410 samples the logical value of at least one of the first comparison result signal Sc1 and the second comparison result signal Sc2 in each bit interval. A bit interval is an interval in the signal where one bit of data occupies. For example, the digital comparator 410 samples the logical value of the signal in the center of each bit interval. The sampling period of the digital comparator 410 may be the same as the length of the bit interval of the signal.

[0038] The timing measurement section 420 measures the timing of the edges of the input signal. In a functional test, the timing measurement section 420 may measure at least one of the jitter, frequency, and slew rate of the voltage measurement signal Svm or the current measurement signal Sim based on the timing of the edges of the voltage measurement signal Svm or the current measurement signal Sim input to the functional testing section 400.

[0039] The timing measurement section 420 may measure the jitter of the voltage measurement signal Svm or the current measurement signal Sim (i.e., the signal under test Sout). Jitter refers to fluctuations in the edge timing of the signal under test Sout. The larger the jitter, the smaller the eye opening of the signal under test Sout. In a functional test, the functional testing section 400 may determine whether the magnitude of the jitter of the signal under test Sout is within an acceptable range.

[0040] At least one of the first comparison result signal Sc1 and the second comparison result signal Sc2 is input to the timing measurement section 420. The timing measurement section 420 samples the logical value of the input signal at a period shorter than the length of the bit section of the input signal. As an example, the sampling period of the timing measurement section 420 is 1 / 10 or less of the length of the bit section. The timing measurement section 420 may determine the timing at which the sampled logical value transitions as the timing of an edge of the input signal.

[0041] In the functional test, the timing measurement section 420 may measure the magnitude of the gradient of the edge of the voltage measurement signal Svm or the current measurement signal Sim (i.e., the signal under measurement Sout). The timing measurement section 420 may measure the magnitude of the gradient of the edge of the signal under measurement Sout from the difference between the edge timing of the first comparison result signal Sc1 output by the first comparing section 284 and the edge timing of the second comparison result signal Sc2 output by the second comparing section 288. The edge timing of the first comparison result signal Sc1 is the timing at which the signal level of the signal under measurement Sout reaches a first reference value, and the edge timing of the second comparison result signal Sc2 is the timing at which the signal level of the signal under measurement Sout reaches a second reference value. The gradient of the edge of the signal under measurement Sout can be calculated by dividing the difference between the first and second reference values ​​by the difference in edge timing.

[0042] The timing measuring section 420 may calculate the magnitude of the gradient of the edge of the signal under measurement Sout as the slew rate (i.e., the rate of change in amplitude of the signal under measurement Sout with respect to time (di / dt)).

[0043] In addition, in the functional test, the timing measurement section 420 may measure the frequency of the voltage measurement signal Svm or the current measurement signal Sim (i.e., the signal under measurement Sout). The timing measurement section 420 may measure the timing of an edge at which the logical value changes for at least one of the first comparison result signal Sc1 and the second comparison result signal Sc2, and calculate the frequency from the timing of the edge.

[0044] The test apparatus 10 may use the timing measurement section 420 of the functional testing section 400 when measuring the pulse width of the current signal output by the device under test 20. In this case, the timing measurement section 420 measures the pulse width of the current measurement signal Sim based on the timing of the edges of the current measurement signal Sim input to the functional testing section 400. The functional testing section 400 of this example receives a first comparison result signal Sc1 and a second comparison result signal Sc2 generated from the current measurement signal Sim. The timing measurement section 420 measures the timing of the edges at which the logical value of at least one of the first comparison result signal Sc1 and the second comparison result signal Sc2 changes. The timing measurement section 420 may measure the pulse width of the current measurement signal Sim by calculating the interval between two adjacent edges in the time direction from the measurement result. The timing measurement section 420 may determine whether the measured pulse width satisfies a set condition.

[0045] In another example, the test apparatus 10 may use the digital comparing section 410 of the functional testing section 400 when measuring the pulse width of the current signal output by the device under test 20. The digital comparing section 410 may also sample the logical values ​​of the first comparison result signal Sc1 and the second comparison result signal Sc2 at a predetermined sampling period. The digital comparing section 410 may calculate the period during which a predetermined logical value (e.g., H) continues in the first comparison result signal Sc1 or the second comparison result signal Sc2 as the pulse width of the current signal.

[0046] The sampling period in the timing measurement section 420 is shorter than the sampling period in the digital comparison section 410. Therefore, the timing measurement section 420 can measure the pulse width of the current signal more accurately than the digital comparison section 410. On the other hand, the digital comparison section 410 can measure the pulse width of the current signal faster than the timing measurement section 420.

[0047] The control unit 500 is connected to the input unit 200, the DC testing unit 300, and the functional testing unit 400. The control unit 500 may transmit control signals to the input unit 200, the DC testing unit 300, and the functional testing unit 400 in accordance with a test program. The control unit 500 may also transmit instructions to the input unit 200 to connect or disconnect the multiple switches included in the connection switching unit 210 and the first input switching unit 270 in accordance with the test program.

[0048] The DC testing section 300 may be provided for each input section 200, or may be provided in common to the plurality of input sections 200. When a common DC testing section 300 is provided for the plurality of input sections 200, the DC testing section 300 may measure signals input from each input section 200 in sequence. The functional testing section 400 may be provided for each input section 200, or may be provided in common to the plurality of input sections 200. When a common functional testing section 400 is provided for the plurality of input sections 200, the functional testing section 400 may measure signals input from each input section 200 in sequence.

[0049] 2 is a diagram illustrating an example of a signal under test Sout tested by the test apparatus 10. FIG. 2 shows a signal output by a micro LED driver, with the vertical axis representing current value and the horizontal axis representing time. The micro LED driver outputs a signal with a pulse width (pulse width a, pulse width b, and pulse width c in FIG. 2) corresponding to the luminance for each frame in which the image on the display switches. The test apparatus 10 of this embodiment can accurately measure the pulse width of the signal under test Sout using the timing measurement unit 420 or the digital comparison unit 410 used in functional testing.

[0050] 3 shows an example of the operation of the test apparatus 10 of this embodiment. In this embodiment, the test apparatus 10 tests the pulse width of the signal under test Sout output by the device under test 20. The test apparatus 10 starts the test under the control of the control unit 500. The test apparatus 10 causes the device under test 20 to output the signal under test Sout having a set pulse width.

[0051] In step S1300, the control unit 500 turns off the first switch 212 and turns on the second switch 214. The control unit 500 also controls the third switch 272 to input the current measurement signal Sim to the level comparison circuit 280. The level comparison circuit 280 outputs a first comparison result signal Sc1 and a second comparison result signal Sc2. The first and second reference values ​​set in the first and second reference value setting units 282 and 286 may be the same as or different from those used when a functional test is performed.

[0052] The timing measurement section 420 measures the timing of the rising edge and the falling edge of at least one of the first comparison result signal Sc1 and the second comparison result signal Sc2. The timing measurement section 420 may store timestamps indicating the timing of each edge. For example, the timing measurement section 420 detects the logical value of the comparison result signal in each cycle of the clock signal. The timing measurement section 420 stores timestamps indicating in which cycle of the clock signal the edge was detected. The timing measurement section 420 may use the stored timestamps to calculate the interval between the rising and falling edges of the signal as the pulse width. For example, the timing measurement section 420 calculates the pulse width of the current measurement signal Sim by subtracting the average value of the rising time of the first comparison result signal Sc1 and the rising time of the second comparison result signal Sc2 from the average value of the falling time of the first comparison result signal Sc1 and the falling time of the second comparison result signal Sc2.

[0053] The timing measurement section 420 may store, as a timestamp, the number of cycles of the clock signal counted from a reference time such as the test start time or a reference cycle of the clock signal. The timing measurement section 420 may indicate the pulse width of the current signal using the number of cycles of the clock signal.

[0054] In step S1400, the timing measurement section 420 determines whether the difference between the pulse width calculated in step S1300 and the expected value of the pulse width is within a predetermined reference range. The timing measurement section 420 may receive and store the expected value of the pulse width in advance from the control section 500, such as at the start of testing. If the timing measurement section 420 determines that the difference between the calculated pulse width and the expected value is within the predetermined reference range (Yes in step S1400), it may output a pass signal to the control section 500 indicating that the device under test 20 is not defective (step S1500). On the other hand, if the timing measurement section 420 determines that the difference between the calculated pulse width and the expected value is not within the predetermined reference range (No in step S1400), it may output a fail signal to the control section 500 indicating that the device under test 20 is defective (step S1600).

[0055] FIG. 4 shows another example of the operation of the test apparatus 10 of this embodiment. Similar to the example of FIG. 3 , the test apparatus 10 of this example also tests the pulse width of the signal under test Sout (current signal) output by the device under test 20. Steps S1300 and S1400 in FIG. 4 are the same as those in the example of FIG. 3 . In addition to the steps shown in FIG. 3 , the test apparatus 10 of this example further executes steps S1000 to S1200. The control unit 500 of this example sets different reference values ​​in the level comparison circuit 280 when performing a functional test of the device under test 20 and when measuring the pulse width of the current measurement signal Sim. The control unit 500 may set the first and second reference values ​​in the level comparison circuit 280 depending on the signal level of the current measurement signal Sim.

[0056] In step S1000, the test apparatus 10 measures the DC signal level of the signal under test Sout using the DC testing section 300. The control section 500 controls the input section 200 to input the signal under test Sout from the device under test 20 to the DC testing section 300. For example, the control section 500 controls the first switch 212 to be off and the second switch 214 to be on, thereby connecting the current measuring section 230 to the AD conversion section 260.

[0057] The DC testing section 300 measures the signal level of the input current measurement signal Sim. The DC testing section 300 may receive a digital signal indicating the signal level of the current measurement signal Sim from the AD conversion section 260, measure the signal level (voltage value), and supply it to the control section 500. The control section 500 may then set a first reference value and a second reference value in the level comparison circuit 280 based on the signal level supplied from the DC testing section 300. The control section 500 may set the first reference value to be greater than the signal level measured by the DC testing section 300. The control section 500 may set the second reference value to be smaller than the signal level measured by the DC testing section 300. However, the second reference value may be greater than 0 V. The second reference value may be half the signal level of the current measurement signal Sim. The timing measurement section 420 of this example may calculate the pulse width of the current measurement signal Sim from the edge timing of the second comparison result signal Sc2. The digital comparator 410 may also determine whether the first comparison result signal Sc1 matches a predetermined expected value pattern (e.g., all L logic). This makes it possible to detect an abnormal state in which the signal level of the current measurement signal Sim is greater than a first reference value. The control unit 500 may also set the value obtained by subtracting a predetermined value m from the voltage value of the signal level as the first reference value, and the control unit 500 may set the value obtained by subtracting a predetermined value n (n > m) from the voltage value of the signal level as the second reference value.

[0058] In step S1100, the test apparatus 10 receives the signal under test Sout from the device under test 20 and performs a test using the digital comparing section 410. Step S1000 may be omitted and the process may start from step S1100. The control section 500 controls the input section 200 to input the signal under test Sout from the device under test 20 to the functional testing section 400. For example, the control section 500 controls the first switch 212 to be turned off and the second switch 214 to be turned on, and controls the third switch 272 of the first input switching section 270 to connect the current measuring section 230 to the level comparing circuit 280.

[0059] The level comparison circuit 280 compares the signal level of the current measurement signal Sim with a first reference value and a second reference value, respectively. The level comparison circuit 280 may output a first comparison result signal Sc1 and a second comparison result signal Sc2 corresponding to the comparison results from the first comparing section 284 and the second comparing section 288 to the functional testing section 400, respectively.

[0060] The digital comparing section 410 converts the input first comparison result signal Sc1 and second comparison result signal Sc2 into logic patterns (digital codes). For example, the digital comparing section 410 latches the first comparison result signal Sc1 and the second comparison result signal Sc2 at each sampling period and captures the latched data as a first logic pattern and a second logic pattern. The digital comparing section 410 may compare at least one of the first logic pattern and the second logic pattern with an expected value pattern pre-specified by the control section 500 and determine whether at least one of the first logic pattern and the second logic pattern matches the expected value pattern. The expected value pattern may be a logic pattern in which a range corresponding to a predetermined pulse width of the signal under test (a range in which the current measurement signal is H) is a first logic pattern (for example, 1) and another range (a range in which the current measurement signal is L) is a second logic pattern (for example, 0).

[0061] If the first reference value is greater than the signal level of the current measurement signal Sim and the second reference value is less than the signal level of the current measurement signal Sim, the first comparison result signal Sc1 indicates whether the signal level of the current measurement signal Sim exhibits an abnormal value, as described above. The digital comparator 410 may compare the first logic pattern of the first comparison result signal Sc1 with an expected value pattern that is maintained at a predetermined logic value (e.g., L) during the test period. The second comparison result signal Sc2 indicates the approximate timing of pulses of the current measurement signal Sim. For example, the second logic pattern of the second comparison result signal Sc2 has a predetermined first logic value (e.g., H) during periods when pulses of the current measurement signal Sim are present and a predetermined second logic value (e.g., L) during periods when pulses are not present. The digital comparator 410 may compare the second logic pattern of the second comparison result signal Sc2 with an expected value pattern that has a first logic value during periods when pulses are expected to be present and a second logic value during other periods.

[0062] When both the first and second reference values ​​are smaller than the signal level of the current measurement signal Sim, both the first comparison result signal Sc1 and the second comparison result signal Sc2 indicate the approximate timing of the pulses of the current measurement signal Sim. In this case, the digital comparator 410 may compare an expected value pattern, which is a first logical value during the period when a pulse is expected to exist and a second logical value during other periods, with the first logical pattern of the first comparison result signal Sc1 and the second logical pattern of the second comparison result signal Sc2.

[0063] If the digital comparing section 410 determines that both the first and second logic patterns match the expected pattern (Yes in step S1200), the test apparatus 10 proceeds to step S1300. On the other hand, if the digital comparing section 410 determines that at least one of the first and second logic patterns does not match the expected pattern (No in step S1200), the test apparatus 10 may output a fail signal to the control section 500 (step S1600). In this case, the test apparatus 10 may determine that the device under test 20 being tested is defective and terminate the test operation.

[0064] In step S1300, the timing measurement section 420 measures the pulse width of the current measurement signal Sim based on the timing of the edges of the current measurement signal Sim in response to the digital comparison section 410 determining in step S1200 that the logic pattern corresponding to the current measurement signal Sim matches the expected value pattern. The processing in step S1300 is similar to the example in FIG.

[0065] In step S1400, the timing measurement section 420 determines whether the difference between the pulse width calculated in step S1300 and the expected pulse width is within a predetermined reference range. The process in step S1400 is the same as that in the example of FIG.

[0066] 5 shows an example of the relationship between signals in the test apparatus 10. Temporal changes are shown for the current measurement signal Sim output by the current measuring section 230, the second comparison result signal Sc2 output by the second comparing section 288, the first comparison result signal Sc1 output by the first comparing section 284, the second logic pattern of the second comparison result signal Sc2 captured by the digital comparing section 410, and the clock signal input to the timing measuring section 420.

[0067] The current measurement signal Sim is a signal obtained by amplifying the signal under test Sout by the current measuring section 230, but has substantially the same pulse width as the signal under test Sout. The level comparison circuit 280 compares the current measurement signal Sim with a first reference value and a second reference value in the first comparing section 284 and the second comparing section 288, and outputs a first comparison result signal Sc1 and a second comparison result signal Sc2, respectively. The first comparison result signal Sc1 rises when the current measurement signal Sim changes from less than the first reference value to equal to or greater than the first reference value, and falls when it subsequently falls below the first reference value. The second comparison result signal Sc2 rises when the current measurement signal Sim changes from less than the second reference value to equal to or greater than the second reference value, and falls when it subsequently falls below the second reference value.

[0068] The second logic pattern of the second comparison result signal Sc2 is a pattern of 0s and 1s that is captured in each sampling period by the digital comparison section 410. The digital comparison section 410 captures a logic pattern of 1s when the second comparison result signal Sc2 is H and 0s when it is L. The digital comparison section 410 compares the logic pattern with the corresponding expected value pattern in each sampling period.

[0069] The timing measurement unit 420 stores a timestamp TS2 in response to the clock signal when the first comparison result signal Sc1 changes from L to H, and stores a timestamp TS3 in response to the clock signal when the first comparison result signal Sc1 changes from H to L. The timing measurement unit 420 stores a timestamp TS1 in response to the clock signal when the second comparison result signal Sc2 changes from L to H, and stores a timestamp TS4 in response to the clock signal when the second comparison result signal Sc2 changes from H to L. The timing measurement unit 420 can calculate the pulse width by subtracting the average value ((TS1+TS2) / 2) of the time indicated by the timestamp TS1 and the time indicated by the timestamp TS2 from the average value ((TS3+TS4) / 2) of the time indicated by the timestamp TS3 and the time indicated by the timestamp TS4.

[0070] Because the sampling period in the digital comparing section 410 is longer than the period of the clock signal used in the timing measuring section 420, the pulse width measurement by the timing measuring section 420 is more accurate than the comparison result in the digital comparing section 410. However, because the digital comparing section 410 does not require post-processing (pulse width calculation) in the timing measuring section 420, the processing time until the result is obtained is faster than that of the timing measuring section 420. Therefore, by calculating the pulse width in the timing measuring section 420 only when the comparison result of the logic pattern in the digital comparing section 410 is pass, the frequency of pulse width calculation processing in the timing measuring section 420 can be reduced.

[0071] The test apparatus 10 of this embodiment as described above can accurately measure the pulse width of the signal under test by using the timing measurement unit 420 used in the functional test. This eliminates the need to convert current signals to voltage signals by arranging a circuit such as BOST (built out self test) or BIST (built in self test) in the device under test 20. Furthermore, because the current signals are converted to voltage signals by the test apparatus 10, there is no need to extract characteristics, and the reliability of the pulse width test is improved.

[0072] The input section 200 of the test apparatus 10 may include a circuit for converting a current signal, such as a BOST signal, between the connection switching section 210 and the probe card 100 shown in FIG. 1 or in place of the current measurement section 230. The level comparison circuit 280 may output only one of the first comparison result signal Sc1 and the second comparison result signal Sc2. In this case, the timing measurement section 420 may measure the timing of the edge of only one of the first comparison result signal Sc1 and the second comparison result signal Sc2 to calculate the pulse width of the current measurement signal Sim. The functional testing section 400 and the DC testing section 300 may store in advance the characteristics, such as the amplification factor, of the current measurement section 230, voltage measurement section 220, and AD conversion section 260 arranged in the input section 200, and may convert each measurement result according to the characteristics.

[0073] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0074] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0075] 10 Testing apparatus 20 Device under test 100 Probe card 200 Input section 210 Connection switching section 212 First switch 214 Second switch 220 Voltage measuring section 230 Current measuring section 240 Current output section 250 Second input switching section 260 AD conversion section 270 First input switching section 272 Third switch 280 Level comparison circuit 282 First reference value setting section 284 First comparison section 286 Second reference value setting section 288 Second comparison section 300 DC testing section 400 Functional testing section 410 Digital comparison section 420 Timing measurement section 500 Control section

Claims

1. A test apparatus comprising: an input section connected to a device under test for receiving a signal under test from the device under test; and a functional testing section for performing a functional test of the device under test based on the signal under test, wherein the functional testing section has a timing measurement section for measuring the timing of the edges of the input signal, the input section having: a current measurement section for outputting a current measurement signal corresponding to the current value of the signal under test; and a first input switching section for switching whether or not the current measurement signal is input to the functional testing section, and the timing measurement section measures the pulse width of the current measurement signal based on the timing of the edges of the current measurement signal input to the functional testing section.

2. The test apparatus according to claim 1, wherein the input section further comprises a voltage measurement section which outputs a voltage measurement signal corresponding to a voltage value of the signal under test, and the first input switching section selects either the voltage measurement signal or the current measurement signal and inputs it to the functional testing section.

3. The test device according to claim 2, wherein the input section further comprises a level comparison circuit which inputs to the functional test section a signal corresponding to a comparison result between the signal level of the signal selected by the first input switching section and a reference value.

4. The test apparatus according to claim 2, further comprising a DC test section that performs a DC test on the device under test based on at least one of the voltage measurement signal and the current measurement signal.

5. The test device according to claim 4, wherein the input section further comprises a second input switching section which selects either the voltage measurement signal or the current measurement signal and inputs it to the DC test section.

6. The test apparatus according to claim 1, wherein the input section receives the signal under test from a probe card that contacts the device under test.

7. The test apparatus of claim 1, wherein the functional testing section further comprises a digital comparison section which determines whether a logic pattern corresponding to an input signal matches an expected value pattern, and when measuring the pulse width of the current measurement signal, the digital comparison section receives the current measurement signal, and the timing measurement section measures the pulse width of the current measurement signal based on the timing of an edge of the current measurement signal in response to the digital comparison section determining that the logic pattern corresponding to the current measurement signal matches the expected value pattern.

8. The test apparatus according to claim 3, further comprising a control section that causes the reference value in the level comparison circuit to differ between when performing the functional test of the device under test and when measuring the pulse width of the current measurement signal.

9. The test apparatus according to claim 8, further comprising a DC test section which measures the signal level of the current measurement signal, wherein the level comparison circuit compares each of a first reference value and a second reference value with the signal level of the signal selected by the first input switching section, and wherein the control section, when measuring the pulse width of the current measurement signal, makes the first reference value larger than the signal level measured by the DC test section and makes the second reference value smaller than the signal level measured by the DC test section.

10. The test apparatus according to claim 1, wherein the timing measurement section measures at least one of the jitter, frequency, and slew rate of the current measurement signal based on the timing of an edge of the current measurement signal input to the functional test section.

11. A test method executed by a test apparatus, comprising: a step of receiving a signal under test from a device under test; a step of outputting a current measurement signal corresponding to a current value of the signal under test; a step of switching whether or not to input the current measurement signal to a functional testing section of the test apparatus; and a step of measuring the pulse width of the current measurement signal based on the timing of the edge of the current measurement signal input to the functional testing section.

12. The test method according to claim 11, wherein the step of measuring the pulse width of the current measurement signal includes the steps of: determining whether a logic pattern corresponding to the current measurement signal input to the functional testing section matches an expected value pattern; and measuring the pulse width of the current measurement signal based on the timing of an edge of the current measurement signal in response to determining that the logic pattern matches the expected value pattern.

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