Change-edge detection circuit, time-to-digital converter, and electronic apparatus

Abstract

The present invention reduces an error of a change-edge detection circuit. This change-edge detection circuit includes: a first output node connected to a first output terminal; a second output node connected to a second output terminal; a preliminary charging circuit for charging the first output node and the second output node; a first detection unit, which is constituted by a first discharge circuit and a second discharge circuit connected in parallel to the first output node, the first discharge circuit and second discharge circuit being respectively controlled by a signal of a first input terminal and a signal of a second input terminal and which, of the signal of the first input terminal and the signal of the second input terminal, detects a signal with a change edge generated temporally before; and a second detection unit, which is constituted by a third discharge circuit and a fourth discharge circuit connected in series to the second output node, the third discharge circuit and fourth discharge circuit being respectively controlled by the signal of the first input terminal and the second input terminal and which, of the signal of the first input terminal and the signal of the second input terminal, detects a signal with a change edge generated temporally after.

Description

Changing edge detection circuit, time-to-digital converter and electronic device

[0001] The present disclosure relates to a transition edge detection circuit, a time-to-digital converter, and an electronic device.

[0002] As a time-to-digital converter that converts the time difference between two input signals into a digital value, a pipelined successive approximation register (SAR) type time-to-digital converter has been proposed (see, for example, Patent Document 1).

[0003] This time-to-digital converter is configured by cascading multiple conversion units. Each conversion unit includes a comparator, a transition edge detection circuit (pipeline stage), and a delay stage. The comparator compares two input signals to detect which signal's rising edge is earlier in time. The pipeline stage detects the signal whose rising edge occurs earlier in time and the signal whose rising edge occurs later in time of the two input signals. The delay stage delays the signal whose rising edge detected by the pipeline stage occurs earlier in time. In each conversion unit, the signal whose rising edge occurs earlier in time is detected, delayed by the delay stage, and input to the next conversion unit. On the other hand, the signal whose rising edge detected by the pipeline stage occurs later in time is input to the next conversion unit without being delayed.

[0004] As described above, the time-to-digital converter compares the time difference between the rising edges of the input signals and performs time subtraction so that the time difference between the rising edges gradually approaches zero. The delay of each cascaded delay stage is binary weighted (power of 2). For example, assuming a time-to-digital converter with three cascaded conversion units, the delay stage of the first conversion unit has a delay time of 4Δt (Δt is the unit delay time), the delay stage of the second conversion unit has a delay time of 2Δt, and the delay stage of the third conversion unit has a delay time of Δt. The output of the comparator in each conversion unit is the digital value of the conversion result. The output of the comparator in the first conversion unit represents the most significant bit of the digital value, and the output of the comparator in the second conversion unit represents the next bit of the digital value. In this way, a one-bit digital value is generated from the cascaded conversion units.

[0005] As described above, the pipeline stage detects the signal whose rising edge occurs earlier in time and the signal whose rising edge occurs later in time of two input signals. An OR circuit is used to detect the signal whose rising edge occurs earlier in time of two input signals. An AND circuit is used to detect the signal whose rising edge occurs later in time. The OR circuit propagates the rising edge signal to a subsequent circuit at the timing when the earlier rising edge of the two signals is input. On the other hand, the AND circuit propagates the rising edge signal to a subsequent circuit at the timing when the later rising edge of the two signals is input.

[0006] US Patent Application Publication No. 2023 / 0018398

[0007] However, the above-mentioned conventional technology has a problem in that the delays of the OR circuit and the AND circuit are different, which causes errors in the conversion results.

[0008] Therefore, the present disclosure proposes a changing edge detection circuit that reduces errors, as well as a time-to-digital converter and electronic equipment that use the changing edge detection circuit.

[0009] The changing edge detection circuit according to the present disclosure includes a first output node connected to a first output terminal, a second output node connected to a second output terminal, a pre-charging circuit that charges the first output node and the second output node, a first detection unit configured by a first discharge circuit and a second discharge circuit controlled by a signal at a first input terminal and a signal at a second input terminal, respectively, connected in parallel to the first output node, and detecting a signal at which a changing edge occurs earlier in time out of the signal at the first input terminal and the signal at the second input terminal, and a second detection unit configured by a third discharge circuit and a fourth discharge circuit controlled by the signal at the first input terminal and the signal at the second input terminal, respectively, connected in series to the second output node, and detecting a signal at which a changing edge occurs later in time out of the signal at the first input terminal and the signal at the second input terminal.

[0010] FIG. 1 is a diagram illustrating an example of a configuration of a changing edge detection circuit according to a first embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example of detection of a changing edge according to the first embodiment of the present disclosure. FIG. 3 is a diagram illustrating a conventional changing edge detection circuit. FIG. 4 is a diagram illustrating a conventional changing edge detection circuit. FIG. 5 is a diagram illustrating an example of characteristics of a changing edge detection circuit according to the first embodiment of the present disclosure. FIG. 6 is a diagram illustrating characteristics of a conventional changing edge detection circuit. FIG. 7 is a diagram illustrating an example of a configuration of a changing edge detection circuit according to a second embodiment of the present disclosure. FIG. 8 is a diagram illustrating an example of a configuration of a changing edge detection circuit according to a second embodiment of the present disclosure. FIG. 9 is a diagram illustrating an example of a configuration of a changing edge detection circuit according to a second embodiment of the present disclosure. FIG. 10 is a diagram illustrating an example of a configuration of a changing edge detection circuit according to a third embodiment of the present disclosure. FIG. 11 is a diagram illustrating another example of a configuration of a changing edge detection circuit according to the third embodiment of the present disclosure. FIG. 12 is a diagram illustrating an example of a configuration of a time-to-digital converter according to a fourth embodiment of the present disclosure. FIG. 13 is a diagram illustrating an example of a configuration of an analog-to-digital converter according to a fifth embodiment of the present disclosure. Fig. 10 is a diagram illustrating another configuration example of an analog-to-digital converter according to a fifth embodiment of the present disclosure. Fig. 11 is a diagram illustrating another configuration example of an analog-to-digital converter according to a fifth embodiment of the present disclosure. Fig. 12 is a diagram illustrating an example of the configuration of an electronic device according to an embodiment of the present disclosure.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order. Note that in the following embodiments, the same components are designated by the same reference numerals, and redundant description will be omitted. 1. First embodiment 2. Second embodiment 3. Third embodiment 4. Fourth embodiment 5. Fifth embodiment 6. Application example to electronic device

[0012] (1. First Embodiment) [Configuration of a Changing Edge Detection Circuit] FIG. 1 is a diagram showing a configuration example of a changing edge detection circuit according to a first embodiment of the present disclosure. The same figure is a circuit diagram showing a configuration example of a changing edge detection circuit 100. The changing edge detection circuit 100 detects, of two input signals, a signal in which a changing edge occurs earlier in time and a signal in which a changing edge occurs later in time. Here, the changing edge is either a rising edge or a falling edge.

[0013] The changing edge detection circuit 100 includes a pre-charging circuit 130, a first detection unit 110, a second detection unit 120, and inverting buffers 141 and 142. The changing edge detection circuit 100 also includes a first input terminal 101 and a second input terminal 104 to which two input signals are applied. The changing edge detection circuit 100 also includes a first output terminal 102 that outputs a signal whose changing edge occurs earlier in time and a second output terminal 105 that outputs a signal whose changing edge occurs later in time. The changing edge detection circuit 100 also includes a first output node 103 connected to the first output terminal 102 and a second output node 106 connected to the second output terminal 105. The first output node 103 in FIG. 1 is connected to the first output terminal 102 via an inverting buffer 141. The second output node 106 in FIG. 1 is connected to the second output terminal 105 via an inverting buffer 142. A power supply line Vdd is also connected to the changing edge detection circuit 100. The changing edge detection circuit 100 in FIG. 1 is designed to detect a rising edge as a changing edge.

[0014] The pre-charging circuit 130 charges the first output node 103 and the second output node 106. The pre-charging circuit 130 in FIG. 1 includes MOS transistors 201 and 202. P-channel MOS transistors can be used for the MOS transistors 201 and 202. The source of the MOS transistor 201 is connected to the power supply line Vdd, and the drain is connected to the first output node 103. The source of the MOS transistor 202 is connected to the power supply line Vdd, and the drain is connected to the second output node 106. The gates of the MOS transistors 201 and 202 are commonly connected to a signal line RST. By inputting an ON signal to the signal line RST, the MOS transistors 201 and 202 are rendered conductive, and the first output node 103 and the second output node 106 are charged to the power supply voltage. The signal on the signal line RST is generated by a control circuit (not shown).

[0015] The first detection unit 110 detects the signal whose transition edge occurs earlier in time out of the signal at the first input terminal 101 and the signal at the second input terminal 104, and transmits the detected signal to the first output node 103. The first detection unit 110 in FIG. 1 includes a first discharge circuit 111 and a second discharge circuit 112. The first discharge circuit 111 and the second discharge circuit 112 are connected in parallel to the first output node 103.

[0016] The first discharge circuit 111 is a circuit that is controlled by a signal from the first input terminal 101 and discharges the first output node 103. The first discharge circuit 111 includes a MOS transistor 211. The second discharge circuit 112 is a circuit that is controlled by a signal from the second input terminal 104 and discharges the first output node 103. The second discharge circuit 112 includes a MOS transistor 210. N-channel MOS transistors can be used for the MOS transistors 210 and 211. The gate of the MOS transistor 211 is connected to the first input terminal 101, and the drain is connected to the first output node 103. The source of the MOS transistor 211 is connected to a common GND. The gate of the MOS transistor 210 is connected to the second input terminal 104, and the drain is connected to the first output node 103. The source of the MOS transistor 211 is connected to a common GND.

[0017] In the first detection section 110, when either the signal at the first input terminal 101 or the signal at the second input terminal 104 changes to an H level, the voltage charged at the first output node 103 is discharged.

[0018] The second detection unit 120 detects the signal whose transition edge occurs later in time out of the signal at the first input terminal 101 and the signal at the second input terminal 104, and transmits the detected signal to the second output node 106. The second detection unit 120 includes a third discharge circuit 121 and a fourth discharge circuit 122. The third discharge circuit 121 and the fourth discharge circuit 122 are connected in series to the second output node 106.

[0019] The third discharge circuit 121 is a circuit that is controlled by a signal from the first input terminal 101 and discharges the second output node 106. The third discharge circuit 121 includes a MOS transistor 213. The fourth discharge circuit 122 is a circuit that is controlled by a signal from the second input terminal 104 and discharges the second output node 106. The fourth discharge circuit 122 includes a MOS transistor 212. N-channel MOS transistors can be used for the MOS transistors 212 and 213. The gate of the MOS transistor 213 is connected to the first input terminal 101, and the drain is connected to the source of the MOS transistor 212. The source of the MOS transistor 213 is connected to a common GND. The gate of the MOS transistor 212 is connected to the second input terminal 104, and the drain is connected to the second output node 106.

[0020] In the second detection section 120, when the signal at the first input terminal 101 and the signal at the second input terminal 104 both become H level, the voltage charged at the second output node 106 is discharged.

[0021] 2 is a diagram showing an example of the operation of the changing edge detection circuit according to the first embodiment of the present disclosure. The diagram is a timing diagram showing an example of the operation of the changing edge detection circuit 100. In the diagram, "RST" represents the signal on the signal line RST. "Vin1" represents the signal at the first input terminal 101. "Vin2" represents the signal at the second input terminal 104. "Vout1" represents the signal at the first output terminal 102. "Vout2" represents the signal at the second output terminal 105. Note that the dashed line in the diagram represents the potential of the common GND line.

[0022] In the initial state, an L-level signal is input from the signal line RST. This causes the pre-charging circuit 130 to operate, charging the first output node 103 and the second output node 106 to the power supply voltage. This corresponds to a reset. As a result, the first output terminal 102 and the second output terminal 105 go to the L-level. Thereafter, the signal on the signal line RST changes to the H-level, and charging by the pre-charging circuit 130 stops.

[0023] Thereafter, a signal from the first input terminal 101 and a signal from the second input terminal 104 are input. Fig. 2 shows an example in which a rise in the signal from the first input terminal 101 occurs after the rise in the signal from the second input terminal 104. An H-level signal is output from the first output terminal 102 due to the signal from the second input terminal 104 having a rising edge earlier in time. An H-level signal is output from the second output terminal 105 due to the signal from the first input terminal 101 having a rising edge later in time.

[0024] 1, one p-channel MOS transistor is connected to each of the first output node 103 of the first detection unit 110 and the second output node 106 of the second detection unit 120. This makes it possible to equalize the parasitic capacitances of the p-channel MOS transistors connected to the first output node 103 and the second output node 106. In other words, it is possible to equalize the parasitic capacitances, which are important factors that determine the propagation speeds of the first output node 103 and the second output node 106.

[0025] 1, the p-channel MOS transistor of the pre-charging circuit 130 is turned off after pre-charging. That is, the timing at which the p-channel MOS transistor turns off can be configured not to depend on the transition edge of the signal at the first input terminal 101, etc.

[0026] 1 can equalize the parasitic capacitances connected between the first output node 103 and the second output node 106, thereby eliminating the influence of the timing at which the p-channel MOS transistor transitions to the off state. This makes it possible to equalize the delays between the first output node 103 and the second output node 106, thereby reducing errors.

[0027] 3A and 3B are diagrams showing a conventional changing edge detection circuit. FIG. 3A is a circuit diagram showing a conventional changing edge detection circuit 300 described as a comparative example. This changing edge detection circuit 300 is composed of a NOR circuit 301, a NAND circuit 303, and inverting buffers 302 and 304. The NOR circuit 301 is a circuit that outputs a signal whose rising edge occurs earlier in time than the input signal. The NAND circuit 303 is a circuit that outputs a signal whose rising edge occurs later in time than the input signal.

[0028] FIG. 3B is a circuit diagram showing an example configuration of the NAND circuit 303. P-channel MOS transistors 311 and 312 are connected to an output node 315. A circuit of MOS transistors 313 and 314 connected in series is further connected to the output node 315. Two n-channel MOS transistors (MOS transistors 313 and 314) are connected in series, and two input signals Vin1 and Vin2 are input to their gates. The output node 315 of the NAND circuit 303 is discharged by the MOS transistors 313 and 314 at the timing of the later rising edge of the input signals Vin1 and Vin2. The signal with the earlier rising edge of the input signals Vin1 and Vin2 turns on the n-channel MOS transistor in advance. Then, at the timing of the later rising edge of the input signals Vin1 and Vin2, the other n-channel MOS transistor turns on, discharging the output node 315 and propagating the signal. In the case of the NAND circuit 303, two MOS transistors connected in series exist in the discharge current path.

[0029] FIG. 3C is a circuit diagram showing an example configuration of the NOR circuit 301. A p-channel MOS transistor 317 is connected to the output node 322. This MOS transistor 317 is connected to the power supply line Vdd via a MOS transistor 316. Furthermore, serially connected MOS transistors 318 and 319 and serially connected MOS transistors 320 and 321 are further connected to the output node 322. That is, the circuit of the MOS transistors 318 and 319 and the circuit of the MOS transistors 320 and 321 are connected in parallel to the output node 322. In the NOR circuit 301, one of the input signals Vin1 and Vin2, which has the earliest rising edge timing, turns on one of the serially connected MOS transistor circuits, discharging the output node 322 and propagating the signal. In this way, like the NAND circuit 303, the NOR circuit 301 has two n-channel MOS transistors connected to a path that discharges the output node. This allows the discharge times of the NAND circuit 303 and the NOR circuit 301 to be synchronized.

[0030] However, there are three factors that determine the discharge time of the NAND circuit 303 and the NOR circuit 301: "the discharge capacity of the n-channel MOS transistor," "the parasitic capacitance of the p-channel MOS transistor," and "the timing when the p-channel MOS transistor turns off." In conventional technology, efforts have been made to align the "discharge capacity of the n-channel MOS transistor," but the remaining two issues have not been resolved.

[0031] First, the two p-channel MOS transistors of the NAND circuit 303 are connected in parallel to the output node 315. In contrast, the problem with the NOR circuit 301 is that the two p-channel MOS transistors connected in series are connected to the output node 322. In other words, the parasitic capacitances of the NAND circuit 303 and the NOR circuit 301 are different. This results in a difference in the discharge times of the NAND circuit 303 and the NOR circuit 301.

[0032] Furthermore, when discharging the output node 322, the NOR circuit 301 cannot start discharging using the n-channel MOS transistor unless the p-channel MOS transistor is turned off. In other words, discharging must start after the MOS transistors 316 and 317 connected to Vin1 and Vin2, respectively, are turned off. The MOS transistors 316 and 317 are connected in series, and the timing at which they turn off differs depending on their relative positions. This factor also affects the difference in discharge time between the NAND circuit 303 and the NOR circuit 301.

[0033] 4A is a diagram showing an example of the characteristics of the transition edge detection circuit according to the first embodiment of the present disclosure. This diagram shows an example of the characteristics of the transition edge detection circuit 100. The vertical axis of this diagram represents the delay difference [ps] between the circuit that detects the early edge of the input signal and the circuit that detects the late edge. The horizontal axis represents the delay difference [ps] of the input signal. It is desirable that the delay difference between the circuit that detects the early edge and the circuit that detects the late edge be a value of "0." It can be seen that the delay difference between the circuit that detects the early edge and the circuit that detects the late edge of the transition edge detection circuit 100 in FIG. 1 is a maximum of 2 ps.

[0034] Assume that the transition edge detection circuit 100 of FIG. 1 is combined with a delay unit 180, which will be described later in FIG. 15, to form a time-to-digital converter (time-to-digital converter 20). In this case, it is desirable that the delay difference between the circuit that detects the early edge and the circuit that detects the late edge is smaller than the delay amount Δtu of the inversion buffer 151 of the delay unit 180. For example, when Δtu=10 ps, ​​if there is an error of −5.84 ps in the delay difference, an error of −58.4% will occur in the result of the subtraction operation. By applying the present invention, it is possible to reduce this error to −23.4%.

[0035] FIG. 4B is a diagram showing the characteristics of a conventional changing edge detection circuit. This diagram shows the characteristics of the changing edge detection circuit 300 shown in FIGS. 3A-3C. In this changing edge detection circuit 300, a delay difference of about +2 ps occurs when the horizontal axis is near -30 ps. Furthermore, a delay difference of about +0.4 ps occurs when the horizontal axis is near +30 ps. This is largely due to differences in the timing at which the p-channel MOS transistor in the NOR circuit 301 turns off. In contrast, in the changing edge detection circuit 100 of FIG. 1, as shown in FIG. 4A, the delay difference is about -0.2 ps when the horizontal axis is near ±30 ps, ​​demonstrating a significant improvement.

[0036] Furthermore, in the transition edge detection circuit 100 of Figure 1, the delay difference is improved from -5.84 ps to -2.34 ps even near 0 ps on the horizontal axis. This is because the absolute values ​​of the delay of the circuit that detects the early edge signal and the delay of the circuit that detects the late edge signal are reduced by turning off the p-channel MOS transistors in advance. The transition edge detection circuit 100 of Figure 1 also has a significant improvement effect over the prior art in terms of delay difference.

[0037] 1 can reduce the number of p-channel MOS transistors compared to the conventional changing edge detection circuit 300. This allows the area of ​​the changing edge detection circuit 100 to be reduced.

[0038] As described above, the transition edge detection circuit 100 according to the first embodiment of the present disclosure includes a first detection unit 110 that detects a signal whose transition edge occurs earlier in time and a second detection unit 120 that detects a signal whose transition edge occurs later in time. The number of pre-charging p-channel MOS transistors connected to the first output node 103 of the first detection unit 110 is equal to the number of pre-charging p-channel MOS transistors connected to the second output node 106 of the second detection unit 120. This allows the delay times of the first detection unit 110 and the second detection unit 120 to be matched. Furthermore, the pre-charging circuit 130 pre-charges the first output node 103 and the second output node 106, and a signal is input to the transition edge detection circuit 100 after the pre-charging circuit 130 stops operating. That is, an input signal is input when the p-channel MOS transistors constituting the pre-charging circuit 130 are in an off state. This eliminates the influence of the transition time of the p-channel MOS transistors to the off state, thereby shortening the delay times of the first detection unit 110 and the second detection unit 120.

[0039] 2. Second Embodiment A variation of the changing edge detection circuit 100 of the first embodiment will be described.

[0040] [Configuration of the Changing Edge Detection Circuit] Figure 5 is a diagram showing an example configuration of a changing edge detection circuit according to a second embodiment of the present disclosure. Similar to Figure 1, this diagram is a circuit diagram showing an example configuration of a changing edge detection circuit 100. Note that in the following figures, the first input terminal 101 and other components are omitted. The changing edge detection circuit 100 in Figure 5 differs from the changing edge detection circuit 100 in Figure 1 in that it includes a first detection unit 110 configured with a p-channel MOS transistor and a second detection unit 120 configured with a p-channel MOS transistor. The changing edge detection circuit 100 in Figure 5 also differs from the changing edge detection circuit 100 in Figure 1 in that it includes a pre-charging circuit 130 configured with an n-channel MOS transistor.

[0041] The pre-charging circuit 130 of FIG. 5 includes MOS transistors 219 and 220. These MOS transistors 219 and 220 can be n-channel MOS transistors. The first discharging circuit 111 of the first detecting unit 110 of FIG. 5 includes a MOS transistor 216, which is a p-channel MOS transistor. The second discharging circuit 112 of the first detecting unit 110 of FIG. 5 includes a MOS transistor 215, which is a p-channel MOS transistor. The third discharging circuit 121 of the second detecting unit 120 of FIG. 5 includes a MOS transistor 218, which is a p-channel MOS transistor. The fourth discharging circuit 122 of the second detecting unit 120 of FIG. 5 includes a MOS transistor 217, which is a p-channel MOS transistor.

[0042] 6 is a diagram showing a configuration example of a changing edge detection circuit according to a second embodiment of the present disclosure. Similar to FIG. 1, this diagram is a circuit diagram showing a configuration example of a changing edge detection circuit 100. The changing edge detection circuit 100 in FIG. 6 differs from the changing edge detection circuit 100 in FIG. 1 in that it includes a first discharge circuit 111 configured by connecting two MOS transistors in series and a second discharge circuit 112 configured by connecting two MOS transistors in series.

[0043] The first discharge circuit 111 is configured with a circuit of a MOS transistor 211 and a MOS transistor 222 connected in series. The second discharge circuit 112 is configured with a circuit of a MOS transistor 210 and a MOS transistor 221 connected in series.

[0044] 7 is a diagram showing a configuration example of a changing edge detection circuit according to a second embodiment of the present disclosure. Similar to FIG. 1, this diagram is a circuit diagram showing a configuration example of a changing edge detection circuit 100. The changing edge detection circuit 100 in FIG. 7 differs from the changing edge detection circuit 100 in FIG. 1 in that the second detection unit 120 further includes a fifth discharge circuit 123 and a sixth discharge circuit 124.

[0045] The fifth discharge circuit 123 is a circuit that discharges the second output node 106. This fifth discharge circuit 123 includes a MOS transistor 231 to whose gate a signal from the first input terminal 101 is applied. The sixth discharge circuit 124 is a circuit that is connected in series with the fifth discharge circuit 123 and discharges the second output node 106. The sixth discharge circuit 124 includes a MOS transistor 232 to whose gate a signal from the second input terminal 104 is applied. Note that the third discharge circuit 121 in FIG. 7 is connected to the second output node 106, and the fourth discharge circuit 122 is connected in series with the third discharge circuit 121.

[0046] The second detection unit 120 further includes a circuit of a MOS transistor 233 and a MOS transistor 234 connected in series, and a circuit of a MOS transistor 235 and a MOS transistor 236 connected in series. In this way, the second detection unit 120 includes six MOS transistors.

[0047] The first detection unit 110 in Fig. 7 is provided with a first discharge circuit 111 and a second discharge circuit 112, similar to the changing edge detection circuit 100 in Fig. 1. A MOS transistor 227 having a gate to which a power supply voltage is applied is connected to the first discharge circuit 111 in Fig. 7. Furthermore, a MOS transistor 228 having a gate to which a power supply voltage is applied is connected to the second discharge circuit 112 in Fig. 7.

[0048] 7 further includes a seventh discharge circuit 113 and an eighth discharge circuit 114. The seventh discharge circuit 113 is configured by connecting in series a MOS transistor 229, whose gate is applied with a power supply voltage, and a MOS transistor 230, whose gate is applied with a signal from the first input terminal 101. The eighth discharge circuit 114 is configured by connecting in series a MOS transistor 225, whose gate is applied with a power supply voltage, and a MOS transistor 226, whose gate is applied with a signal from the second input terminal 104. In this way, the first detection unit 110 includes six MOS transistors, just like the second detection unit 120. This allows the delay times of the first detection unit 110 and the second detection unit 120 to be aligned, further reducing the delay difference.

[0049] 8 is a diagram showing a configuration example of a changing edge detection circuit according to a second embodiment of the present disclosure. Similar to FIG. 1, this diagram is a circuit diagram showing a configuration example of a changing edge detection circuit 100. The changing edge detection circuit 100 in FIG. 8 differs from the changing edge detection circuit 100 in FIG. 1 in that it further includes capacitors 143 and 144.

[0050] Capacitor 143 is connected to first output node 103. Capacitor 144 is connected to second output node 106. These capacitors 143 and 144 are charged by pre-charging circuit 130. Therefore, even if a long time passes from pre-charging until an input signal is input to first input terminal 101 or the like, fluctuations in the potentials of first output node 103 and second output node 106 due to the influence of leakage current can be reduced.

[0051] 9 is a diagram showing a configuration example of a changing edge detection circuit according to a second embodiment of the present disclosure. Similar to FIG. 1, this diagram is a circuit diagram showing a configuration example of a changing edge detection circuit 100. The changing edge detection circuit 100 in this diagram differs from the changing edge detection circuit 100 in FIG. 1 in that it further includes an output stopping unit that stops the output of the detection results of the first detection unit 110 and the second detection unit 120.

[0052] The changing edge detection circuit 100 of FIG. 9 further includes AND gates 145 and 146. Two-input AND gates can be used as the AND gates 145 and 146. The output of the inverting buffer 141 of FIG. 9 is connected to the input of the AND gate 145. The signal line RSTE is connected to the other input of the AND gate 145. The output of the AND gate 145 is connected to the first output terminal 102. The output of the inverting buffer 142 of FIG. 9 is connected to the input of the AND gate 146. The signal line RSTE is connected to the other input of the AND gate 146. The output of the AND gate 146 is connected to the second output terminal 105. The circuits of the AND gates 145 and 146 correspond to the output stopping unit. By inputting an L-level signal to the signal line RSTE, the output of each of the first detection unit 110 and the second detection unit 120 can be stopped.

[0053] The output of the signals from the first detection unit 110 and the second detection unit 120 can be stopped, for example, when the first output node 103 or the like is being charged by the pre-charging circuit 130. As will be described later with reference to FIG. 15 , when the changing edge detection circuit 100 is applied to a time-to-digital converter, the changing edge detection circuits 100 are cascade-connected. Assume that both input signals to the next-stage changing edge detection circuit 100 are at the H level. In this case, if the pre-charging circuit 130 of the next-stage changing edge detection circuit 100 operates, the MOS transistors of the pre-charging circuit 130 and the first detection unit 110 or the like are simultaneously turned on, causing a through current to flow. Therefore, the output stopping unit sets the output signal of the previous-stage changing edge detection circuit 100 to the L level, and the pre-charging circuit 130 in the next-stage changing edge detection circuit 100 operates. This prevents the through current.

[0054] 10 is a diagram showing a configuration example of a changing edge detection circuit according to a second embodiment of the present disclosure. Similar to FIG. 9, this figure is a circuit diagram showing a configuration example of a changing edge detection circuit 100. The changing edge detection circuit 100 in this figure differs from the changing edge detection circuit 100 in FIG. 10 in that it includes NOR gates 148 and 149 instead of inverting buffers 141 and 142 and AND gates 145 and 146.

[0055] Two-input NOR gates can be used for the NOR gates 148 and 149. The first output node 103 in FIG. 10 is connected to the input of the NOR gate 148. The signal line RSTE is connected to the other input of the NOR gate 148. The output of the NOR gate 148 is connected to the first output terminal 102. The second output node 106 in FIG. 10 is connected to the input of the NOR gate 149. The signal line RSTE is connected to the other input of the NOR gate 149. The output of the NOR gate 149 is connected to the second output terminal 105. The circuits of the NOR gates 148 and 149 correspond to the output stopping unit. By inputting an H-level signal to the signal line RSTE, the output of each of the first detection unit 110 and the second detection unit 120 can be stopped.

[0056] FIG. 11 is a diagram illustrating an example configuration of a changing edge detection circuit according to a second embodiment of the present disclosure. Similar to FIG. 1, this diagram is a circuit diagram illustrating an example configuration of a changing edge detection circuit 100. The changing edge detection circuit 100 in FIG. 1 differs from the changing edge detection circuit 100 in FIG. 1 in that it includes an operation stopping unit. This operation stopping unit is a circuit that stops the operation of the first discharge circuit 111, the second discharge circuit 112, the third discharge circuit 121, and the fourth discharge circuit 122. The operation stopping unit is configured with a circuit of MOS transistors 240 to 242. The MOS transistor 240 is connected in series to the second discharge circuit 112. The MOS transistor 241 is connected in series to the first discharge circuit 111. The MOS transistor 242 is connected in series to the fourth discharge circuit 122. The gates of the MOS transistors 240 to 242 are connected to a signal line RST. This allows the MOS transistors 240 to 242 to be turned off while the pre-charging circuit 130 is operating. This makes it possible to stop the operations of the first discharge circuit 111, the second discharge circuit 112, the third discharge circuit 121, and the fourth discharge circuit 122. The transition edge detection circuit 100 in the figure can also prevent the aforementioned through current.

[0057] 12 is a diagram showing a configuration example of a changing edge detection circuit according to a second embodiment of the present disclosure. Similar to FIG. 11, this diagram is a circuit diagram showing a configuration example of a changing edge detection circuit 100. The changing edge detection circuit 100 in this diagram differs from the changing edge detection circuit 100 in FIG. 11 in that a MOS transistor 240 is commonly connected to the first discharge circuit 111 and the second discharge circuit 112.

[0058] The configuration of the changing edge detection circuit 100 other than that described above is the same as the configuration of the changing edge detection circuit 100 in the first embodiment of the present disclosure, and therefore description thereof will be omitted.

[0059] (3. Third Embodiment) An application example of the changing edge detection circuit 100 of the first embodiment will be described.

[0060] 13 is a diagram illustrating a configuration example of a changing edge detection circuit according to a third embodiment of the present disclosure. The diagram illustrates an example in which a delay unit 180 is connected to the output of the changing edge detection circuit 100.

[0061] The delay unit 180 is inserted into a node that transmits a signal from the first detection unit 110. This delay unit 180 is composed of a circuit of an inverting buffer 151 and an inverting buffer 152 that are cascaded. By providing this delay unit 180, it is possible to delay the output timing of a signal whose changing edge occurs earlier in time. On the other hand, a signal whose changing edge occurs later in time is output as is. In other words, the circuit in FIG. 13 is a circuit that determines a signal whose changing edge occurs earlier in time and subtracts the propagation time of the delay unit 180.

[0062] It is also possible to cascade-connect a plurality of circuits each including a changing edge detection circuit 100 and a delay section 180 in multiple stages. In this case, the delay amount of the delay section 180 of each circuit can be changed.

[0063] 14 is a diagram showing another example of the configuration of the changing edge detection circuit according to the third embodiment of the present disclosure. Similar to FIG. 13, this diagram shows an example in which a delay unit (delay unit 181) is connected to the output of the changing edge detection circuit 100.

[0064] 14 is composed of an inverting buffer 151 and MOS transistors 245 and 246. A p-channel MOS transistor can be used for the MOS transistor 245. An n-channel MOS transistor can be used for the MOS transistor 246. The source of the MOS transistor 245 is connected to the power supply line Vdd, and the drain is connected to the drain of the MOS transistor 246 and the input of the inverting buffer 151. The gate of the MOS transistor 245 is connected to a signal line RST. The source of the MOS transistor 246 is connected to a common GND line, and the gate is connected to the output of the inverting buffer 141.

[0065] As shown in FIG. 14 , the delay circuit in the preceding stage of the delay unit 181 and the circuit that detects a changing edge have the same circuit configuration. This allows the signal slope (slew rate) to be aligned in the circuit that detects a changing edge and the delay circuit. In other words, the circuit of MOS transistors 245 and 246 can shape the signal waveform. This circuit of MOS transistors 245 and 246 is called a shaping circuit. When the changing edge detection circuit 100 is connected in multiple stages, if the slew rates of the delay circuits in each stage differ, the delay characteristics of each delay circuit may change. By providing this shaping circuit, the slope of the signal edge in each delay circuit can be made the same, making it possible to align the delay characteristics of each delay circuit.

[0066] (4. Fourth Embodiment) A time-to-digital converter using the changing edge detection circuit 100 of the first embodiment described above will be described.

[0067] 15 is a diagram showing an example configuration of a time-to-digital converter according to a fourth embodiment of the present disclosure. The figure is a block diagram showing an example configuration of a time-to-digital converter 20. This time-to-digital converter 20 converts the time difference between two input signals (IN1 and IN2) into a digital signal. The time-to-digital converter 20 includes a conversion unit 10 and a final-stage comparison unit 171. Note that the time-to-digital converter 20 in the figure shows an example in which it includes two cascade-connected conversion units 10 (conversion unit 10a and conversion unit 10b).

[0068] The conversion unit 10 includes a first input terminal 191 and a second input terminal 193, a first output terminal 192 and a second output terminal 194, a comparison unit 170, a changing edge detection circuit 100, and a delay unit 180. The comparison unit 170 compares the changing edge of the signal at the first input terminal 191 with the changing edge of the signal at the second input terminal 193 to detect the signal with the changing edge that occurs earlier in time. Specifically, the comparison unit 170 outputs a value "1" if the changing edge of the signal at the first input terminal 191 occurs earlier in time than the changing edge of the signal at the second input terminal 193. On the other hand, the comparison unit 170 outputs a value "0" if the changing edge of the signal at the second input terminal 193 occurs earlier in time than the changing edge of the signal at the first input terminal 191. The comparison unit 170 can be configured, for example, by an RS flip-flop circuit.

[0069] 1 can be applied to the changing edge detection circuit 100. The signal at the first input terminal 191 and the signal at the second input terminal 193 are transmitted to the first input terminal 101 and the second input terminal 104 of the changing edge detection circuit 100, respectively.

[0070] The delay unit 180 delays the input signal by a predetermined delay amount and transmits the delayed signal to the first output terminal 192. This delay unit can be configured with an inverting buffer. The delay unit 180 of the conversion unit 10b is configured with a circuit of four cascaded inverting buffers (inverting buffers 153 to 156). The delay unit 180 of the conversion unit 10a can be configured with two cascaded inverting buffers (inverting buffers 151 and 152). In this way, the delay unit 180 of each stage has a binary-weighted (power of 2) delay time. That is, the delay unit 180 of the conversion unit 10b has the aforementioned delay of 4Δt. The delay unit 180 of the conversion unit 10a has a delay of 2Δt.

[0071] If the changing edge of the signal at the first input terminal 191 of the conversion unit 10b occurs before the changing edge of the signal at the second input terminal 193, the comparison unit 170 outputs a value "1." Furthermore, the signal at the first input terminal 191 is detected by the changing edge detection circuit 100 and transmitted to the first input terminal 191 of the conversion unit 10a via the delay unit 180. This signal has had a time of 4Δt subtracted from it by the delay unit 180. On the other hand, the signal at the second input terminal 193 is transmitted to the second input terminal 193 of the conversion unit 10a without passing through the delay unit 180.

[0072] If, as a result of the subtraction of 4Δt by the delay unit 180, the changing edge of the signal at the first input terminal 191 of the conversion unit 10a occurs after the changing edge of the signal at the second input terminal 193, the comparison unit 170 of the conversion unit 10a outputs the value "0". Then, the changing edge detection circuit 100 of the conversion unit 10a detects the signal at the second input terminal 193 and outputs it from the first output terminal 192 via the delay unit 180. This signal has had 2Δt subtracted from it by the delay unit 180.

[0073] On the other hand, even after the subtraction of 4Δt by the delay unit 180, if the changing edge of the signal at the first input terminal 191 of the conversion unit 10a occurs before the changing edge of the signal at the second input terminal 193, the comparison unit 170 of the conversion unit 10a outputs the value "1". Then, the changing edge detection circuit 100 of the conversion unit 10a detects the signal at the first input terminal 191 and outputs it from the first output terminal 192 via the delay unit 180. A time of 2Δt is subtracted from this signal by the delay unit 180. In this way, the time-to-digital converter 20 compares the time difference between the changing edges of the input signals and performs time subtraction so that the time difference between the changing edges gradually approaches zero.

[0074] The final stage comparator 171 compares the transition edges of the signals at the first output terminal 192 and the second output terminal 194 of the converter 10a to detect the transition edge of the signal that occurs earlier in time. The final stage comparator 171 can have the same configuration as the comparator 170.

[0075] The digital value output from the time-to-digital converter 20 is represented by OUT. The output digital value is 3-bit data. The output of the comparison unit 170 in the conversion unit 10b is the signal of the most significant bit of OUT (OUT[2]). The output of the comparison unit 170 in the conversion unit 10a is the signal of the second bit of OUT (OUT[1]). The output of the final stage comparison unit 171 is the signal of the least significant bit of OUT (OUT[0]). OUT is transmitted by a signal line 21.

[0076] In this way, the time-to-digital converter 20 according to the fourth embodiment of the present disclosure can be configured using the changing edge detection circuit 100 .

[0077] 5. Fifth Embodiment Analog-to-digital conversion using the changing edge detection circuit 100 of the first embodiment described above will be described.

[0078] 16 is a diagram illustrating a configuration example of an analog-digital converter according to a fifth embodiment of the present disclosure. The figure is a block diagram illustrating a configuration example of an analog-digital converter 1. This analog-digital converter 1 includes a voltage-time converter 30 and a time-to-digital converter 20. Note that in the figure, the "voltage-time converter" is abbreviated as "VTC."

[0079] The voltage-to-time converter 30 converts a voltage corresponding to the difference between the two input signals (VINp and VINn) into time and outputs the converted time signal to the time-to-digital converter 20. The time-to-digital converter 20 may be the same as the time-to-digital converter 20 described in FIG.

[0080] 17 is a diagram showing another configuration example of an analog-digital converter according to the fifth embodiment of the present disclosure. The figure is a block diagram showing another configuration example of the analog-digital converter 1. This analog-digital converter 1 includes an analog-digital converter 50, a voltage-time converter 30, and a time-digital converter 20.

[0081] The analog-to-digital converter 50 performs successive approximation type analog-to-digital conversion. The analog-to-digital converter 50 includes a digital-to-analog converter 51, a comparison circuit 52, and a logic circuit 53. Note that in FIG. 17, the "digital-to-analog converter" is written as "DAC."

[0082] The digital-to-analog converter 51 generates an analog signal under the control of the logic circuit 53 and superimposes it on the input signals VINp and VINn. The input signals VINp and VINn are input to the digital-to-analog converter 51 via switches 61 and 62. The comparator circuit 52 compares the difference between the input signals VINp and VINn with a predetermined value (e.g., 0 V) ​​and outputs the comparison result to the logic circuit 53. The logic circuit 53 controls the entire analog-to-digital converter 50.

[0083] The values ​​of the input signals VINp and VINn are changed by the digital-to-analog converter 51. The logic circuit 53 performs conversion by changing the output of the digital-to-analog converter 51 until the difference between the values ​​of the input signals VINp and VINn reaches a predetermined value. The analog-to-digital converter 50 outputs the converted residual voltage to the voltage-to-time converter 30.

[0084] The voltage-to-time converter 30 converts the residual voltage from the analog-to-digital converter 50 into a time signal and outputs it to the time-to-digital converter 20. The voltage-to-time converter 30 is composed of inverting buffers 31 and 32, switches 33 and 34, and constant current circuits 35 and 36.

[0085] 18 is a diagram showing another example configuration of an analog-digital converter according to the fifth embodiment of the present disclosure. This figure is a block diagram showing another example configuration of the analog-digital converter 1. The analog-digital converter 1 in this figure differs from the analog-digital converter 1 in FIG. 17 in the configuration of the voltage-time converter 30. The voltage-time converter 30 in this figure further includes voltage buffers 37 and 38, switches 39 and 40, and capacitors 41 and 42. The voltage-time converter 30 in this figure can hold the output of the analog-digital converter 50 using the circuits of the voltage buffers 37 and 38 and the capacitors 41 and 42. This allows the analog-digital converter 50 and the voltage-time converter 30 to operate in parallel.

[0086] In this way, the analog-to-digital converter 50 according to the fifth embodiment of the present disclosure can be configured using the changing edge detection circuit 100 .

[0087] (6. Application Examples to Electronic Devices) The changing edge detection circuit 100 of the above-described embodiment can be applied to electronic devices.

[0088] 19 is a diagram illustrating an example configuration of an electronic device according to an embodiment of the present disclosure. The figure is a block diagram illustrating an example configuration of an electronic device 80. The electronic device 80 includes a voltage-to-time converter 30, a time-to-digital converter 20, and a processor 70.

[0089] The voltage-to-time converter 30 converts the input PAM4 signal into a time signal.

[0090] The time-to-digital converter 20 converts the signal from the voltage-to-time converter 30 into a digital value.

[0091] The processor 70 processes the digital value output from the time-to-digital converter 20. The processor 70 is an example of a "processing circuit" in the present disclosure. The electronic device 80 can be configured as, for example, an IC.

[0092] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0093] The present technology may also be configured as follows: (1) A changing edge detection circuit including: a first output node connected to a first output terminal, a second output node connected to a second output terminal, a pre-charging circuit that charges the first output node and the second output node, a first detection unit configured by connecting a first discharge circuit and a second discharge circuit controlled by a signal at a first input terminal and a signal at a second input terminal, respectively, in parallel to the first output node, and detecting a signal at which a changing edge occurs earlier in time out of the signal at the first input terminal and the signal at the second input terminal, and a second detection unit configured by connecting a third discharge circuit and a fourth discharge circuit controlled by the signal at the first input terminal and the signal at the second input terminal, respectively, in series to the second output node, and detecting a signal at which a changing edge occurs later in time out of the signal at the first input terminal and the signal at the second input terminal. (2) The changing edge detection circuit according to (1), wherein the first discharge circuit is configured by a MOS transistor having a gate to which the signal from the first input terminal is input, the second discharge circuit is configured by a MOS transistor having a gate to which the signal from the second input terminal is input, the third discharge circuit is configured by a MOS transistor having a gate to which the signal from the first input terminal is input, and the fourth discharge circuit is configured by a MOS transistor having a gate to which the signal from the second input terminal is input. (3) The changing edge detection circuit according to (2), wherein the first discharge circuit is configured by two MOS transistors connected in series, each having a gate to which the signal from the first input terminal is input, and the second discharge circuit is configured by two MOS transistors connected in series, each having a gate to which the signal from the second input terminal is input. (4) The changing edge detection circuit according to (1) or (2), wherein the second detection unit further includes a fifth discharge circuit to which a signal from the first input terminal is input and which is connected to the second output node, and a sixth discharge circuit to which a signal from the second input terminal is input and which is connected in series to the fifth discharge circuit, the fourth discharge circuit is connected to the second output node, and the third discharge circuit is connected in series to the fourth discharge circuit.(5) The changing edge detection circuit according to any one of (1), (2) and (4), further comprising: a seventh discharge circuit configured by a series connection of a MOS transistor having a gate to which a predetermined bias voltage is applied and connected to the first output node, and a MOS transistor having a gate to which the signal from the first input terminal is input; and an eighth discharge circuit configured by a series connection of a MOS transistor having a gate to which a predetermined bias voltage is applied and connected to the first output node, and a MOS transistor having a gate to which the signal from the second input terminal is input; wherein the first discharge circuit is configured by a series connection of a MOS transistor having a gate to which the signal from the first input terminal is input and connected to the first output node, and a MOS transistor having a gate to which a predetermined bias voltage is applied; and wherein the second discharge circuit is configured by a series connection of a MOS transistor having a gate to which the signal from the second input terminal is input and connected to the first output node, and a MOS transistor having a gate to which a predetermined bias voltage is applied. (6) The changing edge detection circuit according to any one of (1) to (5), wherein the first detection unit further comprises a capacitor connected to the first output node, and the second detection unit further comprises a capacitor connected to the second output node. (7) The changing edge detection circuit according to any one of (1) to (6), further comprising an output stopping unit that stops output of the detection results of the first detection unit and the second detection unit. (8) The changing edge detection circuit according to any one of (1) to (6), further comprising an operation stopping unit that stops operation of the first discharge circuit, the second discharge circuit, the third discharge circuit, and the fourth discharge circuit. (9) The changing edge detection circuit according to any one of (1) to (8), further comprising a shaping circuit that shapes an output signal of the detection result of the first detection unit. (10) The transition edge detection circuit according to any one of (1) to (9), wherein the pre-charging circuit is composed of a MOS transistor that applies a charging voltage to the first output node and a MOS transistor that applies a charging voltage to the second output node.(11) A first input terminal and a second input terminal; a first output terminal and a second output terminal; a comparison unit that compares a transition edge of a signal at the first input terminal with a transition edge of a signal at the second input terminal to detect a signal of a transition edge that occurs earlier in time; and a delay unit that delays an input signal by a predetermined delay amount and transmits the delayed signal to the first output terminal. a conversion unit including a first output node connected to the first output terminal, a second output node connected to the second output terminal, a pre-charging circuit that charges the first output node and the second output node, a first detection unit configured by a first discharge circuit and a second discharge circuit controlled by a signal at the first input terminal and a signal at the second input terminal, respectively, connected in parallel to the first output node, and detecting a signal at which a changing edge occurs earlier in time out of the signal at the first input terminal and the signal at the second input terminal, and inputting the signal to the delay unit, and a second detection unit configured by a third discharge circuit and a fourth discharge circuit controlled by the signal at the first input terminal and the signal at the second input terminal, respectively, connected in series to the second output node, and detecting a signal at which a changing edge occurs later in time out of the signal at the first input terminal and the signal at the second input terminal, and transmitting the signal to the second output terminal; a final stage comparison unit that compares a changing edge of the signal at the first output terminal of the conversion unit with a changing edge of the signal at the second output terminal of the conversion unit, and detects the signal of the changing edge that occurs earlier in time.(12) A first input terminal and a second input terminal; a first output terminal and a second output terminal; a comparison unit that compares a transition edge of a signal at the first input terminal with a transition edge of a signal at the second input terminal to detect a signal of a transition edge that occurs earlier in time; and a delay unit that delays an input signal by a predetermined delay amount and transmits the delayed signal to the first output terminal. a pre-charging circuit for charging the first output node and the second output node; a first detecting unit configured by a first discharging circuit and a second discharging circuit controlled by a signal at the first input end and a signal at the second input end, respectively, connected in parallel to the first output node, detecting a signal at which a changing edge occurs earlier in time out of the signal at the first input end and the signal at the second input end, and inputting the detected signal to the delay unit; and a second detecting unit configured by a third discharging circuit and a fourth discharging circuit controlled by a signal at the first input end and a signal at the second input end, respectively, connected in series to the second output node, detecting a signal at which a changing edge occurs later in time out of the signal at the first input end and the signal at the second input end, and transmitting the detected signal to the second output end. an electronic device comprising: a time-to-digital converter including a final-stage comparison unit that compares a changing edge of a signal at a first output terminal of the conversion unit with a changing edge of a signal at a second output terminal of the conversion unit, and detects a signal of a changing edge that occurs earlier in time; and a processing circuit that processes the detection results of the comparison unit of the edge detection circuit of the time-to-digital converter and the detection results of the final-stage comparison unit of the time-to-digital converter.

[0094] 1, 50 Analog-digital converter 10, 10a, 10b Conversion unit 20 Time-digital converter 30 Voltage-time converter 41 Capacitor 51 Digital-analog converter 80 Electronic device 100 Changing edge detection circuit 101, 191 First input terminal 102, 192 First output terminal 103 First output node 104, 193 Second input terminal 105, 194 Second output terminal 106 Second output node 110 First detection unit 111 First discharge circuit 112 Second discharge circuit 120 Second detection unit 121 Third discharge circuit 122 Fourth discharge circuit 123 Fifth discharge circuit 124 Sixth discharge circuit 130 Pre-charging circuit 170 Comparison unit 171 Final stage comparison unit 180, 181 Delay unit

Claims

a pre-charging circuit for charging the first output node and the second output node; a first detection unit configured to detect a signal whose changing edge occurs earlier in time of the signal at the first input end and the signal at the second input end, in which a first discharge circuit and a second discharge circuit controlled by a signal at a first input end and a signal at a second input end, respectively, are connected in parallel to the first output node; and a second detection unit configured to detect a signal whose changing edge occurs earlier in time of the signal at the first input end and the signal at the second input end, in which a third discharge circuit and a fourth discharge circuit controlled by a signal at the first input end and a signal at the second input end, respectively, are connected in series to the second output node, in which the second detection unit detects a signal whose changing edge occurs later in time of the signal at the first input end and the signal at the second input end.

2. The changing edge detection circuit according to claim 1, wherein the first discharge circuit is constituted by a MOS transistor having a gate to which the signal from the first input terminal is input, the second discharge circuit is constituted by a MOS transistor having a gate to which the signal from the second input terminal is input, the third discharge circuit is constituted by a MOS transistor having a gate to which the signal from the first input terminal is input, and the fourth discharge circuit is constituted by a MOS transistor having a gate to which the signal from the second input terminal is input.

3. The changing edge detection circuit according to claim 2, wherein the first discharge circuit is configured by connecting two MOS transistors in series, each of which receives a signal from the first input terminal at its gate, and the second discharge circuit is configured by connecting two MOS transistors in series, each of which receives a signal from the second input terminal at its gate.

4. The changing edge detection circuit of claim 1, wherein the second detection unit further comprises a fifth discharge circuit which receives a signal from the first input terminal and is connected to the second output node, and a sixth discharge circuit which receives a signal from the second input terminal and is connected in series to the fifth discharge circuit, the fourth discharge circuit is connected to the second output node, and the third discharge circuit is connected in series to the fourth discharge circuit.

5. The changing edge detection circuit according to claim 1, further comprising: a seventh discharge circuit configured by connecting in series a MOS transistor having a gate to which a predetermined bias voltage is applied and connected to the first output node and a MOS transistor to which the signal from the first input terminal is input; and an eighth discharge circuit configured by connecting in series a MOS transistor having a gate to which a predetermined bias voltage is applied and connected to the first output node and a MOS transistor to which the signal from the second input terminal is input, wherein the first discharge circuit is configured by connecting in series a MOS transistor having a gate to which the signal from the first input terminal is input and connected to the first output node and a MOS transistor to which a predetermined bias voltage is applied, and the second discharge circuit is configured by connecting in series a MOS transistor having a gate to which the signal from the second input terminal is input and connected to the first output node and a MOS transistor to which a predetermined bias voltage is applied.

6. The changing edge detection circuit according to claim 1, wherein the first detection section further comprises a capacitor connected to the first output node, and the second detection section further comprises a capacitor connected to the second output node.

7. The transition edge detection circuit according to claim 1, further comprising an output stopping section for stopping the output of the detection results of said first detection section and said second detection section.

8. The transition edge detection circuit according to claim 1, further comprising an operation stopping section which stops the operations of said first discharge circuit, said second discharge circuit, said third discharge circuit and said fourth discharge circuit.

9. The transition edge detection circuit according to claim 1, further comprising a shaping circuit for shaping an output signal of the detection result of said first detection section.

10. The transition edge detection circuit according to claim 1, wherein said pre-charging circuit is constituted by a MOS transistor for applying a charging voltage to said first output node and a MOS transistor for applying a charging voltage to said second output node.

11. A first input terminal and a second input terminal; a first output terminal and a second output terminal; a comparison section which compares a changing edge of a signal at the first input terminal with a changing edge of a signal at the second input terminal to detect a signal of a changing edge which occurs earlier in time; and a delay section which delays an input signal by a predetermined delay amount and transmits the delayed signal to the first output terminal. a conversion unit including a first output node connected to the first output terminal, a second output node connected to the second output terminal, a pre-charging circuit for charging the first output node and the second output node, a first detection unit configured to connect a first discharge circuit and a second discharge circuit controlled by a signal at the first input terminal and a signal at the second input terminal in parallel to the first output node, and detect a signal at which a changing edge occurs earlier in time among the signals at the first input terminal and the second input terminal, and input the detected signal to the delay unit, and a second detection unit configured to connect a third discharge circuit and a fourth discharge circuit controlled by a signal at the first input terminal and a signal at the second input terminal in series to the second output node, and detect a signal at which a changing edge occurs later in time among the signals at the first input terminal and the second input terminal, and transmit the detected signal to the second output terminal; a final stage comparison unit that compares a changing edge of a signal at a first output terminal of the conversion unit with a changing edge of a signal at a second output terminal of the conversion unit, and detects a signal of a changing edge that occurs earlier in time.

12. A first input terminal and a second input terminal; a first output terminal and a second output terminal; a comparison section which compares a changing edge of a signal at said first input terminal with a changing edge of a signal at said second input terminal to detect a signal of a changing edge which occurs earlier in time; and a delay section which delays an input signal by a predetermined delay amount and transmits the delayed signal to said first output terminal. a pre-charging circuit for charging the first output node and the second output node; a first detection unit configured to connect a first discharge circuit and a second discharge circuit controlled by a signal at the first input end and a signal at the second input end, respectively, in parallel to the first output node, and detect a signal at which a changing edge occurs earlier in time among the signal at the first input end and the signal at the second input end, and input the detected signal to the delay unit; and a second detection unit configured to connect a third discharge circuit and a fourth discharge circuit controlled by a signal at the first input end and a signal at the second input end, respectively, in series to the second output node, and detect a signal at which a changing edge occurs later in time among the signal at the first input end and the signal at the second input end, and transmit the detected signal to the second output end. an electronic device comprising: a time-to-digital converter including a final stage comparison unit that compares a changing edge of a signal at a first output terminal of the conversion unit with a changing edge of a signal at a second output terminal of the conversion unit, and detects a signal of a changing edge that occurs earlier in time; and a processing circuit that processes the detection result of the comparison unit of the edge detection circuit of the time-to-digital converter and the detection result of the final stage comparison unit of the time-to-digital converter.

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