Multilayer filter and front end module comprising same

Abstract

A multilayer filter according to an embodiment comprises: first and second ground layers; a plurality of conductive pattern layers stacked vertically between the first and second ground layers; a dielectric layer disposed between the first and second ground layers and the plurality of conductive pattern layers; and vias passing through the dielectric layer and connecting each of the first and second ground layers and the plurality of conductive pattern layers, wherein each of the plurality of conductive pattern layers includes an inductance pattern layer forming a plurality of inductors, the other parts of the plurality of conductive pattern layers include capacitance pattern layers facing each other vertically and facing each of the first and second ground layers to form a plurality of capacitors, and the plurality of inductors and the plurality of capacitors are connected vertically and horizontally using the vias. Therefore, the multilayer filter can filter a signal having a desired frequency band.

Description

Multilayer filter and front-end module including same

[0001] The embodiment relates to a multilayer filter and a front-end module including the same.

[0002] Wi-Fi 6E is the next extension to Wi-Fi 6 (also known as 802.11ax), enabling functionality in the 6 GHz band in addition to the currently supported 2.4 GHz and 5 GHz bands. Wi-Fi 6E operates under the same Wi-Fi standard as Wi-Fi 6, but with a wider spectrum. 6 GHz is a new frequency band ranging from 5.945 GHz to 7.125 GHz, allowing for up to 1,200 MHz of additional spectrum. Unlike existing frequencies where many channels are densely packed into a limited spectrum, the 6 GHz band allows networks to operate with greater bandwidth, faster speeds, and lower latency without the problems of overlap and interference.

[0003] However, as the frequency increases, the directivity of the radio waves increases, resulting in greater signal level attenuation and a decrease in data throughput. To compensate for this, a front-end module is required to distinguish between frequency bands.

[0004] A front-end module (FEM) is a transceiver device that controls radio signals used in mobile communication terminals. It is a composite component that integrates multiple electronic components uniformly on a single substrate, minimizing the integrated space. Most existing FEMs utilize elastic wave filters, such as surface acoustic wave (SAW) or bulk acoustic wave (BAW) filters. This has increased the price and size of existing FEMs, prompting ongoing research into this issue.

[0005] The embodiment provides an inexpensive and compact multilayer filter and a front-end module including the same.

[0006] According to one embodiment, a multilayer filter comprises first and second ground layers; a plurality of conductive pattern layers vertically stacked between the first and second ground layers; a dielectric layer disposed between the first and second ground layers and the plurality of conductive pattern layers; and a via penetrating the dielectric layer to connect each of the first and second ground layers and the plurality of conductive pattern layers, wherein each of the plurality of conductive pattern layers includes an inductance pattern layer forming a plurality of inductors, and the other of the plurality of conductive pattern layers includes a capacitance pattern layer forming a plurality of capacitors facing each other in the vertical direction and facing each of the first and second ground layers, and the plurality of inductors and the plurality of capacitors are connected in the vertical direction and the horizontal direction using the via, so as to filter a signal having a desired frequency band.

[0007] For example, the planar area of ​​each of the first and second ground layers may be larger than the planar area of ​​each of the plurality of conductive pattern layers.

[0008] For example, at least a portion of the inductance pattern layer may have a shape that is symmetrical with respect to an imaginary horizontal line that passes through the center of the long axis of the multilayer filter and is parallel to the short axis direction of the multilayer filter.

[0009] For example, the capacitance pattern layer may have a shape that is symmetrical with respect to an imaginary horizontal line that passes through the center of the long axis of the multilayer filter and is parallel to the short axis direction of the multilayer filter.

[0010] For example, the plurality of conductive pattern layers may include first to fifth conductive pattern layers sequentially stacked between the first ground layer and the second ground layer.

[0011] For example, the inductance pattern layer may include first and second inductor layers disposed on the first conductive pattern layer and electrically connected to each other; a third inductor layer disposed across the second conductive pattern layer and the third conductive pattern layer; fourth and fifth inductor layers disposed across the fourth conductive pattern layer and the fifth conductive pattern layer; a sixth inductor layer disposed across the second conductive pattern layer and the third conductive pattern layer while being spaced apart from the third inductor layer; a seventh inductor layer disposed across the first conductive pattern layer and the second conductive pattern layer while being spaced apart from the first and second inductor layers; an eighth inductor layer disposed on the fourth conductive pattern layer while being spaced apart from the fourth and fifth inductor layers, respectively; a ninth inductor layer disposed on the first conductive pattern layer while being spaced apart from the first and second inductor layers, respectively; It may include a tenth inductor layer disposed on the fourth conductive pattern layer and spaced apart from the fourth, fifth, and eighth inductor layers, respectively; and an eleventh inductor layer disposed on the first conductive pattern layer and connected to the seventh inductor layer and spaced apart from the first, second, and ninth inductor layers, respectively.

[0012] For example, at least some of the first to eleventh inductor layers may have a planar shape that is bent at least once in the horizontal direction.

[0013] For example, the capacitance pattern layer may include first to fourth capacitor layers disposed on the second conductive pattern layer while being spatially spaced apart from each other; a fifth capacitor layer disposed on the third conductive pattern layer while facing the first and second capacitor layers in the vertical direction; a sixth capacitor layer disposed on the third conductive pattern layer while being spaced apart from the fifth capacitor layer; seventh and eighth capacitor layers disposed on the fourth conductive pattern layer while being spaced apart from each other in the vertical direction with the fifth capacitor layer; ninth and tenth capacitor layers disposed on the fourth conductive pattern layer while being spaced apart from each other in the vertical direction with the sixth capacitor layer; an eleventh capacitor layer disposed on the fifth conductive pattern layer while being spaced apart from the seventh and eighth capacitor layers in the vertical direction with the fifth capacitor layer; and a twelfth capacitor layer disposed on the fifth conductive pattern layer while being spaced apart from the eleventh capacitor layer.

[0014] For example, the via forms a first contact point connecting the first and second inductor layers to each other, and a first via connecting the first capacitor layer and the seventh capacitor layer; a second via connecting the fifth capacitor layer and the eleventh capacitor layer and connected to the eighth inductor layer; a third via forming a third contact point connecting the second and third capacitor layers to each other, and connected to the ninth inductor layer; a fourth via connecting the sixth capacitor layer and the twelfth capacitor layer and connected to the tenth inductor layer; a fifth via forming a fifth contact point connecting the seventh and eleventh inductor layers to each other, and connecting the fourth capacitor layer and the tenth capacitor layer; a sixth via connecting the first inductor layer disposed on each of the first and second conductive pattern layers; a seventh via connecting the first inductor layer to the first or second ground layer; an eighth via connecting the second inductor layer to the first or second ground layer; A ninth via connecting the seventh inductor layer disposed on each of the first and second conductive pattern layers; a tenth via connecting the seventh inductor layer to the first or second ground layer; an eleventh via connecting the ninth inductor layer to the first or second ground layer; a twelfth via connecting the eleventh inductor layer to the first or second ground layer; a thirteenth via connecting the second capacitor layer and the eighth capacitor layer; a fourteenth via connecting the third capacitor layer and the ninth capacitor layer; a fifteenth via connecting the third inductor layer disposed on each of the second and third conductive pattern layers; a sixteenth via connecting the sixth inductor layer disposed on each of the second and third conductive pattern layers; a seventeenth via connecting the eighth inductor layer to the first or second ground layer; an eighteenth via connecting the tenth inductor layer to the first or second ground layer; A 19th via connecting the fourth inductor layer disposed on each of the fourth and fifth conductive pattern layers;A 20th via connecting the fifth inductor layer disposed on each of the fourth and fifth conductive pattern layers; and a ground via connecting the first and second ground layers to each other by penetrating the first to fifth conductive pattern layers.

[0015] For example, the fifth capacitor layer may include a first through hole through which the first via passes and is spaced apart from the first via; and a second through hole through which the thirteenth via passes and is spaced apart from the thirteenth via; and the sixth capacitor layer may include a third through hole through which the fourteenth via passes and is spaced apart from the fourteenth via; and a fourth through hole through which the fifth via passes and is spaced apart from the fifth via.

[0016] For example, the seventh and eighth capacitor layers may have a planar shape spaced apart from each other with the second via interposed therebetween.

[0017] For example, the 9th and 10th capacitor layers may have a planar shape spaced apart from each other with the 4th via interposed therebetween.

[0018] For example, the first inductor layer may include a first upper inductor layer connecting the first via and the sixth via in the first conductive pattern layer; and a first lower inductor layer connecting the sixth via and the seventh via in the second conductive pattern layer; and the seventh inductor layer may include a seventh upper inductor layer connecting the fifth via and the ninth via in the first conductive pattern layer; and a seventh lower inductor layer connecting the ninth via and the tenth via in the second conductive pattern layer.

[0019] For example, the third inductor layer may include a third upper inductor layer connecting the 15th via and the first capacitor layer in the second conductive pattern layer; and a third lower inductor layer connecting the 15th via and the 5th capacitor layer in the third conductive pattern layer; and the sixth inductor layer may include a sixth upper inductor layer connecting the 16th via and the 4th capacitor layer in the second conductive pattern layer; and a sixth lower inductor layer connecting the 16th via and the 6th capacitor layer in the third conductive pattern layer.

[0020] For example, the fourth inductor layer may include a fourth upper inductor layer connecting the 19th via and the 8th capacitor layer in the fourth conductive pattern layer; and a fourth lower inductor layer connecting the 19th via and the 11th capacitor layer in the fifth conductive pattern layer; and the fifth inductor layer may include a fifth upper inductor layer connecting the 20th via and the 9th capacitor layer in the fourth conductive pattern layer; and a fifth lower inductor layer connecting the 20th via and the 12th capacitor layer in the fifth conductive pattern layer.

[0021] A multilayer filter according to another embodiment comprises: a first inductor having one end connected to a first port; a second inductor connected between the other end of the first inductor and ground; a third inductor having one end connected to the other end of the first inductor; a fourth inductor having one end connected to the other end of the third inductor; a fifth inductor having one end connected to the other end of the fourth inductor; a sixth inductor having one end connected to the other end of the fifth inductor; a seventh inductor connected between the other end of the sixth inductor and the second port; an eighth inductor connected between the other end of the third inductor and ground; a ninth inductor connected between the other end of the fourth inductor and ground; a tenth inductor connected between the other end of the fifth inductor and ground; an eleventh inductor connected between the other end of the sixth inductor and ground; a first capacitor connected in parallel with the second inductor; It may include a second capacitor connected in parallel to the third inductor; a third capacitor connected in parallel to the fourth inductor; a fourth capacitor connected in parallel to the fifth inductor; a fifth capacitor connected in parallel to the sixth inductor; a sixth capacitor connected in parallel to the eighth inductor; a seventh capacitor connected in parallel to the ninth inductor; an eighth capacitor connected in parallel to the tenth inductor; and a ninth capacitor connected in parallel to the eleventh inductor.

[0022] For example, the first, sixth, seventh, eighth and ninth capacitors may be parasitic capacitors.

[0023] A front-end module according to another embodiment may include: an antenna; a first amplifier that amplifies a signal received through the antenna; a multilayer filter that filters and outputs the signal amplified by the first amplifier; a second amplifier that amplifies a signal to be transmitted through the antenna; and a switch disposed between each of an input terminal of the first amplifier and an output terminal of the second amplifier and the antenna.

[0024] A multilayer filter according to an embodiment and a front-end module including the same can implement a shunt capacitor as a parasitic capacitance, so that it has a small size and can easily tune the frequency without requiring a separate capacitor layer, has a configuration that can easily increase or adjust the capacitance and inductance, and has excellent frequency selectivity.

[0025] Figure 1 shows a cross-sectional view of a multilayer filter according to an embodiment.

[0026] FIG. 2 schematically illustrates a perspective view according to one embodiment of the multilayer filter illustrated in FIG. 1.

[0027] Figure 3 shows a circuit diagram of a multilayer filter according to one embodiment.

[0028] Figure 4a shows a perspective view of the appearance of a multilayer filter according to one embodiment.

[0029] Figure 4b shows a plan view of a multilayer filter according to one embodiment.

[0030] FIG. 5a shows a perspective view of an embodiment in which the first ground layer is removed from the multilayer filter illustrated in FIG. 4a.

[0031] Figure 5b shows a plan view according to an embodiment of the perspective view shown in Figure 5a.

[0032] Fig. 6 shows a plan view according to an embodiment of the first challenge pattern layer illustrated in Fig. 5b.

[0033] Fig. 7a shows a perspective view according to an embodiment in which the first challenge pattern layer is removed in Fig. 5a.

[0034] Figure 7b shows a plan view of a second challenge pattern layer according to an embodiment.

[0035] Fig. 8a shows a perspective view of an embodiment in which the second challenge pattern layer is removed from Fig. 7a.

[0036] Figure 8b shows a plan view of a third challenge pattern layer according to an embodiment.

[0037] Fig. 9a shows a perspective view of an embodiment in which the third challenge pattern layer is removed from Fig. 8a.

[0038] Figure 9b shows a plan view of the fourth challenge pattern layer according to an embodiment.

[0039] Fig. 10a shows a perspective view of an embodiment in which the fourth challenge pattern layer is removed from Fig. 9a.

[0040] Figure 10b shows a plan view of the fifth challenge pattern layer according to an embodiment.

[0041] Fig. 11a shows a perspective view of an embodiment in which the fifth challenge pattern layer is removed from Fig. 10a.

[0042] Figure 11b shows a plan view of a second ground layer according to an embodiment.

[0043] Fig. 12 is a cross-sectional view according to an embodiment of the multilayer filter illustrated in Fig. 4a cut along line I-I'.

[0044] Fig. 13 is a graph showing the insertion loss of a multilayer filter according to an embodiment.

[0045] Fig. 14 is a graph showing return loss according to an embodiment.

[0046] Fig. 15 shows a block diagram of a front-end module according to an embodiment.

[0047] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0048] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0049] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0050] In addition, the terminology used in the embodiments of the present invention is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0051] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and are not intended to limit the nature, order, or sequence of the components.

[0052] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0053] Additionally, when described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when expressed as "above" or "below," it can include the meaning of a downward direction as well as an upward direction based on one component.

[0054] Hereinafter, a multilayer filter (100, 100A) and a front-end module (200) including the same according to an embodiment will be described with reference to the attached drawings as follows. For convenience, the multilayer filter (100, 100A) will be described using a Cartesian coordinate system (x-axis, y-axis, z-axis), but it is obvious that the multilayer filter (100, 100A) can also be described using other coordinate systems. In addition, according to the Cartesian coordinate system, the x-axis, y-axis, and z-axis are orthogonal to each other, but the embodiment is not limited thereto. That is, the x-axis, y-axis, and z-axis may intersect each other. Hereinafter, for convenience of description, the x-axis direction is referred to as a 'first direction', the y-axis direction is referred to as a 'second direction', and the z-axis direction is referred to as a 'third direction'.

[0055] Figure 1 shows a cross-sectional view of a multilayer filter (100) according to an embodiment.

[0056] According to an embodiment, the multilayer filter (100) includes a plurality of layers. That is, as illustrated in FIG. 1, the multilayer filter (100) may include a first ground (or ground) layer (GL1), a second ground layer (GL2), first to Nth conductive pattern layers (TL1 to TLN), a dielectric layer (or printed circuit board (PCB)) [DL1 to DL(N+1)], and a via (not illustrated). Here, N is a positive integer greater than or equal to 3.

[0057] The first to Nth conductive pattern layers (TL1 to TLN) can be sequentially stacked and arranged in a third direction, which is a vertical direction, between the first ground layer (GL1) and the second ground layer (GL2).

[0058] According to an embodiment, the ground connected to each of the first and second ground layers (GL1, GL2) may be an RF ground or a DC ground. Here, when the multilayer filter (100) is a single product, each of the first and second ground layers (GL1, GL2) is connected to an RF ground, and when the multilayer filter (100) is included in a front-end module (200) described later, each of the first and second ground layers (GL1, GL2) may be connected to an RF or DC ground, but the embodiment is not limited thereto. The first and second ground layers (GL1, GL2) may have a configuration that caps the first to Nth conductive pattern layers (TL1 to TLN), the dielectric layers [DL1 to DL(N+1)], and the vias. The first and second ground layers (GL1, GL2) may perform an isolation role between an RF signal and a DC signal in the WiFi module.

[0059] In addition, the dielectric layers [DL1 to DL(N+1)] may be disposed between the first and second ground layers (GL1, GL2) and the first to Nth conductive pattern layers (TL1 to TLN). That is, the first dielectric layer (DL1) may be disposed between the first ground layer (GL1) and the first conductive pattern layer (TL1), and the N+1th dielectric layer [DL(N+1)] may be disposed between the Nth conductive pattern layer (TLN) and the second ground layer (GL2). In this way, the kth dielectric layer (DLk) may be disposed between the kth conductive pattern layer (TLk) and the k+1th conductive pattern layer (TL(k+1)). Here, 1≤k≤N-1. In this way, the number of dielectric layers may be one more than the number of conductive pattern layers.

[0060] If N=3, the first to third conductive pattern layers (TL1 to TL3) may be sequentially laminated between the first ground layer (GL1) and the second ground layer (GL2), and the first to fourth dielectric layers (DL1 to DL4) may be arranged between the first ground layer (GL1), the first to third conductive pattern layers (TL1 to TL3), and the second ground layer (GL2).

[0061] Vias penetrate the dielectric layers [DL1 to DL(N+1)] and connect the first and second grounds (GL1, GL2) and multiple conductive pattern layers, respectively. This will be described in detail later.

[0062] FIG. 2 schematically shows a perspective view according to one embodiment (100A) of the multilayer filter (100) illustrated in FIG. 1.

[0063] When N=5, as illustrated in FIG. 2, first to fifth conductive pattern layers (TL1 to TL5) may be sequentially stacked and arranged between the first ground layer (GL1) and the second ground layer (GL2), and first to sixth dielectric layers (DL1 to DL6) may be arranged between the first ground layer (GL1), the first to fifth conductive pattern layers (TL1 to TL5), and the second ground layer (GL2), respectively.

[0064] Each of the first to Nth conductive pattern layers (TL1 to TLN) may include an inductance pattern layer forming a plurality of inductors. For this purpose, the inductance pattern layer may be implemented as a conductor. For example, each of the first to fifth conductive pattern layers (TL1 to TL5) may include an inductance pattern layer.

[0065] In addition, some of the first to Nth conductive pattern layers (TL1 to TLN) may include capacitance pattern layers that face each other in a third direction, which is a vertical direction, to form a capacitance. For example, vertically adjacent second to fifth conductive pattern layers (TL2) to fifth conductive pattern layers (TL5) may each have their respective capacitor pattern layers implemented as conductors having electrical conductivity, and second to fifth dielectric layers (DL2 to DL5) made of a dielectric material may be disposed therebetween, thereby forming a plurality of capacitors.

[0066] Additionally, according to an embodiment, the capacitance pattern layer may form a capacitor having a parasitic capacitance facing each of the first and second ground layers (GL1, GL2).

[0067] As described above, the multilayer filter (100, 100A) according to the implemented embodiment may be a bandpass filter that filters a signal having a desired frequency band by vertically connecting a capacitor and an inductor using a via and horizontally connecting a capacitor and an inductor.

[0068] Hereinafter, a multilayer filter according to an embodiment in which N=5, the second to fifth conductive pattern layers (TL2 to TL5) except for the first conductive pattern layer (TL1) include a capacitance pattern layer, and each of the first to fifth conductive pattern layers (TL1 to TL5) includes an inductance pattern layer is described as follows.

[0069] Figure 3 shows a circuit diagram of a multilayer filter according to one embodiment.

[0070] The multilayer filter according to the embodiment illustrated in FIG. 3 is a type of band-pass filter and includes first to eleventh inductors (L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11) and first to ninth capacitors (C1, C2, C3, C4, C5, C6, C7, C8, C9).

[0071] The first inductor (L1) has one end connected to the first port (P1). The second inductor (L2) can be connected between the first contact point (NP1), which is the other end of the first inductor (L1), and ground. The third inductor (L3) has one end connected to the other end (NP1) of the first inductor (L1). The fourth inductor (L4) has one end connected to the second contact point (NP2), which is the other end of the third inductor (L3). The fifth inductor (L5) has one end connected to the third contact point (NP3), which is the other end of the fourth inductor (L4). The sixth inductor (L6) has one end connected to the fourth contact point (NP4), which is the other end of the fifth inductor (L5). The seventh inductor (L7) can be connected between the fifth contact (NP5), which is the other end of the sixth inductor (L6), and the second port (P2).

[0072] The first port (P1) may be an input port from which a signal enters, and the second port (P2) may be an output port from which a signal is output. Alternatively, the first port (P1) may be an output port from which a signal is output, and the second port (P2) may be an input port from which a signal enters.

[0073] The eighth inductor (L8) may be connected between the other terminal (NP2) of the third inductor (L3) and ground. The ninth inductor (L9) may be connected between the other terminal (NP3) of the fourth inductor (L4) and ground. The tenth inductor (L10) may be connected between the other terminal (NP4) of the fifth inductor (L5) and ground. The eleventh inductor (L11) may be connected between the other terminal (NP5) of the sixth inductor (L6) and ground.

[0074] Meanwhile, the first capacitor (C1) may be connected in parallel to the second inductor (L2), the second capacitor (C2) may be connected in parallel to the third inductor (L3), the third capacitor (C3) may be connected in parallel to the fourth inductor (L4), the fourth capacitor (C4) may be connected in parallel to the fifth inductor (L5), the fifth capacitor (C5) may be connected in parallel to the sixth inductor (L6), the sixth capacitor (C6) may be connected in parallel to the eighth inductor (L8), the seventh capacitor (C7) may be connected in parallel to the ninth inductor (L9), the eighth capacitor (C8) may be connected in parallel to the tenth inductor (L10), and the ninth capacitor (C9) may be connected in parallel to the eleventh inductor (L11).

[0075] According to an embodiment, the first, sixth, seventh, eighth and ninth capacitors (C1, C6, C7, C8, C9) can be implemented as parasitic capacitances.

[0076] The multilayer filter (100, 100A) according to the embodiment may have various configurations to perform the function of the bandpass filter illustrated in FIG. 3, and an example is described below with reference to FIGS. 4 to 12, but the embodiment is not limited thereto. That is, the multilayer filter (100, 100A) according to the embodiment may implement a filter having a configuration different from the circuit illustrated in FIG. 3.

[0077] Hereinafter, an implementation example of a multilayer filter (100, 100A) according to an embodiment will be described with reference to the attached drawings as follows. To facilitate understanding, it is described that N=5. That is, the plurality of conductive pattern layers are described as including first to fifth conductive pattern layers (TL1, TL2, TL3, TL4, TL5) sequentially laminated between the first ground layer (GL1) and the second ground layer (GL2), but the following description is not limited to a specific number of N.

[0078] FIG. 4a is a perspective view showing the appearance of a multilayer filter according to an embodiment, FIG. 4b is a plan view showing a multilayer filter according to an embodiment, FIG. 5a is a perspective view showing the multilayer filter shown in FIG. 4a with the first ground layer (GL1) removed, FIG. 5b is a plan view showing the perspective view shown in FIG. 5a, FIG. 6 is a plan view showing the first conductive pattern layer (TL1) shown in FIG. 5b, FIG. 7a is a perspective view showing the first conductive pattern layer (TL1) removed from FIG. 5a, FIG. 7b is a plan view showing the second conductive pattern layer (TL2), FIG. 8a is a perspective view showing the second conductive pattern layer (TL2) removed from FIG. 7a, FIG. 8b is a plan view showing the third conductive pattern layer (TL3), FIG. 9a is a perspective view showing the third conductive pattern layer (TL3) removed from FIG. 8a, and FIG. 9b is a plan view showing the fourth conductive pattern layer (TL1). A plan view of a pattern layer (TL4) is shown, FIG. 10a is a perspective view of FIG. 9a with the fourth conductive pattern layer (TL4) removed, FIG. 10b is a plan view of a fifth conductive pattern layer (TL5), FIG. 11a is a perspective view of FIG. 10a with the fifth conductive pattern layer (TL5) removed, FIG. 11b is a plan view of a second ground layer (GL2), and FIG. 12 is a cross-sectional view taken along line I-I' of the multilayer filter shown in FIG. 4a.

[0079] According to an embodiment, in a multilayer filter, the ground layer can perform a complex function of a ground, a function of forming a parasitic capacitance, and a function of shielding from the outside. In particular, for the shielding function, the planar area of ​​each of the first and second ground layers (GL1, GL2) can be larger than the planar area of ​​each of the plurality of conductive pattern layers (TL1 to TL5). This is to ensure that the first and second ground layers (GL1, GL2) cover the entirety of the first to fifth conductive pattern layers (TL1 to TL5).

[0080] Just as the circuit illustrated in FIG. 3 is symmetrical left / right, at least some of the inductance pattern layers illustrated in FIGS. 4a to 10b may have a symmetrical shape based on an imaginary horizontal line (IH) that passes through the center of the long axis (i.e., x-axis) of the multilayer filter and is parallel to the second direction, which is the short axis direction of the multilayer filter.

[0081] Similarly, at least some of the conductance pattern layers illustrated in FIGS. 4A to 10B may have a shape that is symmetrical with respect to an imaginary horizontal line (IH) that passes through the center of the major axis (i.e., x-axis) of the multilayer filter and is parallel to the second direction, which is the minor axis direction of the multilayer filter.

[0082] The inductance pattern layer may include first to eleventh inductor layers (LP1 to LP11).

[0083] The first inductor layer (LP1) implements the first inductor (L1) illustrated in FIG. 3, and the second inductor layer (LP2) is a layer implementing the second inductor (L2). As illustrated in FIG. 6, the first upper inductor layer (LPU1), which is part of the first inductor layer (LP1), and the second inductor layer (LP2) can meet at the first via (VA1) and be electrically connected to each other. As illustrated in FIGS. 6 to 7b, the first inductor layer (LP1) can be arranged across the first conductive pattern layer (TL1) and the second conductive pattern layer (TL2), whereas the second inductor layer (LP2) can be arranged only on the first conductive pattern layer (TL1).

[0084] In addition, the third inductor layer (LP3) is a layer that implements the third inductor (L3) illustrated in FIG. 3, and can be arranged across the second conductive pattern layer (TL2) and the third conductive pattern layer (TL3).

[0085] In addition, the fourth inductor layer (LP4) implements the fourth inductor (L4) illustrated in FIG. 3, and the fifth inductor layer (LP5) is a layer implementing the fifth inductor (L5), and each of the fourth and fifth inductor layers (LP4, LP5) can be arranged across the fourth conductive pattern layer (TL4) and the fifth conductive pattern layer (TL5).

[0086] In addition, the sixth inductor layer (LP6) is a layer that implements the sixth inductor (L6) illustrated in FIG. 3, and can be arranged across the second conductive pattern layer (TL2) and the third conductive pattern layer (TL3) while being spaced apart from the third inductor layer (LP3).

[0087] In addition, the seventh inductor layer (LP7) is a layer that implements the seventh inductor (L7) illustrated in FIG. 3, and may be arranged across the first conductive pattern layer (TL1) and the second conductive pattern layer (TL1). At this time, the seventh inductor layer (LP7) may be arranged while being spaced apart from the first, second, and ninth inductor layers (LP1, LP2, LP9) on the first conductive pattern layer (TL1).

[0088] In addition, the eighth inductor layer (LP8) is a layer that implements the eighth inductor (L8) illustrated in FIG. 3, and can be placed on the fourth conductive pattern layer (TL4) while being spaced apart from each of the fourth, fifth, and tenth inductor layers (L4, L5, L1).

[0089] In addition, the ninth inductor layer (LP9) is a layer that implements the ninth inductor (L9) illustrated in FIG. 3, and can be placed on the first conductive pattern layer (TL1) while being spaced apart from the first, second, seventh, and eleventh inductor layers (L1, L2, L7, L11), respectively.

[0090] In addition, the 10th inductor layer (LP10) is a layer that implements the 10th inductor (L10) illustrated in FIG. 3, and can be placed on the 4th conductive pattern layer (TL4) while being spaced apart from the 4th, 5th, and 8th inductor layers (LP4, LP5, LP8), respectively.

[0091] In addition, the 11th inductor layer (LP11) is a layer that implements the 11th inductor (L11) illustrated in FIG. 3, and may be spaced apart from the first, second, and ninth inductor layers (LP1, LP2, LP9), connected to the seventh inductor layer (LP7), and arranged on the first conductive pattern layer (TL1).

[0092] Meanwhile, the capacitance pattern layer may include first to ninth capacitor layers (CP1, CP2, CP3, CP4, CP5, CP6, CP7, CP8, CP9).

[0093] The first to fourth capacitor layers (CP1 to CP4) may be arranged on the second conductive pattern layer (TL2) while being spatially spaced apart from each other. Referring to FIG. 7b, the first and second capacitor layers (CP1 and CP2) may have a planar shape in which the first and second capacitor layers (CP2 and CP3) are spaced apart from each other by a first width (W1) in the first direction, the second and third capacitor layers (CP2 and CP3) are spaced apart from each other by a second width (W2) in the first direction, and the third and fourth capacitor layers (CP3 and CP4) are spaced apart from each other by a third width (W3) in the first direction.

[0094] At least a portion of the fifth capacitor layer (CP5) may be disposed on the third conductive pattern layer (TL3) while facing the first and second capacitor layers (CP1, CP2) in a third direction, which is a vertical direction. At least a portion of the sixth capacitor layer (CP6) may be disposed on the third conductive pattern layer (TL3) while facing the third and fourth capacitor layers (CP3, CP4) in a third direction, which is a vertical direction, and while being spaced apart from the fifth capacitor layer (CP5) in a horizontal direction. Referring to FIG. 8B, the fifth and sixth capacitor layers (CP5 and CP6) may have a planar shape spaced apart from each other by a fourth width (W4) in the first direction.

[0095] At least a portion of the seventh and eighth capacitor layers (CP7, CP8) may be disposed horizontally spaced apart from each other in the fourth conductive pattern layer (TL4) while facing the fifth capacitor layer (CP5) in a third direction, which is a vertical direction. At least a portion of the ninth and tenth capacitor layers (CP9, CP10) may be disposed horizontally spaced apart from each other in the fourth conductive pattern layer (TL4) while facing the sixth capacitor layer (CP6) in a third direction, which is a vertical direction. Referring to FIG. 9b, the eighth and ninth capacitor layers (CP8 and CP9) may have a planar shape spaced apart from each other in the first direction by a fifth width (W5).

[0096] At least a portion of the eleventh capacitor layer (CP11) may be disposed on the fifth conductive pattern layer (TL5) while facing in a third direction, which is a vertical direction, with respect to the seventh and eighth capacitor layers (CP7, CP8). At least a portion of the twelfth capacitor layer (CP12) may be disposed on the fifth conductive pattern layer (TL5) while facing in a third direction, which is a vertical direction, with respect to the ninth and tenth capacitor layers (CP9, CP10) and while being spaced apart from the eleventh capacitor layer (CP11) in a horizontal direction. Referring to FIG. 10b, the eleventh and twelfth capacitor layers (CP11 and CP12) may have a planar shape spaced apart in the first direction by a sixth width (W6).

[0097] According to an embodiment, the first to sixth widths (W1 to W6) may be the same or different. For example, the second, fourth, fifth, and sixth widths (W2, W4, W5, W6) may be the same.

[0098] Each of the first to sixth widths (W1 to W6) may be, for example, 25 μm or more, preferably 50 μm or more or 120 μm or more. In some cases, if each of the first to sixth widths (W1 to W6) is less than 50 μm, undesired parasitic capacitance may be generated, narrowing the bandwidth of the pass band or generating spurious waves, which may affect harmonics. If each of the first to sixth widths (W1 to W6) is greater than 300 μm, there may be minimal change in performance and only an increase in the size of the multilayer filter. Therefore, each of the first to sixth widths (W1 to W6) may be 50 μm to 300 μm, but the embodiment is not limited thereto.

[0099] As illustrated, the first capacitor layer (CP1) and the seventh capacitor layer (CP7) are connected to each other, the second capacitor layer (CP2) and the eighth capacitor layer (CP8) are electrically connected to each other, the fifth capacitor layer (CP5) and the eleventh capacitor layer (CP11) are electrically connected to each other, the first and second capacitor layers (CP1, CP2) face each other with the fifth capacitor layer (CP5) and the third dielectric layer (DL3) interposed therebetween, the fifth capacitor layer (CP5) faces each other with the seventh and eighth capacitor layers (CP7, CP8) and the fourth dielectric layer (DL4) interposed therebetween, and the seventh and eighth capacitor layers (CP7, CP8) face each other with the eleventh capacitor layer (CP11) and the fifth dielectric layer (DL5) interposed therebetween, thereby implementing the second and third capacitors (C2, C3) illustrated in FIG. 3.

[0100] In addition, the third capacitor layer (CP3) and the ninth capacitor layer (CP9) are connected to each other, the fourth capacitor layer (CP4) and the tenth capacitor layer (CP10) are electrically connected to each other, the sixth capacitor layer (CP6) and the twelfth capacitor layer (CP12) are electrically connected to each other, the third and fourth capacitor layers (CP3, CP4) face each other with the sixth capacitor layer (CP6) and the third dielectric layer (DL3) interposed therebetween, the sixth capacitor layer (CP6) faces each other with the ninth and tenth capacitor layers (CP9, CP10) and the fourth dielectric layer (DL4) interposed therebetween, and the ninth and tenth capacitor layers (CP9, CP10) face each other with the twelfth capacitor layer (CP12) and the fifth dielectric layer (DL5) interposed therebetween, thereby implementing the fourth and fifth capacitors (C4, C5) illustrated in FIG. 3.

[0101] Meanwhile, the multilayer filter may include multiple vias (e.g., VA1 to VA22, VG1 to VG8).

[0102] The first via (VA1) corresponds to the first contact point (NP1) illustrated in FIG. 3, where the first and second inductor layers (LP1, LP2) meet, and serves to connect the first capacitor layer (CP1) and the seventh capacitor layer (CP7).

[0103] The second via (VA2) connects the fifth capacitor layer (CP5) and the eleventh capacitor layer (CP11), corresponds to the second contact point (NP2) illustrated in FIG. 3, and can be connected to the eighth inductor layer (LP8).

[0104] The third via (VA3) connects the second and third capacitor layers (CP2, CP3) to each other, corresponds to the third contact point (NP3) illustrated in FIG. 3, and can connect the ninth inductor layer (LP9) and the second and third capacitor layers (CP2, CP3).

[0105] The fourth via (VA4) connects the sixth capacitor layer (CP6) and the twelfth capacitor layer (CP12), corresponds to the fourth contact point (NP4) illustrated in FIG. 3, and can be connected to the tenth inductor layer (LP10).

[0106] The fifth via (VA5) is connected to the sixth inductor layer (LP6) via the fourth capacitor layer (CP4) in the second conductive pattern layer (TL2) and the seventh and eleventh inductor layers (LP7, LP11) in the first conductive pattern layer (TL1), and corresponds to the fifth contact point (NP5) illustrated in FIG. 3, and can connect the fourth capacitor layer (CP4) and the tenth capacitor layer (CP10).

[0107] The sixth via (VA6) serves to connect the first inductor layer (LP1) disposed on each of the first and second conductive pattern layers (TL1, TL2). The first inductor layer (LP1) may include a first upper inductor layer (LPU1) and a first lower inductor layer (LPL1). The first upper inductor layer (LPU1) is disposed between the first via (VA1) and the sixth via (VA6) in the first conductive pattern layer (TL1) while connecting them. The first lower inductor layer (LPL1) is disposed between the sixth via (VA6) and the seventh via (VA7) in the second conductive pattern layer (TL2) while connecting them.

[0108] The seventh via (VA7) serves to connect the first inductor layer (LP1) (e.g., the first lower inductor layer (LPL1) in the illustrated case) to the first or second ground layer (GL1, GL2) (e.g., GL2 in the illustrated case).

[0109] The eighth via (VA8) serves to connect the second inductor layer (LP2) to the first or second ground layer (GL1, GL2) (e.g., GL1 in the illustrated case).

[0110] The ninth via (VA9) serves to connect the seventh inductor layer (LP7) arranged on each of the first and second conductive pattern layers (TL1, TL2).

[0111] The tenth via (VA10) serves to connect the seventh inductor layer (LP7) to the first or second ground layer (GL1, GL2) (e.g., GL2 in the illustrated case). The seventh inductor layer (LP7) may include a seventh upper inductor layer (LPU7) and a seventh lower inductor layer (LPL7). The seventh upper inductor layer (LPU7) is disposed between the fifth via (VA5) and the ninth via (VA9) in the first conductive pattern layer (TL1) and connects them. The seventh lower inductor layer (LPL7) is disposed between the ninth via (VA9) and the tenth via (VA10) in the second conductive pattern layer (TL2).

[0112] The eleventh via (VA11) serves to connect the ninth inductor layer (LP9) to the first or second ground layer (GL1, GL2) (e.g., GL1 in the illustrated case).

[0113] The 12th via (VA12) serves to connect the 11th inductor layer (LP11) to the first or second ground layer (GL1, GL2) (e.g., GL1 in the illustrated case).

[0114] The 13th via (VA13) serves to connect the second capacitor layer (CP2) and the eighth capacitor layer (CP8).

[0115] The 14th via (VA14) serves to connect the third capacitor layer (CP) and the ninth capacitor layer (CP9).

[0116] The fifteenth via (VA15) serves to connect the third inductor layer (LP3) disposed on each of the second and third conductive pattern layers (TL2, TL3). The third inductor layer (LP3) may include a third upper inductor layer (LPU3) and a third lower inductor layer (LPL3). The third upper inductor layer (LPU3) may be disposed between the fifteenth via (VA15) and the first capacitor layer (CP1) in the second conductive pattern layer (TL2) while connecting them. At this time, a twenty-first via (VA21) may further be disposed between the third upper inductor layer (LPU3) and the first capacitor layer (CP1). The third lower inductor layer (LPL3) can be placed between the fifth capacitor layer (CP5) and the fifteenth via (VA15) in the third conductive pattern layer (TL3).

[0117] The sixteenth via (VA16) serves to connect the sixth inductor layer (LP6) disposed on each of the second and third conductive pattern layers (TL2, TL3). The sixth inductor layer (LP6) may include a sixth upper inductor layer (LPU6) and a sixth lower inductor layer (LPL6). The sixth upper inductor layer (LPU6) may be disposed between the sixteenth via (VA16) and the fourth capacitor layer (CP4) in the second conductive pattern layer (TL2). At this time, a twenty-second via (VA22) may further be disposed between the sixth upper inductor layer (LPU6) and the fourth capacitor layer (CP4). The sixth lower inductor layer (LPL6) can be placed between the sixteenth via (VA16) and the sixth capacitor layer (CP6) in the third conductive pattern layer (TL3) while connecting them (VA16, CP6).

[0118] The 17th via (VA17) serves to connect the 8th inductor layer (LP8) to the first or second ground layer (GL1, GL2) (e.g., GL2 in the illustrated case).

[0119] The 18th via (VA18) serves to connect the 10th inductor layer (LP10) to the first or second ground layer (GL1, GL2) (e.g., GL2 in the illustrated case).

[0120] The nineteenth via (VA19) serves to connect the fourth inductor layer (LP4) disposed on each of the fourth and fifth conductive pattern layers (TL4, TL5). The fourth inductor layer (LP4) may include a fourth upper inductor layer (LPU4) and a fourth lower inductor layer (LPL4). The fourth upper inductor layer (LPU4) may be disposed between the nineteenth via (VA19) and the eighth capacitor layer (CP8) in the fourth conductive pattern layer (TL4) while connecting them (VA19, CP8). The fourth lower inductor layer (LPL4) may be disposed between the nineteenth via (VA19) and the eleventh capacitor layer (CP11) in the fifth conductive pattern layer (TL5) while connecting them (VA19, CP11).

[0121] The 20th via (VA20) serves to connect the fifth inductor layer (LP5) disposed on each of the fourth and fifth conductive pattern layers (TL4, TL5). The fifth inductor layer (LP5) may include a fifth upper inductor layer (LPU5) and a fifth lower inductor layer (LPL5). The fifth upper inductor layer (LPU5) may be disposed between the 20th via (VA20) and the ninth capacitor layer (CP9) in the fourth conductive pattern layer (TL4) while connecting them (VA20, CP9). The fifth lower inductor layer (LPL5) may be disposed between the 20th via (VA20) and the twelfth capacitor layer (CP12) in the fifth conductive pattern layer (TL5) while connecting them (VA19, CP12).

[0122] Meanwhile, the ground vias serve to connect the first and second ground layers (GL1, GL2) by penetrating the first to fifth conductive pattern layers (TL1 to TL5). As illustrated, the ground vias may include first, fourth, fifth, and eighth ground vias (VG1, VG4, VG5, VG8) arranged on the outside of each layer (GL1, GL2, TL1 to TL5) and second, third, sixth, and seventh ground vias (VG2, VG3, VG6, VG7) arranged on the inside of each layer (GL1, GL2, TL1 to TL5), but the embodiments are not limited to a specific number of ground vias or a specific arrangement position.

[0123] According to an embodiment, at least some of the first to eleventh inductor layers (LP1 to LP11) may have a planar shape that is folded at least once in the horizontal direction. For example, as illustrated, each of the first and seventh lower inductor layers (LPL1, LPL7), the second to sixth upper inductor layers (LPU2, LPU3, LPU4, LPU5, LPU6), and the eighth to eleventh inductor layers (LP8, LP9, LP10, LP11) may have a planar shape that is folded once or twice in the horizontal direction, but the embodiment is not limited to a specific number of times the inductor layers are folded.

[0124] Meanwhile, as illustrated in FIG. 8b, the fifth capacitor layer (CP5) may include first and second through holes (TH1, TH2), and the sixth capacitor layer (CP6) may include third and fourth through holes (TH3, TH4).

[0125] The first through-hole (TH1) may be spaced apart from the first via (VA1) while the first via (VA1) passes through it, and the second through-hole (TH2) may be spaced apart from the 13th via (VA13) while the 13th via (VA13) passes through it. In order for the first and 13th vias (VA1, VA13) to be electrically spaced apart from the fifth capacitor layer (CP5), the diameter of the first through-hole (TH1) may be formed larger than the diameter of the first via (VA1), and the diameter of the second through-hole (TH2) may be formed larger than the diameter of the 13th via (VA13).

[0126] The third through hole (TH3) may be spaced apart from the fourteenth via (VA14) while the fourteenth via (VA14) passes through it, and the fourth through hole (TH4) may be spaced apart from the fifth via (VA5) while the fifth via (VA5) passes through it. In order for the fourteenth and fifth vias (VA14, VA5) to be electrically spaced apart from the sixth capacitor layer (CP6), the diameter of the third through hole (TH3) may be formed larger than the diameter of the fourteenth via (VA14), and the diameter of the fourth through hole (TH4) may be formed larger than the diameter of the fifth via (VA5).

[0127] As illustrated in FIG. 9b, the seventh and eighth capacitor pattern layers (CP7, CP8) may have a planar shape spaced apart from each other with the second via (VA2) interposed therebetween. Therefore, the seventh and eighth capacitor pattern layers (CP7, CP8) may be electrically spaced apart from the second via (VA2). In addition, the ninth and tenth capacitor pattern layers (CP9, CP10) may have a planar shape spaced apart from each other with the fourth via (VA4) interposed therebetween. Therefore, the ninth and tenth capacitor pattern layers (CP9, CP10) may be electrically spaced apart from the fourth via (VA4).

[0128] It can be seen that the aforementioned inductance pattern layer and capacitance pattern layer are vertically connected to each other by vias to implement the circuit shown in FIG. 3.

[0129] As described above, the second to fifth capacitors (C2, C3, C4, C5) illustrated in FIG. 3 can be implemented by vertically arranging the first to twelfth capacitor pattern layers (CP1 to CP12) so as to be vertically opposite each other while connecting them with vias. However, the first, sixth, seventh, eighth, and ninth capacitors (C1, C6, C7, C8, C9) illustrated in FIG. 3 can be implemented as follows with parasitic capacitance.

[0130] For convenience of explanation, only the first and second ground layers (GL1, GL2) and the first to twelfth capacitor layers (CP1 to CP12) are illustrated in FIG. 12.

[0131] The capacitance of the first capacitor (C1) illustrated in FIG. 3 is a result of synthesizing the 11th capacitance formed by opposing the first ground layer (GL1) and the first capacitor layer (CP1) spaced apart by a distance (Z11), the 12th capacitance formed by opposing the first capacitor layer (CP1) and the second ground layer (GL2) spaced apart by a distance (Z12), the 13th capacitance formed by opposing the first ground layer (GL1) and the seventh capacitor layer (CP7) spaced apart by a distance (Z13), and the 14th capacitance formed by opposing the seventh capacitor layer (CP7) and the second ground layer (GL2) spaced apart by a distance (Z14).

[0132] In addition, the capacitance of the sixth capacitor (C6) is a result of synthesizing the 61st capacitance formed by opposing the first ground layer (GL1) and the fifth capacitor layer (CP5) spaced apart by a distance (Z61), the 62nd capacitance formed by opposing the fifth capacitor layer (CP5) and the second ground layer (GL2) spaced apart by a distance (Z62), the 63rd capacitance formed by opposing the first ground layer (GL1) and the eleventh capacitor layer (CP11) spaced apart by a distance (Z63), and the 64th capacitance formed by opposing the eleventh capacitor layer (CP11) and the second ground layer (GL2) spaced apart by a distance (Z64).

[0133] In addition, the capacitance of the seventh capacitor (C7) is a result of synthesizing the 71st capacitance formed by opposing the first ground layer (GL1) and the third capacitor layer (CP3) spaced apart by a distance (Z71), the 72nd capacitance formed by opposing the first ground layer (GL1) and the 9th capacitor layer (CP9) spaced apart by a distance (Z72), the 73rd capacitance formed by opposing the third capacitor layer (CP3) and the second ground layer (GL2) spaced apart by a distance (Z73), and the 74th capacitance formed by opposing the 9th capacitor layer (CP9) and the second ground layer (GL2) spaced apart by a distance (Z74).

[0134] In addition, the capacitance of the eighth capacitor (C8) is a result of synthesizing the 81st capacitance formed by opposing the first ground layer (GL1) and the sixth capacitor layer (CP6) spaced apart by a distance (Z81), the 82nd capacitance formed by opposing the sixth capacitor layer (CP6) and the second ground layer (GL2) spaced apart by a distance (Z82), the 83rd capacitance formed by opposing the first ground layer (GL1) and the 12th capacitor layer (CP12) spaced apart by a distance (Z83), and the 84th capacitance formed by opposing the 12th capacitor layer (CP12) and the second ground layer (GL2) spaced apart by a distance (Z84).

[0135] In addition, the capacitance of the ninth capacitor (C9) is a result of synthesizing the 91st capacitance formed by opposing the first ground layer (GL1) and the fourth capacitor layer (CP4) spaced apart by a distance (Z91), the 92nd capacitance formed by opposing the fourth capacitor layer (CP4) and the second ground layer (GL2) spaced apart by a distance (Z92), the 93rd capacitance formed by opposing the first ground layer (GL1) and the tenth capacitor layer (CP11) spaced apart by a distance (Z93), and the 94th capacitance formed by opposing the tenth capacitor layer (CP10) and the second ground layer (GL2) spaced apart by a distance (Z94).

[0136] Unlike the second to fifth capacitors (C2 to C5) described above, it can be seen that the first, sixth to ninth capacitors (C1, C6 to C9) are implemented with parasitic capacitance components.

[0137] Hereinafter, the operation of a multilayer filter according to an embodiment is described with reference to the attached drawings.

[0138] Fig. 13 is a graph showing the insertion loss of a multilayer filter according to an embodiment, where the horizontal axis represents frequency and the vertical axis represents insertion loss, respectively.

[0139] Fig. 14 is a graph showing return loss according to an embodiment, where the horizontal axis represents frequency and the vertical axis represents return loss, respectively.

[0140] Figures 13 and 14 show the simulation results of applying a multilayer filter according to an embodiment to WiFi 6E having a passband of 5.925 GHz to 7.125 GHz, and it can be seen that it has characteristics of -10 dB or less.

[0141] In the embodiment, since four series resonators (L3-C2, L4-C3, L5-C4, L6-C5) and five shunt resonators (L2-C1, L8-C6, L9-C7, L10-C8, L11-C9) are adopted, as shown in Fig. 13, the frequency selectivity is very excellent as the insertion loss is in the form of a right angle (A), and as shown in the 'B' part of the return loss shown in Fig. 14, it can be seen that it has the characteristics of a fifth-order resonator with five resonators.

[0142] Hereinafter, a front-end module according to an embodiment is described with reference to the attached drawings.

[0143] Fig. 15 shows a block diagram of a front-end module (200) according to an embodiment.

[0144] The front-end module (200) according to the embodiment illustrated in FIG. 15 may include an antenna (210), first and second amplifiers (220, 240), a multilayer filter (230), and a switch (250).

[0145] The first amplifier (220) can amplify a signal received through the antenna (210) and provide the amplified result to a multilayer filter (230). For example, the first amplifier (220) can be a low noise amplifier (LNA).

[0146] The multilayer filter (230) filters the signal amplified by the first amplifier (220) and outputs it through the output terminal OUT. Since it may be the multilayer filter (100, 100A) according to the above-described embodiment, a duplicate description is omitted.

[0147] The second amplifier (240) amplifies a signal coming through the input terminal IN and transmits the amplified result through the antenna (210). For example, the second amplifier (240) may be a power amplifier (PA).

[0148] A switch (250) is placed between the input terminal of the first amplifier (220) and the output terminal of the second amplifier (240) and the antenna, and serves to select their signal paths.

[0149] According to an embodiment, when a multilayer filter (100, 100A) is embedded inside a front-end module using LCiP (Inductance & Capacitance in Package) technology and the second capacitor (C1, C6 to C9), which is a shunt capacitor, is implemented with parasitic capacitance as described above, there is no need to form a separate capacitor layer for these capacitors (C1, C6 to C9).

[0150] That is, in the case of the multilayer filter according to the embodiment, the first to twelfth capacitor layers (CP1 to CP12) are arranged to obtain the capacitance of the second to fifth capacitors (C2 to C5), and the capacitance of the first, sixth to ninth capacitors (C1, C6 to C9) can be formed using the parasitic capacitance between the first to twelfth capacitor layers (CP1 to CP12) and the first and second ground layers (GL1, GL2). Therefore, separate capacitor layers are not required to form the capacitance of the first, sixth to ninth capacitors (C1, C6 to C9). Thanks to this, the size of the multilayer filter (100, 100A) or the front-end module (200) can be reduced, and the frequency can be easily tuned.

[0151] Additionally, in the case of a multilayer filter according to one embodiment, since a plurality of capacitor layers overlapping in the vertical direction are connected by vias, a structure in which capacitors are connected in parallel can be achieved, thereby increasing the capacitance as desired.

[0152] In addition, in the case of the embodiment, in order to obtain a desired capacitance, the ground layers (GL1, GL2) and the capacitor layers (CP1 to CP12) can be overlapped in the vertical direction as much as desired, and the permittivity of the dielectric layer disposed between the ground layers (GL1, GL2) and the capacitor layers (CP1 to CP12) can be adjusted, and the area of ​​the capacitor layers forming the capacitance facing each other can be adjusted.

[0153] However, in another embodiment, if there is no need to increase the capacitance, at least one of the vias connecting the capacitor layers to each other may be optionally omitted.

[0154] In addition, the second to fifth capacitors (C2 to C5) described above are related to the skirt characteristics of the band filter and form a transmission zero, so the capacitances of these (C2 to C5) can be determined by taking this into consideration. In addition, the first, sixth to ninth capacitors (C1, C6 to C9) are related to the bandwidth of the band filter, so the capacitances of these (C1, C6 to C9) can be determined by taking this into consideration.

[0155] In addition, in the case of the embodiment, the inductance can be easily increased by vertically stacking the inductor layers to increase the length. For example, each of the first, third, and seventh inductor layers (LP1, LP3, and LP7) can be increased in length so that the inductor has a desired inductance by arranging the upper and lower inductor layers on conductive pattern layers that are vertically adjacent to each other and connecting them using vias.

[0156] The multilayer filter and front-end module according to the above-described embodiment can be applied to a field having a frequency band of 6 GHz or higher, and can be applied to, for example, a module for an antenna including a television, a mobile device, Bluetooth, or WiFi.

[0157] Although the above has been described focusing on embodiments, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiment. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

[0158] The mode for carrying out the invention has been sufficiently described in the above-mentioned “Best mode for carrying out the invention.”

[0159] The multilayer filter and the front-end module including the same according to the embodiment can be used in a field having a frequency band of 6 GHz or higher, and can be used, for example, in a module for an antenna including a television, a mobile device, Bluetooth, or WiFi.

Claims

1. First and second ground layers; A plurality of conductive pattern layers arranged and stacked vertically between the first ground layer and the second ground layer; A dielectric layer disposed between the first and second ground layers and the plurality of conductive pattern layers; and Including a via penetrating the dielectric layer and connecting each of the first and second grounds and the plurality of conductive pattern layers, Each of the plurality of challenge pattern layers includes an inductance pattern layer forming a plurality of inductors, Among the plurality of challenge pattern layers, the other part includes a capacitance pattern layer that forms a plurality of capacitors by facing each other in the vertical direction and facing each of the first and second ground layers, A multilayer filter that filters a signal having a desired frequency band by connecting a plurality of inductors and a plurality of capacitors in the vertical and horizontal directions using the above vias.

2. In paragraph 1, A multilayer filter wherein each of the first and second ground layers has a planar area larger than each of the plurality of conductive pattern layers.

3. In paragraph 1, A multilayer filter in which at least a portion of the inductance pattern layer has a shape symmetrical with respect to an imaginary horizontal line passing through the center of the long axis of the multilayer filter and parallel to the short axis direction of the multilayer filter.

4. In paragraph 1, The above capacitance pattern layer is a multilayer filter having a symmetrical shape based on an imaginary horizontal line passing through the center of the long axis of the multilayer filter and parallel to the short axis direction of the multilayer filter.

5. In the first paragraph, a multilayer filter including first to fifth conductive pattern layers sequentially laminated between the first ground layer and the second ground layer.

6. In paragraph 5, The above inductance pattern layer First and second inductor layers arranged on the first challenge pattern layer and electrically connected to each other; A third inductor layer arranged across the second conductive pattern layer and the third conductive pattern layer; Fourth and fifth inductor layers arranged across the fourth and fifth conductive pattern layers; A sixth inductor layer arranged across the second conductive pattern layer and the third conductive pattern layer while being spaced apart from the third inductor layer; A seventh inductor layer arranged across the first conductive pattern layer and the second conductive pattern layer while being spaced apart from the first and second inductor layers; An eighth inductor layer disposed on the fourth conductive pattern layer and spaced apart from the fourth and fifth inductor layers, respectively; A ninth inductor layer disposed on the first conductive pattern layer and spaced apart from the first and second inductor layers, respectively; A tenth inductor layer arranged on the fourth conductive pattern layer and spaced apart from the fourth, fifth and eighth inductor layers respectively; and A multilayer filter comprising an eleventh inductor layer disposed on the first conductive pattern layer and connected to the seventh inductor layer while being spaced apart from the first, second and ninth inductor layers, respectively.

7. A multilayer filter in accordance with claim 6, wherein at least some of the first to eleventh inductor layers have a planar shape that is folded at least once in a horizontal direction.

8. In paragraph 6, The above capacitance pattern layer First to fourth capacitor layers arranged on the second challenge pattern layer while being spatially spaced from each other; A fifth capacitor layer disposed vertically opposite to the first and second capacitor layers and on the third conductive pattern layer; A sixth capacitor layer arranged on the third conductive pattern layer and spaced apart from the fifth capacitor layer; Seventh and eighth capacitor layers spaced apart from each other in the fourth conductive pattern layer while facing the fifth capacitor layer in the vertical direction; Ninth and tenth capacitor layers spaced apart from each other in the fourth conductive pattern layer while facing the sixth capacitor layer in the vertical direction; An 11th capacitor layer disposed on the 5th conductive pattern layer while facing the 7th and 8th capacitor layers in the vertical direction; and A multilayer filter comprising the 9th and 10th capacitor layers and a 12th capacitor layer disposed on the 5th conductive pattern layer while being vertically opposed to the 11th capacitor layer and spaced apart from the 11th capacitor layer.

9. In Article 8 The above via A first contact point is formed to connect the first and second inductor layers to each other, and a first via is formed to connect the first capacitor layer and the seventh capacitor layer; A second via connecting the fifth capacitor layer and the eleventh capacitor layer and connected to the eighth inductor layer; A third contact point is formed to connect the second and third capacitor layers to each other, and a third via is connected to the ninth inductor layer; A fourth via connecting the sixth capacitor layer and the twelfth capacitor layer and connected to the tenth inductor layer; A fifth contact point is formed to connect the seventh and eleventh inductor layers to each other, and a fifth via is formed to connect the fourth capacitor layer and the tenth capacitor layer; A sixth via connecting the first inductor layer disposed on each of the first and second challenge pattern layers; A seventh via connecting the first inductor layer to the first or second ground layer; An eighth via connecting the second inductor layer to the first or second ground layer; A ninth via connecting the seventh inductor layer disposed on each of the first and second challenge pattern layers; A tenth via connecting the seventh inductor layer to the first or second ground layer; An eleventh via connecting the ninth inductor layer to the first or second ground layer; A twelfth via connecting the eleventh inductor layer to the first or second ground layer; A 13th via connecting the second capacitor layer and the eighth capacitor layer; A 14th via connecting the third capacitor layer and the ninth capacitor layer; A 15th via connecting the third inductor layer disposed on each of the second and third challenge pattern layers; A 16th via connecting the sixth inductor layer disposed on each of the second and third challenge pattern layers; A 17th via connecting the 8th inductor layer to the first or second ground layer; An 18th via connecting the 10th inductor layer to the first or second ground layer; A 19th via connecting the fourth inductor layer disposed on each of the fourth and fifth challenge pattern layers; A 20th via connecting the fifth inductor layer arranged on each of the fourth and fifth challenge pattern layers; and A multilayer filter including a ground via penetrating the first to fifth challenge pattern layers and connecting the first and second ground layers to each other.

10. Antenna; A first amplifier for amplifying a signal received through the antenna; A multilayer filter described in claim 1 that filters and outputs a signal amplified by the first amplifier; a second amplifier for amplifying a signal to be transmitted through the antenna; and A front-end module including a switch positioned between each of the input terminal of the first amplifier and the output terminal of the second amplifier and the antenna.

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