Systems and methods for supply noise immune high- speed, high resolution analog voltage generation

Abstract

A device can include a non-linear voltage regulator including a first output voltage port and configured to regulate a voltage at the first output port via a reference voltage. A linear voltage regulator can include a second output voltage port, and configured to regulate a voltage at the second output port via the reference voltage, the non-linear voltage regulator having a transient response at its first output port that is faster than that of the linear voltage regulator at its second output port. Further, a switching circuit can be configured to: for a first duration, couple the first output port of the non-linear voltage regulator with an output node, and for a second duration following a start of the first duration, couple the second output port of the linear voltage regulator with the output node.

Description

SYSTEMS AND METHODS FOR SUPPLY NOISE IMMUNE HIGHSPEED, HIGH RESOLUTION ANALOG VOLTAGE GENERATIONCROSS-REFERENCE TO RELATED APPLICATIONThis Application claims the benefit and right of priority under 35 U.S.C. § 119(e) to United States Provisional Patent Application Number 63 / 606,017, filed December 4, 2023, the contents of which are expressly incorporated by reference as if fully set forth herein.TECHNICAL FIELD

[0001] This disclosure relates to in-memory computing arrays, and in particular to supply noise immune high-speed, high-resolution analog voltage generation.DESCRIPTION OF THE RELATED TECHNOLOGY

[0002] Using in-memory computing for neural network acceleration is an emerging and innovative approach that leverages the unique properties of memory devices to enhance the speed and efficiency of neural network computations. Traditional neural network training and inference processes involve moving data back and forth between memory (RAM) and processing units (CPUs or GPUs), which can be a significant bottleneck in terms of speed and energy consumption. In-memory computing seeks to overcome these limitations by processing data directly within the memory itself.SUMMARY

[0003] In some aspects, the techniques described herein relate to a circuit, including: a non-linear voltage regulator including a first supply input port and a first output voltage port, the non-linear voltage regulator configured to regulate a voltage at the first output voltage port based on a reference voltage; a linear voltage regulator including a second supply input port and a second output voltage port, the linear voltage regulator configured to regulate a voltage at the second output voltage port based on the reference voltage, wherein the non-linear voltage regulator has a transient response to voltage changes at the first output voltage port that is faster than that of the linear voltage regulator at the second output voltage port; and a switching circuit configured to: for a first duration, couple the first output voltage port of the non-linear voltage regulator with an output node, and for a second duration following a start of the first duration, couple the second output voltage port of the linear voltage regulator with the output node.

[0004] In some aspects, the techniques described herein relate to a circuit, wherein the first duration and the second duration overlap and the second duration is longer than the first duration.

[0005] In some aspects, the techniques described herein relate to a circuit, wherein the first duration corresponds to a duration within which the non-linear voltage regulator regulates the voltage at the first output voltage port to within a threshold value of the reference voltage.

[0006] In some aspects, the techniques described herein relate to a circuit, wherein the first duration corresponds to a first half period of a clock signal and the second duration corresponds to a second half period of the clock signal.

[0007] In some aspects, the techniques described herein relate to a circuit, wherein a first supply input port of the non-linear voltage regulator receives a voltage that is less than a voltage received at a second supply input port of the linear voltage regulator.

[0008] In some aspects, the techniques described herein relate to a circuit, wherein the accuracy of the linear voltage regulator is greater than the accuracy of the non-linear voltage regulator.

[0009] In some aspects, the techniques described herein relate to a circuit, wherein the non-linear voltage regulator includes a non-linear error amplifier.

[0010] In some aspects, the techniques described herein relate to a circuit, wherein the non-linear voltage regulator includes a first comparator and a pull-up transistor, wherein the negative terminal of the comparator receives the reference voltage and the positive terminal of the comparator is coupled with the first output voltage port, and wherein the pull-up transistor is positioned between the first supply input port and the first output voltage port, and an output terminal of the first comparator is coupled to the gate of the pull-up transistor.

[0011] In some aspects, the techniques described herein relate to a circuit, wherein the non-linear voltage regulator includes a second comparator and a pull-down transistor, wherein the negative terminal of the second comparator receives the reference voltage and the positive terminal of the second comparator is coupled with the first output voltage port, and wherein the pull-down transistor is positioned between the first output voltage port and a low voltage or ground terminal, and an output terminal of the second comparator is coupled to the gate of the pull-down transistor.

[0012] In some aspects, the techniques described herein relate to a circuit, wherein the linear voltage regulator includes a low drop-out voltage regulator.

[0013] In some aspects, the techniques described herein relate to a circuit, wherein the voltage applied to the first supply input port has higher noise than the voltage applied to the second supply input port.

[0014] In some aspects, the techniques described herein relate to a circuit, further including: a first voltage selection circuit configured to select a voltage source applied to the first supply input port, from a plurality of voltage sources, each of the plurality of voltage sources having a different voltage.

[0015] In some aspects, the techniques described herein relate to a circuit, wherein the first voltage selection circuit configured to select the voltage source applied to the first supply input port, based on the reference voltage.

[0016] In some aspects, the techniques described herein relate to a circuit, further including: a second voltage selection circuit configured to select a voltage source applied to the second supply input port, from a plurality of voltage sources, at least two voltages sources of the plurality of voltage sources having different noise levels.

[0017] In some aspects, the techniques described herein relate to a circuit, further including: a second voltage selection circuit configured to select a voltage source applied to the second supply input port, from a plurality of voltage sources, each of the plurality of voltage sources having a different voltage.

[0018] In some aspects, the techniques described herein relate to a circuit, wherein the second voltage selection circuit configured to select the voltage source applied to the second supply input port, based on the reference voltage.

[0019] In some aspects, the techniques described herein relate to a method for providing analog voltages, including: for a first duration, coupling a first output voltage port of a non-linear voltage regulator with an output node, the non-linear voltage regulator including a first supply input port and a first output voltage port, the non-linear voltage regulator configured to regulate a voltage at the first output voltage port; and for a second duration following a start of the first duration, coupling a second output voltage port of a linear voltage regulator with the output node, the linear voltage regulator configured to regulate a voltage at the second output voltage port based on a reference voltage, wherein the non-linear voltage regulator has a transient response to voltage changes at the first output voltage port that is faster than that of the linear voltage regulator at the second output voltage port.

[0020] In some aspects, the techniques described herein relate to a method, wherein the first duration and the second duration overlap and the second duration is longer than thefirst duration.

[0021] In some aspects, the techniques described herein relate to a method, wherein the first duration corresponds to a duration within which the non-linear voltage regulator regulates the voltage at the first output voltage port to within a threshold value of the reference voltage.

[0022] In some aspects, the techniques described herein relate to a method, wherein the first duration corresponds to a first half period of a clock signal and the second duration corresponds to a second half period of the clock signal.

[0023] In some aspects, the techniques described herein relate to a method, wherein a first supply input port of the non-linear voltage regulator receives a voltage that is less than a voltage received at a second supply input port of the linear voltage regulator.

[0024] In some aspects, the techniques described herein relate to a method, wherein the accuracy of the linear voltage regulator is greater than the accuracy of the non-linear voltage regulator.

[0025] In some aspects, the techniques described herein relate to a method, wherein the non-linear voltage regulator includes a non-linear error amplifier.

[0026] In some aspects, the techniques described herein relate to a method, wherein the non-linear voltage regulator includes a first comparator and a pull-up transistor, wherein the negative terminal of the first comparator receives the reference voltage and the positive terminal of the first comparator is coupled with the first output voltage port, and wherein the pull-up transistor is positioned between the first supply input port and the first output voltage port, and an output terminal of the first comparator is coupled to the gate of the pull-up transistor.

[0027] In some aspects, the techniques described herein relate to a method, wherein the non-linear voltage regulator includes a second comparator and a pull-down transistor, wherein the negative terminal of the second comparator receives the reference voltage and the positive terminal of the second comparator is coupled with the first output voltage port, and wherein the pull-down transistor is positioned between the first output voltage port and a low voltage or ground terminal, and an output terminal of the second comparator is coupled to the gate of the pull-down transistor.

[0028] In some aspects, the techniques described herein relate to a method, wherein the linear voltage regulator includes a low drop-out voltage regulator.

[0029] In some aspects, the techniques described herein relate to a method, wherein a voltage applied to a first supply input port of the non-linear voltage regulator has highernoise than a voltage applied to a second supply input port of the linear voltage regulator.

[0030] In some aspects, the techniques described herein relate to a method, wherein a voltage applied to a second supply input port of the linear voltage regulator during the first duration has a higher noise level than the voltage applied to a second supply input port of the linear voltage regulator during the second duration.

[0031] In some aspects, the techniques described herein relate to a method, further including: selecting a voltage applied to a first supply input port of the non-linear voltage regulator from a plurality of voltage sources, each of the plurality of voltage sources having a different voltage.

[0032] In some aspects, the techniques described herein relate to a method, further including: selecting the voltage applied to the first supply input port of the non-linear voltage regulator from the plurality of voltage sources based on the reference voltage.

[0033] In some aspects, the techniques described herein relate to a method, further including: selecting a voltage applied to a second supply input port of the linear voltage regulator from a plurality of voltage sources, each of the plurality of voltage sources having a different voltage.

[0034] In some aspects, the techniques described herein relate to a method, further including: selecting the voltage applied to the second supply input port from the plurality of voltage sources based on the reference voltage.BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG. 1 depicts a block diagram of an example in-memory computing architecture.

[0036] FIG. 2 shows a block diagram of a compute in-memory array.

[0037] FIG. 3 shows an example circuit diagram of the computing cells discussed above in relation to FIG. 2.

[0038] FIG. 4 shows a first example analog voltage delivery circuit for delivering analog voltages to the CIM array.

[0039] FIG. 5 shows an example analog voltage driver circuit.

[0040] FIG. 6 shows a first example non-linear error amplifier.

[0041] FIG. 7 shows a second example non-linear error amplifier.

[0042] FIG. 8 shows a first example linear amplifier.

[0043] FIG. 9 shows a second example analog voltage delivery circuit.

[0044] FIG. 10 shows a first example source voltage selection circuit.

[0045] FIG. 11 shows a second example source voltage selection circuit.

[0046] Like reference numbers and designations in the various drawings indicate likeelements.DETAILED DESCRIPTION

[0047] The various concepts introduced above and discussed in greater detail below can be implemented in any of numerous ways, as the described concepts are not limited to any particular manner of implementation. Examples of specific implementations and applications are provided primarily for illustrative purposes.

[0048] As will be apparent to those of skill in the art upon reading this disclosure, each of the individual aspects described and illustrated herein has discrete components and features which can be readily separated from or combined with the features of any of the other several aspects without departing from the scope or spirit of the present disclosure.

[0049] Any recited method can be carried out in the order of events recited or in any other order that is logically possible. That is, unless otherwise expressly stated, it is in no way intended that any method or aspect set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not specifically state in the claims or descriptions that the steps are to be limited to a specific order, it is no way intended that an order be inferred, in any respect. This holds for any possible nonexpress basis for interpretation, including matters of logic with respect to arrangement of steps or operational flow, plain meaning derived from grammatical organization or punctuation, or the number or type of aspects described in the specification.

[0050] All publications mentioned herein are incorporated herein by reference to disclose and describe the methods and / or materials in connection with which the publications are cited. All such publications and patents are herein incorporated by references as if each individual publication or patent were specifically and individually indicated to be incorporated by reference. Such incorporation by reference is expressly limited to the methods and / or materials described in the cited publications and patents and does not extend to any lexicographical definitions from the cited publications and patents. Any lexicographical definition in the publications and patents cited that is not also expressly repeated in the instant specification should not be treated as such and should not be read as defining any terms appearing in the accompanying claims. The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. Nothing herein is to be construed as an admission that the present invention is not entitled to antedate such publication by virtue of prior invention. Further, the dates of publication provided herein can be different from the actual publication dates, which can require independent confirmation.

[0051] While aspects of the present disclosure can be described and claimed in a particular statutory class, such as the system statutory class, this is for convenience only and one of skill in the art will understand that each aspect of the present disclosure can be described and claimed in any statutory class.

[0052] It is also to be understood that the terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosed compositions and methods belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0053] It should be noted that ratios, concentrations, amounts, and other numerical data can be expressed herein in a range format. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint. It is also understood that there are a number of values disclosed herein, and that each value is also herein disclosed as “about” that particular value in addition to the value itself. For example, if the value “10” is disclosed, then “about 10” is also disclosed. Ranges can be expressed herein as from “about” one particular value, and / or to “about” another particular value. Similarly, when values are expressed as approximations, by use of the antecedent “about,” it will be understood that the particular value forms a further aspect. For example, if the value “about 10” is disclosed, then “10” is also disclosed.

[0054] When a range is expressed, a further aspect includes from the one particular value and / or to the other particular value. For example, where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the disclosure, e.g. the phrase “x to y” includes the range from ‘x’ to ‘y’ as well as the range greater than ‘x’ and less than ‘y’. The range can also be expressed as an upper limit, e.g. ‘about x, y, z, or less’ and should be interpreted to include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ as well as the ranges of Tess than x’, less than y’, and Tess than z’. Likewise, the phrase ‘about x, y, z, or greater’ should be interpreted to include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ as well as the ranges of ‘greater than x’, greater than y’, and ‘greater than z’. In addition, the phrase“about ‘x’ to ‘y’”, where ‘x’ and ‘y’ are numerical values, includes “about ‘x’ to about y”.

[0055] It is to be understood that such a range format is used for convenience and brevity, and thus, should be interpreted in a flexible manner to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited. To illustrate, a numerical range of “about 0.1% to 5%” should be interpreted to include not only the explicitly recited values of about 0.1% to about 5%, but also include individual values (e.g., about 1%, about 2%, about 3%, and about 4%) and the sub-ranges (e.g., about 0.5% to about 1.1%; about 5% to about 2.4%; about 0.5% to about 3.2%, and about 0.5% to about 4.4%, and other possible sub-ranges) within the indicated range.

[0056] As used herein, the terms “about,” “approximate,” “at or about,” and “substantially” mean that the amount or value in question can be the exact value or a value that provides equivalent results or effects as recited in the claims or taught herein. That is, it is understood that amounts, sizes, formulations, parameters, and other quantities and characteristics are not and need not be exact, but can be approximate and / or larger or smaller, as desired, reflecting tolerances, conversion factors, rounding off, measurement error and the like, and other factors known to those of skill in the art such that equivalent results or effects are obtained. In some circumstances, the value that provides equivalent results or effects cannot be reasonably determined. In such cases, it is generally understood, as used herein, that “about” and “at or about” mean the nominal value indicated ±10% variation unless otherwise indicated or inferred. In general, an amount, size, formulation, parameter or other quantity or characteristic is “about,” “approximate,” or “at or about” whether or not expressly stated to be such. It is understood that where “about,” “approximate,” or “at or about” is used before a quantitative value, the parameter also includes the specific quantitative value itself, unless specifically stated otherwise.

[0057] Prior to describing the various aspects of the present disclosure, the following definitions are provided and should be used unless otherwise indicated. Additional terms can be defined elsewhere in the present disclosure.

[0058] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0059] As used in the specification and the appended claims, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a proton beam degrader,” “a degrader foil,” or “a conduit,” includes, but is not limited to, two or more such proton beam degraders, degrader foils, or conduits, and the like.

[0060] The terms “configured for” or “configured to,” as used herein with respect to a specified operation or function, refer to a device, component, circuit, structure, machine, signal, etc. that is physically constructed, programmed, formatted and / or arranged to perform the specified operation or function.

[0061] The various concepts introduced above and discussed in greater detail below can be implemented in any of numerous ways, as the described concepts are not limited to any particular manner of implementation. Examples of specific implementations and applications are provided primarily for illustrative purposes.

[0062] As used herein, the terms “optional” or “optionally” means that the subsequently described event or circumstance can or cannot occur, and that the description includes instances where said event or circumstance occurs and instances where it does not.

[0063] Unless otherwise specified, temperatures referred to herein are based on atmospheric pressure (i.e. one atmosphere).

[0064] In-memory Computing Architecture

[0065] FIG. 1 depicts a block diagram of an example in-memory computing architecture 100. The in-memory computing architecture 100 can be adapted, for example, to a scalable neural network accelerator architecture based on in-memory computing (IMC). However, the in-memory computing architecture 100 is not limited to neural network applications, and can be employed in numerous applications where high data throughput with low power consumption is desired. The in-memory computing architecture 100 includes a plurality of Compute In-Memory unit (CIMU) tiles 102. The plurality of CIMU tiles 102 are arranged in an array within the architecture. The plurality of CIMU tiles 102 can be individually enabled / disabled based on the computations to be carried out by the in-memory computing architecture 100. In examples where the in-memory computing architecture 100 can be used to implement neural networks, the neural networks can be mapped to one or more CIMU tiles of the plurality of CIMU tiles 102. The remainder of the CIMU tiles of the plurality of CIMU tiles 102 can be disabled to reduce power consumption.

[0066] The in-memory computing architecture 100 can include, in part, activation buffers104, segmented weight buffers 106, and one or more phase-locked loops (PLLs) 108. The activation buffers 104 can provide signals representative of activations from previous stages of computation, for instance previous layers in a neural network. The segmented weight buffers 106 can provide data required for computation together with the activations / data from previous stages, for instance these weight buffers could store the weights of neural network layers. The one or more PLLs 108 can provide reference clock signals to various portions of the in-memory computing architecture 100. The in-memory computing architecture 100 can also include off-chip interfaces 110 (referenced in FIG. 1 as “off-chip control” element 110) for communication with off-chip processors or software to send and receive control or data signals. The off-chip interface 110 can, by itself or in concert with other elements, provide circuits and protocols for high-speed interfaces for wired or wireless connections involving data, control signals, or both, to other processors or other arrays of CIMU tiles, for example, enabling the in-memory computing architecture 100 to scale upward as desired.

[0067] Each of the plurality of CIMU tiles 102 can include a plurality of CIMUs 112, an on-chip network 114, and a weight network 116. While FIG. 1 shows each of the plurality of CIMU tiles 102 including four CIMUs 112, this is only an example, and the CIMU tiles 102 can include fewer or more CIMUs 112. One or more of the CIMUs 112 can include a compute in-memory (CIM) array 118, compute dataflow buffers 120, programmable digital single instruction multiple data (SIMD) module 122, and a programming and control module 124. The CIM array 118 can be an array of computing cells, discussed further below. The CIM array 118 can carry out computations based on data stored in the computing cells and data provided by the activation buffers 104. The computing cells can be used to perform computational operations between inputs and data stored in a memory cell within the computing cells. The operations can include logical operations (AND, NOR, etc.) or multiplication operations carried out between inputs. The CIM array 118 can carry out matrix operations between multi -bit operands, which is particularly useful in neural network computations where activations are multiplied with weights. In some such applications, the weights can be stored in the memory cells of the CIM array 118 and activations can be provided as input vectors. Each computing cell in the CIM array 118 can perform the multiplication operation between a 1 -bit weight and a portion of the input activation, which can be represented in digital or analog signal form. Some example computing cells can generate a result that is in the form of an electrical signal. For example, the computing cell can output an analog voltage that isrepresentative of the computation result. In some other examples, the computing cell can output an electrical current that is representative of the computation result. The electrical signals of various computing cells can be accumulated and processed to generate the overall matrix multiplication result. For example, electrical signals representative of computation from all computing cells in a single column of the CIM array 118 can be accumulated to represent a portion of the computation. Accumulated electrical signals from multiple columns of computing cells of the CIM array 118 can be combined and processed to generate an overall matrix multiplication result. For instances where the electrical signal generated by the computing cells is an electrical current, the currents from various computing cells within a column can be summed to generate a representative accumulated electrical current. In instances where the electrical signal generated by the computing cell is an analog voltage, the analog voltage generated by each computing cell can be stored in capacitors within the computing cell and then accumulated as a voltage that is representative of a portion of the overall matrix multiplication result. The accumulated result, whether an electrical current or an analog voltage, can be converted into digital form using analog to digital converters (ADCs) and further processed, stored, or passed on to other CIM arrays 118 for further computations.

[0068] The programmable digital SIMD 122 can have an instruction set for flexible element-wise operation and the compute dataflow buffers 120 can support wide range of neural network dataflows. Each of the CIMUs 112 can provide a high-level of configurability and can be abstracted into a software library of instructions for interfacing with a compiler (for allocating / mapping an application, neural network and the like to the architecture), and where instructions can thus also be added prospectively. That is, the library can include single / fused instructions such as element mult / add, h(») activation, (N- step convolutional stride + matrix-vector-multiplication (MVM) + batch norm. +h(») activation + max. pool), (dense + MVM) and the like. In various nonlimiting examples, h(») can indicate an activation function, including without limitation the rectified linear unit ReLU(x) function, the sigmoid function (o(x)), and other such functions. Max pooling, a downsampling technique for reducing spatial dimensions to maintain computational efficiency while retaining other important features of the CIMU array or the network, can also be a subject of the computation. The N-step convolutional stride can refer to the number of pixels or other information bits that a kernel or convolutional filter moves or glides across the input image during convolution to effect operations like feature detection, pattern recognition, blurring, image sharpening, image recognition, andthe like.

[0069] The on-chip network 114 (OCN) can include routing channels within Network In / Out Blocks, and a Switch Block, which provides flexibility via a disjoint architecture as shown, for example, by the disjoint buffer switch 133 in the enlarged view of OCN 114. This flexibility, among other benefits, enables modules that are independent of one another to work in parallel. The OCN 114 works with configurable CIMU input / output ports to optimize data structuring to / from an in-memory computing engine, to maximize data locality across MVM dimensionalities and tensor depth / pixel indices. The OCN 114 routing channels can include bidirectional wire pairs as shown by the duo-directional pipelined routing structure 131 in the expanded view if the OCN 114, so as to ease repeater / pipeline-FF insertion, while providing sufficient density.

[0070] The in-memory computing architecture 100 can be used to implement a neural network (NN) accelerator, wherein a plurality of compute in memory units (CIMUs 112) are arrayed and interconnected using a very flexible on-chip network (OCN 114) wherein the outputs of one CIMU can be connected to or flow to the inputs of another CIMU or to multiple other CIMUs, the outputs of many CIMUs can be connected to the inputs of one CIMU, the outputs of one CIMU can be connected to the inputs of another CIMU and so on. The OCN 114 can be implemented as a single on-chip network, as a plurality of on-chip network portions, or as a combination of on-chip and off-chip network portions.

[0071] The CIMUs 112 can be surrounded by an on-chip network for moving activations between CIMUs 112 (activation network) as well as moving weights from embedded L2 memory to CIMUs 112 (weight-loading interface). This has similarities with architectures used for coarse-grained reconfigurable arrays (CGRAs), but with cores providing high- efficiency MVM and element-wise computations targeted for neural network acceleration. Various options exist for implementing the on-chip network. The approach in FIG. 1 enables routing segments along a CIMU 112 to take outputs from that CIMU 112 and / or to provide inputs to that CIMU 112. In this manner data originating from any CIMU 112 can be routed to any CIMU 112, and any number of CIMUs 112.

[0072] Each CIMU 112 is associated with an input buffer (not shown) for receiving computational data from the on-chip network and composing the received computational data into an input vector for matrix vector multiplication (MVM) processing by the CIMU to generate thereby computed data including an output vector.

[0073] Each CIMU 112 is associated with a shortcut buffer (not shown), for receivingcomputational data from the on-chip network 114, imparting a temporal delay to the received computational data, and forwarding delayed computation data toward a next CIMU 112 or an output in accordance with a dataflow map such that dataflow alignment across multiple CIMUs 112 is maintained. At least some of the input buffers can be configured to impart a temporal delay to computational data received from the on-chip network 114 or from a shortcut buffer. The dataflow map can support pixel-level pipelining to provide pipeline latency matching.

[0074] The temporal delay imparted by a shortcut or input buffers includes at least one of an absolute temporal delay, a predetermined temporal delay, a temporal delay determined with respect to a size of input computational data, a temporal delay determined with respect to an expected computational time of the CIMU 112, a control signal received from a dataflow controller, a control signal received from another CIMU 112, and a control signal generated by the CIMU 112 in response to the occurrence of an event within the CIMU. In some aspects, at least one of the input buffer and shortcut buffers of each of the plurality of CIMUs 112 in the array of CIMUs 112 can be configured in accordance with a dataflow map supporting pixel-level pipelining to provide pipeline latency matching. The array of CIMUs 112 can also include parallelized computation hardware configured for processing input data received from at least one of respective input and shortcut buffers.

[0075] At least a subset of the CIMUs 112 can be associated with on-chip network 114 portions including operand loading network portions configured in accordance with a dataflow of an application mapped onto the IMC. The application mapped onto the IMC includes a neural network (NN) mapped onto the IMC such that parallel output computed data of configured CIMUs executing at a given layer are provided to configured CIMUs 112 executing at a next layer, said parallel output computed data forming respective NN feature-map pixels.

[0076] The input buffer can be configured for transferring input NN feature-map data to parallelized computation hardware within the CIMU in accordance with a selected stride step, such as discussed above. The NN can include a convolution neural network (CNN), and the input buffer can be used to buffer a number of rows of an input feature map corresponding to a size or height of the CNN kernel.

[0077] The CIM array 118 in each CIMU 112 can perform matrix vector multiplication (MVM) in accordance with a bit-parallel, bit-serial (BP / BS) computing process in which single bit computations are performed using an iterative barrel shifting with columnweighting process, followed by a results accumulation process.

[0078] FIG. 2 shows additional details of a portion of the in-memory computing architecture 100 shown in FIG. 1, and in particular, details of an example compute inmemory (CIM) array 200 and associated components. The CIM array 200 can be used, for example, to implement, in part, the CIM array 118 discussed above in relation to the in-memory computing architecture 100 shown in FIG. 1. In one example implementation, the CIM array 200 can include a fully row / column-parallel (1152 row X 256 column) array of computing cells 202 of an in-memory-computing (IMC) macro enabling N-bit (5-bit) input processing. The number of rows (1152), the number or columns (256), and the number of bits (5-bit) of input shown in FIG. 2 are only examples, and any or all of these quantities and circuit configurations can be varied based on desired implementations. The computing cells can be used to perform computational operations between inputs and data stored in a memory cell within the computing cells. The operations can include logical operations (AND, NOR, etc.) or multiplication operations carried out between inputs. In some examples, the operands of the computation can be 1 -bit each. In some other examples, one of the operands can be an analog signal (voltage or current) while the other operand can be a 1 -bit operand stored in the memory cell.

[0079] The in-memory computing architecture 100, in some examples, can be utilized for matrix vector multiplication (MVM) operations, which dominate compute-intensive and data-intensive Al workloads, in a manner that reduces compute energy and data movement by orders of magnitude. This is achieved through efficient analog compute in the computing cells 202, and by thus accessing a compute result (e.g., inner product), rather than individual bits, from memory. But, doing so fundamentally instates an energy / throughput-vs.-SNR tradeoff, where going to analog introduces compute noise and accessing a compute result increases dynamic range (i.e., reducing SNR for given readout architecture). The computing cells 202, which store computational results in the form of a voltage in capacitors within the computing cells 202, can employ metal-fringing capacitors, which can achieve very low noise from analog nonidealities, and thus have the potential for extremely high dynamic range.

[0080] FIG. 2 shows a block diagram of the CIM array 200 including a 1152 (row) X 256 (col.) array of 10T (“ten transistor”) SRAM computing cells 202, which in this example are multiplying bit-cells (M-BCs) (such as, for example, a 10T M-BC 202, although the number of transistors of SRAM interface 204 and M-BCs 202 is purely implementationdependent and the circuit can use different numbers of transistors or other circuit elementswithout departing from the principles of the disclosure); peripheral circuits for standard writing / reading thereto (e.g., a bit line (BL) decoder 204 and 256 BL drivers 206-1 through 206-256 (collectively referred to as BL drivers 206), a word line (WL) or address decoder 208 and 1152 WL drivers 210-1 through 210-1152 (collectively referred to as WL drivers 210), and control block 212 for controlling the BL decoder 204 and the WL decoder 208); peripheral circuitry for providing 5-bit input-vector elements thereto (e.g., 1152 Dynamic-Range Doubling (DRD) DACs 214-1 through 214-1152 (collectively referred to as DRD DACs 214), and a corresponding in-memory computing (IMC) controller (“IMC control block”) 216); peripheral circuitry for digitizing the compute result from each column (e.g., 256 8-bit successive approximation register (SAR) ADCs 218-1 through 218-256 (collectively referred to as SAR ADCs 218), and column reset mechanisms 220-1 through 220-256 (collectively referred to as column reset mechanisms 220) (e.g., CMOS switches configured to pull the output voltage levels of column compute lines CLs to a reset voltage VRST during a reset phase of operation, and allow the voltage levels of column compute lines CLs to reflect their respective compute results during an evaluation phase of operation). For example, the RST switches corresponding to CL1-CL256, or a subset thereof, can close to produce the desired reset voltage VRST during the reset phase. The RST switches can then open during an ensuing evaluation phase, thereby enabling the voltage values at the CLs to reflect the computed product.

[0081] In addition, the lower right portion of the figure depicts an example enlarged view of a representative one of the 256 8-bit ADCs, which includes various switch mechanisms ADCRST (Analog-to-Digital Converter Reset), ADCSMP (Analog-to-Digital Converter Sample) and voltage designations VADCRST and VCMPR, the latter voltage designation connected in this example to a positive terminal of the comparator CMPR and the former voltage designation selectively applied via the ADCRST and ADCSMP switch to reset the comparator. The negative terminal of comparator CMPR receives a CL value when the circuit is activated. An output of comparator CMPR is coupled to SAR logic for outputting an 8-bit digital result. It will be appreciated, however, that the implementation details of the above circuits are representative in nature and that variations to the circuits are possible without departing from the scope or spirit of the present disclosure.

[0082] While writing / reading is typically performed row-by-row, MVM operations are typically performed by applying input-vector elements corresponding to neural -network input activations to all rows at once. That is, each DRD DAC 214j, in response to a respective 5-bit input-vector element Xj[4:0], generates a respective differential outputsignal (lAj / IAbj) which is subjected to a 1-bit multiplication with the stored weights (Aij / Abij) at each computing cells 202j in the corresponding row of computing cells 202, and accumulation through charge-redistribution across computing cells 202 capacitors CM-BC on the compute line (CL) to yield an inner product in each column, which is then digitized via the respective SAR ADCs 218 of each column.

[0083] FIG. 3 shows an example circuit diagram of the computing cells 202 discussed above in relation to FIG. 2. The computing cells 202 can include a highly dense structure for achieving weight storage and multiplication, thereby minimizing data-broad-cast distance and control signals within the context of i-row, j -column arrays implemented using such computing cells, such as the 1152 (row) X 256 (col.) CIM array 200 of 10T SRAM multiplying bit cells (M-BCs).

[0084] The exemplary computing cells 202 includes a six-transistor bit cell portion 222 (here, NMOS transistors 226a, 226b, 226e, 226f and PMOS transistors 226c and 226d), a first switch SW1, a second switch SW2, a capacitor C, a word line (WL) 224, a first bit line (BLj) 227, a second bit line (BLbj) 228, and a compute line (CL) 230.

[0085] The six-transistor bit cell portion 222 is depicted as being located in a middle portion of the computing cells 202, and includes six transistors 226a-226f. The 6- transistor bit cell portion 222 can be used for storage, and to read and write data. In one example, the 6-transistor bit cell portion 222 stores the filter weight. In some examples, data is written to the computing cells 202 through the word line (WL) 224, the first bit line (BL) 227, and the second bit line (BLb) 228.

[0086] The computing cells 202 can include a first CMOS switch SW1 and a second CMOS switch SW2. The first switch SW 1 is depicted as being controlled by a first stored signal Aij such that, when closed, the first switch SW1 couples one of the received differential output signals (lA / IAb) provided by the DRD DACs 214, illustratively IA, to a first terminal of the capacitor C. The second switch SW2 is depicted as being controlled by a second stored signal Abij such that, when closed, the second switch SW2 couples the other one of the received differential output signals of the corresponding DRD DACs 214, illustratively lAb, to the first terminal of the capacitor C. The second terminal of the capacitor C is connected to a compute line (CL) 230 via an output port 232 that provides a result of the computation of the computation cell 202. It is noted that in various other examples, the input signals provided to the first and second switches SW 1 and SW2 can include a fixed voltage (e.g., Vaa), ground, or some other voltage level.

[0087] The computing cells 202, including the first SW1 and second SW2 switches, canimplement computation on the data stored in the six-transistor bit cell portion 222. The result of a computation is sampled as charge on the capacitor C. According to various implementations, the capacitor C can be is positioned above the computing cell 202 and utilize no additional area on the circuit. In some implementations, a logic value of either Vdd or ground is stored on the capacitor C. In other implementations, the voltage stored on the capacitor C can include a positive or negative voltage in accordance with the operation of the first and the second switches SW 1 and SW2, and the output voltage level generated by the corresponding DRD DACs 214 shown in FIG. 2.

[0088] Thus, with continued reference to FIG. 3, the value that is stored on the capacitor C is highly stable, since the capacitor C value is either driven up to a fixed analog voltage or down to ground. In some examples, the capacitor C is a metal-oxide-metal (MOM) finger capacitor, and in some examples, the capacitor C can be about 0.1 femto-Farhads (fF) to about 10 fF or can be about 1.2 fF. MOM capacitors have very good matching temperature and process characteristics, and thus have highly linear and stable compute operations. Note that other types of logic functions can be implemented using the computing cells 202 by changing the way the transistors 226a-226f and / or the first and the second switches SW 1 and SW2 are connected and / or operated during the reset and evaluation phases of operation. The six-transistor bit cell portion 222 can be implemented using different numbers of transistors and can have different architectures. In some examples, the six-transistor bit cell portion 222 can be a SRAM, DRAM, MRAM, or an RRAM.

[0089] Analog Voltage Delivery Circuits

[0090] FIG. 4 shows a first example analog voltage delivery circuit 400 for delivering analog voltages to the CIM array 402. The CIM array 402 can be similar to the CIM array 118 or the CIM array 200 discussed above in relation to FIG. 1 and FIG. 2. The first example analog voltage delivery circuit 400 can be utilized to generate a set of analog voltages (VAi-VAm) that can be utilized for the differential output signal (lAj / IAbj) provided to each row of the CIM array (see e.g., DRD DACs 214 that provide the differential output signal (lAj / IAbj) to the rows of the CIM array 200). The first example analog voltage delivery circuit 400 can include a set of m DACs: DAC-1 404-1 to DAC- m 404-m (collectively referred to as “the set of DACs 404”). The set of DACs 404 can receive digital inputs VCNTRL-I[K:0] to VcNTRL-m[K:0], which can be converted into corresponding analog reference voltages VREF-I to VREF-HI. The digital inputs VCNTRL- i[K:0] to VcNTRL-m[K:0] can be digital representations of the analog voltages that are tobe used to carry out computations in the computing cells 202. The first example analog voltage delivery circuit 400 can include a set of m drivers: Driver- 1 406-1 to Driver-m 406-m (collectively referred to as “the set of drivers 406”). Each driver of the set of drivers 406 receives a reference voltage VREF and generates a corresponding analog voltage VA that accurately reflects the reference voltage VREF. A supply voltage VDC 408 can provide power to the set of drivers 406. As an example, the supply voltage VDC can be generated on-chip or received from off the chip. On-chip supply voltage generation circuits can include, for example, buck regulators.

[0091] While not shown in FIG. 4, a selection circuit can select one of the set of analog voltages generated by the first example analog voltage delivery circuit 400 as one of the differential output signals. While the value of the differential output signals can vary from row to row, it is likely that one of the set of analog voltages is provided as one of the differential output signals of multiple rows. For example, referring to FIG. 2, a same value of voltage can be selected for at least one of the differential outputs (lAj / IAbj) of several of the 1152 rows. Thus, for example, VAi can be connected to differential outputs of several of the 1152 rows. The large number of rows of differential outputs connected to the analog voltage VAi can cause loading on the output of the driver 406-1. The loading, in turn, can affect the ability of the driver to keep the analog voltage VAi substantially constant. For example, the selection circuit can include one or more switches that when switched ON, can connect several rows of differential outputs to each of the analog voltage outputs of the drivers. This causes a sudden increase in load at the output of the drivers. This increase in load can cause a decrease in the voltage at the output of the driver. The driver can regulate its output by pulling the output voltage back up to the desired voltage VA. However, it is preferable that the driver regulate the output voltage with accuracy (i.e., as close to corresponding VREF) and as quickly as possible. As discussed herein, the drivers are designed to provide both accuracy and quick regulation in response to changes in loads at their respective outputs.

[0092] FIG. 5 shows an example driver circuit 500. The driver circuit 500 can be used to implement one or more of the set of drivers 406 discussed in relation to the first example analog voltage delivery circuit 400 shown in FIG. 4. The example driver circuit 500 can include a non-linear voltage regulator 502 and a linear voltage regulator 504. The non-linear voltage regulator 502 can include a first supply input port 506 and a first output voltage port 508. The linear voltage regulator 504 can include a second supply input port 510 and a second output voltage port 512. Both the non-linear voltage regulator 502 andthe linear voltage regulator 504 can receive a reference voltage VREF, which the driver circuit 500 can use to generate its output voltage VA at the respective output voltage port. The driver circuit 500 can include a first switch 514 positioned between the first output voltage port 508 of the non-linear voltage regulator 502 and the output node 518, and a second switch 516 positioned between the second output voltage port 512 of the linear voltage regulator 504 and the output node 518.

[0093] A controller 520 can control the states of the first switch 514 and the second switch 516. The controller 520, the first switch 514, and the second switch 516 can be collectively referred to as “a switching circuit.” The controller 520 can be a microcontroller, microprocessor, state machine, or other processing circuitry that can provide control signals for the first switch 514 and the second switch 516. In some instances, the controller 520 can be a clock signal source, where the clock signal can be provided to one switch and an inverted clock signal is provided to the other switch. As an example, the first duration can correspond to the first half of the period of the clock signal and the second duration can correspond to the second half of the period of the clock signal. In some examples, the controller 520 can include a 2 phase clock generator, which generates a first clock signal which is provided to one switch and another clock signal provided to the other switch, such that the first clock signal switches ON the first switch 514 for a first duration and after the start of the first duration, the second clock signal switches ON the second switch 516 for a second duration. In some examples, the first duration and the second duration can begin at the same time and overlap with the second duration being longer that the first duration. In some other examples, the first duration and the second duration may not overlap.

[0094] As mentioned above in relation to the first example analog voltage delivery circuit 400, the set of drivers 406 can experience large electrical load when connected to the CIM array 402. Generally, it is desirable that the drivers output a constant voltage at their respective output terminals. But the application and removal of the large load can cause undesirable voltage changes at the outputs of the drivers. The driver circuit 500 can quickly and accurately bring the voltage at the output node 518 to its desired value.

[0095] The driver circuit 500 can provide power to the output node 518 through one or both of the non-linear voltage regulator 502 and the linear voltage regulator 504. The non-linear voltage regulator 502 receives supply from the first supply input port 506, which, in some examples, can be noisy compared to the second supply input port 510. However, the non-linear voltage regulator 502 can have a transient response to voltagechanges at the first output voltage port 508 (effectively the output node 518 when the first switch 514 is switched ON), that is faster than that of the linear voltage regulator 504. Example settling time of the non-linear voltage regulator 502 can be between about 0.1 ns and about 1 ns while the settling time of the linear voltage regulator 504 can be between about 10ns and about 100ns. The linear voltage regulator 504 can provide a more accurate regulation of the voltage at the output node 518 compared to the non-linear voltage regulator 502 but at a relatively slower rate than the non-linear voltage regulator 502. In some examples, the linear voltage regulator 504 can have a first measure of accuracy in the range of + / -100 pV of the desired voltage VREF while the non-linear voltage regulator can have a second measure of accuracy in the range of + / -10 mV of the desired voltage VREF. In some examples, the first measure of accuracy can be expressed in terms of a percentage error from the desired voltage VREF (e.g., 1% or less). Similarly, the second measure of accuracy can also be expressed in terms of a percentage error from the desired voltage VREF, and for the non-linear voltage regulator 502, the value of the second measure of accuracy can be about 5% to about 15% or about 10%. The driver circuit 500 can combine the benefits of the non-linear voltage regulator 502 and the linear voltage regulator 504 to quickly and accurately regulate the voltage at the output node 518.

[0096] Under load conditions, the controller 520 can switch ON the first switch 514 for a first duration to couple the first output voltage port 508 with the output node 518 to provide quick regulation of the voltage at the output node 518. The non-linear voltage regulator 502 can be configured to quickly bring the voltage at the output node 518 to within a threshold value of the desired voltage (e.g., the reference voltage VREF). the threshold value can be, for example, a percentage of the desired voltage (e.g., 10%, 20%, 30% or any value between about 5% to about 30%), or can be an absolute value (e.g., 0.1 mV, 0.2 mV, or any value between about 1 mV and about 10 mV). The selection of the threshold value can be based, in part, on the total allocated settling time and / or the total slew rate of the non-linear voltage regulator. In some examples, the first duration can be selected to be sufficient to allow the non-linear voltage regulator 502 to regulate the voltage at the output node 518 to within the threshold value of the desired voltage. Thereafter, the controller can switch ON the second switch 516 to couple the second output voltage port 512 with the output node 518 to provide accurate regulation of the voltage at the output node 518 to the desired voltage.

[0097] In some examples, the controller 520 can switch OFF the first switch 514 at the same time as switching ON the second switch 516, thereby decoupling the non-linearvoltage regulator 502 and coupling the linear voltage regulator 504 to the first output voltage port 508, without overlap, but with as small a duration as possible for which neither of the non-linear voltage regulator 502 and the linear voltage regulator 504 are coupled with the output node 518. In this manner, the linear voltage regulator 504 can take over the regulation of the voltage at the output node 518 as soon as the non-linear voltage regulator 502 is decoupled. To avoid the scenario where neither the non-linear voltage regulator 502 nor the linear voltage regulator 504 is coupled with the output node 518 during loading conditions, the controller 520 can switch ON the second switch 516 to couple the 504 to the output node 518 while the non-linear voltage regulator 502 is also coupled with the output node 518. In other words, there is overlap between the first duration and the second duration. During the overlap, both the non-linear voltage regulator 502 and the linear voltage regulator 504 source / drain current to / from the output node 518. After the completion of the first duration, and the resulting decoupling of the non-linear voltage regulator 502 from the output node 518, the linear voltage regulator 504 can continue to regulate the voltage at the output node 518.

[0098] FIG. 6 shows a first example non-linear regulator circuit 600. The first example non-linear regulator circuit 600 can be utilized to implement the non-linear voltage regulator 502 discussed in relation to the driver circuit 500 shown in FIG. 5. The first example non-linear regulator circuit 600 shown in FIG. 6 can be viewed as an example of a non-linear error amplifier. It should be noted that the first example non-linear regulator circuit 600 is only one example of the non-linear voltage regulator 502, and that other types of non-linear regulators can be utilized, such as, for example, switched regulators. The non-linear regulator circuit 600 can include a first comparator 620 and a pull-up transistor 614. The negative terminal of the first comparator 620 receives the input reference voltage VREF and the positive terminal of the first comparator 620 is coupled with the first output voltage port 508. The pull-up transistor 614 is positioned between the first supply input port 506 and the first output voltage port 508. Specifically, a drain / source terminal of the pull-up transistor 614 is coupled with the first supply input port 506 and the source / drain terminal of the pull-up transistor 614 is coupled with the first output voltage port 508. The first comparator 620 can receive power from a power supply 626 (AVDD). In the example shown in FIG. 6, the pull-up transistor 614 can be a p-type transistor (e.g., PMOS transistor). In some other examples, the pull-up transistor 614 can be a n-type transistor (e.g., NMOS transistor). In such examples, the positive terminal of the first comparator 620 can receive the input reference voltage VREF and thenegative terminal of the first comparator 620 can be coupled with the first output voltage port 508.

[0099] Assuming that the voltage at the output node 518 is below the desired reference voltage VREF due to loading and that the controller switches the first switch 514 ON, the positive terminal of the 620 will have a voltage that is less than the reference voltage VREF at the positive terminal, causing the output of the first comparator 620 to go low. This, in turn, results in the pull-up transistor 614 to switch ON and create a current path between the first supply input port 506 and the first output voltage port 508. The current flow from the first supply input port 506 to the first output voltage port 508 will cause the voltage at the first output voltage port 508 to increase. Once the voltage at the first output voltage port 508 reaches within an input offset voltage of the reference voltage, the output of the first comparator 620 will go high, switching OFF the pull-up transistor 614.

[0100] As mentioned above in relation to the non-linear voltage regulator 502, the first duration (the duration for which the first switch 514 is switched ON) can correspond to a duration within which the non-linear voltage regulator 502 regulates the voltage at the first output voltage port 508 to within a threshold value of the reference voltage. One approach to implementing this in the non-linear regulator circuit 600 can be to set the input offset voltage of the first comparator 620 to be equal to the threshold value. The time taken to raise the voltage of the first output voltage port 508 to a value that is within a threshold value from the reference voltage to result in the switching OFF of the pull-up transistor 614 can be a function of, in part, the drive strength of the pull-up transistor 614, the speed of the first comparator 620, and the load on the output node 518. The first duration can then be equal to the time from the instant when the first switch 514 is closed to the instant when voltage at the first output voltage port 508 rises to a value that is within a threshold value from the reference voltage. At the end of the first duration, even if the 514 is still maintained in the ON position, because the pull-up transistor 614 is switched OFF, there is not current flow from the first supply input port 506 to the output node 518.

[0101] In another approach, the time taken for the non-linear regulator circuit 600 to raise the voltage at the output node 518 to within the threshold value from the reference voltage can be analytically or experimentally determined. This time can then be set to be equal to the first duration, and the controller 520 can be configured to keep the first switch 514 in the ON position for that first duration.

[0102] FIG. 7 shows a second example non-linear regulator circuit 700. In particular, the second example non-linear regulator circuit 700 can be utilized to implement the non-linear voltage regulator 502 discussed in relation to the driver circuit 500 shown in FIG. 5. It should be noted that the second example non-linear regulator circuit 700 is only one example of the non-linear voltage regulator 502, and that other types of non-linear regulators can be utilized, such as, for example, switched regulators. The first example non-linear regulator circuit 600 discussed above in relation to FIG. 6 can be used only to pull the voltage at the first output voltage port 508 up to the desired voltage. However, the first example non-linear regulator circuit 600 can be insufficient when the voltage at the first output voltage port 508 becomes greater than the desired reference voltage. The second example non-linear regulator circuit 700 can include both pull-up and pull-down circuitry. For example, the pull-up circuitry can be similar to the first example non-linear regulator circuit 600 discussed above. The pull-down circuitry can include a second comparator 720, the negative terminal of which receives the reference voltage and the positive terminal of which receives the output voltage at the first output voltage port 508. The output terminal of the second comparator 720 can be coupled with the gate of a pulldown transistor 714, one terminal (source / drain) of which is coupled with the first output voltage port 508 and the other terminal (drain / source) is coupled with a low voltage or a ground terminal. A capacitor 730 can be coupled between the first output voltage port 508 and the low voltage or ground terminal. The operation of the pull-down circuitry is similar to the first example non-linear regulator circuit 600 discussed above. When the output voltage at the first output voltage port 508 rises above the reference voltage by the input offset of the second comparator 720, the output of the second comparator 720 will go high and switch ON the pull-down transistor 714. As a result, the output voltage at the first output voltage port 508 will be pulled down. The pull-down transistor 714 will remain ON until the value of the output voltage at the first output voltage port 508 is within the input offset voltage of the second comparator 720. In this manner, the combination of the pull-up and the pull-down circuit shown in the second example nonlinear regulator circuit 700 can ensure that the voltage at the first output voltage port 508, when deviating from the reference voltage, is quickly brought back towards the reference voltage.

[0103] Similar to the first comparator 620, the second comparator 720 can also be configured to have the input offset voltage set to the threshold value. This will cause the pull-down circuit to activate only when the output voltage at the first output voltage port 508 exceeds the reference voltage by the first threshold value. The value of the first duration discussed above in relation to the first example non-linear regulator circuit 600can be similarly applied to the second example non-linear regulator circuit 700.

[0104] FIG. 8 shows a first example linear regulator 800. In particular, the first example linear regulator 800 can be utilized to implement the linear voltage regulator 504 discussed above in relation to the driver circuit 500 shown in FIG. 5. It should be noted that the first example linear regulator 800 is only illustrative rather than restrictive, and that other linear regulators such as, for example, low drop-out regulators can also be used to implement the linear voltage regulator 504. The first example linear regulator 800 can include a differential to single ended amplifier 802, the positive input terminal of which receives the reference voltage and the negative input terminal of which is coupled with the second output voltage port 512. The differential to single ended amplifier 802 can be a multi-stage amplifier, an operational amplifier, or any other suitable amplifier. The differential to single ended amplifier 802 can receive power from the second supply input port 510, which can be connected to a DC supply voltage. In some examples, the voltage received at the first supply input port 506 to the non-linear voltage regulator 502 can be less than the voltage received at the second supply input port 510 to the linear voltage regulator 504. A capacitor C can be coupled between the second output voltage port 512 and the low voltage or ground terminal. The first example linear regulator 800 utilizes negative feedback to maintain the voltage at the second output voltage port 512 at the reference voltage VREF. Thus, any deviations in the voltage at the second output voltage port 512 from the reference voltage will be corrected by the differential to single ended amplifier 802.

[0105] When the controller 520 switches the second switch 516 ON, and assuming that the voltage at the second output voltage port 512 is different from the desired reference voltage, the differential to single ended amplifier 802 will source or sink current from the second output voltage port 512 to raise or lower the voltage at the second output voltage port 512, respectively, in order to bring the voltage back to the reference voltage. The controller 520 can maintain the second switch 516 in the ON position for a second duration at a time after switching ON the first switch 514, as described with reference to FIG. 5.

[0106] As discussed above, the second duration can overlap the first duration or can begin at the end of the first duration. As the non-linear voltage regulator 502 is predominantly responsible for bringing the voltage at the output node 518 to within a threshold value of the reference voltage, the linear voltage regulator 504 is generally responsible for regulating the voltage at the output node 518 above or below the reference voltage by thethreshold value. That is, if the voltage of the output node 518 exceeds the threshold value, the non-linear voltage regulator 502 is activated to bring the voltage at the output node 518 to at, above or below the reference voltage by a threshold value, and then the linear voltage regulator 504 is activated to bring the voltage from that point to be equal to the reference voltage. As the linear voltage regulator 504 predominantly operates to regulate the voltage at the output node 518 within a window that is above or below the reference voltage by a threshold value, the linear voltage regulator 504 can quickly and accurately regulate this voltage.

[0107] Power consumed by the set of drivers 406 (FIG. 4) to regulate the voltage at their respective output nodes can be, in part, a function of the supply voltage provided to the drivers. In particular, for a driver, the power consumed by the driver can be a function of the difference between the supply voltage and reference voltage. The greater the difference, the larger the power consumption. One approach to reduce the power consumption can be to select a supply voltage that is greater than and closest to the desired reference voltage. The desired reference voltage generated by the drivers can change during operation. To reduce power consumption, the supply voltages to the drivers can accordingly be changed as well to the closest greater available supply voltage.

[0108] The accuracy of the outputs of the set of drivers 406 can be degraded by the noise level on the first supply input port 506 and the second supply input port 510 due to power supply rejection properties of the driver circuit. This can require the plurality of voltage sources 908 to be high quality, low noise level voltage sources. The generation of high quality, low noise level voltage sources can be very power inefficient. One approach to reducing the power and simultaneously improving the overall accuracy of the driver circuits is to use a power-efficient albeit noisy voltage supply applied to the first supply input port 506 of non-linear voltage regulator 502 and a cleaner (or lower noise level), albeit less power-efficient voltage supply applied to the second supply input port 510 of the linear voltage regulator 504. For large voltage excursions at the output node 518, most of the current needed to regulate the output node back to VREF is drawn by the nonlinear voltage regulator 502 and a relatively small amount of current is drawn by the linear voltage regulator 504. During the initial transient, the non-linear voltage regulator 502 can take its supply from the highly efficient, but noisy, power supply and bring the output node 518 close to VREF. Once the non-linear voltage regulator 502 has brought the output close to VREF, the non-linear voltage regulator 502 can be turned off and the output node 518 can be disconnected from the noisy voltage supply. At this point, the linear voltageregulator 504, which uses the cleaner, less efficient power supply can be turned on and high accuracy can be achieved. In this way, both power efficiency and accuracy can be achieved. Additionally, a power-efficient albeit noisy voltage supply can be applied to the second supply input port 510 of the linear regulator 504 during the first duration and then dynamically switched to the cleaner, albeit less power efficient voltage supply during the second duration. This improves the power efficiency further by improving the power efficiency of the linear voltage regulator 504 during the first duration.

[0109] FIG. 9 shows a second example analog voltage delivery circuit 900. The second example voltage delivery circuit 900 is similar to the first example analog voltage delivery circuit 400 discussed in relation to FIG. 4. However, unlike the first example analog voltage delivery circuit 400, which included only a single supply voltage VDC 408, the second example analog voltage delivery circuit 900 can include a plurality of voltage sources. Specifically, the second example analog voltage delivery circuit 900 can include a plurality of supply voltages VDC-I (908-1) to VDC-N (908-n) (collectively referred to as “a plurality of voltage sources 908”). Each supply voltage of the plurality of voltage sources 908 can provide a different voltage. For example, the plurality of voltage sources 908 can provide voltage values of 0.5 V, 0.6 V, 0.7 V, and 0.8 V. Of course, these values are only examples, and the number of voltage sources and the voltages each of them provides can be based on the specific implementation. In some examples, at least two voltage sources of the plurality of voltage sources 908 can have different noise levels. For example, the noise level at the voltage sources can manifest as deviations from the expected DC voltage and can, for example, take the form of voltage ripple. In some examples, the noise level can be measured as the ratio of the magnitude of the deviations over the magnitude of the DC voltage expected at the output of the voltage source. In some other examples, the root-mean-square value of the deviations instead of the magnitude can be utilized. In some other examples, other parameters of the deviations in the voltage can be utilized to represent the noise level. As discussed herein, having voltage sources with different noise levels can enable selection of one voltage source with higher noise level but greater power efficiency over another voltage source that has lower noise level but lower power efficiency. The plurality of voltage sources 908 can include voltage sources with the same DC output voltage but with two or more different noise levels.

[0110] The second example analog voltage delivery circuit 900 can also include a set of selection circuits (selection ckt-1 910-1 to selection ckt-m 910-m) (collectively referredto as “a set of selection circuits 910”) corresponding to the set of drivers 406. Each of the set of selection circuits 910 can be configured to select one voltage source from the plurality of voltage sources 908. For example, the selection ckt-1 can select one voltage source to be coupled with the first supply input port 506 of the non-linear voltage regulator 502 (FIG. 5). In some examples, the voltage generators that generate the voltages on the plurality of voltage sources 908 can be substantially noisier than the voltage source that provide voltage to the linear voltage regulator 504. Therefore, the voltage to the linear voltage regulator 504 may not be provided from one of the plurality of voltage sources 908. In some such instances, where the ability to select a voltage source for the linear voltage regulator 504 is also needed, another plurality of voltage sources that have substantially less noise than the plurality of voltage sources 908 can be provided. To that end, each of the set of selection circuits 910 can include a first selection circuit to select a voltage source for the non-linear voltage regulator 502 from the plurality of voltage sources 908 and a second selection circuit to select a voltage source for the linear voltage regulator 504 from a different plurality of voltage sources (not shown). In instances where both the non-linear voltage regulator 502 and the linear voltage regulator 504 are provided with the same supply voltage, the set of selection circuits 910 can select a single voltage source from the plurality of voltage sources 908 to provide to both the non-linear voltage regulator 502 and the linear voltage regulator 504. In instances where the non-linear voltage regulator 502 and the linear voltage regulator 504 are provided voltages from the same plurality of voltage sources 908, the first selection circuit and the second selection circuit can select voltage sources for the non-linear voltage regulator 502 and the linear voltage regulator 504 respectively from the plurality of voltage sources 908, which can include voltage sources with different values and with different noise levels. [OHl] FIG. 10 shows a first example source voltage selection circuit 1000. The first example selection circuit 1000 can be utilized to implement any of the set of selection circuits 910 discussed above in relation to the second example analog voltage delivery circuit 900 shown in FIG. 9. The first example selection circuit 1000 can include switches 1004-1 to 1004-n (collectively referred to as “a plurality of source selection switches 1004”), where each of the plurality of source selection switches 1004 is coupled with one of the plurality of voltage sources 908. The first example selection circuit 1000 also includes a decoder 1002-1, which receives a digital selection input SEL[ / :0] and generates a plurality of control signals for the plurality of source selection switches 1004. The digital selection input SEL[ / :0] can be an l+l bit data signal that can be generated by acontrol logic on-chip (e.g., the controller 520 (FIG. 5)) or can be data from a register which is updated by software, where the determination of the appropriate voltage source for a given reference voltage is carried out. The 1002-1 can decode the digital selection input and generate an enable signal for the switch that is coupled with the selected voltage source (VDC-I to VDC-N). The selected voltage source can then be provided to the driver circuit 406-1. In examples where two separate voltage sources are to be provided to the driver — one for the non-linear voltage regulator 502 and the other for the linear voltage regulator 504 — the selection circuit 910-1 can include another decoder and set of source selection switches for selecting the second source voltage from a separate plurality of voltage sources.

[0112] FIG. 11 shows a second example source voltage selection circuit 1100. The second example source voltage selection circuit 1100 is similar to the first example selection circuit 1000 discussed in relation to FIG. 10. However, unlike the first example selection circuit 1000, in which the decision of selecting the voltage source is externally made, the second example source voltage selection circuit 1100 itself can make the decision for the selection of the voltage source. For example, the second example source voltage selection circuit 1100 can include a voltage range sensor 1102-1 that is coupled with the reference voltage input that provides the reference voltage VREF to the Driver- 1 406-1. The voltage range sensor 1102-1 can include circuitry that senses the reference voltage and selects the nearest greater voltage source from the plurality of voltage sources 908. For example, if the reference voltage is 0.5 V and three voltage sources of value 0.4 V, 0.6 V, and 0.8 V are available, then the voltage range sensor 1102-1 can select the voltage source of value 0.6 V. In some examples, the voltage range sensor 1102-1 can include a plurality of comparators that compare the reference voltage with progressively increasing values of voltage sources to identify the voltage sources that are greater than the reference voltage and include logic circuitry to then select the output of the first comparator that has a high output as the control signal to the corresponding one of the source selection switches. Other approaches of selecting the nearest greatest voltage source to the reference voltage can also be employed. In examples where two separate voltage sources are to be provided to the driver — one for the non-linear voltage regulator 502 and the other for the linear voltage regulator 504 — the selection circuit 910-1 can include another voltage range sensor and set of source selection switches for selecting the second source voltage from a separate plurality of voltage sources.

[0113] In some examples, the voltage range sensor 1102-1 can select a nearest greatervoltage source to a sum of the reference voltage VREF and a headroom voltage. For example, if the reference voltage is 0.5 V and the headroom voltage is 0.1 V, and the three voltage sources of value 0.4 V, 0.6 V, and 0.8 V are available, then the voltage range sensor 1102-1 can select the voltage source of value 0.8 V. The headroom voltage can ensure reliable operation of the voltage regulator, as in some instances, the voltage regulator my not operate reliably if the reference voltage is too close to the source voltage.ASPECTS OF THE DISCLOSURE

[0114] The present disclosure will be better understood upon reading the following numbered aspects, which should not be confused with the claims. Each of the numbered aspects described below can, in some instances, be combined with aspects described elsewhere in the disclosure. The following listing of example aspects is supported by the disclosure provided herein.

[0115] Aspect 1. A circuit, including: a non-linear voltage regulator including a first supply input port and a first output voltage port, the non-linear voltage regulator configured to regulate a voltage at the first output voltage port based on a reference voltage; a linear voltage regulator including a second supply input port and a second output voltage port, the linear voltage regulator configured to regulate a voltage at the second output voltage port based on the reference voltage, wherein the non-linear voltage regulator has a transient response to voltage changes at the first output voltage port that is faster than that of the linear voltage regulator at the second output voltage port; and a switching circuit configured to: for a first duration, couple the first output voltage port of the non-linear voltage regulator with an output node, and for a second duration following a start of the first duration, couple the second output voltage port of the linear voltage regulator with the output node.

[0116] Aspect 2. The circuit of any one of Aspects 1-15, wherein the first duration and the second duration overlap and the second duration is longer than the first duration.

[0117] Aspect 3. The circuit of any one of Aspects 1-15, wherein the first duration corresponds to a duration within which the non-linear voltage regulator regulates the voltage at the first output voltage port to within a threshold value of the reference voltage.

[0118] Aspect 4. The circuit of any one of Aspects 1-15, wherein the first duration corresponds to a first half period of a clock signal and the second duration corresponds to a second half period of the clock signal.

[0119] Aspect 5. The circuit of any one of Aspects 1-15, wherein a first supply input port of the non-linear voltage regulator receives a voltage that is less than a voltagereceived at a second supply input port of the linear voltage regulator.

[0120] Aspect 6. The circuit of any one of Aspects 1-15, wherein an accuracy of the linear voltage regulator is greater than the accuracy of the non-linear voltage regulator.

[0121] Aspect ?. The circuit of any one of Aspects 1-15, wherein the non-linear voltage regulator includes a non-linear error amplifier.

[0122] Aspect s. The circuit of any one of Aspects 1-15, wherein the non-linear voltage regulator includes a first comparator and a pull-up transistor, wherein a negative terminal of the comparator receives the reference voltage and a positive terminal of the comparator is coupled with the first output voltage port, and wherein the pull-up transistor is positioned between the first supply input port and the first output voltage port, and an output terminal of the first comparator is coupled to the gate of the pull-up transistor.

[0123] Aspect 9. The circuit of any one of Aspects 1-15, wherein the non-linear voltage regulator includes a second comparator and a pull-down transistor, wherein the negative terminal of the second comparator receives the reference voltage and the positive terminal of the second comparator is coupled with the first output voltage port, and wherein the pull-down transistor is positioned between the first output voltage port and a low voltage or ground terminal, and an output terminal of the second comparator is coupled to the gate of the pull-down transistor.

[0124] Aspect 10. The circuit of any one of Aspects 1-15, wherein the linear voltage regulator includes a low drop-out voltage regulator.

[0125] Aspect 11. The circuit of any one of Aspects 1-5, wherein the voltage applied to the first supply input port has higher noise than the voltage applied to the second supply input port.

[0126] Aspect 12. The circuit of any one of Aspects 1-15, further including: a first voltage selection circuit configured to select a voltage source applied to the first supply input port, from a plurality of voltage sources, each of the plurality of voltage sources having a different voltage.

[0127] Aspect 13. The circuit of any one of Aspects 1-15, wherein: the first voltage selection circuit is configured to select the voltage source applied to the first supply input port, based on the reference voltage.

[0128] Aspect 14. The circuit of any one of Aspects 1-15, further including: a second voltage selection circuit configured to select a voltage source applied to the second supply input port, from a plurality of voltage sources, at least two voltages sources of the plurality of voltage sources having different noise levels.

[0129] Aspect 15. The circuit of any one of Aspects 1-15, further including: a second voltage selection circuit configured to select a voltage source applied to the second supply input port, from a plurality of voltage sources, each of the plurality of voltage sources having a different voltage.

[0130] Aspect 16. The circuit of any one of Aspects 1-14, wherein: the second voltage selection circuit is configured to select the voltage source applied to the second supply input port, based on the reference voltage.

[0131] Aspect 17. A method for providing analog voltages, including: for a first duration, coupling a first output voltage port of a non-linear voltage regulator with an output node, the non-linear voltage regulator including a first supply input port and a first output voltage port, the non-linear voltage regulator configured to regulate a voltage at the first output voltage port; and for a second duration following a start of the first duration, coupling a second output voltage port of a linear voltage regulator with the output node, the linear voltage regulator configured to regulate a voltage at the second output voltage port based on a reference voltage, wherein the non-linear voltage regulator has a transient response to voltage changes at the first output voltage port that is faster than that of the linear voltage regulator at the second output voltage port.

[0132] Aspect 18. The method of any one of Aspects 17-32, wherein the first duration and the second duration overlap and the second duration is longer than the first duration.

[0133] Aspect 19. The method of any one of Aspects 17-32, wherein the first duration corresponds to a duration within which the non-linear voltage regulator regulates the voltage at the first output voltage port to within a threshold value of the reference voltage.

[0134] Aspect 20. The method of any one of Aspects 17-32, wherein the first duration corresponds to a first half period of a clock signal and the second duration corresponds to a second half period of the clock signal.

[0135] Aspect 21. The method of any one of Aspects 17-32, wherein a first supply input port of the non-linear voltage regulator receives a voltage that is less than a voltage received at a second supply input port of the linear voltage regulator.

[0136] Aspect 22. The method of any one of Aspects 17-32, wherein an accuracy of the linear voltage regulator is greater than an accuracy of the non-linear voltage regulator.

[0137] Aspect 23. The method of claim 17, wherein the non-linear voltage regulator includes a non-linear error amplifier.

[0138] Aspect 24. The method of any one of Aspects 17-32, wherein the non-linear voltage regulator includes a first comparator and a pull-up transistor, wherein a negativeterminal of the first comparator receives the reference voltage and a positive terminal of the first comparator is coupled with the first output voltage port, and wherein the pull-up transistor is positioned between the first supply input port and the first output voltage port, and an output terminal of the first comparator is coupled to the gate of the pull-up transistor.

[0139] Aspect 25. The method of any one of Aspects 17-32, wherein the non-linear voltage regulator includes a second comparator and a pull-down transistor, wherein the negative terminal of the second comparator receives the reference voltage and the positive terminal of the second comparator is coupled with the first output voltage port, and wherein the pull-down transistor is positioned between the first output voltage port and a low voltage or ground terminal, and an output terminal of the second comparator is coupled to the gate of the pull-down transistor.

[0140] Aspect 26. The method of any one of Aspects 17-32, wherein the linear voltage regulator includes a low drop-out voltage regulator.

[0141] Aspect 27. The method of any one of Aspects 17-32, wherein a voltage applied to a first supply input port of the non-linear voltage regulator has higher noise than a voltage applied to a second supply input port of the linear voltage regulator.

[0142] Aspect 28. The method of any one of Aspects 17-32, wherein a voltage applied to a second supply input port of the linear voltage regulator during the first duration has a higher noise level than the voltage applied to a second supply input port of the linear voltage regulator during the second duration.

[0143] Aspect 29. The method of any one of Aspects 17-32, further including: selecting a voltage applied to a first supply input port of the non-linear voltage regulator from a plurality of voltage sources, each of the plurality of voltage sources having a different voltage.

[0144] Aspect 30. The method of any one of Aspects 17-32, further including: selecting the voltage applied to the first supply input port of the non-linear voltage regulator from the plurality of voltage sources based on the reference voltage.

[0145] Aspect 31. The method of any one of Aspects 17-32, further including: selecting a voltage applied to a second supply input port of the linear voltage regulator from a plurality of voltage sources, each of the plurality of voltage sources having a different voltage.

[0146] Aspect 32. The method of any one of Aspects 17-31, further including: selecting the voltage applied to the second supply input port from the plurality of voltagesources based on the reference voltage.

[0147] The examples disclosed herein are illustrative and not limiting in nature. Details disclosed with respect to the methods described herein included in one example or aspect can be applied to other examples and aspects. Any aspect of the present disclosure that has been described herein can be disclaimed, i.e., exclude from the claimed subject matter whether by proviso or otherwise.

[0148] Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein.

Claims

CLAIMSWhat is claimed is:

1. A circuit, comprising: a non-linear voltage regulator including a first supply input port and a first output voltage port, the non-linear voltage regulator configured to regulate a voltage at the first output voltage port based on a reference voltage; a linear voltage regulator including a second supply input port and a second output voltage port, the linear voltage regulator configured to regulate a voltage at the second output voltage port based on the reference voltage, wherein the non-linear voltage regulator has a transient response to voltage changes at the first output voltage port that is faster than that of the linear voltage regulator at the second output voltage port; and a switching circuit configured to: for a first duration, couple the first output voltage port of the non-linear voltage regulator with an output node, and for a second duration following a start of the first duration, couple the second output voltage port of the linear voltage regulator with the output node.

2. The circuit of claim 1, wherein the first duration and the second duration overlap and the second duration is longer than the first duration.

3. The circuit of claim 1, wherein the first duration corresponds to a duration within which the non-linear voltage regulator regulates the voltage at the first output voltage port to within a threshold value of the reference voltage.

4. The circuit of claim 1, wherein the first duration corresponds to a first half period of a clock signal and the second duration corresponds to a second half period of the clock signal.

5. The circuit of claim 1, wherein a first supply input port of the non-linear voltage regulator receives a voltage that is less than a voltage received at a second supply input port of the linear voltage regulator.

6. The circuit of claim 1, wherein an accuracy of the linear voltage regulator is greater than the accuracy of the non-linear voltage regulator.

7. The circuit of claim 1, wherein the non-linear voltage regulator includes a nonlinear error amplifier.

8. The circuit of claim 1, wherein the non-linear voltage regulator includes a first comparator and a pull-up transistor, wherein a negative terminal of the comparator receives the reference voltage and a positive terminal of the comparator is coupled with the first output voltage port, and wherein the pull-up transistor is positioned between the first supply input port and the first output voltage port, and an output terminal of the first comparator is coupled to a gate of the pull-up transistor.

9. The circuit of claim 8, wherein the non-linear voltage regulator includes a second comparator and a pull-down transistor, wherein the negative terminal of the second comparator receives the reference voltage and the positive terminal of the second comparator is coupled with the first output voltage port, and wherein the pull-down transistor is positioned between the first output voltage port and a low voltage or ground terminal, and an output terminal of the second comparator is coupled to the gate of the pull-down transistor.

10. The circuit of claim 1, wherein the linear voltage regulator includes a low dropout voltage regulator.

11. The circuit of claim 1, wherein the voltage applied to the first supply input port has higher noise than the voltage applied to the second supply input port.

12. The circuit of claim 1, further comprising: a first voltage selection circuit configured to select a voltage source applied to the first supply input port, from a plurality of voltage sources, each of the plurality of voltage sources having a different voltage.

13. The circuit of claim 12, wherein:the first voltage selection circuit is configured to select the voltage source applied to the first supply input port, based on the reference voltage.

14. The circuit of claim 12, further comprising: a second voltage selection circuit configured to select a voltage source applied to the second supply input port, from a plurality of voltage sources, at least two voltages sources of the plurality of voltage sources having different noise levels.

15. The circuit of claim 12, further comprising: a second voltage selection circuit configured to select a voltage source applied to the second supply input port, from a plurality of voltage sources, each of the plurality of voltage sources having a different voltage.

16. The circuit of claim 15, wherein: the second voltage selection circuit is configured to select the voltage source applied to the second supply input port, based on the reference voltage.

17. A method for providing analog voltages, comprising: for a first duration, coupling a first output voltage port of a non-linear voltage regulator with an output node, the non-linear voltage regulator including a first supply input port and a first output voltage port, the non-linear voltage regulator configured to regulate a voltage at the first output voltage port; and for a second duration following a start of the first duration, coupling a second output voltage port of a linear voltage regulator with the output node, the linear voltage regulator configured to regulate a voltage at the second output voltage port based on a reference voltage, wherein the non-linear voltage regulator has a transient response to voltage changes at the first output voltage port that is faster than that of the linear voltage regulator at the second output voltage port.

18. The method of claim 17, wherein the first duration and the second duration overlap and the second duration is longer than the first duration.

19. The method of claim 17, wherein the first duration corresponds to a duration within which the non-linear voltage regulator regulates the voltage at the first output voltage port to within a threshold value of the reference voltage.

20. The method of claim 17, wherein the first duration corresponds to a first half period of a clock signal and the second duration corresponds to a second half period of the clock signal.

21. The method of claim 17, wherein a first supply input port of the non-linear voltage regulator receives a voltage that is less than a voltage received at a second supply input port of the linear voltage regulator.

22. The method of claim 17, wherein an accuracy of the linear voltage regulator is greater than an accuracy of the non-linear voltage regulator.

23. The method of claim 17, wherein the non-linear voltage regulator includes a nonlinear error amplifier.

24. The method of claim 17, wherein the non-linear voltage regulator includes a first comparator and a pull-up transistor, wherein a negative terminal of the first comparator receives the reference voltage and a positive terminal of the first comparator is coupled with the first output voltage port, and wherein the pull-up transistor is positioned between the first supply input port and the first output voltage port, and an output terminal of the first comparator is coupled to a gate of the pull-up transistor.

25. The method of claim 24, wherein the non-linear voltage regulator includes a second comparator and a pull-down transistor, wherein the negative terminal of the second comparator receives the reference voltage and the positive terminal of the second comparator is coupled with the first output voltage port, and wherein the pull-down transistor is positioned between the first output voltage port and a low voltage or ground terminal, and an output terminal of the second comparator is coupled to the gate of the pull-down transistor.

26. The method of claim 17, wherein the linear voltage regulator includes a low dropout voltage regulator.

27. The method of claim 17, wherein a voltage applied to a first supply input port of the non-linear voltage regulator has higher noise than a voltage applied to a second supply input port of the linear voltage regulator.

28. The method of claim 17, wherein a voltage applied to a second supply input port of the linear voltage regulator during the first duration has a higher noise level than the voltage applied to a second supply input port of the linear voltage regulator during the second duration.

29. The method of claim 17, further comprising: selecting a voltage applied to a first supply input port of the non-linear voltage regulator from a plurality of voltage sources, each of the plurality of voltage sources having a different voltage.

30. The method of claim 29, further comprising: selecting the voltage applied to the first supply input port of the non-linear voltage regulator from the plurality of voltage sources based on the reference voltage.

31. The method of claim 17, further comprising: selecting a voltage applied to a second supply input port of the linear voltage regulator from a plurality of voltage sources, each of the plurality of voltage sources having a different voltage.

32. The method of claim 31, further comprising: selecting the voltage applied to the second supply input port from the plurality of voltage sources based on the reference voltage.

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