Systems and methods for high-resolution, high-speed, analog voltage delivery to in-memory computing arrays

Abstract

A device can include a linear error amplifier coupled with an output node and configured to regulate a voltage at the output node based on an input reference voltage, the linear error amplifier receiving a first voltage source as a supply voltage, the linear error amplifier having a first transient response time and a first measure of accuracy. A device can include a non-linear error amplifier coupled with the output node and receiving a second voltage source as a supply voltage to regulate the output node responsive to the voltage at the output node going below the reference voltage by a first magnitude, the non-linear error amplifier having a second transient response time that is lower than the first transient response time, and has a second measure of accuracy indicating that the non-linear amplifier is less accurate than the linear error amplifier.

Description

SYSTEMS AND METHODS FOR HIGH-RESOLUTION, HIGHSPEED, ANALOG VOLTAGE DELIVERY TO IN-MEMORY COMPUTING ARRAYSCROSS-REFERENCE TO RELATED APPLICATIONSThis Application claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 606,023 filed December 4, 2023.TECHNICAL FIELD

[0001] This disclosure relates to in-memory computing arrays, and in particular to circuits for providing analog voltages to in-memory computing arrays.DESCRIPTION OF THE RELATED TECHNOLOGY

[0002] Using in-memory computing for neural network acceleration is an emerging and innovative approach that leverages the unique properties of memory devices to enhance the speed and efficiency of neural network computations. Traditional neural network training and inference processes involve moving data back and forth between memory (RAM) and processing units (CPUs or GPUs), which can be a significant bottleneck in terms of speed and energy consumption. In-memory computing seeks to overcome these limitations by processing data directly within the memory itself.SUMMARY

[0003] In some aspects, the techniques described herein relate to a circuit, including: a linear error amplifier coupled with an output node and configured to regulate a voltage at the output node based on an input reference voltage, the linear error amplifier receiving a first voltage source as a supply voltage, the linear error amplifier having a first transient response time and a first measure of accuracy; and a non-linear error amplifier coupled with the output node and receiving a second voltage source as a supply voltage to regulate the output node responsive to the voltage at the output node going below the reference voltage by a first magnitude, the non-linear error amplifier having a second transient response time that is lower than the first transient response time, and has a second measure of accuracy indicating that the non-linear amplifier is less accurate than the linear error amplifier.

[0004] In some aspects, the techniques described herein relate to a circuit, wherein the non-linear error amplifier has an offset voltage equal to the first magnitude.

[0005] In some aspects, the techniques described herein relate to a circuit, wherein the offset voltage is programable.

[0006] In some aspects, the techniques described herein relate to a circuit, wherein the linear error amplifier includes a positive terminal coupled with the input reference voltage and a negative terminal coupled with the output node.

[0007] In some aspects, the techniques described herein relate to a circuit, wherein the non-linear error amplifier includes a first comparator and a pull up transistor, wherein the negative terminal of the first comparator receives the input reference voltage and the positive terminal of the first comparator is coupled with the output node, and wherein the pull up transistor is positioned between the second voltage source and the output node, and an output terminal of the first comparator is coupled to the gate terminal of the pull up transistor.

[0008] In some aspects, the techniques described herein relate to a circuit, wherein the pull up transistor is a PMOS transistor.

[0009] In some aspects, the techniques described herein relate to a circuit, wherein the non-linear error amplifier includes a first comparator and a pull up transistor, wherein the positive terminal of the first comparator receives the input reference voltage and the negative terminal of the first comparator is coupled with the output node, and wherein the pull up transistor is positioned between the second voltage source and the output node, and an output terminal of the first comparator is coupled to the gate terminal of the pull up transistor.

[0010] In some aspects, the techniques described herein relate to a circuit, wherein the pull up transistor is a NMOS transistor.

[0011] In some aspects, the techniques described herein relate to a circuit, wherein the non-linear error amplifier is a first non-linear error amplifier, the circuit further including: a second non-linear error amplifier coupled with the output node and configured to reduce the voltage at the output node responsive to the voltage at the output node going above the reference voltage by a second magnitude, the second non-linear error amplifier selectively coupling the output node to a low voltage terminal or ground.

[0012] In some aspects, the techniques described herein relate to a circuit, wherein the second comparator has an offset voltage equal to the second magnitude.

[0013] In some aspects, the techniques described herein relate to a circuit, wherein the offset voltage of the second comparator is programable.

[0014] In some aspects, the techniques described herein relate to a circuit, wherein thesecond non-linear error amplifier includes a second comparator and a pull down transistor, wherein the positive terminal of the second comparator is coupled with the output node and the negative terminal of the second comparator receives the input reference voltage, and wherein the pull down transistor is positioned between the output node and the low voltage terminal or ground and an output terminal of the second comparator is coupled to the gate terminal of the pull down transistor.

[0015] In some aspects, the techniques described herein relate to a circuit, wherein the pull down transistor is a NMOS transistor.

[0016] In some aspects, the techniques described herein relate to a circuit, wherein the second non-linear error amplifier includes a second comparator and a pull down transistor, wherein the positive terminal of the second comparator is configured to receive the input reference voltage and the negative terminal of the second comparator is coupled with the output node, and wherein the pull down transistor is positioned between the output node and the low voltage terminal or ground and an output terminal of the second comparator is coupled to the gate terminal of the pull down transistor.

[0017] In some aspects, the techniques described herein relate to a circuit, wherein the pull down transistor is a PMOS transistor.

[0018] In some aspects, the techniques described herein relate to a circuit, wherein the linear error amplifier includes at least two amplifier stages, an output of a last amplifier stage of the at least two amplifier stages coupled with the output node and at least one amplifier stage preceding the last amplifier stage generating a differential signal corresponding to a difference between the voltage at the output node and the input reference voltage, wherein input terminals of both the first non-linear error amplifier and the second non-linear error amplifier are coupled to the differential signal.

[0019] In some aspects, the techniques described herein relate to a circuit, further including: a voltage selection circuit, with a plurality of input terminals coupled with a plurality of voltages and an output terminal coupled with the second voltage, the voltage selection circuit configured to select the second voltage source from the plurality of voltage sources, each of the plurality of second voltage sources having a different voltage, the second voltage source providing a voltage that is nearest in value to the input reference voltage.

[0020] In some aspects, the techniques described herein relate to a circuit, further including: a compute in-memory array (CIMA) including a plurality of rows of bit-cells, each bit-cell of the plurality of rows of bit-cells computing a portion of a compute in-memory operation, the plurality of rows of bit-cells being provided the output node voltage; and an output node switch positioned between the output node and the CIMA, the output node switch configured to close prior to the compute in-memory operation in the CIMA.

[0021] In some aspects, the techniques described herein relate to a circuit, wherein the output node switch is switched periodically between an on state and an off state based on a switching duration, wherein the non-linear error amplifier and the linear amplifier are configured to settle the voltage at the output node within the switching duration subsequent to output node switching to the on state.

[0022] In some aspects, the techniques described herein relate to a circuit, wherein the switching duration is between 0.1 nanoseconds (ns) and 1 millisecond (ms).

[0023] In some aspects, the techniques described herein relate to a method for providing a reference voltage at an output node, including: regulating a voltage at an output node using a linear error amplifier coupled with the output node, the linear error amplifier regulating the voltage at the output node based on an input reference voltage, the linear error amplifier receiving a first voltage source as a supply voltage, the linear error amplifier having a first transient response time and a first measure of accuracy; and responsive to the voltage at the output node going below the reference voltage by a first magnitude, regulating the voltage at the output node using a non-linear voltage regulator coupled with the output node, the non-linear error amplifier receiving a second voltage source as a supply voltage, the non-linear error amplifier having a second transient response time that is lower the first transient response time and a second measure of accuracy indicating that the non-linear amplifier is less accurate than the linear error amplifier.

[0024] In some aspects, the techniques described herein relate to a method, wherein the non-linear voltage regulator has an offset voltage equal to the first magnitude.

[0025] In some aspects, the techniques described herein relate to a method, further including: programming the offset voltage into the non-linear voltage regulator.

[0026] In some aspects, the techniques described herein relate to a method, wherein the linear error amplifier includes a positive terminal coupled with the input reference voltage and a negative terminal coupled with the output node.

[0027] In some aspects, the techniques described herein relate to a method, wherein the non-linear error amplifier includes a first comparator and a first pull up transistor, wherein the negative terminal of the first comparator receives the input reference voltage and thepositive terminal of the first comparator is coupled with the output node, and wherein the pull up transistor is positioned between the second voltage source and the output node, and an output terminal of the first comparator is coupled with the gate terminal of the pull up transistor.

[0028] In some aspects, the techniques described herein relate to a method, wherein the pull up transistor is a PMOS transistor.

[0029] In some aspects, the techniques described herein relate to a method, wherein the non-linear error amplifier includes a first comparator and a pull up transistor, wherein the positive terminal of the first comparator receives the input reference voltage and the negative terminal of the first comparator is coupled with the output node, and wherein the pull up transistor is positioned between the second voltage source and the output node, and an output terminal of the first comparator is coupled to the gate terminal of the pull up transistor.

[0030] In some aspects, the techniques described herein relate to a method, wherein the pull up transistor is a NMOS transistor.

[0031] In some aspects, the techniques described herein relate to a method, wherein the non-linear error amplifier is a first non-linear error amplifier, the method further including; responsive to the voltage at the output node exceeding the reference voltage by a second magnitude, reducing the voltage at the output node using a second non-linear error amplifier coupled with the output node, the second non-linear error amplifier selectively coupling the output node to low voltage terminal or ground.

[0032] In some aspects, the techniques described herein relate to a method, wherein the second non-linear error amplifier includes a second comparator and a pull down transistor, wherein the positive terminal of the second comparator is coupled with the output node and the negative terminal of the second comparator receives the input reference voltage, and wherein the second switch is positioned between the output node and the low voltage terminal or ground and an output terminal of the second comparator is coupled with the gate terminal of the pull down transistor.

[0033] In some aspects, the techniques described herein relate to a method, wherein the pull down transistor is a NMOS transistor.

[0034] In some aspects, the techniques described herein relate to a method, wherein the second non-linear error amplifier includes a second comparator and a pull down transistor, wherein the positive terminal of the second comparator receives the input reference voltage and the negative terminal of the second comparator is coupled with theoutput node, and wherein the pull down transistor is positioned between the output node and the low voltage terminal or ground and an output terminal of the second comparator is coupled to the gate terminal of the pull down transistor.

[0035] In some aspects, the techniques described herein relate to a method, wherein the pull down transistor is a PMOS transistor.

[0036] In some aspects, the techniques described herein relate to a method, wherein the linear error amplifier includes at least two amplifier stages, an output of a last amplifier stage of the at least two amplifier stages coupled with the output node and at least one amplifier stage preceding the last amplifier stage generating a differential signal corresponding to a difference between the voltage at the output node and the input reference voltage, wherein input terminals of both the first non-linear error amplifier and the second non-linear error amplifier are coupled to the differential signal.

[0037] In some aspects, the techniques described herein relate to a method, wherein the second non-linear error amplifier has an offset voltage equal to the second magnitude.

[0038] In some aspects, the techniques described herein relate to a method, wherein the offset voltage is programable.

[0039] In some aspects, the techniques described herein relate to a method, further including: periodically switching an output node switch based on a switching duration, the output node switch coupled between the output node and a compute in-memory array (CIMA) including a plurality of rows of bit-cells, each bit-cell of the plurality of bit-cells computing a portion of a compute in-memory operation, the plurality of rows of bit-cells being provided the output node voltage.

[0040] In some aspects, the techniques described herein relate to a method, wherein the non-linear voltage regulator and the linear amplifier are configured to settle the voltage at the output node within the switching duration subsequent to switching the output node switch to a on state that couples the output node with the plurality of rows of bit-cells.

[0041] In some aspects, the techniques described herein relate to a method, wherein the switching duration is between 0.1 ns and 1 ms.BRIEF DESCRIPTION OF THE DRAWINGS

[0042] FIG. 1 depicts a block diagram of an example in-memory computing architecture.

[0043] FIG. 2 shows a block diagram of a compute in-memory array.

[0044] FIG. 3 shows an example circuit diagram of the computing cells discussed above in relation to FIG. 2.

[0045] FIG. 4 shows a first example analog voltage delivery circuit for delivering analogvoltages to the compute in-memory array.

[0046] FIG. 5 shows a first example driver circuit.

[0047] FIG. 6 shows a second example driver circuit.

[0048] FIG. 7 shows a third example driver circuit including a multi-stage linear error amplifier.

[0049] Like reference numbers and designations in the various drawings indicate like elements.DETAILED DESCRIPTION

[0050] The various concepts introduced above and discussed in greater detail below can be implemented in any of numerous ways, as the described concepts are not limited to any particular manner of implementation. Examples of specific implementations and applications are provided primarily for illustrative purposes.

[0051] As will be apparent to those of skill in the art upon reading this disclosure, each of the individual aspects described and illustrated herein has discrete components and features which can be readily separated from or combined with the features of any of the other several aspects without departing from the scope or spirit of the present disclosure.

[0052] Any recited method can be carried out in the order of events recited or in any other order that is logically possible. That is, unless otherwise expressly stated, it is in no way intended that any method or aspect set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not specifically state in the claims or descriptions that the steps are to be limited to a specific order, it is no way intended that an order be inferred, in any respect. This holds for any possible nonexpress basis for interpretation, including matters of logic with respect to arrangement of steps or operational flow, plain meaning derived from grammatical organization or punctuation, or the number or type of aspects described in the specification.

[0053] All publications mentioned herein are incorporated herein by reference to disclose and describe the methods and / or materials in connection with which the publications are cited. The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. Nothing herein is to be construed as an admission that the present invention is not entitled to antedate such publication by virtue of prior invention. Further, the dates of publication provided herein can be different from the actual publication dates, which can require independent confirmation.

[0054] While aspects of the present disclosure can be described and claimed in a particular statutory class, such as the system statutory class, this is for convenience onlyand one of skill in the art will understand that each aspect of the present disclosure can be described and claimed in any statutory class.

[0055] It is also to be understood that the terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosed compositions and methods belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0056] It should be noted that ratios, concentrations, amounts, and other numerical data can be expressed herein in a range format. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint. It is also understood that there are a number of values disclosed herein, and that each value is also herein disclosed as “about” that particular value in addition to the value itself. For example, if the value “10” is disclosed, then “about 10” is also disclosed. Ranges can be expressed herein as from “about” one particular value, and / or to “about” another particular value. Similarly, when values are expressed as approximations, by use of the antecedent “about,” it will be understood that the particular value forms a further aspect. For example, if the value “about 10” is disclosed, then “10” is also disclosed.

[0057] When a range is expressed, a further aspect includes from the one particular value and / or to the other particular value. For example, where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the disclosure, e.g. the phrase “x to y” includes the range from ‘x’ to ‘y’ as well as the range greater than ‘x’ and less than ‘y’. The range can also be expressed as an upper limit, e.g. ‘about x, y, z, or less’ and should be interpreted to include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ as well as the ranges of Tess than x’, less than y’, and Tess than z’. Likewise, the phrase ‘about x, y, z, or greater’ should be interpreted to include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ as well as the ranges of ‘greater than x’, greater than y’, and ‘greater than z’. In addition, the phrase “about ‘x’ to ‘y’”, where ‘x’ and ‘y’ are numerical values, includes “about ‘x’ to about ‘y’”.

[0058] It is to be understood that such a range format is used for convenience and brevity, and thus, should be interpreted in a flexible manner to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited. To illustrate, a numerical range of “about 0.1% to 5%” should be interpreted to include not only the explicitly recited values of about 0.1% to about 5%, but also include individual values (e.g., about 1%, about 2%, about 3%, and about 4%) and the sub-ranges (e.g., about 0.5% to about 1.1%; about 5% to about 2.4%; about 0.5% to about 3.2%, and about 0.5% to about 4.4%, and other possible sub-ranges) within the indicated range.

[0059] As used herein, the terms “about,” “approximate,” “at or about,” and “substantially” mean that the amount or value in question can be the exact value or a value that provides equivalent results or effects as recited in the claims or taught herein. That is, it is understood that amounts, sizes, formulations, parameters, and other quantities and characteristics are not and need not be exact, but can be approximate and / or larger or smaller, as desired, reflecting tolerances, conversion factors, rounding off, measurement error and the like, and other factors known to those of skill in the art such that equivalent results or effects are obtained. In some circumstances, the value that provides equivalent results or effects cannot be reasonably determined. In such cases, it is generally understood, as used herein, that “about” and “at or about” mean the nominal value indicated ±10% variation unless otherwise indicated or inferred. In general, an amount, size, formulation, parameter or other quantity or characteristic is “about,” “approximate,” or “at or about” whether or not expressly stated to be such. It is understood that where “about,” “approximate,” or “at or about” is used before a quantitative value, the parameter also includes the specific quantitative value itself, unless specifically stated otherwise.

[0060] Prior to describing the various aspects of the present disclosure, the following definitions are provided and should be used unless otherwise indicated. Additional terms can be defined elsewhere in the present disclosure.

[0061] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0062] As used in the specification and the appended claims, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise. Thus, forexample, reference to “a proton beam degrader,” “a degrader foil,” or “a conduit,” includes, but is not limited to, two or more such proton beam degraders, degrader foils, or conduits, and the like.

[0063] The terms “configured for” or “configured to,” as used herein with respect to a specified operation or function, refer to a device, component, circuit, structure, machine, signal, etc. that is physically constructed, programmed, formatted and / or arranged to perform the specified operation or function.

[0064] The various concepts introduced above and discussed in greater detail below can be implemented in any of numerous ways, as the described concepts are not limited to any particular manner of implementation. Examples of specific implementations and applications are provided primarily for illustrative purposes.

[0065] As used herein, the terms “optional” or “optionally” means that the subsequently described event or circumstance can or cannot occur, and that the description includes instances where said event or circumstance occurs and instances where it does not.

[0066] Unless otherwise specified, temperatures referred to herein are based on atmospheric pressure (i.e. one atmosphere).

[0067] In-memory Computing Architecture

[0068] FIG. 1 depicts a block diagram of an example in-memory computing architecture 100. The in-memory computing architecture 100 can be adapted, for example, to a scalable neural network accelerator architecture based on in-memory computing (IMC). However, the in-memory computing architecture 100 is not limited to neural network applications, and can be employed in numerous applications where high data throughput with low power consumption is desired. The in-memory computing architecture 100 includes a plurality of Compute In-Memory unit (CIMU) tiles 102. The plurality of CIMU tiles 102 are arranged in an array within the architecture. The plurality of CIMU tiles 102 can be individually enabled / disabled based on the computations to be carried out by the in-memory computing architecture 100. In examples where the in-memory computing architecture 100 can be used to implement neural networks, the neural networks can be mapped to one or more CIMU tiles of the plurality of CIMU tiles 102. The remainder of the CIMU tiles of the plurality of CIMU tiles 102 can be disabled to reduce power consumption.

[0069] The in-memory computing architecture 100 can include, in part, activation buffers 104, segmented weight buffers 106, and one or more phase-locked loops (PLLs) 108. The activation buffers 104 can provide signals representative of activations from previousstages of computation, for instance previous layers in a neural network. The segmented weight buffers 106 can provide data required for computation together with the activations / data from previous stages, for instance these weight buffers could store the weights of neural network layers. The one or more PLLs 108 can provide reference clock signals to various portions of the in-memory computing architecture 100. The in-memory computing architecture 100 can also include off-chip control elements 110 or interfaces 110 for communication with off-chip processors or software to send and receive control or data signals. The off-chip interface 110 can, by itself or in concert with other elements, provide circuits and protocols for high-speed interfaces for wired or wireless connections involving data, control signals, or both, to other processors or other arrays of CIMU tiles, for example, enabling the in-memory computing architecture 100 to scale upward as desired.

[0070] Each of the plurality of CIMU tiles 102 can include a plurality of CIMUs 112, an on-chip network 114, and a weight network 116. While FIG. 1 shows each of the plurality of CIMU tiles 102 including four CIMUs 112, this is only an example, and the CIMU tiles 102 can include fewer or more CIMUs 112. One or more of the CIMUs 112 can include a compute in-memory (CIM) array 118, compute dataflow buffers 120, programmable digital single instruction multiple data (SIMD) 122, and a programming and control module 124. The CIM array 118 can be an array of computing cells, discussed further below. The CIM array 118 can carry out computations based on data stored in the computing cells and data provided by the activation buffers 104. The computing cells can be used to perform computational operations between inputs and data stored in a memory cell within the computing cells. The operations can include logical operations (AND, NOR, etc.) or multiplication operations carried out between inputs. The CIM array 118 can carry out matrix operations between multi -bit operands, which is particularly useful in neural network computations where activations are multiplied with weights. In some such applications, the weights can be stored in the memory cells of the CIM array 118 and activations can be provided as input vectors. Each computing cell in the CIM array 118 can perform the multiplication operation between a 1 -bit weight and a portion of the input activation, which can be represented in digital or analog signal form. Some example computing cells can generate a result that is in the form of an electrical signal. For example, the computing cell can output an analog voltage that is representative of the computation result. In some other examples, the computing cell can output an electrical current that is representative of the computation result. The electricalsignals of various computing cells can be accumulated and processed to generate the overall matrix multiplication result. For example, electrical signals representative of computation from all computing cells in a single column of the CIM array 118 can be accumulated to represent a portion of the computation. Accumulated electrical signals from multiple columns of computing cells of the CIM array 118 can be combined and processed to generate an overall matrix multiplication result. For instances where the electrical signal generated by the computing cells is an electrical current, the currents from various computing cells within a column can be summed to generate a representative accumulated electrical current. In instances where the electrical signal generated by the computing cell is an analog voltage, the analog voltage generated by each computing cell can be stored in capacitors within the computing cell and then accumulated as a voltage that is representative of a portion of the overall matrix multiplication result. The accumulated result, whether an electrical current or an analog voltage, can be converted into digital form using analog to digital converters (ADCs) and further processed, stored, or passed on to other CIM arrays 118 for further computations.

[0071] The programmable digital SIMD 122 can have an instruction set for flexible element-wise operation and the compute dataflow buffers 120 can support wide range of neural network dataflows. Each CIMUs 112 can provide a high-level of configurability and can be abstracted into a software library of instructions for interfacing with a compiler (for allocating / mapping an application, neural network and the like to the architecture), and where instructions can thus also be added prospectively. That is, the library can include single / fused instructions such as element mult / add, h(») activation, (N-step convolutional stride + matrix-vector-multiplication (MVM) + batch norm. +h(») activation + max. pool), (dense + MVM) and the like. In various nonlimiting examples, h(») can indicate an activation function, including without limitation the rectified linear unit ReLU(x) function, the sigmoid function (o(x)), and other such functions. Max pooling, a downsampling technique for reducing spatial dimensions to maintain computational efficiency while retaining other important features of the CIMU array or the network, can also be a subject of the computation. The N-step convolutional stride can refer to the number of pixels or other information bits that a kernel or convolutional filter moves or glides across the input image during convolution to effect operations like feature detection, pattern recognition, blurring, image sharpening, image recognition, and the like.

[0072] The on-chip network 114 (OCN) can include routing channels within NetworkIn / Out Blocks, and a Switch Block, which provides flexibility via a disjoint architecture as shown, for example, by the disjoint buffer switch 133 in the enlarged view of OCN 114. This flexibility, among other benefits, enables modules that are independent of one another to work in parallel. The OCN 114 works with configurable CIMU input / output ports to optimize data structuring to / from an in-memory computing engine, to maximize data locality across MVM dimensionalities and tensor depth / pixel indices. The OCN 114 routing channels can include bidirectional wire pairs as shown by the exemplary duodirectional pipelined routing structure 131 in the expanded view if the OCN 114, so as to ease repeater / pipeline-FF insertion, while providing sufficient density.

[0073] The in-memory computing architecture 100 can be used to implement a neural network (NN) accelerator, wherein a plurality of compute in memory units (CIMUs 112) are arrayed and interconnected using a very flexible on-chip network (OCN 114) wherein the outputs of one CIMU can be connected to or flow to the inputs of another CIMU or to multiple other CIMUs, the outputs of many CIMUs can be connected to the inputs of one CIMU, the outputs of one CIMU can be connected to the inputs of another CIMU and so on. The OCN 114 can be implemented as a single on-chip network, as a plurality of on-chip network portions, or as a combination of on-chip and off-chip network portions.

[0074] The CIMUs 112 can be surrounded by an on-chip network 114 for moving activations between CIMUs 112 (activation network) as well as moving weights from embedded L2 memory to CIMUs 112 (weight-loading interface). This has similarities with architectures used for coarse-grained reconfigurable arrays (CGRAs), but with cores providing high-efficiency MVM and element-wise computations targeted for neural network acceleration. Various options exist for implementing the on-chip network. The approach in FIG. 1 enables routing segments along a CIMU 112 to take outputs from that CIMU 112 and / or to provide inputs to that CIMU 112. In this manner data originating from any CIMU 112 can be routed to any CIMU 112, and any number of CIMUs 112.

[0075] Each CIMU 112 is associated with an input buffer (not shown) for receiving computational data from the on-chip network and composing the received computational data into an input vector for MVM processing by the CIMU to generate thereby computed data including an output vector.

[0076] Each CIMU 112 is associated with a shortcut buffer (not shown), for receiving computational data from the on-chip network 114, imparting a temporal delay to the received computational data, and forwarding delayed computation data toward a nextCIMU 112 or an output in accordance with a dataflow map such that dataflow alignment across multiple CIMUs 112 is maintained. At least some of the input buffers can be configured to impart a temporal delay to computational data received from the on-chip network 114 or from a shortcut buffer. The dataflow map can support pixel-level pipelining to provide pipeline latency matching.

[0077] The temporal delay imparted by shortcut or input buffers includes at least one of an absolute temporal delay, a predetermined temporal delay, a temporal delay determined with respect to a size of input computational data, a temporal delay determined with respect to an expected computational time of the CIMU 112, a control signal received from a dataflow controller, a control signal received from another CIMU 112, and a control signal generated by the CIMU 112 in response to the occurrence of an event within the CIMU. In some aspects, at least one of the input buffer and shortcut buffers of each of the plurality of CIMUs 112 in the array of CIMUs 112 can be configured in accordance with a dataflow map supporting pixel-level pipelining to provide pipeline latency matching. The array of CIMUs 112 can also include parallelized computation hardware configured for processing input data received from at least one of respective input and shortcut buffers.

[0078] A least a subset of the CIMUs 112 can be associated with on-chip network 114 portions including operand loading network portions configured in accordance with a dataflow of an application mapped onto the IMC. The application mapped onto the IMC includes a neural network (NN) mapped onto the IMC such that parallel output computed data of configured CIMUs executing at a given layer are provided to configured CIMUs 112 executing at a next layer, said parallel output computed data forming respective NN feature-map pixels.

[0079] The input buffer can be configured for transferring input NN feature-map data to parallelized computation hardware within the CIMU in accordance with a selected stride step, such as discussed above. The NN can include a convolution neural network (CNN), and the input buffer can be used to buffer a number of rows of an input feature map corresponding to a size or height of the CNN kernel.

[0080] The CIM array 118 in each CIMU 112 can perform matrix vector multiplication (MVM) in accordance with a bit-parallel, bit-serial (BP / BS) computing process in which single bit computations are performed using an iterative barrel shifting with column weighting process, followed by a results accumulation process.

[0081] FIG. 2 shows additional details of a portion of the in-memory computingarchitecture 100 shown in FIG. 1, and in particular, details of an example compute inmemory (CIM) array 200 and associated components. The CIM array 200 can be used, for example, to implement, in part, the CIM array 118 discussed above in relation to the in-memory computing architecture 100 shown in FIG. 1. In one example implementation, the CIM array 200 can include a fully row / column-parallel (1152 rowX 256 column) array of computing cells 202 of an in-memory-computing (IMC) macro enabling N-bit (5-bit) input processing. For example, the label “10T SRAM array” (1152x256) corresponding to CIM array 200 and the designations 10T in each memory cell of the array refer to an example design where each memory cell in the array uses 10 transistors (“10T”) to construct the memory cell. Other designs, however, are possible. The number of rows (1152), the number or columns (256), and the number of bits (5-bit) of input shown in FIG. 2 are only examples, and these quantities and circuit configurations can be varied based on desired implementations. The computing cells 202 can be used to perform computational operations between inputs and data stored in a memory cell within the computing cells. The operations can include logical operations (AND, NOR, etc.) or multiplication operations carried out between inputs. In some examples, the operands of the computation can be 1 -bit each. In some other examples, one of the operands can be an analog signal (voltage or current) while the other operand can be a 1 -bit operand stored in the memory cell.

[0082] The in-memory computing architecture 100, in some examples, can be utilized for matrix vector multiplication (MVM) operations, which dominate compute-intensive and data-intensive Al workloads, in a manner that reduces compute energy and data movement by orders of magnitude. This is achieved through efficient analog compute in the computing cells 202, and by thus accessing a compute result (e.g., inner product), rather than individual bits, from memory. But, doing so fundamentally instates an energy / throughput-vs.-SNR tradeoff, where going to analog introduces compute noise and accessing a compute result increases dynamic range (i.e., reducing SNR for given readout architecture). The computing cells 202, which store computational results in the form of a voltage in capacitors (e.g., CM-BC) within the computing cells 202, can employ metal-fringing capacitors, which can achieve very low noise from analog nonidealities, and thus have the potential for extremely high dynamic range.

[0083] FIG. 2 shows a block diagram of the CIM array 200 including a 1152 (row) X 256 (col.) array of 10T SRAM computing cells 202, which in this example are multiplying bit-cells (M-BCs) (such as, for example, a 10T M-BC 202, although the number oftransistors of SRAM interface 204 and M-BCs 202 is implementation-dependent and the circuit can use different numbers of transistors or other circuit elements without departing from the principles of the disclosure); peripheral circuits for standard writing / reading thereto (e.g., a bit line (BL) decoder 204 (also referred to as SRAM interface) and 256 BL drivers 206-1 through 206-256 (collectively referred to as BL drivers 206), a word line (WL) or address decoder 208 and 1152 WL drivers 210-1 through 210-1152 (collectively referred to as WL drivers 210), and control block 212 for controlling the BL decoder 204 such as SRAM interface and the WL decoder 208); peripheral circuitry for providing 5-bit input-vector elements thereto (e.g., 1152 Dynamic-Range Doubling (DRD) DACs 214-1 through 214-1152 (collectively referred to as DRD DACs 214), and a corresponding in-memory computing (IMC) controller (“control block” 216); peripheral circuitry for digitizing the compute result from each column (e.g., 256 8-bit successive approximation register (SAR) ADCs 218-1 through 218-256 (collectively referred to as SAR ADCs 218), and column reset mechanisms 220-1 through 220-256 (collectively referred to as column reset mechanisms 220) (e.g., CMOS switches configured to pull the output voltage levels of column compute lines CLs to a reset voltage VRST during a reset phase of operation, and allow the voltage levels of column compute lines CLs to reflect their respective compute results during an evaluation phase of operation). For example, the RST switches corresponding to CL1-CL256, or a subset thereof, can close to produce the desired reset voltage VRST during the reset phase. The RST switches can then open during an ensuing evaluation phase, thereby enabling the voltage values at the CLs to reflect the computed product.

[0084] In addition, the lower right portion of FIG. 2 depicts an example enlarged view of a representative one of the 256 8-bit ADCs, which includes various switch mechanisms ADCRST (Analog-to-Digital Converter Reset), ADCSMP (Analog-to-Digital Converter Sample) and voltage designations VADCRST and VCMPR, the latter voltage designation connected in this example to a positive terminal of the comparator CMPR and the former voltage designation selectively applied via the ADCRST and ADCSMP switch to reset the comparator. The negative terminal of comparator CMPR receives a compute line (CL) value when the circuit is activated. An output of comparator CMPR is coupled to SAR logic for outputting an 8-bit digital result. It will be appreciated, however, that the implementation details of the above circuits are representative in nature and that variations to the circuits are possible without departing from the scope or spirit of the present disclosure.

[0085] While writing / reading is typically performed row-by-row, MVM operations are typically performed by applying input-vector elements corresponding to neural -network input activations to all rows at once. That is, each DRD DAC 214j, in response to a respective 5-bit input-vector element Xj [4:0], generates a respective differential output signal (lAj / IAbj) which is subjected to a 1-bit multiplication with the stored weights (Aij / Abij) at each computing cells 202j in the corresponding row of computing cells 202, and accumulation through charge-redistribution across computing cells 202 capacitors on the compute line (CL) to yield an inner product in each column, which is then digitized via the respective SAR ADCs 218 of each column.

[0086] FIG. 3 shows an example circuit diagram of the computing cells 202 discussed above in relation to FIG. 2. The computing cells 202 can include a highly dense structure for achieving weight storage and multiplication, thereby minimizing data-broad-cast distance and control signals within the context of i-row, j -column arrays implemented using such computing cells, such as the 1152 (row) X 256 (col.) CIM array 200 of 10T SRAM multiplying bit cells (M-BCs).

[0087] The exemplary computing cells 202 includes a six-transistor bit cell portion 222, a first switch SW1, a second switch SW2, a capacitor C, a word line (WL) 224, a first bit line (BLj) 227, a second bit line (BLbj) 228, and a compute line (CL) 230.

[0088] The six-transistor bit cell portion 222 is depicted as being located in a middle portion of the computing cells 202, and includes six transistors 226a-226f in this example. The 6-transistor bit cell portion 222 can be used for storage, and to read and write data. In one example, the 6-transistor bit cell portion 222 stores the filter weight. In some examples, data is written to the computing cells 202 through the word line (WL) 224, the first bit line (BL) 227, and the second bit line (BLb) 228.

[0089] The computing cells 202 can include a first CMOS switch SW1 and a second CMOS switch SW2. The first switch SW 1 is depicted as being controlled by a first stored signal Aij such that, when closed, the first switch SW1 couples one of the received differential output signals provided by the DRD DACs 214, illustratively IA, to a first terminal of the capacitor C. The second switch SW2 is depicted as being controlled by a second stored signal Abij such that, when closed, the second switch SW2 couples the other one of the received differential output signals (lA / IAb) of the corresponding DRD DACs 214, illustratively lAb, to the first terminal of the capacitor C. The second terminal of the capacitor C is connected to a compute line (CL) 230 via an output port 232 that provides a result of the computation of the computation cell 202. It is noted that in various otherexamples, the input signals provided to the first and second switches SW 1 and SW2 can include a fixed voltage (e.g., Vaa), ground, or some other voltage level.

[0090] The computing cells 202, including the first SW1 and second SW2 switches, can implement computation on the data stored in the six-transistor bit cell portion 222. The result of a computation is sampled as charge on the capacitor C. According to various implementations, the capacitor C can be positioned above the computing cell 202 and utilize no additional area on the circuit. In some implementations, a logic value of either Vdd or ground is stored on the capacitor C. In other implementations, the voltage stored on the capacitor C can include a positive or negative voltage in accordance with the operation of the first and the second switches SW 1 and SW2, and the output voltage level generated by the corresponding DRD DACs 214 as shown in FIG. 2.

[0091] Thus, with continued reference to FIG. 3, the value that is stored on the capacitor C is highly stable, since the capacitor C value is either driven up to a fixed analog voltage or down to ground. In some examples, the capacitor C is a metal-oxide-metal (MOM) finger capacitor, and in some examples, the capacitor C can be about 0.1 femto-Farhads (fF) to about 10 fF or can be about 1.2 fF. MOM capacitors have very good matching temperature and process characteristics, and thus have highly linear and stable compute operations. Note that other types of logic functions can be implemented using the computing cells 202 by changing the way the transistors 226a-226f and / or the first and the second switches SW 1 and SW2 are connected and / or operated during the reset and evaluation phases of operation. The six-transistor bit cell portion 222 can be implemented using different numbers of transistors and can have different architectures. In some examples, the six-transistor bit cell portion 222 can be a SRAM, DRAM, MRAM, or an RRAM.

[0092] Analog Voltage Delivery Circuits

[0093] FIG. 4 shows a first example analog voltage delivery circuit 400 for delivering analog voltages to the CIM array 402. The CIM array 402 can be similar to the CIM array 118 or the CIM array 200 discussed above in relation to FIG. 1 and FIG. 2. The first example analog voltage delivery circuit 400 can be utilized to generate a set of analog voltages (VAi-VAm) that can be utilized for the differential output signal (lAj / IAbj) provided to each row of the CIM array (see e.g., DRD DACs 214 that provide the differential output signal (lAj / IAbj) to the rows of the CIM array 200). The first example analog voltage delivery circuit 400 can include a set of m DACs: DAC-1 404-1 to DAC- m 404-m (collectively referred to as “the set of DACs 404”). The set of DACs 404 canreceive digital inputs VCNTRL-I[K:O] to VcNTRL-m[K:O], which can be converted into corresponding analog reference voltages VREF-I to VREF-HI. The digital inputs VCNTRL- I[K:0] to VcNTRL-m[K:O] can be digital representations of the analog voltages that are to be used to carry out computations in the computing cells 202. The first example analog voltage delivery circuit 400 can include a set of m drivers: Driver- 1 406-1 to Driver-m 406-m (collectively referred to as “the set of drivers 406”). Each driver of the set of drivers 406 receive a reference voltage VREF and generates a corresponding analog voltage VA that accurately reflects the reference voltage VREF. A supply voltage VDC 408 can provide power to the set of drivers 406. As an example, the supply voltage VDC can be generated on-chip or received from off the chip. On-chip supply voltage generation circuits can include, for example, buck regulators.

[0094] While not shown in FIG. 4, a selection circuit can select one of the set of analog voltages generated by the first example analog voltage delivery circuit 400 as one of the differential output signals. While the value of the differential output signals can vary from row to row, it is likely that one of the set of analog voltages is provided as one of the differential output signals of multiple rows. For example, referring to FIG. 2, a same value of voltage can be selected for at least one of the differential outputs (lAj / IAbj) of several of the 1152 rows. Thus, for example, VAi can be connected to differential outputs of several of the 1152 rows. The large number of rows of differential outputs connected to the analog voltage VAi can cause loading on the output of Driver 406-1. The loading, in turn, can affect the ability of Driver 406-1 to keep the analog voltage VAi substantially constant. For example, the selection circuit can include one or more switches that when switched ON, can connect several rows of differential outputs to each of the analog voltage outputs of the drivers. This causes a sudden increase in load at the output of the drivers. This increase in load can cause a decrease in the voltage at the output of the driver. The driver can regulate its output by pulling the output voltage back up to the desired voltage VA. However, it is preferable that the driver regulate the output voltage with accuracy (i.e., as close to corresponding VREF) and as quickly as possible. As discussed herein, the drivers are designed to provide both accuracy and quick regulation in response to changes in loads at their respective outputs.

[0095] FIG. 5 shows a first example driver circuit 500. The first example driver circuit 500 can be used to implement the set of drivers 406 discussed above in relation to FIG. 4. The first example driver circuit 500 includes a linear error amplifier 502 coupled with an output node 504 and a non-linear amplifier 506 also coupled with the output node 504.The linear error amplifier 502 can include a single-ended differential amplifier 518, an output of which is coupled with the output node 504. The negative terminal of the differential amplifier 518 is also coupled with the output node 504, thereby forming a negative feedback loop. The positive terminal of the differential amplifier 518 receives an input reference voltage VREF 522. The input reference voltage VREF can correspond to any one of the m reference voltages VREF-I to VREF-IH provided by the set of DACs 404 to the set of drivers 406 (FIG. 4). The linear error amplifier 502 can receive a first voltage source 524 as a supply voltage. In the example shown in FIG. 5, the first voltage source is AVDD, and can represent the supply voltage for other digital and analog circuitry. A capacitor 516 can be positioned between the output node 504 and a ground terminal.

[0096] The non-linear amplifier 506 can include a first comparator 520 and a pull up transistor 514. The negative terminal of the first comparator 520 receives the input reference voltage VREF 522 and the positive terminal of the first comparator 520 is coupled with the output node 504. The pull up transistor 514 is positioned between a second voltage source 528 and the output node 504. Specifically, a source / drain terminal of the pull up transistor 514 is coupled with the second voltage source 528 and the drain / source terminal of the pull up transistor 514 is coupled with the output node 504. In the example shown in FIG. 5, the pull up transistor 514 is a p-type transistor (e.g., a PMOS transistor). In some instances, the pull up transistor 514 can be a n-type transistor (e.g., a NMOS transistor). In such instances, the positive terminal of the first comparator 520 can be coupled with the input reference voltage VREF 522 and the negative terminal of the first comparator 520 can be coupled with output node 504. In addition, the source terminal of the pull up transistor 514 can be coupled with the output node 504 and the drain terminal of the pull up transistor 514 can be coupled with the second voltage source 528.

[0097] The first comparator 520 can receive power from a power supply 526, which in this example, is the same as the first voltage source 524 (AVDD). Although, it should be noted that in other examples, the power supply provided to the first comparator 520 can be different from the power supply provided to the differential amplifier 518. The first comparator 520 can have an associated input offset voltage Vio, which can refer to a difference between the positive and the negative terminals of the first comparator 520 below which the output of the first comparator 520 does not change. As discussed below, the input offset voltage of the first comparator 520 can be utilized as a transition voltage where the first example driver circuit 500 transitions from regulating the output voltage between the linear error amplifier 502 and the non-linear amplifier 506.

[0098] A switch 510 can be positioned between the output node 504 and a CIM array interconnect 512, which can be a part of, for example, a selection circuit that can select the output voltage of the first example driver circuit 500 for one or more differential signals provided to various rows of the CIM array 200.

[0099] Referring again to the linear error amplifier 502, the negative feedback from the output node 504 to the differential amplifier 518 causes the differential amplifier 518 to maintain the output node 504 at the input reference voltage VREF 522. The linear error amplifier 502 can maintain the output node 504 at the input reference voltage VREF 522 fairly accurately at steady state. In some examples, the linear error amplifier 502 can have a first measure of accuracy in the range of + / -100 pV of the desired VREF 522. In some instances, the first measure of accuracy can be expressed in terms of a percentage error from the desired VREF 522 (e.g., 1% or less). The linear error amplifier 502 also can have an associated transient response that, for example, can be represented by a settling time. The settling time can represent the time it takes for the linear error amplifier 502 to reach a specified percentage (e.g., between 1% and 10%) of a steady-state value of the output voltage at the output node 504. Example settling time (or the measure of the transient response) of the linear error amplifier 502 can be between about 10 ns and about 100 ns.

[0100] For large changes in the voltage at the output node 504, the transient response of the linear error amplifier 502 may not be sufficient to bring the voltage at the output node 504 back to the desired voltage (e.g., the input reference voltage VREF 522). In other words, the linear error amplifier 502 can be too slow to regulate the voltage at the output node 504 back to the desired voltage. To that end, the non-linear amplifier 506 can be employed to provide a fast response to large changes in the voltage at the output node 504. In particular, the input offset voltage of the non-linear amplifier 506 can be set to be equal to a first magnitude. If the voltage at the output node 504 goes below the input reference voltage VREF 522 by greater than the first magnitude, the output of the first comparator 520 will go low causing the pull up transistor 514 to switch ON. The switching ON of the pull up transistor 514 can cause current flow from the second voltage source 528 to the output node 504. This current flow can provide the charge to the output node 504 to quickly increase the voltage at the output node 504. As long as the voltage at the output node 504 remains below the input reference voltage VREF 522 by the first magnitude, the pull up transistor 514 will remain switched ON and continue to provide the current from the second voltage source 528 to the output node 504. As soon as thevoltage at the output node 504 increases to within the first magnitude of the input reference voltage VREF 522, the output of the first comparator 520 will go high, causing the pull up transistor 514 to switch OFF and cease the current flow from the second voltage source 528 to the output node 504. After the pull up transistor 514 is switched OFF, the linear error amplifier 502 can take over to bring the voltage, which at this stage is about the first magnitude away from the desired input reference voltage VREF 522, up to the input reference voltage VREF 522.

[0101] The non-linear amplifier 506 can have an associated transient response that, for example, can be represented by a settling time. The settling time can represent the time it takes for the non-linear error amplifier 506 to reach a specified percentage (e.g., between 1% and 10%) of a steady-state value of the output voltage at the output node 504. Example settling time (or the measure of the transient response) of the non-linear error amplifier 506 can be between about 0.1 ns and about 1 ns. The measure of the transient response of the non-linear amplifier 506 can be lower (meaning faster transient response) than the measure of the transient response of the linear error amplifier 502, discussed above. In some examples, the transient response time of the non-linear amplifier 506 can be at least an order of magnitude less than the transient response time of the linear error amplifier 502. Further, the non-linear amplifier 506 can have an associated second measure of accuracy. The second measure of accuracy can be described as the how close the non-linear amplifier 506 regulates the voltage at the output node 504 to the desired input reference voltage VREF 522 in steady state. In some respects, the second measure of accuracy of the non-linear amplifier 506 can be at least the input offset voltage of the non-linear amplifier 506 (or more specifically the input offset voltage of the first comparator 520). In some examples, the non-linear amplifier 506 can have a second measure of accuracy in the range of about 1 mV to about 10 mV of the desired VREF 522. The second measure of accuracy can be expressed in terms of a percentage error from the desired VREF 522 (e.g., about 5% to about 15% or about 10%).

[0102] The combination of the non-linear amplifier 506 and the linear error amplifier 502 can help provide the fast response to quickly raise the voltage at the output node 504 until the voltage reaches within a first magnitude of the input reference voltage VREF 522 and then rely on the more accurate linear error amplifier 502 to regulate the voltage at the output node 504 to the input reference voltage VREF 522. As such, both the high speed of the non-linear amplifier 506 and the high accuracy of the 502 can be leveraged to quickly and accurately raise the voltage at the output node 504 to the desired input referencevoltage VREF 522 in response to large changes in the voltage at the output node 504.

[0103] In some examples, the input offset voltage associated with the non-linear amplifier 506 can be programmable. That is, the input offset voltage of the non-linear amplifier 506 can be changed to the desired magnitude. In some examples, two or more resistors can be placed between VREF and ground and switches used to connect the various intermediate nodes of the resistor network, to the negative input of the first comparator 520. This can lower the voltage at the negative terminal of the first comparator 520 by the resistive voltage divider. In another example, the input differential transistors of the first comparator 520, that have their gates connected to the positive input could have one or more transistors that can be switched in parallel, with the number of input differential transistors of the first comparator 520, having their gates connected to the negative terminal remaining fixed. This can lower the required voltage at the positive terminal of the first comparator 520 that will cause the output of the first comparator 520 to transition high. In these examples, the voltage at the output node 504 would have to go below the input reference voltage VREF 522 by more than the input offset voltage for the pull up transistor 514 to switch ON.

[0104] FIG. 6 shows a second example driver circuit 600. The second example driver circuit 600 is similar to the first example driver circuit 500 discussed in relation to FIG. 5, in that like the first example driver circuit 500, the second example driver circuit 600 also includes the linear error amplifier 502 and the non-linear amplifier 506 (also referred to as “a first non-linear amplifier”). However, the second example driver circuit 600 in addition includes a second non-linear amplifier 530. While the first non-linear amplifier 506 regulated a dip or a reduction in the voltage at the output node 504, the second nonlinear amplifier 530 regulates an increase in the output voltage at the output node 504. For example, if the voltage at the output node 504 increases above the desired input reference voltage VREF 522 by a second magnitude, the second non-linear amplifier 530 can selectively couple the output node 504 with a low voltage terminal or a ground terminal. The second non-linear amplifier 530 includes a second comparator 532, a positive terminal of which is coupled with the output node 504, and the negative terminal of which receives the input reference voltage VREF 522. The output of the second comparator 532 is coupled with the gate terminal of a pull down transistor 534. The drain / source terminal of the pull down transistor 534 is coupled with the output node 504 and the source / drain terminal of the pull down transistor 534 is coupled with the low voltage terminal or the ground terminal. The drain and source terminals of the pull downtransistor 534 are coupled to the two terminals of the capacitor 516. The second comparator 532 can be provided power from a third voltage source 536 (AVDD), which in some examples can be similar to the second voltage source 526 and the first voltage source 524.

[0105] The second non-linear amplifier 530 can have an input offset voltage that is equal to a second magnitude. When the voltage at the output node 504 goes above the input reference voltage VREF 522 by a second magnitude, the output of the second comparator 532 goes high, causing the pull down transistor 534 to switch ON. The switching ON of the pull down transistor 534 results in a current path between the output node 504 and the low voltage or ground terminal, resulting in the reduction in the voltage at the output node 504. The pull down transistor 534 remains switched ON as long as the voltage at the output node 504 is above the input reference voltage VREF 522 by the second magnitude. As soon as the voltage at the output node 504 is within the second magnitude from the input reference voltage VREF 522, the output of the second comparator 532 goes low, causing the 534 to switch OFF. After the pull down transistor 534 is switched OFF, the linear error amplifier 502 can continue to regulate the voltage at the output node 504 by pulling the voltage down to the desired input reference voltage VREF 522.

[0106] In the example shown in FIG. 6, the pull down transistor 534 is a n-type transistor (e.g., a NMOS transistor). In some instances, the pull down transistor 534 can be a p- type transistor (e.g., a PMOS transistor). In such instances, the positive terminal of the second comparator 532 can be coupled with the input reference voltage VREF 522 and the negative terminal of the first comparator 520 can be coupled with output node 504. In addition, the source terminal of the pull up transistor 514 can be coupled with the output node 504 and the drain terminal of the pull up transistor 514 can be coupled with the second voltage source 528

[0107] Similar to the non-linear amplifier 506, the second non-linear amplifier 530 can have a third transient response time that is lower than the first transient response time of the linear error amplifier 502. In addition, the second non-linear amplifier 530 can have a third measure of accuracy that is less than the first measure of accuracy of the linear error amplifier 502. In some instances, the third transient response time and the third measure of accuracy can be similar to the second transient response time and the second measure of accuracy, respectively, discussed in relation to the non-linear amplifier 506. In some examples, similar to the first non-linear amplifier 506, the input offset voltage of the second non-linear amplifier 530 can be programmable. That is, the input offsetvoltage of the second non-linear amplifier 530 can be adjusted or modified to the desired value.

[0108] The second example driver circuit 600 can regulate voltage changes at the output node 504 in both directions from the desired input reference voltage VREF 522. If the voltage goes below the input reference voltage VREF 522 by the first magnitude, the first non-linear amplifier 506 (similar to the first non-linear amplifier 506 discussed above in relation to FIG. 5), will quickly bring the voltage up to within the first magnitude from the input reference voltage VREF 522, after which the linear error amplifier 502 can accurately bring the output voltage to the desired input reference voltage VREF 522. Similarly, if the output voltage at the output node 504 goes above the input reference voltage VREF 522 by the second magnitude, the second non-linear amplifier 530 will quickly bring the volage down to within the second magnitude from the input reference voltage VREF 522 after which the linear error amplifier 502 can accurately bring the output voltage to the desired input reference voltage VREF 522.

[0109] FIG. 7 shows a third example driver circuit 700 including a multi-stage linear error amplifier. In particular, the third example driver circuit 700 includes a two-stage linear error amplifier 702. The third example driver circuit 700 also includes the first non-linear amplifier 506 and the second non-linear amplifier 530, similar to those discussed in relation to FIG. 5 and FIG. 6. The two-stage linear error amplifier 702 includes a first amplifier stage 704 and a second amplifier stage 706. The first amplifier stage 704 can be a differential amplifier with differential outputs, which are coupled with the inputs of the second amplifier stage 706. Specifically, a first output 708 of the first amplifier stage 704 is coupled with the negative terminal of the second amplifier stage 706 and the second output 710 of the first amplifier stage 704 is coupled with the positive terminal of the second amplifier stage 706. The output of the second amplifier stage 706 is coupled with the output node 504. Each of the first amplifier stage 704 and the second amplifier stage 706 can have an associated gain, which in some examples can be greater than 1. The positive input of the first comparator 520 is coupled with the first output 708 of the first amplifier stage 704 and the negative terminal of the first comparator 520 is coupled with the second output 710 of the first amplifier stage 704. The positive terminal of the second comparator 532 is coupled with the first output 708 of the first amplifier stage 704 and the negative terminal of the second comparator 532 is coupled with the second output 710 of the first amplifier stage 704.

[0110] The first non-linear amplifier 506 and the second non-linear amplifier 530 receiveas inputs an amplified difference between the desired input reference voltage VREF 522 and the output voltage at the output node 504. Thus, these non-linear amplifiers are activated only when there is a difference between the input reference voltage VREF 522 and the output voltage 504. The offset of the first comparator 520 and the second comparator 532 in the third example driver circuit 700 can be set internal to the comparators using programable differential input pairs.[OHl] In some examples, the example drivers discussed herein can include a voltage selection circuit to select an appropriate supply voltage VDC 408 to provide to the drivers. In some such instances, the voltage selection circuit including a plurality of input terminals can be coupled with a plurality of supply voltages with different magnitudes and an output terminal that is coupled with the set of drivers 406. In particular, the output terminal can be coupled with the second voltage source 528 of the set of drivers 406. The voltage selection circuit can be configured to select a second voltage source from the plurality of supply voltages that is nearest in value to, but greater than, the input reference voltage VREF 522. By selecting the voltage source that is nearest in value to, but greater than, the input reference voltage VREF 522, power losses can be reduced.

[0112] In some examples, the linear error amplifier and the non-linear error amplifier can settle any changes in the output voltage at the output node 504 within a certain time duration that can be dictated by a data load cycle or a switching duration of the CIM array 200. In some examples, the switching duration can be between about 0.1 ns to about 1 ms. The set of drivers 406 can be capable of settling the output voltage at their respective output nodes to the desired input reference voltage VREF within this switching duration.

[0113] The examples disclosed herein are illustrative and not limiting in nature. Details disclosed with respect to the methods described herein included in one example or aspect can be applied to other examples and aspects. Any aspect of the present disclosure that has been described herein can be disclaimed, i.e., exclude from the claimed subject matter whether by proviso or otherwise.ASPECTS OF THE DISCLOSURE

[0114] The present disclosure will be better understood upon reading the following numbered aspects, which should not be confused with the claims. Each of the numbered aspects described below can, in some instances, be combined with aspects described elsewhere in the disclosure. The following listing of example aspects is supported by the disclosure provided herein.

[0115] Aspect 1. A circuit, including: a linear error amplifier coupled with an output nodeand configured to regulate a voltage at the output node based on an input reference voltage, the linear error amplifier receiving a first voltage source as a supply voltage, the linear error amplifier having a first transient response time and a first measure of accuracy; and a non-linear error amplifier coupled with the output node and receiving a second voltage source as a supply voltage to regulate the output node responsive to the voltage at the output node going below the reference voltage by a first magnitude, the non-linear error amplifier having a second transient response time that is lower than the first transient response time, and has a second measure of accuracy indicating that the non-linear amplifier is less accurate than the linear error amplifier.

[0116] Aspect 2. The circuit of any one of Aspects 1-22, wherein the non-linear error amplifier has an offset voltage equal to the first magnitude.

[0117] Aspect 3. The circuit of any one of Aspects 1-22, wherein the offset voltage is programable.

[0118] Aspect 4. The circuit of any one of Aspects 1-22, wherein the linear error amplifier includes a positive terminal coupled with the input reference voltage and a negative terminal coupled with the output node.

[0119] Aspect s. The circuit of any one of Aspects 1-22, wherein the non-linear error amplifier includes a first comparator and a pull up transistor, wherein a negative terminal of the first comparator receives the input reference voltage and a positive terminal of the first comparator is coupled with the output node, and wherein the pull up transistor is positioned between the second voltage source and the output node, and an output terminal of the first comparator is coupled to a gate terminal of the pull up transistor.

[0120] Aspect 6. The circuit of any one of Aspects 1-22, wherein the pull up transistor is a PMOS transistor.

[0121] Aspect 7. The circuit of any one of Aspects 1-22, wherein the non-linear error amplifier includes a first comparator and a pull up transistor, wherein a positive terminal of the first comparator receives the input reference voltage and a negative terminal of the first comparator is coupled with the output node, and wherein the pull up transistor is positioned between the second voltage source and the output node, and an output terminal of the first comparator is coupled to a gate terminal of the pull up transistor.

[0122] Aspect s. The circuit of any one of Aspects 1-22, wherein the pull up transistor is a NMOS transistor.

[0123] Aspect 9. The circuit of any one of Aspects 1-22, wherein the non-linear error amplifier is a first non-linear error amplifier, the circuit further including: a second non-linear error amplifier coupled with the output node and configured to reduce the voltage at the output node responsive to the voltage at the output node going above the reference voltage by a second magnitude, the second non-linear error amplifier selectively coupling the output node to a low voltage terminal or ground.

[0124] Aspect 10. The circuit of any one of Aspects 1-22, wherein the second nonlinear error amplifier includes a second comparator and a pull down transistor.

[0125] Aspect 11. The circuit of any one of Aspects 1-22, wherein the second comparator has an offset voltage equal to the second magnitude.

[0126] Aspect 12. The circuit of any one of Aspects 1-22, wherein the offset voltage of the second comparator is programable.

[0127] Aspect 13. The circuit of any one of Aspects 1-22, wherein a positive terminal of the second comparator is coupled with the output node and a negative terminal of the second comparator receives the input reference voltage, and wherein the pull down transistor is positioned between the output node and the low voltage terminal or ground and an output terminal of the second comparator is coupled to a gate terminal of the pull down transistor.

[0128] Aspect 14. The circuit of any one of Aspects 1-22, wherein the pull down transistor is a NMOS transistor.

[0129] Aspect 15. The circuit of any one of Aspects 1-22, wherein a positive terminal of the second comparator receives the input reference voltage and a negative terminal of the second comparator is coupled with the output node, and wherein the pull down transistor is positioned between the output node and the low voltage terminal or ground and an output terminal of the second comparator is coupled to a gate terminal of the pull down transistor.

[0130] Aspect 16. The circuit of any one of Aspects 1-22, wherein the pull down transistor is a PMOS transistor.

[0131] Aspect 17. The circuit of any one of Aspects 1-22, wherein the linear error amplifier includes at least two amplifier stages, an output of a last amplifier stage of the at least two amplifier stages coupled with the output node and at least one amplifier stage preceding the last amplifier stage generating a differential signal corresponding to a difference between the voltage at the output node and the input reference voltage, wherein input terminals of both the first non-linear error amplifier and the second non-linear erroramplifier are coupled to the differential signal.

[0132] Aspect 18. The circuit of any one of Aspects 1-22, wherein the linear error amplifier includes at least two amplifier stages, an output of a last amplifier stage of the at least two amplifier stages coupled with the output node and at least one amplifier stage preceding the last amplifier stage generating a differential signal corresponding to a difference between the voltage at the output node and the input reference voltage, wherein input terminals of both the first non-linear error amplifier and the second nonlinear error amplifier are coupled to the differential signal.

[0133] Aspect 19. The circuit of any one of Aspects 1-22, further including: a voltage selection circuit, with a plurality of input terminals coupled with a plurality of voltages and an output terminal coupled with the second voltage, the voltage selection circuit configured to select the second voltage source from the plurality of voltage sources, each of the plurality of second voltage sources having a different voltage, the second voltage source providing a voltage that is nearest in value to the input reference voltage.

[0134] Aspect 20. The circuit of any one of Aspects 1-22, further including: a compute in-memory array (CIMA) including a plurality of rows of bit-cells, each bit-cell of the plurality of rows of bit-cells computing a portion of a compute in-memory operation, the plurality of rows of bit-cells being provided the output node voltage; and an output node switch positioned between the output node and the CIMA, the output node switch configured to close prior to the compute in-memory operation in the CIMA.

[0135] Aspect 21. The circuit of any one of Aspects 1-22, wherein the output node switch is switched periodically between an on state and an off state based on a switching duration, wherein the non-linear error amplifier and the linear amplifier are configured to settle the voltage at the output node within the switching duration subsequent to output node switching to the on state.

[0136] Aspect 22. The circuit of any one of Aspects 1-21, wherein the switching duration is between 0.1 ns and 1ms.

[0137] Aspect 23. A method for providing a reference voltage at an output node, including: regulating a voltage at an output node using a linear error amplifier coupled with the output node, the linear error amplifier regulating the voltage at the output node based on an input reference voltage, the linear error amplifier receiving a first voltage source as a supply voltage, the linear error amplifier having a first transient response time and a first measure of accuracy; and responsive to the voltage at the output node going below the reference voltage by a first magnitude, regulating the voltage at the output nodeusing a non-linear voltage regulator coupled with the output node, the non-linear error amplifier receiving a second voltage source as a supply voltage, the non-linear error amplifier having a second transient response time that is lower the first transient response time and a second measure of accuracy indicating that the non-linear amplifier is less accurate than the linear error amplifier.

[0138] Aspect 24. The method of any one of Aspects 23-42, wherein the non-linear voltage regulator has an offset voltage equal to the first magnitude.

[0139] Aspect 25. The method of any one of Aspects 23-42, further including: programming the offset voltage into the non-linear voltage regulator.

[0140] Aspect 26. The method of any one of Aspects 23-42, wherein the linear error amplifier includes a positive terminal coupled with the input reference voltage and a negative terminal coupled with the output node.

[0141] Aspect 27. The method of any one of Aspects 23-42, wherein the non-linear error amplifier includes a first comparator and a first pull up transistor, wherein a negative terminal of the first comparator receives the input reference voltage and a positive terminal of the first comparator is coupled with the output node, and wherein the pull up transistor is positioned between the second voltage source and the output node, and an output terminal of the first comparator is coupled with a gate terminal of the pull up transistor.

[0142] Aspect 28. The method of any one of Aspects 23-42, wherein the pull up transistor is a PMOS transistor.

[0143] Aspect 29. The method of any one of Aspects 23-42, wherein the non-linear error amplifier includes a first comparator and a pull up transistor, wherein a positive terminal of the first comparator receives the input reference voltage and a negative terminal of the first comparator is coupled with the output node, and wherein the pull up transistor is positioned between the second voltage source and the output node, and an output terminal of the first comparator is coupled to a gate terminal of the pull up transistor.

[0144] Aspect 30. The method of any one of Aspects 23-42, wherein the pull up transistor is a NMOS transistor.

[0145] Aspect 31. The method of any one of Aspects 23-42, wherein the non-linear error amplifier is a first non-linear error amplifier, the method further including; responsive to the voltage at the output node exceeding the reference voltage by a second magnitude, reducing the voltage at the output node using a second non-linear erroramplifier coupled with the output node, the second non-linear error amplifier selectively coupling the output node to low voltage terminal or ground.

[0146] Aspect 32. The method of any one of Aspects 23-42, wherein the second nonlinear error amplifier includes a second comparator and a pull down transistor, wherein a positive terminal of the second comparator is coupled with the output node and a negative terminal of the second comparator receives the input reference voltage, and wherein the second switch is positioned between the output node and the low voltage terminal or ground and an output terminal of the second comparator is coupled with a gate terminal of the pull down transistor.

[0147] Aspect 33. The method of any one of Aspects 23-42, wherein the pull down transistor is a NMOS transistor.

[0148] Aspect 34. The method of any one of Aspects 23-42, wherein the second nonlinear error amplifier includes a second comparator and a pull down transistor, wherein a positive terminal of the second comparator receives the input reference voltage and a negative terminal of the second comparator is coupled with the output node, and wherein the pull down transistor is positioned between the output node and the low voltage terminal or ground and an output terminal of the second comparator is coupled to a gate terminal of the pull down transistor.

[0149] Aspect 35. The method of any one of Aspects 23-42, wherein the pull down transistor is a PMOS transistor.

[0150] Aspect 36. The method of any one of Aspects 23-42, wherein the linear error amplifier includes at least two amplifier stages, an output of a last amplifier stage of the at least two amplifier stages coupled with the output node and at least one amplifier stage preceding the last amplifier stage generating a differential signal corresponding to a difference between the voltage at the output node and the input reference voltage, wherein input terminals of both the first non-linear error amplifier and the second non-linear error amplifier are coupled to the differential signal.

[0151] Aspect 37. The method of any one of Aspects 23-42, wherein the linear error amplifier includes at least two amplifier stages, an output of a last amplifier stage of the at least two amplifier stages coupled with the output node and at least one amplifier stage preceding the last amplifier stage generating a differential signal corresponding to a difference between the voltage at the output node and the input reference voltage, wherein input terminals of both the first non-linear error amplifier and the second non-linear error amplifier are coupled to the differential signal.

[0152] Aspect 38. The method of any one of Aspects 23-42, wherein the second nonlinear error amplifier has an offset voltage equal to the second magnitude.

[0153] Aspect 39. The method of any one of Aspects 23-42, wherein the offset voltage is programable.

[0154] Aspect 40. The method of any one of Aspects 23-42, further including: periodically switching an output node switch based on a switching duration, the output node switch coupled between the output node and a compute in-memory array (CIMA) including a plurality of rows of bit-cells, each bit-cell of the plurality of bit-cells computing a portion of a compute in-memory operation, the plurality of rows of bit-cells being provided the output node voltage.

[0155] Aspect 41. The method of any one of Aspects 23-42, wherein the non-linear voltage regulator and the linear amplifier are configured to settle the voltage at the output node within the switching duration subsequent to switching the output node switch to a on state that couples the output node with the plurality of rows of bit-cells.

[0156] Aspect 42. The method of any one of Aspects 23-41, wherein the switching duration is between 0.1 ns and 1 ms, between 0.1 ns and 1 ns, between 1 ns and 10 ns, between 10 ns and 100 ns, between 1000 ns and 0.01 ms, between 0.01 ms and 0.1 ms, or between 0.1 ms and 1 ms.

[0157] Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein.

Claims

CLAIMSWhat is claimed is:

1. A circuit, comprising: a linear error amplifier coupled with an output node and configured to regulate a voltage at the output node based on an input reference voltage, the linear error amplifier receiving a first voltage source as a supply voltage, the linear error amplifier having a first transient response time and a first measure of accuracy; and a non-linear error amplifier coupled with the output node and receiving a second voltage source as a supply voltage to regulate the output node responsive to the voltage at the output node going below the reference voltage by a first magnitude, the non-linear error amplifier having a second transient response time that is lower than the first transient response time, and has a second measure of accuracy indicating that the non-linear amplifier is less accurate than the linear error amplifier.

2. The circuit of claim 1, wherein the non-linear error amplifier has an offset voltage equal to the first magnitude.

3. The circuit of claim 2, wherein the offset voltage is programable.

4. The circuit of claim 1, wherein the linear error amplifier includes a positive terminal coupled with the input reference voltage and a negative terminal coupled with the output node.

5. The circuit of claim 1, wherein the non-linear error amplifier includes a first comparator and a pull up transistor, wherein a negative terminal of the first comparator receives the input reference voltage and a positive terminal of the first comparator is coupled with the output node, and wherein the pull up transistor is positioned between the second voltage source and the output node, and an output terminal of the first comparator is coupled to a gate terminal of the pull up transistor.

6. The circuit of claim 5, wherein the pull up transistor is a PMOS transistor.

7. The circuit of claim 1, wherein the non-linear error amplifier includes a first comparator and a pull up transistor, wherein a positive terminal of the first comparator receives the input reference voltage and a negative terminal of the first comparator is coupled with the output node, and wherein the pull up transistor is positioned between the second voltage source and the output node, and an output terminal of the first comparator is coupled to a gate terminal of the pull up transistor.

8. The circuit of claim 7, wherein the pull up transistor is a NMOS transistor.

9. The circuit of claim 1, wherein the non-linear error amplifier is a first non-linear error amplifier, the circuit further comprising: a second non-linear error amplifier coupled with the output node and configured to reduce the voltage at the output node responsive to the voltage at the output node going above the reference voltage by a second magnitude, the second non-linear error amplifier selectively coupling the output node to a low voltage terminal or ground.

10. The circuit of claim 9, wherein the second non-linear error amplifier comprises a second comparator and a pull down transistor.

11. The circuit of claim 10, wherein the second comparator has an offset voltage equal to the second magnitude.

12. The circuit of claim 11, wherein the offset voltage of the second comparator is programable.

13. The circuit of claim 10, wherein a positive terminal of the second comparator is coupled with the output node and a negative terminal of the second comparator receives the input reference voltage, and wherein the pull down transistor is positioned between the output node and the low voltage terminal or ground and an output terminal of the second comparator is coupled to a gate terminal of the pull down transistor.

14. The circuit of claim 13, wherein the pull down transistor is a NMOS transistor.

15. The circuit of claim 10, wherein a positive terminal of the second comparator receives the input reference voltage and a negative terminal of the second comparator is coupled with the output node, and wherein the pull down transistor is positioned between the output node and the low voltage terminal or ground and an output terminal of the second comparator is coupled to a gate terminal of the pull down transistor.

16. The circuit of claim 15, wherein the pull down transistor is a PMOS transistor.

17. The circuit of claim 13, wherein the linear error amplifier includes at least two amplifier stages, an output of a last amplifier stage of the at least two amplifier stages coupled with the output node and at least one amplifier stage preceding the last amplifier stage generating a differential signal corresponding to a difference between the voltage at the output node and the input reference voltage, wherein input terminals of both the first non-linear error amplifier and the second non-linear error amplifier are coupled to the differential signal.

18. The circuit of claim 15, wherein the linear error amplifier includes at least two amplifier stages, an output of a last amplifier stage of the at least two amplifier stages coupled with the output node and at least one amplifier stage preceding the last amplifier stage generating a differential signal corresponding to a difference between the voltage at the output node and the input reference voltage, wherein input terminals of both the first non-linear error amplifier and the second non-linear error amplifier are coupled to the differential signal.

19. The circuit of claim 1, further comprising: a voltage selection circuit, with a plurality of input terminals coupled with a plurality of voltages and an output terminal coupled with the second voltage, the voltage selection circuit configured to select the second voltage source from the plurality of voltage sources, each of the plurality of second voltage sources having a different voltage, the second voltage source providing a voltage that is nearest in value to the input reference voltage.

20. The circuit of claim 1, further comprising:a compute in-memory array (CIMA) including a plurality of rows of bit-cells, each bit-cell of the plurality of rows of bit-cells computing a portion of a compute in-memory operation, the plurality of rows of bit-cells being provided the output node voltage; and an output node switch positioned between the output node and the CIMA, the output node switch configured to close prior to the compute in-memory operation in the CIMA.

21. The circuit of claim 20, wherein the output node switch is switched periodically between an on state and an off state based on a switching duration, wherein the non-linear error amplifier and the linear amplifier are configured to settle the voltage at the output node within the switching duration subsequent to output node switching to the on state.

22. The circuit of claim 21, wherein the switching duration is between 0.1 ns and 1ms.

23. A method for providing a reference voltage at an output node, comprising: regulating a voltage at an output node using a linear error amplifier coupled with the output node, the linear error amplifier regulating the voltage at the output node based on an input reference voltage, the linear error amplifier receiving a first voltage source as a supply voltage, the linear error amplifier having a first transient response time and a first measure of accuracy; and responsive to the voltage at the output node going below the reference voltage by a first magnitude, regulating the voltage at the output node using a non-linear voltage regulator coupled with the output node, the non-linear error amplifier receiving a second voltage source as a supply voltage, the non-linear error amplifier having a second transient response time that is lower the first transient response time and a second measure of accuracy indicating that the non-linear amplifier is less accurate than the linear error amplifier.

24. The method of claim 23, wherein the non-linear voltage regulator has an offset voltage equal to the first magnitude.

25. The method of claim 24, further comprising: programming the offset voltage into the non-linear voltage regulator.

26. The method of claim 23, wherein the linear error amplifier includes a positive terminal coupled with the input reference voltage and a negative terminal coupled with the output node.

27. The method of claim 23, wherein the non-linear error amplifier includes a first comparator and a first pull up transistor, wherein a negative terminal of the first comparator receives the input reference voltage and a positive terminal of the first comparator is coupled with the output node, and wherein the pull up transistor is positioned between the second voltage source and the output node, and an output terminal of the first comparator is coupled with a gate terminal of the pull up transistor.

28. The method of claim 27, wherein the pull up transistor is a PMOS transistor.

29. The method of claim 23, wherein the non-linear error amplifier includes a first comparator and a pull up transistor, wherein a positive terminal of the first comparator receives the input reference voltage and a negative terminal of the first comparator is coupled with the output node, and wherein the pull up transistor is positioned between the second voltage source and the output node, and an output terminal of the first comparator is coupled to a gate terminal of the pull up transistor.

30. The method of claim 29, wherein the pull up transistor is a NMOS transistor.

31. The method of claim 23, wherein the non-linear error amplifier is a first non-linear error amplifier, the method further comprising; responsive to the voltage at the output node exceeding the reference voltage by a second magnitude, reducing the voltage at the output node using a second non-linear error amplifier coupled with the output node, the second non-linear error amplifier selectively coupling the output node to low voltage terminal or ground.

32. The method of claim 31, wherein the second non-linear error amplifier includes a second comparator and a pull down transistor, wherein a positive terminal of the second comparator is coupled with the output node and a negative terminal of the second comparator receives the input reference voltage, and wherein a second switch ispositioned between the output node and the low voltage terminal or ground and an output terminal of the second comparator is coupled with a gate terminal of the pull down transistor.

33. The method of claim 32, wherein the pull down transistor is a NMOS transistor.

34. The method of claim 31, wherein the second non-linear error amplifier includes a second comparator and a pull down transistor, wherein a positive terminal of the second comparator receives the input reference voltage and a negative terminal of the second comparator is coupled with the output node, and wherein the pull down transistor is positioned between the output node and the low voltage terminal or ground and an output terminal of the second comparator is coupled to a gate terminal of the pull down transistor.

35. The method of claim 34, wherein the pull down transistor is a PMOS transistor.

36. The method of claim 32, wherein the linear error amplifier includes at least two amplifier stages, an output of a last amplifier stage of the at least two amplifier stages coupled with the output node and at least one amplifier stage preceding the last amplifier stage generating a differential signal corresponding to a difference between the voltage at the output node and the input reference voltage, wherein input terminals of both the first non-linear error amplifier and the second non-linear error amplifier are coupled to the differential signal.

37. The method of claim 34, wherein the linear error amplifier includes at least two amplifier stages, an output of a last amplifier stage of the at least two amplifier stages coupled with the output node and at least one amplifier stage preceding the last amplifier stage generating a differential signal corresponding to a difference between the voltage at the output node and the input reference voltage, wherein input terminals of both the first non-linear error amplifier and the second non-linear error amplifier are coupled to the differential signal.

38. The method of claim 31, wherein the second non-linear error amplifier has an offset voltage equal to the second magnitude.

39. The method of claim 38, wherein the offset voltage is programable.

40. The method of claim 23, further comprising: periodically switching an output node switch based on a switching duration, the output node switch coupled between the output node and a compute in-memory array (CIMA) including a plurality of rows of bit-cells, each bit-cell of the plurality of bit-cells computing a portion of a compute in-memory operation, the plurality of rows of bit-cells being provided the output node voltage.

41. The method of claim 40, wherein the non-linear voltage regulator and the linear amplifier are configured to settle the voltage at the output node within the switching duration subsequent to switching the output node switch to a on state that couples the output node with the plurality of rows of bit-cells.

42. The method of claim 40, wherein the switching duration is between 0.1 ns and 1 ms.

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