Semiconductor structure and manufacturing method therefor

Abstract

Disclosed are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: first doped structures each having a first portion, a second portion, and a third portion sequentially arranged in a first direction; second doped structures and third doped structures arranged at intervals, wherein each second doped structure is in contact with and connected to a corresponding first portion, each third doped structure is in contact with and connected to a corresponding third portion, and two adjacent first doped structures in a second direction are in contact with and connected to a same third doped structure; and gate structures each having a first surface and a second surface which are opposite in the second direction, wherein at least the first surface is in contact with and connected to a corresponding second portion, and the second direction intersects the first direction.

Description

Semiconductor structure and method for manufacturing the same

[0001] Cross-references

[0002] This application claims priority to Chinese patent application entitled “Semiconductor Structure and Method for Manufacturing Same” filed on December 12, 2023, application number 202311708789.1, which is incorporated herein by reference in its entirety. Technical Field

[0003] Dynamic Random Access Memory (DRAM) is a memory component used to store programs and various data. DRAM typically consists of capacitors and transistors connected to them. The capacitors store the charge that represents the stored programs and data, while the transistors act as switches that control the flow of charge into and out of the capacitors. When writing data, the word line is high, turning on the transistor and allowing the bit line to charge the capacitor. When reading data, the word line is also high, turning on the transistor and discharging the capacitor, allowing the bit line to receive the read signal.

[0004] However, with the continuous advancement of semiconductor fabrication processes, semiconductor process nodes continue to shrink, resulting in a gradual reduction in the size of various functional structures within the semiconductor structure, as well as a gradual decrease in the spacing between these functional structures. For example, the reduced spacing between a capacitor and a bit line located on the same side of a transistor can increase the coupling effect between the capacitor and the bit line, thereby degrading the electrical performance of the semiconductor structure. Background Art

[0005] Common dynamic random access memory (DRAM) is a 1T1C type, where a single transistor source or drain is electrically connected to a capacitor to form a single memory cell. This structure uses capacitors to store data, but reading data consumes the capacitor's charge, and the capacitor itself leaks electricity, requiring constant refreshing. This results in high DRAM power consumption and unstable electrical performance. Furthermore, the large area required to manufacture the capacitor makes scaling down the capacitor challenging.

[0006] To overcome the difficulties brought by capacitors, capacitor-free memory cell structures are used, but the electrical performance of capacitor-free memory cell structures remains to be studied.

[0007] Summary of the Invention

[0008] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial to improving the electrical performance of the semiconductor structure.

[0009] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a semiconductor structure, including: a first doping structure, having a first part, a second part and a third part arranged in sequence along a first direction; a second doping structure and a third doping structure arranged at intervals, the second doping structure is in contact and connected with the first part, and the third doping structure is in contact and connected with the third part; wherein the first doping structure is doped with one of N-type doping ions and P-type doping ions, the second doping structure and the third doping structure are doped with the other of N-type doping ions and P-type doping ions, and two adjacent first doping structures along the second direction are in contact and connected with the same third doping structure, and the second direction intersects with the first direction; a gate structure, having a first surface and a second surface opposite to each other along the second direction, and at least the first surface or the second surface is in contact and connected with the second part.

[0010] In some embodiments, only the first side or only the second side of the gate structure is in contact with the second portion.

[0011] In some embodiments, the gate structure has a third surface and a fourth surface opposite to each other along the first direction, at least a portion of the third surface is also in contact with the second portion, and at least a portion of the fourth surface is also in contact with the second portion.

[0012] In some embodiments, the gate structure has a third surface and a fourth surface opposite to each other along the first direction, and the second surface and the fourth surface are also in contact with and connected to the second portion.

[0013] In some embodiments, the semiconductor structure further includes: an isolation layer in contact with the third surface, and both the isolation layer and the gate structure are embedded in the first doping structure.

[0014] In some embodiments, the semiconductor structure further includes: an active area, the active area including two first doping structures adjacent to each other along the second direction, and the two gate structures contacting and connected to the two first doping structures are spaced apart from each other and are both located in the active area.

[0015] In some embodiments, at least a portion of the second doped structure is embedded in the first portion, and / or at least a portion of the third doped structure is embedded in the third portion.

[0016] In some embodiments, a plurality of the first doping structures and a plurality of the second doping structures are arranged at intervals along a third direction, and the first doping structures, the second doping structures and the gate structures arranged at intervals along the third direction are all in one-to-one correspondence; the third doping structure extends along the third direction, and the third doping structure is in contact and connected with the plurality of the first doping structures arranged at intervals along the third direction, and the first direction, the second direction and the third direction intersect with each other.

[0017] In some embodiments, a plurality of the first doping structures, a plurality of the second doping structures and a plurality of the third doping structures are arranged at intervals along the third direction, and the first doping structures, the second doping structures, the third doping structures and the gate structures arranged at intervals along the third direction all correspond to each other one by one; the semiconductor structure also includes: a conductive layer extending along the third direction, and the same conductive layer is in contact and connected with the plurality of the third doping structures arranged at intervals along the third direction.

[0018] In some embodiments, the semiconductor structure further includes: a first electrical connection layer, the first electrical connection layer is located on a side of the third doping structure away from the gate structure, and the first electrical connection layer extends along the third direction.

[0019] In some embodiments, the gate structure is in contact with the third doping structure.

[0020] In some embodiments, the gate structure includes: a gate dielectric layer and a gate, and the gate dielectric layer is located between the gate and the second portion.

[0021] In some embodiments, at least the gate dielectric layer is spaced between the gate and the third doping structure.

[0022] In some embodiments, at least a portion of the second doping structure is in contact with the gate dielectric layer.

[0023] In some embodiments, the semiconductor structure further includes a substrate, and the first doping structure, the second doping structure, the third doping structure and the gate structure are all located in the substrate.

[0024] According to some embodiments of the present disclosure, on the other hand, embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, comprising: providing an initial substrate; performing doping treatment on different parts of the initial substrate using different doping processes to form a first doping structure, a second doping structure and a third doping structure; wherein the first doping structure has a first part, a second part and a third part arranged in sequence along a first direction; the second doping structure and the third doping structure are arranged at intervals, the second doping structure is in contact and connected with the first part, and the third doping structure is in contact and connected with the third part; the first doping structure is doped with one of N-type doping ions and P-type doping ions, and the second doping structure and the third doping structure are doped with the other of N-type doping ions and P-type doping ions; two adjacent first doping structures along the second direction are in contact and connected with the same third doping structure, and the second direction intersects with the first direction; forming a gate structure, the gate structure having a first surface and a second surface opposite to each other along the second direction, at least the first surface is in contact and connected with the second part, and the gate structure is in contact and connected with the third doping structure.

[0025] In some embodiments, the initial substrate has a front side and a back side relative to each other along the first direction; the steps of forming the second doping structure and the third doping structure include: performing a first doping treatment on a partial area of ​​the initial substrate to form a plurality of initial first doping structures arranged at intervals, the initial first doping structure extending from the front side toward the interior of the initial substrate, and the initial first doping structure also extending along a fourth direction, the initial first doping structure having a fourth part, a fifth part and a sixth part arranged in sequence along the fourth direction; performing a second doping treatment on both the fourth part and the sixth part, along the first direction, so that the fourth part with a partial thickness is transformed into a second doping structure, and the sixth part with a partial thickness is transformed into another second doping structure, and the second doping structure extends from the front side toward the interior of the initial substrate; performing a patterning treatment on the initial substrate from the back side to expose at least a portion of the fifth part; performing a third doping treatment on the exposed fifth part to form the third doping structure.

[0026] In some embodiments, a plurality of the fifth portions are arranged at intervals along a third direction, and the first direction, the second direction and the third direction intersect with each other; the patterning of the initial substrate from the back side includes: patterning the initial substrate from the back side to form a groove extending along the third direction, and the groove exposes a plurality of the fifth portions arranged at intervals along the third direction; the third doping treatment of the exposed fifth portions includes: performing the third doping treatment on the fifth portions exposed in the groove to form the third doping structure extending along the third direction; the manufacturing method also includes: forming a first electrical connection layer, and the first electrical connection layer fills the groove.

[0027] In some embodiments, a plurality of the fifth parts are arranged at intervals along a third direction, and the first direction, the second direction and the third direction intersect with each other; the patterning of the initial substrate from the back side includes: patterning the initial substrate from the back side to form a plurality of through holes arranged at intervals along the third direction, and one of the through holes exposes the fifth part; the third doping treatment of the exposed fifth part includes: performing the third doping treatment on the fifth part exposed by the through hole to form a plurality of the third doping structures arranged at intervals along the third direction; the manufacturing method also includes: forming a conductive column, the conductive column fills the through hole, and the conductive column and the through hole correspond one to one; forming a second electrical connection layer extending along the third direction, and the same second electrical connection layer is in contact and connected with the plurality of the conductive columns arranged at intervals along the third direction.

[0028] In some embodiments, after forming the second doping structure, the manufacturing method further includes: forming a capacitor structure on the front side that is in contact with the second doping structure, and one second doping structure corresponds to one capacitor structure.

[0029] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0030] The first portion and the third portion are arranged at intervals along the first direction, the second doping structure and the third doping structure are arranged at intervals, the second doping structure is in contact with and connected to the first portion, the third doping structure is in contact with and connected to the third portion, and the second portion is located between the first portion and the third portion, and the gate structure is in contact with and connected to the second portion. In this way, the second doping structure and the third doping structure can be regarded as being located on opposite sides of the gate structure along the first direction, that is, taking a plane parallel to the first direction as a reference plane, the second doping structure and the third doping structure are not directly opposite, that is, the orthographic projections of the second doping structure and the third doping structure on the reference plane do not overlap, so as to increase the spacing between the second doping structure and the third doping structure, thereby facilitating reducing the coupling effect of the second doping structure and the third doping structure on each other. Furthermore, after the first conductive structure is formed on the side of one of the second doping structure and the third doping structure away from the gate structure and the second conductive structure is formed on the side of the other away from the gate structure, it is beneficial to avoid the first conductive structure and the second conductive structure being directly opposite, thereby facilitating reducing the coupling effect of the first conductive structure and the second conductive structure on each other, thereby improving the electrical performance of the semiconductor structure.

[0031] Furthermore, it can be understood that the first doping structure, the second doping structure, the third doping structure, and the gate structure together constitute a transistor structure, wherein the second doping structure and the third doping structure are not in direct contact, but the second doping structure and the third doping structure are respectively in contact with and connected to the first doping structure, i.e., one of the second doping structure and the third doping structure can serve as the source of the transistor structure, and the other can serve as the drain of the transistor structure, and a portion of the first doping structure can serve as the channel region of the transistor structure, and the gate structure controls whether the channel region is turned on or off. Two first doping structures adjacent to each other along the second direction are in contact with and connected to the same third doping structure, i.e., two transistor structures adjacent to each other along the second direction share a third doping structure, which is beneficial for improving the integration density of the transistor structure in the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] 1 to 4 are schematic diagrams of four partial cross-sectional structures of a semiconductor structure provided by an embodiment of the present disclosure;

[0034] FIG5 is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure;

[0035] 6 and 7 are schematic diagrams of two other partial cross-sectional structures of a semiconductor structure provided in an embodiment of the present disclosure;

[0036] 8 and 9 are two other schematic top views of the semiconductor structure provided in one embodiment of the present disclosure;

[0037] FIG10 is a schematic diagram of another partial cross-sectional structure of a semiconductor structure provided by an embodiment of the present disclosure;

[0038] 11 to 19 are schematic cross-sectional views of the structures corresponding to the steps in the method for manufacturing a semiconductor structure according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] As known from the background art, the electrical performance of semiconductor structures needs to be improved.

[0040] The present disclosure provides a semiconductor structure and a method for manufacturing the same, wherein the second doping structure and the third doping structure can be considered to be located on opposite sides of the gate structure along a first direction X, i.e., with a plane parallel to the first direction X as a reference plane, the second doping structure and the third doping structure are not directly opposite, i.e., the orthographic projections of the second doping structure and the third doping structure on the reference plane do not overlap, thereby increasing the spacing between the second doping structure and the third doping structure, thereby facilitating reducing the coupling effect of the second doping structure and the third doping structure on each other. Furthermore, when conductive structures are provided on one side of the gate structure of the second doping structure and the third doping structure, it is beneficial to avoid the two conductive structures being directly opposite each other, thereby facilitating reducing the coupling effect of the two conductive structures on each other, thereby improving the electrical performance of the semiconductor structure. Moreover, the first doping structure, the second doping structure, the third doping structure, and the gate structure together constitute a transistor structure, and two first doping structures adjacent to each other along the second direction are in contact and connected with the same third doping structure, i.e., two transistor structures adjacent to each other along the second direction share a third doping structure, thereby facilitating improving the integration density of the transistor structure in the semiconductor structure.

[0041] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0042] An embodiment of the present disclosure provides a semiconductor structure, and the semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. Figures 1 to 4 are schematic diagrams of four partial cross-sectional structures of the semiconductor structure provided by an embodiment of the present disclosure; Figure 5 is a schematic diagram of a top view structure of the semiconductor structure provided by an embodiment of the present disclosure; Figures 6 and 7 are schematic diagrams of two other partial cross-sectional structures of the semiconductor structure provided by an embodiment of the present disclosure; Figures 8 and 9 are schematic diagrams of two other top views of the semiconductor structure provided by an embodiment of the present disclosure; and Figure 10 is another schematic diagram of a partial cross-sectional structure of the semiconductor structure provided by an embodiment of the present disclosure. It should be noted that, in order to facilitate description and clearly illustrate the semiconductor structure, Figures 1 to 10 in an embodiment of the present disclosure are schematic diagrams of partial structures of the semiconductor structure.

[0043] 1 to 4 , the semiconductor structure may include: a first doping structure 101 having a first portion 111, a second portion 121, and a third portion 131 arranged in sequence along a first direction X; a second doping structure 102 and a third doping structure 103 spaced apart, the second doping structure 102 being in contact with the first portion 111, and the third doping structure 103 being in contact with the third portion 131; wherein the first doping structure 101 is doped with one of N-type doping ions and P-type doping ions, and the second doping structure 102 and the third doping structure 103 are doped with the other of N-type doping ions and P-type doping ions, and two first doping structures 101 adjacent to each other along a second direction Y are in contact with the same third doping structure 103, and the second direction Y intersects the first direction X; and a gate structure 104 having a first surface 114 and a second surface 124 opposite to each other along the second direction Y, and at least the first surface 114 or the second surface 124 being in contact with the second portion 121.

[0044] In some embodiments, the first doping structure 101 may be doped with P-type doping ions, and the second doping structure 102 and the third doping structure 103 may be doped with N-type doping ions; in other embodiments, the first doping structure 101 may be doped with N-type doping ions, and the second doping structure 102 and the third doping structure 103 may be doped with P-type doping ions.

[0045] It should be noted that, for ease of description, the following description will be made using an example in which the first doping structure 101 may be doped with P-type doping ions, and the second doping structure 102 and the third doping structure 103 may be doped with N-type doping ions.

[0046] In some embodiments, the N-type dopant ions may include at least one of arsenic ions, phosphorus ions, or antimony ions; and the P-type dopant ions may include at least one of boron ions, indium ions, or gallium ions.

[0047] It can be understood that the first doping structure 101, the second doping structure 102, the third doping structure 103 and the gate structure 104 together constitute a transistor structure, wherein the second doping structure 102 and the third doping structure 103 are not in direct contact, but the second doping structure 102 and the third doping structure 103 are respectively in contact with the first doping structure 101, that is, one of the second doping structure 102 and the third doping structure 103 can serve as the source of the transistor structure, and the other can serve as the drain of the transistor structure. Part of the first doping structure 101 can serve as the channel region of the transistor structure, and the gate structure 104 controls the conduction or shutoff of the channel region. It should be noted that for ease of description, the second doping structure 102 is used as the drain of the transistor structure, and the third doping structure 103 is used as the source of the transistor structure as an example.

[0048] Thus, two adjacent first doping structures 101 along the second direction Y are in contact with and connected to the same third doping structure 103 , that is, two adjacent transistor structures along the second direction Y share one third doping structure 103 , which is beneficial to improving the integration density of the transistor structure in the semiconductor structure.

[0049] It should be noted that, in the gate structure 104 , at least the first surface 114 is in contact with and connected to the second portion 121 . The relative positional relationship between the gate structure 104 and the second portion 121 will be described in detail later.

[0050] It can be understood that the first portion 111 and the third portion 131 are arranged at intervals along the first direction X, the second doping structure 102 and the third doping structure 103 are arranged at intervals, the second doping structure 102 is in contact with the first portion 111, the third doping structure 103 is in contact with the third portion 131, and the second portion 121 is located between the first portion 111 and the third portion 131, and the gate structure 104 is in contact with the second portion 121. In this way, the second doping structure 102 and the third doping structure 103 can be regarded as being located on opposite sides of the gate structure 104 along the first direction X, that is, with a plane parallel to the first direction X as a reference plane, the second doping structure 102 and the third doping structure 103 are not directly opposite, that is, the orthographic projections of the second doping structure 102 and the third doping structure 103 on the reference plane do not overlap, so as to increase the spacing between the second doping structure 102 and the third doping structure 103, thereby facilitating reducing the coupling effect of the second doping structure 102 and the third doping structure 103 on each other. Furthermore, when one of the second doping structure 102 and the third doping structure 103 is formed as the first conductive structure on the side away from the gate structure 104, and the other is formed as the second conductive structure on the side away from the gate structure 104, it is beneficial to avoid the first conductive structure and the second conductive structure from being directly opposite each other, thereby reducing the coupling effect of the first conductive structure and the second conductive structure on each other, thereby improving the electrical performance of the semiconductor structure.

[0051] In some embodiments, the first conductive structure may be a capacitor structure, and the second conductive structure may be a bit line structure. The bit line structure and the capacitor structure will be described in detail later.

[0052] An embodiment of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0053] 1 to 4 , the gate structure 104 may include a gate dielectric layer 154 and a gate 164, wherein the gate dielectric layer 154 is located between the gate 164 and the second portion 121. It will be appreciated that, regardless of the positional relationship between the gate 164 and the second portion 121, the gate dielectric layer 154 is always located between the gate 164 and the second portion 121.

[0054] In some embodiments, the gate dielectric layer 154 may be made of a material with a high relative dielectric constant, such as silicon oxide, hafnium oxide, or zirconium oxide.

[0055] In some embodiments, the gate 164 may be made of a metal material, such as titanium, tungsten, or copper. Alternatively, the gate 164 may be made of a compound material such as titanium nitride.

[0056] The positional relationship between the gate structure 104 and the second portion 121 includes at least the following embodiments.

[0057] In some embodiments, referring to FIG1 , only the first surface 114 of the gate structure 104 is in contact with the second portion 121. In other embodiments, still referring to FIG1 , only the second surface 124 of the gate structure 104 is in contact with the second portion 121. It is understood that, along the second direction Y, only one surface of the gate structure 104 is in contact with the second portion 121, i.e., the gate dielectric layer 154 is located on the surface of the second portion 121 and is not embedded in the second portion 121, the gate 164 is located on a side of the gate dielectric layer 154 away from the second portion 121, and the gate dielectric layer 154 is at least further located between the third doped structure 103 and the gate 164.

[0058] It should be noted that FIG1a is a schematic diagram of a partial cross-sectional structure of a semiconductor structure provided in one embodiment of the present disclosure, and FIG1b is a schematic diagram of a cross-sectional structure of the two gate structures 104 shown in FIG1a. It is understood that, depending on the relative positional relationship between the gate structure 104 and the second portion 121, the gate dielectric layer 154 in the gate structure 104 can constitute the first surface 114 or the second surface 124.

[0059] In some embodiments, with continued reference to FIG. 1 , on the basis that two first doped structures 101 adjacent along the second direction Y are in contact with the same third doped structure 103, two gate structures 104 corresponding to two second portions 121 adjacent along the second direction Y can both be located between the two second portions 121, and the two gate structures 104 can be spaced apart from each other. For example, two first doped structures 101 adjacent along the second direction Y are divided into A and B, the gate structure 104 in contact with A is considered C, and the gate structure 104 in contact with B is considered D. Along the second direction Y, C is located on the side of A closer to B, and D is located on the side of B closer to A, that is, the first surface 114 of C is in contact with the second portion 121, and the second surface 124 of D is in contact with the second portion 121.

[0060] In practical applications, along the second direction Y, while C is located on the side of A close to B, D can also be located on the side of B away from A, with only one C between A and B. In other words, in both C and D, the first surface 114 is in contact with the second portion 121 .

[0061] In other embodiments, referring to FIG2 , on the basis that the first surface 114 or the second surface 124 of the gate structure 104 is in contact and connected with the second portion 121, the gate structure 104 has a third surface 134 and a fourth surface 144 that are opposite to each other along the first direction X. At least a portion of the third surface 134 is also in contact and connected with the second portion 121, and at least a portion of the fourth surface 144 is also in contact and connected with the second portion 121. It will be understood that the gate dielectric layer 154 forms a first groove with an opening facing the second direction Y. The outer wall of the first groove is in contact and connected with the second portion 121, and the inner wall of the first groove is in contact and connected with the gate 164, and the gate 164 completely fills the first groove.

[0062] It should be noted that FIG2(2a) shows an example in which the entire third surface 134 and the entire fourth surface 144 are in contact with the second portion 121, that is, the gate structure 104 is entirely embedded in the second portion 121, and the second portion 121 exposes the first surface 114 or the second surface 124. In actual applications, it is possible that part of the third surface 134 is in contact with the second portion 121, and part of the fourth surface 144 is in contact with the second portion 121, that is, part of the gate structure 104 is embedded in the second portion 121. In addition, FIG2(2a) is another partial cross-sectional structural schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure, and FIG2(2b) is a cross-sectional structural schematic diagram of the two gate structures 104 shown in FIG2(2a).

[0063] In some embodiments, with continued reference to FIG. 2 , on the basis that two first doped structures 101 adjacent along the second direction Y are in contact with and connected to the same third doped structure 103, two gate structures 104 corresponding to two second portions 121 adjacent along the second direction Y may both be located between the two second portions 121, with the two gate structures 104 spaced apart from each other. For example, two first doped structures 101 adjacent along the second direction Y are divided into A and B, the gate structure 104 in contact with A is considered C, and the gate structure 104 in contact with B is considered D. Along the second direction Y, C is located on the side of A closer to B, and D is located on the side of B closer to A. That is, the first surface 114, at least a portion of the third surface 134, and at least a portion of the fourth surface 144 of C are all in contact with and connected to the second portion 121, and the second surface 124, at least a portion of the third surface 134, and at least a portion of the fourth surface 144 of D are all in contact with and connected to the second portion 121.

[0064] In practical applications, along the second direction Y, while C is located on the side of A closer to B, D can also be located on the side of B farther from A, with only one C between A and B. In other words, in both C and D, the first surface 114, at least a portion of the third surface 134, and at least a portion of the fourth surface 144 are in contact with and connected to the second portion 121.

[0065] In yet other embodiments, referring to FIG3 and FIG4 , on the basis that the first surface 114 or the second surface 124 of the gate structure 104 is in contact and connected with the second portion 121, the gate structure 104 has a third surface 134 and a fourth surface 144 that are opposite to each other along the first direction X. The second surface 124 and the fourth surface 144 are also in contact and connected with the second portion 121, that is, the entire gate structure 104 is embedded in the second portion 121. It will be understood that the gate dielectric layer 154 forms a second groove with an opening facing the first direction X. The outer wall of the second groove is in contact and connected with the second portion 121, and the inner wall of the second groove is in contact and connected with the gate 164, and the gate 164 completely fills the second groove.

[0066] It should be noted that 3a in FIG3 is another partial cross-sectional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure, and 3b in FIG3 is a cross-sectional structural diagram of any gate structure 104 shown in 3a.

[0067] In some embodiments, with continued reference to FIG. 3 and FIG. 4 , the semiconductor structure may further include: an isolation layer 105 in contact with the third surface 134 , and both the isolation layer 105 and the gate structure 104 are embedded in the first doped structure 101 .

[0068] In some embodiments, the isolation layer 105 may be made of dielectric materials such as silicon nitride, silicon oxynitride, or silicon carbonitride.

[0069] In some embodiments, referring to Figure 4, the semiconductor structure may further include: an active area 106, the active area 106 includes two first doped structures 101 adjacent along the second direction Y, and two gate structures 104 contacting and connected to the two first doped structures 101 are spaced apart from each other and are both located in the active area 106.

[0070] It should be noted that in Figure 4, box I and box II respectively frame the approximate areas of the two first doping structures 101 in the active area 106. In actual applications, the active area 106 is an integral structure. In order to facilitate the description of the positional relationship between different second doping structures 102, different gate structures 104 and third doping structure 103 in the active area 106, the active area 106 is divided to divide the two first doping structures 101.

[0071] It can be understood that the active area 106 including two first doped structures 101 adjacent along the second direction Y means that the two first doped structures 101 adjacent along the second direction Y are both part of the active area 106. With reference to Figures 4 and 5, one active area 106 corresponds to two second doped structures 102, two gate structures 104, and one third doped structure 103, wherein one second doped structure 102, one gate structure 104, and the third doped structure 103 constitute a transistor structure, and another second doped structure 102, another gate structure 104, and the third doped structure 103 constitute another transistor structure, that is, one active area 106 corresponds to two transistor structures.

[0072] It should be noted that 5a in FIG5 is a schematic top-view structural diagram illustrating the relative positional relationship between the active region 106 and the bitline structure BL and wordline structure WL in the semiconductor structure; 5b in FIG5 is a schematic top-view structural diagram illustrating any active region 106 shown in 5a and the two corresponding second doped structures 102; and FIG4 is a schematic partial cross-sectional structural diagram along a first cross-sectional direction AA1 of the semiconductor structure shown in 5a in FIG5 , where the first cross-sectional direction AA1 is a second direction Y, i.e., the extension direction U of the active region 106. It should be understood that the bitline structure BL and wordline structure WL depicted in FIG5 are merely intended to illustrate the relative positional relationship between the bitline structure BL, wordline structure WL, and active region 106 in a top-view diagram. FIG5 does not limit the internal structure of the bitline structure BL and wordline structure WL, nor does it limit the three-dimensional positional relationship between the bitline structure BL, wordline structure WL, and active region 106. Furthermore, to clearly illustrate the relative positional relationship between the active region 106, the bit line structure BL, and the word line structure WL in the top view, both the word line structure WL and the active region 106 are drawn in perspective. Furthermore, for ease of illustration, FIG5 does not depict the third doped structure 103 and the gate structure 104 embedded in the active region 106.

[0073] In some embodiments, a shallow trench isolation structure (not shown) is provided between adjacent active regions 106 .

[0074] In some embodiments, the bitline structure BL extends in the third direction Z, and the wordline structure WL extends in the fifth direction V. Referring to 5a in FIG5 , the plurality of active areas 106 are not only arranged in a spaced relationship along both the third direction Z and the fifth direction V, but also two adjacent groups of active areas arranged in a spaced relationship along the fifth direction V are staggered in the third direction Z. The extension direction U, the first direction X, and the second direction Y of the active areas 106 intersect with each other, and the extension direction U, the third direction Z, and the fifth direction V of the active areas 106 lie in a single plane. It is understood that the plurality of active areas 106 arranged in a spaced relationship along the third direction Z are considered a column, and along the fifth direction V, two adjacent columns are staggered, with the two columns separated by one column being arranged in the same manner.

[0075] It should be noted that in actual applications, the multiple active areas can also be arranged in an array along the third direction Z and the fifth direction V, or in other arrangements. The arrangement of the multiple active areas can be adjusted according to actual needs and is not limited here. For ease of explanation, the following detailed description uses the arrangement of the multiple active areas 106 in the arrangement shown in Figure 5a as an example.

[0076] In some embodiments, referring to FIG4 and FIG5 , the word line structure WL includes a plurality of gate structures 104 spaced apart along a third direction Z and an isolation layer 105 located on the gate structures 104. In other embodiments, the plurality of gate structures 104 spaced apart along the third direction Z may be an integral structure extending along the third direction Z, that is, the plurality of active regions 106 spaced apart along the third direction Z share one gate structure 104, and on this basis, the isolation layer 105 may also be an integral structure extending along the third direction Z.

[0077] In some embodiments, referring to Figures 1 to 4 , at least a portion of the second doped structure 102 is embedded in the first portion 111. It should be noted that Figures 1 to 4 illustrate an example in which the entire thickness of the second doped structure 102 along the first direction X is embedded in the first portion 111. In actual applications, the second doped structure 102 along a portion of the thickness along the first direction X may also be embedded in the first portion 111.

[0078] In some embodiments, referring to Figures 1 to 4 , at least a portion of the third doped structure 103 is embedded in the third portion 131. It should be noted that Figures 1 to 4 illustrate an example in which the entire thickness of the third doped structure 103 along the first direction X is embedded in the third portion 131. In actual applications, a portion of the thickness of the third doped structure 103 along the first direction X may also be embedded in the third portion 131.

[0079] It should be noted that the division of the first part 111, the second part 121 and the third part 131 in the first doping structure 101 is related to the relative positions of the second doping structure 102, the gate structure 104 and the third doping structure 103 and the first doping structure 101. The part of the first doping structure 101 that is at least in contact with the second doping structure 102 is regarded as the first part 111, the part that is at least in contact with the third doping structure 103 is regarded as the third part 131, and the remaining first doping structure 101 is regarded as the second part 121.

[0080] In some embodiments, referring to FIG. 2 to FIG. 4 , the gate structure 104 may be in contact with the third doping structure 103 .

[0081] In some embodiments, the gate structure 104 may include a gate dielectric layer 154 and a gate 164 , and the third doped structure 103 is only in contact with the gate dielectric layer 154 , that is, at least the gate dielectric layer 154 is spaced between the gate 164 and the third doped structure 103 .

[0082] In some embodiments, continuing to refer to Figures 2 to 4, on the basis that the gate 164 and the second doping structure 102 are insulated from each other and the gate 164 and the third doping structure 103 are insulated from each other, the third doping structure 103 can not only be in contact and connected with the third part 131, but also be in contact and connected with the second part 121 along the upper thickness of the first direction X.

[0083] In other embodiments, referring to Figure 6, the second doped structure 102 and the gate structure 104 correspond one to one, and the second doped structure 102 is located on the same side of the corresponding gate structure 104 along the second direction Y. For example, in Figure 6, the second doped structure 102 is located on the first side of the corresponding gate structure 104, and the two adjacent gate structures 104 with a gap are located in the same active area 106.

[0084] It should be noted that, referring to Figures 2 to 4 and 6, the gate structure 104 can not only be in contact with the second portion 121, but also, provided that the gate 164 and the second doped structure 102 are insulated from each other and the gate 164 and the third doped structure 103 are insulated from each other, the gate structure 104 can also be in contact with the first portion 111 along a portion of the thickness along the first direction X. In practical applications, the gate structure 104 can be in contact with only the second portion 121. In addition, in Figure 6, the approximate regions of the two first doped structures 101 in the active region 106 are framed by boxes I and II, respectively.

[0085] In some embodiments, referring to FIG7 , the semiconductor structure may further include: a substrate 100, a first doping structure 101, a second doping structure 102, a third doping structure 103, and a gate structure 104, all of which are located in the substrate 100. It is understood that the substrate 100 has a plurality of active regions 106 arranged at intervals, and at least a portion of the first doping structure 101, the second doping structure 102, the third doping structure 103, and the gate structure 104 are all embedded in the active regions 106.

[0086] It can be understood that, continuing to refer to Figure 7, in the same active area 106, along the second direction Y, the third doping structure 103 is located between two adjacent gate structures 104, and the two adjacent gate structures 104 are located between two adjacent second doping structures 102, so that two transistor structures share one third doping structure 103.

[0087] The third doping structure 103 is described in detail below through two embodiments.

[0088] In some embodiments, with reference to Figures 5 and 7, a plurality of first doping structures 101 and a plurality of second doping structures 102 are arranged at intervals along the third direction Z, and the first doping structures 101, the second doping structures 102 and the gate structures 104 arranged at intervals along the third direction Z all correspond to each other; the third doping structure 103 extends along the third direction Z, and a third doping structure 103 is in contact and connected with the plurality of first doping structures 101 arranged at intervals along the third direction Z, and the first direction X, the second direction Y and the third direction Z intersect with each other.

[0089] It can be understood that the first doped structure 101 is part of the active area 106. A second doped structure 102 is embedded at each end of an active area 106 along its extension direction U. The region between the two second doped structures 102 in the active area 106 that are in contact with it corresponds to a bit line structure BL and two word line structures WL. For any active area 106, the region corresponding to the word line structure WL is embedded with a gate structure 104, and the region corresponding to the bit line structure BL is embedded with a third doped structure 103. The relationship between the word line structure WL and the gate structure 104, as well as the relationship between the bit line structure BL and the third doped structure 103, will be described in detail later.

[0090] In some embodiments, referring to 5a in FIG5 , a plurality of bit line structures BL are arranged at intervals along a fifth direction V, and a plurality of word line structures WL are arranged at intervals along a third direction Z. It will be appreciated that the plurality of bit line structures BL and the plurality of word line structures WL form a plurality of rectangular windows in a top view, each of which forms a capacitor contact hole. Each capacitor contact hole exposes a second doped structure 102, and the capacitor contact hole forms a capacitor structure in contact with the second doped structure 102 based on the capacitor contact hole.

[0091] In some embodiments, referring to 5a in Figure 5, a gate structure 104 and an isolation layer 105 are embedded in the active area 106 opposite to the word line structure WL. It can be understood that the word line structure WL includes the gate structure 104 and the isolation layer 105, and the multiple active areas 106 arranged at intervals along the fifth direction V are all opposite to a part of the word line structure WL, that is, the positive projection of part of the gate structure 104 on the active area 106 coincides with the active area 106, and the multiple active areas 106 arranged at intervals along the fifth direction V share one gate structure 104.

[0092] With reference to Figures 7 and 8 , the third doping structure 103 extends along the third direction Z. It can be understood that the multiple active regions 106 spaced apart along the third direction Z are all directly opposite to a portion of the third doping structure 103, that is, the orthographic projection of a portion of the third doping structure 103 on the active region 106 coincides with the active region 106, and the multiple active regions 106 spaced apart along the third direction Z share one third doping structure 103. It should be noted that the bit line structure BL includes the third doping structure 103. In addition, the first doping structure 101 is a portion of the active region 106. A second doping structure 102 is embedded at each end of an active region 106 along its extension direction U. An active region 106 can be regarded as a basic component constituting two transistor structures, and the two transistor structures share one third doping structure 103.

[0093] In some embodiments, referring to FIG7 , the semiconductor structure may further include: a first electrical connection layer 117 , the first electrical connection layer 117 being located on a side of the third doped structure 103 away from the gate structure 104 , and the first electrical connection layer 117 extending along a third direction Z. It will be appreciated that the bit line structure BL (refer to FIG5 ) may include the first electrical connection layer 117 and the third doped structure 103 in contact with the first electrical connection layer 117 , and a bit line structure BL corresponds to a first electrical connection layer 117 and a third doped structure 103 .

[0094] It should be noted that, in order to clearly illustrate the relative positional relationship between the active region 106 and the third doping structure 103 in the top view, the active region 106 is drawn in perspective in FIG. 8 .

[0095] In other embodiments, with reference to Figures 9 and 10, a plurality of first doping structures 101, a plurality of second doping structures 102, and a plurality of third doping structures 103 are arranged at intervals along the third direction Z, and the first doping structures 101, the second doping structures 102, the third doping structures 103, and the gate structures 104 arranged at intervals along the third direction Z all correspond to each other one by one.

[0096] It is understood that the first doped structure 101 is part of the active area 106, and a second doped structure 102 is embedded at each end of the active area 106 along its extension direction U. In the top view shown in FIG9 , a gate structure 104 (see FIG7 ) is provided between the second doped structure 102 and the third doped structure 103 (see FIG7 ) corresponding to the same active area 106. It is understood that the third doped structure 103 can serve as a bit line contact layer in the bit line structure BL. It should be noted that the parts that are the same as or corresponding to the above embodiments are not repeated here.

[0097] Continuing with reference to Figures 9 and 10, the semiconductor structure may further include: a conductive layer 107 extending along a third direction Z, and the same conductive layer 107 is in contact with a plurality of third doped structures 103 arranged at intervals along the third direction Z. It can be understood that the bit line structure BL includes a plurality of third doped structures 103 arranged at intervals along the third direction Z and a conductive layer 107 in contact with the third doped structures 103. In addition, an active region 106 can be considered as a basic component constituting two transistor structures, each of which has its own second doped structure 102 and its own gate structure 104, and the two transistor structures share a third doped structure 103.

[0098] In some embodiments, referring to Figure 10, the conductive layer 107 may include: a second electrical connection layer 137 and a plurality of conductive pillars 127 that are in contact with the second electrical connection layer 137 and are arranged at intervals along the third direction Z, wherein the conductive pillars 127 and the third doping structures 103 correspond one to one, a conductive pillar 127 is in contact with a third doping structure 103, the second electrical connection layer 137 extends along the third direction Z, and the same second electrical connection layer 137 is in contact with the plurality of conductive pillars 127 arranged at intervals along the third direction Z.

[0099] In some embodiments, the orthographic projections of the conductive pillar 127 and the third doped structure 103 on the substrate 100 may overlap.

[0100] It should be noted that, in order to clearly illustrate the relative positional relationship between the active region 106 and the third doping structure 103 in the top view, the active region 106 is drawn in perspective in FIG. 9 .

[0101] In the above embodiments, referring to FIG. 7 or FIG. 10 , the semiconductor structure may further include: a capacitor structure 109 located on a side of the second doped structure 102 away from the gate structure 104; and a bit line structure BL including a third doped structure 103 located on a side of the gate structure 104 away from the capacitor structure 109. This arrangement helps prevent the capacitor structure 109 and the bit line structure BL from being directly opposite each other, thereby reducing the coupling effect between the capacitor structure 109 and the bit line structure BL, thereby improving the electrical performance of the semiconductor structure.

[0102] In some cases, at least a portion of the second doped structure 102 is in contact with the gate dielectric layer 154 in the corresponding gate structure 104 .

[0103] In summary, the second doping structure 102 and the third doping structure 103 can be considered to be located on opposite sides of the gate structure 104 along the first direction X. That is, with a plane parallel to the first direction X as a reference plane, the second doping structure 102 and the third doping structure 103 are not directly opposite each other, that is, the orthographic projections of the second doping structure 102 and the third doping structure 103 on the reference plane do not overlap, thereby increasing the spacing between the second doping structure 102 and the third doping structure 103, thereby facilitating the reduction of the coupling effect between the second doping structure 102 and the third doping structure 103. Furthermore, the capacitor structure 109 is located on the side of the second doping structure 102 away from the gate structure 104, and the bit line structure BL is located on the side of the gate structure 104 away from the capacitor structure 109, which helps avoid the capacitor structure 109 and the bit line structure BL from being directly opposite each other, thereby facilitating the reduction of the coupling effect between the capacitor structure 109 and the bit line structure BL, thereby improving the electrical performance of the semiconductor structure. In addition, two adjacent transistor structures along the second direction Y share the same third doping structure 103, which helps improve the integration density of the transistor structure in the semiconductor structure.

[0104] Another embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, which is used to form the semiconductor structure provided in the aforementioned embodiment. Figures 11 to 19 are schematic cross-sectional views corresponding to the steps in the method for manufacturing a semiconductor structure provided in another embodiment of the present disclosure. It should be noted that, in order to facilitate description and clearly illustrate the steps of the method for manufacturing a semiconductor structure, Figures 11 to 19 in this embodiment are schematic views of the partial structures of the semiconductor structure. In addition, the parts that are the same as or corresponding to the aforementioned embodiments are not repeated here.

[0105] 1 to 19 , a method for manufacturing a semiconductor structure includes: providing an initial substrate 110; performing doping treatment on different portions of the initial substrate 110 using different doping processes to form a first doping structure 101, a second doping structure 102, and a third doping structure 103; wherein the first doping structure 101 includes a first portion 111, a second portion 121, and a third portion 131 sequentially arranged along a first direction X; the second doping structure 102 and the third doping structure 103 are spaced apart, the second doping structure 102 is in contact with the first portion 111, and the third doping structure 103 is in contact with the third portion 131. ; The first doping structure 101 is doped with one of N-type doping ions and P-type doping ions, and the second doping structure 102 and the third doping structure 103 are doped with the other of N-type doping ions and P-type doping ions; the two first doping structures 101 adjacent to each other along the second direction Y are in contact with the same third doping structure 103, and the second direction Y intersects with the first direction X; a gate structure 104 is formed, and the gate structure 104 has a first surface 114 and a second surface 124 opposite to each other along the second direction Y, at least the first surface 114 is in contact with the second portion 121, and the gate structure 104 is in contact with the third doping structure 103.

[0106] It should be noted that the order of the steps of forming the second doping structure 102, the third doping structure 103, and the gate structure 104 can be adjusted, which is described in detail below. In addition, for ease of understanding, the manufacturing method is exemplified by forming the semiconductor structure shown in Figure 4. In actual applications, the various semiconductor structures in the aforementioned embodiments can be manufactured using the manufacturing method provided in another embodiment of the present disclosure.

[0107] In some embodiments, the initial substrate 110 has a front surface 120 and a back surface 130 opposite to each other along a first direction X. Referring to FIG. 11 to FIG. 19 , forming the second doping structure 102 and the third doping structure 103 may include the following steps:

[0108] 11 and 12 , a first doping treatment is performed on a partial area of ​​the initial substrate 110 to form a plurality of initial first doping structures 141 arranged at intervals. The initial first doping structure 141 extends from the front side 120 toward the interior of the initial substrate 110. The initial first doping structure 141 also extends along the fourth direction U. The initial first doping structure 141 has a fourth portion 151, a fifth portion 161, and a sixth portion 171 arranged sequentially along the fourth direction U.

[0109] It should be noted that the first doping structure 101 is subsequently formed based on the initial first doping structure 141 , and thus the initial first doping structure 141 is drawn in FIG. 11 to FIG. 19 using the same filling method as the first doping structure 101 .

[0110] In some embodiments, performing the first doping treatment on a portion of the initial substrate 110 includes doping P-type dopant ions into the portion of the initial substrate 110, so that the initial first doping structure 141 is doped with P-type dopant ions. In other embodiments, performing the first doping treatment on a portion of the initial substrate 110 includes doping N-type dopant ions into the portion of the initial substrate 110, so that the initial first doping structure 141 is doped with N-type dopant ions.

[0111] It can be understood that the initial first doping structure 141 can be regarded as the active area 106 before the second doping structure 102, the third doping structure 103 and the gate structure 104 are embedded. The orthographic projection of the initial first doping structure 141 on the top view plane coincides with the orthographic projection of the active area 106 on the top view plane, and the top view plane is a plane formed by the third direction Z and the fifth direction V.

[0112] In some embodiments, with reference to FIG11 and FIG12 , FIG11 is a schematic diagram of a partial cross-sectional structure of the semiconductor structure shown in FIG12 along the second cross-sectional direction BB1. The plurality of initial first doping structures 141 are not only arranged at intervals along both the third direction Z and the fifth direction V, but also two adjacent groups of initial first doping structures arranged at intervals along the fifth direction V are staggered in the third direction Z. The extension directions U, Z, and V of the initial first doping structures 141 intersect with each other, and the extension directions U, Z, and V of the initial first doping structures 141 are located in the same plane. It is understood that the plurality of initial first doping structures 141 arranged at intervals along the third direction Z are considered a column, and along the fifth direction V, two adjacent columns are staggered, with the two columns spaced one apart being arranged in the same manner.

[0113] It should be noted that in actual applications, the multiple initial first doping structures can also be arranged in an array along the third direction Z and the fifth direction V, or in other arrangements. The arrangement of the multiple active regions can be adjusted according to actual needs and is not limited here. For ease of explanation, the following detailed description uses the arrangement of the multiple initial first doping structures 141 shown in FIG. 12 as an example.

[0114] With reference to Figures 11 to 14, Figure 13 is a schematic diagram of a partial cross-sectional structure of the semiconductor structure shown in Figure 14 along the second cross-sectional direction BB1. A second doping treatment is performed on both the fourth portion 151 and the sixth portion 171. Along the first direction X, a portion of the thickness of the fourth portion 151 is transformed into a second doped structure 102, and a portion of the thickness of the sixth portion 171 is transformed into another second doped structure 102. The second doped structure 102 extends from the front surface 120 into the interior of the initial substrate 110.

[0115] It is understood that the two second doping structures 102 are formed from two different regions of an initial first doping structure 141, that is, the two second doping structures 102 correspond to one initial first doping structure 141. Subsequently, the third doping structure 103 and the gate structure 104 can be formed in the fifth portion 161. In addition, the types of doping ions doped in the first doping process and the second doping process are different.

[0116] In some embodiments, based on the initial doping of the first doping structure 141 with P-type dopant ions, performing the second doping treatment on the fourth portion 151 and the sixth portion 171 includes: doping N-type dopant ions into the fourth portion 151 and the sixth portion 171, so that the second doping structure 102 is doped with N-type dopant ions. In other embodiments, based on the initial doping of the first doping structure 141 with N-type dopant ions, performing the second doping treatment on the fourth portion 151 and the sixth portion 171 includes: doping P-type dopant ions into the fourth portion 151 and the sixth portion 171, so that the second doping structure 102 is doped with P-type dopant ions.

[0117] 15 and 16 or 18 and 19 , the initial substrate 110 is patterned from the back side 130 to expose at least a portion of the fifth portion 161 ; referring to FIG17 or 10 , the exposed fifth portion 161 is subjected to a third doping treatment to form a third doping structure 103 .

[0118] The steps of forming the third doping structure 103 are described in detail below through two embodiments.

[0119] 13 and 14 , the plurality of fifth portions 161 are spaced apart along the third direction Z, and the first direction X, the second direction Y, and the third direction Z intersect with each other. The second direction Y is the extension direction U of the initial first doping structure 141 .

[0120] In some embodiments, the second direction Y, the third direction Z, and the fifth direction V intersect in pairs and form a plane, and the first direction X is perpendicular to the plane.

[0121] Patterning the initial substrate 110 from the back side 130 may include the following steps:

[0122] Referring to Figures 15 and 16, Figure 15 is a schematic diagram of the local cross-sectional structure of the semiconductor structure shown in Figure 16 along the second cross-sectional direction BB1. The initial substrate 110 is patterned from the back side 130 to form a groove 108 extending along the third direction Z, and the groove 108 exposes a plurality of fifth portions 161 arranged at intervals along the third direction Z.

[0123] It should be noted that, in order to clearly illustrate the relative positional relationship between the groove 108 and the initial substrate 110 in the top view, the initial substrate 110 is drawn in perspective in FIG. 16 .

[0124] With reference to Figures 15 to 17 and Figure 8 , the step of performing a third doping treatment on the exposed fifth portion 161 may include performing the third doping treatment on the fifth portion 161 exposed by the trench 108 to form a third doping structure 103 extending along the third direction Z. It will be understood that one third doping structure 103 is in contact with and connected to the plurality of fifth portions 161 spaced apart along the third direction Z. In addition, the ion type doped in the third doping treatment is the same as that in the second doping treatment.

[0125] In some embodiments, based on the initial doping of the first doping structure 141 with P-type dopant ions, performing the third doping treatment on the exposed fifth portion 161 includes: doping N-type dopant ions into the exposed fifth portion 161, so that the third doping structure 103 is doped with N-type dopant ions. In other embodiments, based on the initial doping of the first doping structure 141 with N-type dopant ions, performing the third doping treatment on the exposed fifth portion 161 includes: doping P-type dopant ions into the exposed fifth portion 161, so that the third doping structure 103 is doped with P-type dopant ions.

[0126] With reference to FIG17 and FIG7 , the manufacturing method may further include forming a first electrical connection layer 117, wherein the first electrical connection layer 117 completely fills the trench 108. It is understood that the bit line structure BL may include the first electrical connection layer 117 and the third doping structure 103 in contact with the first electrical connection layer 117, and a bit line structure BL may correspond to a first electrical connection layer 117 and a third doping structure 103.

[0127] In other embodiments, referring to Figures 13 and 14 , a plurality of fifth portions 161 are spaced apart along the third direction Z, and the first direction X, the second direction Y, and the third direction Z intersect with each other. It should be noted that parts identical or corresponding to the above embodiments are not described in detail here.

[0128] Patterning the initial substrate 110 from the back side 130 may include the following steps:

[0129] 18 and 19 , FIG18 is a schematic diagram of a partial cross-sectional structure of the semiconductor structure shown in FIG19 along the second cross-sectional direction BB1 , and the initial substrate 110 is patterned from the back side 130 to form a plurality of through holes 118 spaced apart along the third direction Z, and a through hole 118 exposes a fifth portion 161 .

[0130] It should be noted that, in order to clearly illustrate the relative positional relationship between the through hole 118 and the initial substrate 110 in the top view, the initial substrate 110 is drawn in perspective in FIG. 19 .

[0131] With reference to FIG18 to FIG19 , FIG9 , and FIG10 , the step of performing the third doping treatment on the exposed fifth portion 161 may include performing the third doping treatment on the fifth portion 161 exposed by the through hole 118 to form a plurality of third doping structures 103 spaced apart along the third direction Z. It will be understood that one third doping structure 103 is only in contact with and connected to one fifth portion 161 , i.e., one third doping structure 103 corresponds to one fifth portion 161 .

[0132] With reference to FIG18 and FIG10 , the manufacturing method may further include forming conductive pillars 127, wherein the conductive pillars 127 completely fill the through-holes 118, with the conductive pillars 127 corresponding one to the through-holes 118. Thus, the conductive pillars 127 correspond one to one to the third doping structures 103, i.e., one conductive pillar 127 is in contact with one third doping structure 103.

[0133] 10 , a second electrical connection layer 137 extending along the third direction Z is formed. The second electrical connection layer 137 is in contact with and connected to the plurality of conductive pillars 127 spaced apart along the third direction Z.

[0134] It can be understood that the second electrical connection layer 137 and the multiple conductive pillars 127 that are in contact with the second electrical connection layer 137 and arranged at intervals along the third direction Z together constitute the conductive layer 107, and the bit line structure BL includes the conductive layer 107 and the multiple third doping structures 103 that are in contact with the conductive layer 107.

[0135] In practical applications, after the initial substrate is patterned from the back side to form multiple through-holes spaced apart along the third direction, and the fifth portion exposed by the through-holes is subjected to a third doping process to form a third doped structure, the back side of the substrate is patterned again to form a trench extending along the third direction. Each trench exposes multiple third doped structures spaced apart along the third direction, and a third electrical connection layer is formed in the trench. In this manner, the bitline structure can include a third electrical connection layer and multiple third doped structures in contact with the third electrical connection layer. It will be appreciated that after the third doped structure is formed using the through-holes, the through-holes are expanded into trenches, and the third electrical connection layer is formed in the trenches, so that the third electrical connection layer can supply power to the multiple third doped structures.

[0136] In some embodiments, with reference to FIG5 and FIG10 , the step of forming the gate structure 104 includes: patterning the fifth portion 161 (see FIG11 ) from the front surface 120 to form a second trench (not shown) extending along a fifth direction V; wherein one fifth portion 161 corresponds to two adjacent second trenches along the third direction Z; and sequentially forming the gate structure 104 and the isolation layer 105 in the second trenches. It should be noted that the manufacturing method provided in another embodiment of the present disclosure does not limit the specific process for forming the gate structure 104 and the isolation layer 105 and can be adjusted according to actual needs.

[0137] It should be noted that the step of forming the gate structure 104 may be performed before or after forming the second doping structure 102 and the third doping structure 103. In addition, after forming the second doping structure 102, the third doping structure 103, and the gate structure 104 in the initial first doping structure 141, the initial first doping structure 141 remains as the first doping structure 101.

[0138] It is understandable that after forming the second doping structure 102 , the third doping structure 103 and the gate structure 104 , the remaining initial first doping structure 141 serves as the first doping structure 101 , and the remaining initial substrate 110 serves as the substrate 100 .

[0139] In some embodiments, continuing to refer to FIG. 10 , after forming the second doping structure 102 , the manufacturing method may further include forming a capacitor structure 109 on the front side 120 that is in contact with the second doping structure 102 , with one second doping structure 102 corresponding to one capacitor structure 109 .

[0140] To sum up, in the formed semiconductor structure, the second doping structure 102 and the third doping structure 103 can be regarded as being located on opposite sides of the gate structure 104 along the first direction X, that is, taking the plane parallel to the first direction X as the reference plane, the second doping structure 102 and the third doping structure 103 are not directly opposite, that is, the orthographic projections of the second doping structure 102 and the third doping structure 103 on the reference plane do not overlap, so as to increase the spacing between the second doping structure 102 and the third doping structure 103, thereby helping to reduce the coupling influence of the second doping structure 102 and the third doping structure 103 on each other. Furthermore, the capacitor structure 109 is located on the side of the second doping structure 102 away from the gate structure 104, and the bit line structure BL is located on the side of the gate structure 104 away from the capacitor structure 109, which is beneficial to avoid the capacitor structure 109 and the bit line structure BL from being directly opposite, thereby helping to reduce the coupling influence of the capacitor structure 109 and the bit line structure BL on each other, thereby improving the electrical performance of the semiconductor structure. In addition, two transistor structures adjacent to each other along the second direction Y share a third doping structure 103 , which is beneficial for improving the integration density of the transistor structures in the semiconductor structure.

[0141] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure, comprising: The first doping structure (101) has a first portion (111), a second portion (121), and a third portion (131) arranged in sequence along a first direction (X); The second doping structure (102) and the third doping structure (103) are spaced apart. The second doping structure (102) is in contact connection with the first portion (111), and the third doping structure (103) is in contact connection with the third portion (131); Wherein, one of N-type doping ions and P-type doping ions is doped in the first doping structure (101), and the other of N-type doping ions and P-type doping ions is doped in the second doping structure (102) and the third doping structure (103). Two adjacent first doping structures (101) along a second direction (Y) are in contact connection with the same third doping structure (103). The second direction (Y) intersects with the first direction (X); The gate structure (104) has a first surface (114) and a second surface (124) opposite to each other along the second direction (Y). At least the first surface (114) or the second surface (124) is in contact connection with the second portion (121).

2. The semiconductor structure according to claim 1, wherein, Only the first surface (114) or only the second surface (124) of the gate structure (104) is in contact connection with the second portion (121).

3. The semiconductor structure according to claim 2, wherein, The gate structure (104) has a third surface (134) and a fourth surface (144) opposite to each other along the first direction (X). At least part of the third surface (134) is also in contact connection with the second portion (121), and at least part of the fourth surface (144) is also in contact connection with the second portion (121).

4. The semiconductor structure according to claim 2, wherein, The gate structure (104) has a third surface (134) and a fourth surface (144) opposite to each other along the first direction (X). The second surface (124) and the fourth surface (144) are also in contact connection with the second portion (121).

5. The semiconductor structure according to claim 4, further comprising: The isolation layer (105) is in contact connection with the third surface (134), and both the isolation layer (105) and the gate structure (104) are embedded in the first doping structure (101).

6. The semiconductor structure according to claim 4, further comprising: The active region (106) includes two first doping structures (101) adjacent to each other along the second direction (Y). The two gate structures (104) in contact connection with the two first doping structures (101) are spaced apart from each other and are both located in the active region (106).

7. The semiconductor structure according to any one of claims 1 to 6, wherein, At least part of the second doping structure (102) is embedded in the first portion (111), and / or at least part of the third doping structure (103) is embedded in the third portion (131).

8. The semiconductor structure according to any one of claims 1 to 6, wherein, A plurality of the first doping structures (101) and a plurality of the second doping structures (102) are arranged at intervals along a third direction (Z). The first doping structures (101), the second doping structures (102), and the gate structures (104) arranged at intervals along the third direction (Z) are in one-to-one correspondence. The third doping structure (103) extends along the third direction (Z). One third doping structure (103) is in contact connection with a plurality of the first doping structures (101) arranged at intervals along the third direction (Z). The first direction (X), the second direction (Y), and the third direction (Z) intersect pairwise.

9. The semiconductor structure according to any one of claims 1 to 6, wherein, A plurality of the first doping structures (101), a plurality of the second doping structures (102), and a plurality of the third doping structures (103) are arranged at intervals along a third direction (Z). The first doping structures (101), the second doping structures (102), the third doping structures (103), and the gate structures (104) arranged at intervals along the third direction (Z) are in one-to-one correspondence. The semiconductor structure further includes: a conductive layer (107) extending along the third direction (Z), and the same conductive layer (107) is in contact connection with a plurality of the third doping structures (103) arranged at intervals along the third direction (Z).

10. The semiconductor structure according to any one of claims 1 to 6, further comprising: A first electrical connection layer (117), the first electrical connection layer (117) is located on a side of the third doping structure (103) away from the gate structure (104), and the first electrical connection layer (117) extends along the third direction (Z).

11. The semiconductor structure according to any one of claims 1 to 6, wherein, The gate structure (104) is in contact connection with the third doping structure (103).

12. The semiconductor structure according to claim 11, wherein, The gate structure (104) includes: a gate dielectric layer (154) and a gate (164), and the gate dielectric layer (154) is located between the gate (164) and the second part (121).

13. The semiconductor structure according to claim 12, wherein, At least the gate dielectric layer (154) is provided between the gate (164) and the third doping structure (103).

14. The semiconductor structure according to claim 12, wherein, At least a partial region of the second doping structure (102) is in contact connection with the gate dielectric layer (154).

15. The semiconductor structure according to claim 1, further comprising: A substrate (100), the first doping structure (101), the second doping structure (102), the third doping structure (103), and the gate structure (104) are all located in the substrate (100).

16. A method for manufacturing a semiconductor structure, comprising: Provide an initial substrate (110); Use different doping processes to perform doping treatments on different parts of the initial substrate (110) to form a first doping structure (101), a second doping structure (102), and a third doping structure (103). Among them, the first doping structure (101) has a first part (111), a second part (121), and a third part (131) arranged in sequence along a first direction (X); the second doping structure (102) and the third doping structure (103) are arranged at intervals, the second doping structure (102) is in contact connection with the first part (111), and the third doping structure (103) is in contact connection with the third part (131); one of N-type doping ions and P-type doping ions is doped in the first doping structure (101), and the other of N-type doping ions and P-type doping ions is doped in the second doping structure (102) and the third doping structure (103); two adjacent first doping structures (101) along a second direction (Y) are in contact connection with the same third doping structure (103), and the second direction (Y) intersects with the first direction (X). A gate structure (104) is formed. The gate structure (104) has a first surface (114) and a second surface (124) opposite to each other along the second direction (Y). At least the first surface (114) is in contact connection with the second part (121), and the gate structure (101) is in contact connection with the third doping structure (103).

17. The manufacturing method according to claim 16, wherein, The initial substrate (110) has a front surface (120) and a back surface (130) opposite to each other along the first direction (X); the steps of forming the second doping structure (102) and the third doping structure (103) include: Performing a first doping process on a partial region of the initial substrate (110) to form a plurality of initial first doping structures (141) arranged at intervals. The initial first doping structures (141) extend from the front surface (120) into the initial substrate (110), and the initial first doping structures (141) also extend along a fourth direction (U). The initial first doping structure (141) has a fourth part (151), a fifth part (161), and a sixth part (171) arranged in sequence along the fourth direction (U). Performing a second doping process on both the fourth part (151) and the sixth part (171). Along the first direction (X), such that a partial thickness of the fourth part (151) is transformed into one second doping structure (102), and a partial thickness of the sixth part (171) is transformed into another second doping structure (102). The second doping structure (102) extends from the front surface (120) into the initial substrate (110). Performing a patterning process on the initial substrate (110) from the back surface (130) to expose at least a part of the fifth part (161). Performing a third doping process on the exposed fifth part (161) to form the third doping structure (103).

18. The manufacturing method according to claim 17, wherein, A plurality of the fifth parts (161) are arranged at intervals along a third direction (Z). The first direction (X), the second direction (Y), and the third direction (Z) intersect pairwise. Patterning the initial substrate (110) from the back surface (130) includes: Patterning the initial substrate (110) from the back surface (130) to form trenches (108) extending along the third direction (Z), and the trenches (108) expose a plurality of the fifth portions (161) spaced apart along the third direction (Z); The third doping process for the exposed fifth portion (161) includes: Performing the third doping process on the fifth portion (161) exposed by the trenches (108) to form the third doping structure (103) extending along the third direction (Z); The manufacturing method further includes: forming a first electrical connection layer (117), and the first electrical connection layer (117) fills the trenches (108).

19. The manufacturing method according to claim 17, wherein, A plurality of the fifth portions (161) are spaced apart along the third direction (Z), and the first direction (X), the second direction (Y), and the third direction (Z) intersect pairwise; Patterning the initial substrate (110) from the back surface (130) includes: Patterning the initial substrate (110) from the back surface (130) to form a plurality of through holes (118) spaced apart along the third direction (Z), and one through hole (118) exposes one fifth portion (161); The third doping process for the exposed fifth portion (161) includes: Performing the third doping process on the fifth portion (161) exposed by the through holes (118) to form a plurality of the third doping structures (103) spaced apart along the third direction (Z); The manufacturing method further includes: forming conductive posts (127), the conductive posts (127) fill the through holes (118), and the conductive posts (127) and the through holes (118) are in one-to-one correspondence; Forming a second electrical connection layer (137) extending along the third direction (Z), and the same second electrical connection layer (137) is in contact connection with a plurality of the conductive posts (117) spaced apart along the third direction (Z).

20. The manufacturing method according to claim 17, wherein, After forming the second doping structure (102), it further includes; forming a capacitor structure (109) in contact connection with the second doping structure (102) on the front surface (120), and one second doping structure (102) and one capacitor structure (109) correspond.

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