Cryogenic quasi-static embedded dram for high-energy-efficiency computing-in-memory

Abstract

Disclosed in the present invention is a cryogenic quasi-static embedded DRAM for high-energy-efficiency computing-in-memory. An cryogenic quasi-static embedded DRAM array is composed of four-transistor transmission gate gain cell (4T TGGC) memory cells; each 4TTGGC memory cell is composed of a PMOS transistor P1 and three NMOS transistors N1, N2 and N3. According to a cryogenic 4T TGGC topology provided by the present invention, the advantages of the cryogenic 4T TGGC topology in the aspects of reducing leakage and line transmission delay are fully used so as to achieve a quasi-static storage operation at a low temperature. In addition, the present invention uses a cryogenic write bitline (WBL) biasing technique and a dedicated readout circuit to optimize the power consumption of a read-write operation.

Description

Low-Temperature Quasi-Static Embedded DRAM for High-Energy-Efficient In-Memory Computing Technical Field The present invention relates to a low-temperature quasi-static embedded memory design. Background Art Over time, the logic-memory gap has been continuously expanding, and memory access has become the main bottleneck of computing performance in data-intensive applications [1-2]. A promising solution is in-memory computing (CIM), which is commonly used to mitigate the overhead between the processing unit and storage due to data transmission [3-4]. Generally, to achieve energy-efficient CIM, the storage design needs to meet the requirements of high speed, high capacity, high reliability, and low power consumption. FIG. 1 shows a typical CIM framework, in which the storage topology can be implemented using static random access memory (SRAM), dynamic random access memory (DRAM), or non-volatile memory modules (such as resistive random access memory (RRAM) and magnetic random access memory (MRAM)) [5-8]. Among the existing memory technologies, embedded DRAM (eDRAM) has become an attractive option due to its process compatibility and high density. However, different from the cross-coupled SRAM circuit, eDRAM lacks a latch design, which inevitably leads to data floating. Therefore, a forced refresh operation (refresh cycle ranging from microseconds to milliseconds) needs to be introduced to maintain data reliability, which in turn causes additional power consumption overhead and reduces data access efficiency. Therefore, the dynamic storage characteristics of eDRAM limit the computing energy efficiency of CIM based on DRAM at room temperature, especially for complex neural network computing applications. Given that the inherent dynamic storage characteristics of eDRAM are caused by the limited retention time (ranging from microseconds to milliseconds) due to leakage, previous research efforts have optimized its performance through various means [9]. For example, to extend the data retention time, internal feedback has been proposed to compensate for the leakage of the storage node

[0010] ; at the same time, word line voltage enhancement technology has been adopted to ensure the reliable storage of "1" or "0", but these strategies will increase power consumption and reduce device reliability

[0011] . Another option is based on the working principle of metal-oxide-semiconductor field effect transistor (MOSFET) (i.e., the basic unit of eDRAM), and the leakage current I in the subthreshold region Sub has an exponential relationship with temperature T (i.e., I sub∝ exp(-eV / kT), where e is the electron charge, k is the Boltzmann constant, and V is the gate voltage of the transistor). In this case, the low-leakage mode of the MOSFET at low temperatures can, in principle, significantly enhance the stability of data storage in eDRAM cells without the need for a refresh operation. Therefore, integrating such a low-temperature quasi-static eDRAM (CQS-eDRAM) module into the CIM architecture (b in Figure 1) can not only increase the storage density (due to the simplified memory circuit) but also improve the computational efficiency of the system. [1] Mark Horowitz. 1.1 computing’s energy problem (and what we can do about it). In 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pages 10 - 14, 2014. [2] Xiaowei Xu, Yukun Ding, Sharon Xiaobo Hu, Michael Niemier, Jason Cong, Yu Hu, and Yiyu Shi. Scaling for edge inference of deep neural networks. Nature Electronics, 1(4): 216 - 222, 2018. [3] Stefano Ambrogio, Pritish Narayanan, Hsinyu Tsai, Robert M Shelby, Irem Boybat, Carmelo Di Nolfo, Severin Sidler, Massimo Giordano, Martina Bodini, Nathan CP Farinha, et al. Equivalent-accuracy accelerated neural-network training using analogue memory. Nature, 558(7708): 60 - 67, 2018. [4] Daniele Ielmini and H-S Philip Wong. In-memory computing with resistive switching devices. Nature electronics,1(6):333-343,2018. [5] Chen, Zhengyu, Xi Chen, and Jie Gu. “15.3A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS / W System Energy Efficiency.” 2021 IEEE International Solid-State Circuits Conference(ISSCC). Vol.64. IEEE, 2021. [6] Xie, Shanshan, et al. “16.2 eDRAM-CIM: compute-in-memory design with reconfigurable embedded-dynamic-memory array realizing adaptive data converters and charge-domain computing.” 2021 IEEE International Solid-State Circuits Conference(ISSCC). Vol.64. IEEE, 2021. [7] Fujiwara, Hidehiro, et al. “A 5-nm 254-TOPS / W 221-TOPS / mm 2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations.” 2022 IEEE International Solid-State Circuits Conference(ISSCC). Vol.65. IEEE, 2022. [8]Weier Wan, Rajkumar Kubendran, Clemens Schaefer, Sukru Burc Eryilmaz, Wenqiang Zhang, Dabin Wu, Stephen Deiss, Priyanka Raina, He Qian, Bin Gao, et al. A compute-in-memory chip based on resistive random-access memory. Nature, 608(7923): 504 - 512, 2022. [9]A. Agarwal, S. Mukhopadhyay, A. Raychowdhury, K. Roy, and C. H. Kim. Leakage power analysis and reduction for nanoscale circuits. IEEE Micro, 26(2): 68 - 80, Mar. 2006.

[0010] Robert Giterman, Alexander Fish, Andreas Burg, and Adam Teman. A 4-transistor nmos-only logic-compatible gain-cell embedded dram with over 1.6-ms retention time at 700mv in 28-nm fd-soi. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(4): 1245 - 1256, Apr. 2018.

[0011] J. R. Hoff, G. W. Deptuch, Guoying Wu, and Ping Gui. Cryogenic lifetime studies of 130nm and 65nm nmos transistors for high-energy physics experi-ments. IEEE Transactions on Nuclear Science, 62(3): 1255 - 1261, Jun. 2015.

[0012] Theodore Van Duzer,Lizhen Zheng,Stephen R.Whiteley,Hoki Kim,Jaewoo Kim,Xiaofan Meng,and Thomas Ortlepp.64-kb hybrid josephson-cmos 4 kelvin ram with 400 ps access time and 12 mw read power.IEEE Transactions on Applied Super-conductivity,23(3):1700504-1700504,Jun.2013.

[0013] Masamitsu Tanaka,Masato Suzuki,Gen Konno,Yuki Ito,Akira Fujimaki,and Nobuyuki Yoshikawa.Josephson-cmos hybrid memory with nanocry-otrons.IEEE Transactions on Applied Supercon-ductivity,27(4):1-4,Jun.2017.

[0014] Gyu-Hyeon Lee,Seongmin Na,Ilkwon Byun,Dong-moon Min,and Jangwoo Kim.Cryoguard:A near refresh-free robust dram design for cryogenic computing.In 2021 ACM / IEEE 48th Annual International Symposium on Computer Architecture(ISCA),pages 637-650,Jun.2021.

[0015] Rakshith Saligram, Suman Datta, and Arijit Ray-chowdhury. Cryomem: A 4k-300k 1.3ghz edram macro with hybrid 2t-gain-cell in a 28nm logic pro-cess for cryogenic applications. In 2021 IEEE Cus-tom Integrated Circuits Conference (CICC), pages 1-2, Apr. 2021. Summary of the Invention The objective of the present invention is to provide a cryogenic quasi-static eDRAM (CQS-eDRAM) module. After integrating it into the CIM architecture, while increasing the storage density (due to the simplified memory circuit), the computing efficiency of the system is improved. To achieve the above objective, the technical solution of the present invention is to provide a cryogenic quasi-static embedded DRAM for energy-efficient in-memory computing, characterized in that the cryogenic quasi-static embedded DRAM array is composed of 4TTGGC memory cells, and each 4T TGGC memory cell is composed of a PMOS transistor P1 and three NMOS transistors N1, N2, and N3, where: A PMOS transistor P1 and an NMOS transistor N1 configured in parallel constitute a transmission-gate-based write port topology. The PMOS transistor is controlled by the write word line bar WWLB, and the NMOS transistor is controlled by the write word line WWL; The remaining two NMOS transistors N2 and N3 constitute a 2T-NMOS read port. Preferably, the gate of the PMOS transistor P1 is connected to the write word line bar WWLB, the source is connected to the write bit line WBL, and the drain is connected to the gate of the NMOS transistor N2; the drain of the NMOS transistor N1 is connected to the write bit line WBL, the source is connected to the gate of the NMOS transistor N2, and the gate is connected to the write word line; the source of the NMOS transistor N2 is grounded, and the drain is connected to the source of the NMOS transistor N3; the gate of the NMOS transistor N3 is connected to the read word line RWL, and the drain is connected to the read bit line RBL. Preferably, the performance of the cryogenic quasi-static embedded DRAM is optimized using the DVS strategy or the DRPS strategy; or the performance of the cryogenic quasi-static embedded DRAM is optimized using a combined strategy of DVS and DRPS. Preferably, the read circuit of the cryogenic quasi-static embedded DRAM employs a sense amplifier with an additional reference voltage. The present invention proposes a method for implementing energy-efficient CIM applications using CQS-eDRAM. Based on an accurate cryogenic device model and a process design kit (PDK), the present invention proposes a cryogenic four-transistor transmission gate gain cell (4T TGGC) topology, which realizes quasi-static storage operation at low temperature by making full use of its advantages in reducing leakage and wire transmission delay. In addition, the present invention adopts a cryogenic write bit line (WBL) biasing technique and a dedicated readout circuit to optimize the power consumption of read and write operations. Experimental data of a 4Kb CQS-eDRAM chip shows that at 4.2K, the retention time reaches 66.50 seconds, and the retention time distribution is more uniform. In addition, by using dynamic voltage scaling (DVS) and dynamic refresh period scaling (DRPS) techniques, CQS-eDRAM achieves a 7.1% reduction in retention power and a 13.6% reduction in dynamic power consumption at an acceptable data error rate. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a design diagram of a CQS-eDRAM architecture, where: a shows a cryogenic test device with the test chip placed inside a liquid helium tank; b shows a CIM-based computing architecture composed of a processing unit and a CIM module. The processing unit includes an arithmetic logic unit (ALU), a controller, and an on-chip cache, while the CIM module for a dedicated algorithm includes an interface, a peripheral circuit, and a main memory; c shows the configuration of a CQS-eDRAM array and its surrounding read and write control circuits; FIG. 2 shows the design of a 4T TGGC storage cell of CQS-eDRAM, where: a shows the schematic diagram of 4TTGGC (four-transistor TGGC) and the signal voltages under different operations; b shows the waveform of 4TTGGC in the write operation, demonstrating full-swing data storage; c shows the relationship between the retention time and different WBL bias voltages; d shows the waveforms of `1′ (top) and `0′ (bottom) of 4T TGGC in the read operation, with fast data access; e shows the circuit architecture diagram of a 4Kb CQS-eDRAM; f shows the influence of the SN voltage on the read speed and power consumption at low temperature; FIG. 3 shows the retention time and power consumption characteristics of a 4Kb CQS-eDRAM chip, where: a shows a chip photo of the cryogenic package and the CQS-eDRAM chip; b and c respectively show the retention heat maps of a 4Kb CQS-eDRAM array (chip 1) at 300K and 4.2K; d shows the corresponding retention time histogram showing the normal distribution of the retention time at 300K and 4.2K; e and f respectively show the statistical retention times from chip 1 to chip 6 at 4.2K and 300K and the variation of σ, where the values are normalized with respect to chip 1, and the average value and standard deviation of chip 1 are defined as and σ0; Figure 4 illustrates the impact of DVS and DPRS on the performance of CQS-eDRAM, where: a and b respectively illustrate the comparison of the average retention time and the standard deviation of the retention time with the supply voltage at 4.2K and 300K; c and d respectively illustrate the refresh period and the array retention power consumption related to the supply voltage at 300K and 4.2K; e and f respectively illustrate the comparison of the error rate and the retention power consumption of a 4Kb CQS-eDRAM array with different refresh periods at 4.2K and 300K. Detailed implementation manners The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of this application. Figure 1 illustrates the low-temperature chip architecture disclosed in the embodiment of the present invention. Due to negligible leakage, the refresh period of this memory is much longer than that at room temperature. In previous studies, we comprehensively characterized the temperature dependence of NMOS and PMOS devices in the 40-nanometer low-power (40LP) process of Huahong Semiconductor Limited (HLMC) and revealed the basic mechanisms of key electrical parameters at low temperatures. Based on the physical model of the devices, we also developed an improved BSIM compact model and a general PDK, which can be applied to full-size devices over the entire temperature range, thus enabling the VLSI design of low-temperature CMOS devices. With the help of this platform, we successfully designed an eDRAM architecture suitable for low-temperature operation. First, we compared the write performance of different eDRAM bit-cell designs (from 2T to 4T) at low temperatures. A single type of write port controlled by the write word line (WWL) is not effective enough due to the signal degradation when writing to the storage node (SN). To solve this problem, word-line voltage boosting technology is widely used to ensure a significant initial voltage difference by driving the gate voltage. However, at low temperatures, due to V th ​When the offset is greater than 0.11V, this strategy becomes less attractive, which in turn leads to greater power consumption and performance loss in the single-type write port design. Instead, in the design shown in part a of Figure 2, the present invention adopts a transmission gate (TG)-based write port topology, where the NMOS and PMOS pairs in parallel configuration (controlled by the write word line WWL and the write word line bar WWLB) ensure full swing during the write operation, as shown in part b of Figure 2. In addition, we found that during non-write access, the write bit line WBL bias voltage plays a crucial role in the retention time of the GC-eDRAM design. Part c of Figure 2 shows the negative correlation between the retention time and the WBL bias voltage, and at low temperature, the optimal bias condition for WBL is found to be 0v, compared with v = V DD , and the retention time is improved by 1.48 times. In terms of the read operation, traditional eDRAM bit cells usually use a 1T read port to save layout area. However, the unselected read word line (RWL) hinders the read performance, resulting in longer access time and more power consumption overhead. To achieve non-destructive and high-speed read operations, we utilize a 2T-NMOS read port, as shown in part a of Figure 2, because at low temperature, the driving strength of the NMOS transistor exceeds that of the PMOS transistor. The simulated read waveforms in part d of Figure 2 verify the successful read "0" and "1" operations, where the read bit line (RBL) discharges only during the read "1" operation. According to our simulation results, the 4T TGGC eDRAM proposed by the present invention has an improvement of 1.98 times in power consumption overhead and 1.41 times improvement in read access time compared with the 1T-NMOS read port configuration. In addition to the optimization of individual bit cells, we also redesigned the read circuit of the 4Kb CQS-eDRAM for low-temperature operation, considering speed and power consumption. As shown in part e of Figure 2, the read circuit adopts a sense amplifier (SA) with an additional reference voltage (V REF ), and there are 128 of them placed at the bottom of the memory array in the column direction. Part f of Figure 2 shows the simulation results of the energy-delay product (EDP) versus the SN voltage, comparing the differential SA and inverter (Inv) configurations. By comparing these two read circuit structures, we can observe that regardless of the SN voltage, the SA structure always has a smaller EDP than the Inv structure. As the SN voltage decreases from V DD to 0.6v, the EDP difference between the two read circuits further increases (from 3.04 times to 7.40 times). After the optimized 4T-TGGC cell design was completed, we designed a 4Kb CQS-eDRAM chip using the 40LP process. Part a of Figure 3 shows the low-temperature package and chip photos of the 4Kb CQS-eDRAM. We prepared six test chips labeled Chip 1 to Chip 6. For low-temperature measurements, the I / O pins of the chip were directly connected to the low-temperature package board through wire bonding. The test chip was then connected to the field programmable gate array (FPGA) board through a customized conversion printed circuit board (PCB) to achieve control signal transmission and data processing. The sampled data on the FPGA was then sent to the host PC for subsequent data processing. Parts b to c of Figure 3 show the retention time thermal diagrams of Chip 1 at 300K and 4.2K. Surprisingly, as the base temperature dropped to 4.2K, the average retention time The retention time of the memory array is significantly increased from 112.09 μs at 300 K to 67.01 s at 4.2 K, as shown in part d of Figure 3. Such a significant improvement (i.e., six orders of magnitude improvement over the retention time at 300 K) is mainly attributed to the suppression of subthreshold current and reverse biased junction diode leakage, both of which are exponentially dependent on temperature. In addition, the retention time standard deviation (std, σ) of the entire memory array is about 16.80 us at 300 K and about 134 ms at 4.2 K. Apart from In addition, retention time variation is another key parameter for evaluating eDRAM performance. Therefore, the normalized average retention time (light gray column) and standard deviation (dark gray column) of six CQS-eDRAM chips are summarized in Figure 3, as shown in parts e and f of Figure 3. Due to the reduction of leakage current and thermal noise, the normalized retention time remains basically constant at T = 4.2K, where σ of different chips 4.2K / σ0 also shows negligible changes, as shown in part e of Figure 3. In contrast, when the temperature of the CQS-eDRAM chip rises to T = 300K, the increase in thermal noise introduces more current fluctuations. and σ 300K The variation between the six chips ranged from -15% to +7% (see Figure 3). f). To evaluate the dispersion of retention times at different temperatures, we used As a criterion, in order to make fair comparisons between datasets of different scales. As shown in part d of Figure 3, The value decreases from 0.150 at 300K to 0.002 at 4.2K, corresponding to a 75-fold improvement in stability. Considering that the retention time and error rate of the eDRAM array depend on the supply voltage and refresh period, we can further optimize the performance of CQS-eDRAM using DVS and DRPS strategies. Parts a to b in Figure 4 show the mean and standard deviation of the retention time of Chip 1 at 4.2K and 300K when the supply voltage V DD increases from 0.6V to 1.1V. It is observed that and σ are positively correlated with V DD : increases from 16.02s (22.69μs) at 0.6V to 67.01s (112.09μs) at 1.1V, and the corresponding σ 4.2K (σ 300K ) improves by 3.90× (3.67×). Considering the impact of V DD on the operation of CQS-eDRAM, parts c and d in Figure 4 show the refresh period t min (i.e., the shortest time to ensure the complete reliability of stored data) and the retention power consumption (i.e., P retention =(E read +E write +E leakage ) / t min , where E read and E write are the total energy consumption during read and write operations respectively, and E leakage is the total leakage energy during the refresh process) as a function of the supply voltage, for the operation of CQS-eDRAM at 300K and 4.2K respectively. At room temperature (as shown in part c of Figure 4), it can be seen that a higher V DD helps to extend the retention time. By optimizing the retention power consumption through voltage adjustment, the minimum retention power consumption can be achieved at 1.1V, but this comes at the cost of a maximum dynamic power consumption of 131μW. On the contrary, when CQS-eDRAM operates at T = 4.2K (Figure 4(d)), it is determined that V DD = 1.0V is the optimal operating condition for achieving a minimum retention power consumption of 104fW (a 7.1% reduction compared to V DD = 1.1V) and a 13.6% reduction in dynamic power consumption. In addition to DVS, DRPS is another useful adjustment method for eDRAM optimization. According to the working principle of eDRAM, an increase in the refresh period leads to an increase in the error rate of memory operations. This observation is consistent with our experimental results at T = 4.2K and 300K, as shown in parts e and f of Figure 4. It is worth noting that compared with the data obtained at room temperature, the error rate at 4.2K is more sensitive to the refresh period, probably because the refresh period is more strictly restricted, and even a slight change will have a significant impact on the error rate. In practical applications, it is crucial to ensure that the refresh period remains below 66.50s to mitigate the error rate problem. According to the power supply voltage-related data given in Figure 4, in applications pursuing energy efficiency, a combined strategy of DVS and DRPS is recommended to meet the low-power budget requirements. On the other hand, for applications that value computational accuracy and performance, DVS has proven to be a valuable method to reduce system-level power consumption while retaining the required performance benchmarks. In summary, the present invention proposes a 4TTGGC eDRAM bit cell design that employs a quasi-static memory operation mode at low temperatures. Through low-temperature measurements, we have demonstrated that the TG-based write port can achieve high-quality write operations without the need for word-line enhancement techniques, while the 2T-NMOS read port can achieve faster and more energy-efficient operations. The 4Kb CQS-eDRAM chip implemented in a 40LP process achieved a retention time of 66.50s at 4.2K (1.37×10 6 times higher than at 300K), with a retention power consumption of 112fW (i.e., 28fW / Kb), ensuring 100% data reliability. In addition, compared with other designs at low temperatures, it also performs excellently in terms of retention time, dynamic power consumption, and retention power consumption, as summarized in Table 1 below [12-15] . Moreover, our 4T TGGC-based CQS-eDRAM design has significantly reduced dynamic and retention power consumptions and has a more compact bit cell area than 6T SRAM, making it an attractive candidate for high-density and low-power memory implementation in low-temperature computing applications. JJ: Josephson Junction nTron: Nanacryotrons N / A: Not Applicable N / R: Not Reported * Calculated from the reported data Off-chip and IO power are not included Table 1: Comparison results of working with different low-temperature storage designs

Claims

1. A low-temperature quasi-static embedded DRAM for energy-efficient in-memory computing, characterized in that: The low-temperature quasi-static embedded DRAM array is composed of 4T TGGC memory cells, each of which is composed of a PMOS transistor P1 and three NMOS transistors N1, N2, and N3, where: A PMOS transistor P1 and an NMOS transistor N1 configured in parallel form a write port topology based on a transmission gate, the PMOS transistor is controlled by a write word line bar WWLB, and the NMOS transistor is controlled by a write word line WWL; The remaining two NMOS transistors N2 and N3 constitute a 2T-NMOS read port.

2. A low-temperature quasi-static embedded DRAM for energy-efficient in-memory computing as claimed in claim 1, characterized in that: The gate of the PMOS transistor P1 is connected to the write word line bar WWLB, the source is connected to the write bit line WBL, and the drain is connected to the gate of the NMOS transistor N2; the drain of the NMOS transistor N1 is connected to the write bit line WBL, the source is connected to the gate of the NMOS transistor N2, and the gate is connected to the write word line; the source of the NMOS transistor N2 is grounded, and the drain is connected to the source of the NMOS transistor N3; the gate of the NMOS transistor N3 is connected to the read word line RWL, and the drain is connected to the read bit line RBL.

3. A low-temperature quasi-static embedded DRAM for energy-efficient in-memory computing as claimed in claim 1, characterized in that: The performance of the low-temperature quasi-static embedded DRAM is optimized by using a DVS strategy or a DRPS strategy; or the performance of the low-temperature quasi-static embedded DRAM is optimized by using a combined strategy of DVS and DRPS.

4. A low-temperature quasi-static embedded DRAM for energy-efficient in-memory computing as claimed in claim 1, characterized in that: The read circuit of the low-temperature quasi-static embedded DRAM adopts a sensitive amplifier with an additional reference voltage.

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