Data processing method and apparatus, server and storage medium

Abstract

The present application relates to a data processing method and apparatus, a server and a storage medium. The method is applied to a storage server, the storage server comprising a network interface card and a solid-state hard disk, the solid-state hard disk comprising a controller memory buffer area, and the method comprising: by means of the network interface card, receiving a data operating command sent by a host, the data operating command carrying input / output data; by means of the network interface card, sending the input / output data to the solid-state hard disk on the basis of the data operating command; and, by means of the solid-state hard disk, operating the controller memory buffer area on the basis of the input / output data. Using the method can bypass CPUs of storage servers for data transmission, saving consumption of CPU resources.

Description

Data processing method, device, server and storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on December 12, 2023, with application number 202311697134.9, and application name “Data processing method, device, server and storage medium”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of computer technology, and in particular to a data processing method, device, server, and storage medium. Background Art

[0004] Current market demand is driving a surge in global storage data volumes at the zettabyte level. This has resulted in significant increases in the performance of individual storage hard drives, the memory access bandwidth of internal CPUs, and the network interface bandwidth used by storage. Customers are also placing higher demands on storage system I / O performance (higher bandwidth, IOPS, and lower latency). However, the slowdown in semiconductor process technology development in the post-Moore era and the stagnation of single-core computing power (52% to 3.5%) have posed significant performance challenges to storage system design.

[0005] EBOF (Ethernet Bunch of Flash) is a new type of high-density, high-performance storage server based on Ethernet as the underlying network transmission technology. It mainly accesses and manages storage NVMe Flash SSDs through NOF (NVMe over Fabric) connections, achieving efficient resource pooling and sharing with near-local media access performance. Computing and storage resources can be expanded independently.

[0006] In the data path of current EBOP storage servers, input and output data must flow into and out of the L3 cache and DDR (Double Data Rate) memory module in the CPU for each data movement, thereby increasing the power consumption of the CPU.

[0007] Summary of the Invention

[0008] A data processing method is applied to a storage server, wherein the storage server includes a network card and a solid-state drive, and the solid-state drive includes a controller memory buffer, including:

[0009] Receive data operation commands sent by the host through the network card, and the data operation commands carry input and output data;

[0010] Send input and output data to the solid-state drive through the network card according to data operation commands;

[0011] The controller memory buffer is operated based on input and output data through the solid-state drive.

[0012] In one embodiment, the solid-state drive further includes a controller, a flash memory device, and an internal direct random access memory, wherein the internal direct random access memory includes a controller memory buffer.

[0013] In one embodiment, when the data operation command is a data read command, the input and output data are address information, and the solid-state hard disk operates the controller memory buffer according to the input and output data, including: receiving the address information through the controller, sending the address information to the internal direct random access memory, determining the target address corresponding to the controller memory buffer according to the address information through the internal direct random access memory, and reading the address from the controller memory buffer through the internal direct random access memory.

[0014] In one embodiment, the method further includes: sending the target data to the controller via the internal direct random access memory, sending the target data to the network card via the controller as a read completion message, and returning the read completion message to the host via the network card.

[0015] In one embodiment, the controller memory buffer includes at least one buffer, and reading target data from a target address of the controller memory buffer through an internal direct random access memory includes: determining a first target buffer in the at least one buffer according to the target address through the internal direct random access memory, and reading the target data from the first target buffer through the internal direct random access memory.

[0016] In one embodiment, when the data operation command is a data write command, the input and output data are the data to be written and the corresponding write address information, and the solid-state hard drive operates on the controller memory buffer according to the input and output data, including: receiving the data to be written and the corresponding write address information through the controller, sending the data to be written and the corresponding write address information to the internal direct random access memory, determining the address to be written corresponding to the controller memory buffer according to the write address information through the internal direct random access memory, and writing the data to be written to the address to be written corresponding to the controller memory buffer through the internal direct random access memory.

[0017] In one embodiment, the above method also includes: obtaining the written data from the controller memory buffer through the internal direct random access memory, sending the written data to the flash memory device, storing the written data through the flash memory device, and generating a write completion message, sending it to the controller, sending the write completion message to the network card through the controller, and returning the write completion message to the host through the network card.

[0018] In one embodiment, the controller memory buffer includes at least one buffer, and writing the data to be written to the address to be written corresponding to the controller memory buffer through the internal direct random access memory includes: determining a second target buffer from at least one buffer according to the address to be written through the internal direct random access memory, and writing the data to be written to the second target buffer through the internal direct random access memory.

[0019] In one embodiment, the controller includes a first register and a second register, and the first register and the second register are respectively used to describe different attribute information of the controller memory buffer.

[0020] In one embodiment, the first register defines a location of a controller memory buffer, and the first attribute information corresponding to the first register is set to indicate that the controller supports the controller memory buffer.

[0021] In one embodiment, the second register defines the size of the controller memory buffer, and the second attribute information corresponding to the second register is set to indicate that the controller supports the controller memory buffer.

[0022] In one embodiment, the input and output data are sent to the solid-state drive according to the data operation command through the network card, including: sending the input and output data to a high-speed serial computer expansion bus standard switching unit according to the data operation command through the network card, and sending the input and output data to the solid-state drive through the high-speed serial computer expansion bus standard switching unit.

[0023] A data processing device is applied to a storage server. The storage server includes a network card and a solid-state hard disk. The solid-state hard disk includes a controller memory buffer, including:

[0024] A receiving module is used to receive data operation commands sent by the host through the network card, and the data operation commands carry input and output data;

[0025] A sending module is used to send input and output data to the solid-state drive through the network card according to the data operation command;

[0026] The operation module is used to operate the controller memory buffer according to input and output data through the solid state drive.

[0027] A server includes a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor, wherein when the processor executes the computer-readable instructions, the following steps are implemented:

[0028] Receive data operation commands sent by the host through the network card, and the data operation commands carry input and output data;

[0029] Send input and output data to the solid-state drive through the network card according to data operation commands;

[0030] The controller memory buffer is operated based on input and output data through the solid-state drive.

[0031] One or more non-transitory computer-readable storage media storing computer-readable instructions, which, when executed by one or more processors, cause the one or more processors to perform the following steps:

[0032] Receive data operation commands sent by the host through the network card, and the data operation commands carry input and output data;

[0033] Send input and output data to the solid-state drive through the network card according to data operation commands;

[0034] The controller memory buffer is operated based on input and output data through the solid-state drive. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG1 is a schematic flow chart of a data processing method in one or more embodiments;

[0036] FIG1-A is a data flow diagram of a data processing method in the prior art in one or more embodiments;

[0037] FIG1-B is a data flow diagram of a data processing method according to one or more embodiments;

[0038] FIG2 is a flow diagram of controller memory buffer operation steps in one or more embodiments;

[0039] FIG2-A is a schematic diagram of the internal structure of a solid-state drive in one or more embodiments;

[0040] FIG3 is a flow chart illustrating steps for operating a controller memory buffer in one or more embodiments;

[0041] FIG4 is a schematic flow diagram of a target data reading step in one or more embodiments;

[0042] FIG5 is a flow chart illustrating the operation steps of a controller memory buffer in one or more embodiments;

[0043] FIG6 is a flowchart illustrating the operation steps of a controller memory buffer in one or more embodiments;

[0044] FIG7 is a flow chart illustrating the steps of writing data into the controller memory buffer in one or more embodiments;

[0045] FIG8 is a flow chart of steps for sending a data operation command in one or more embodiments;

[0046] FIG9 is a block diagram of a data processing apparatus according to one or more embodiments;

[0047] FIG10 is a diagram illustrating the internal structure of a computer device in one or more embodiments. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0049] In one embodiment, as shown in FIG1 , a data processing method is provided. The method is described by taking a storage server as an example. The storage server includes a network card and a solid-state drive. The solid-state drive includes a controller memory buffer. The method includes the following steps:

[0050] Step 102: Receive a data operation command sent by the host through the network card, where the data operation command carries input and output data.

[0051] The storage server here can be an EBOF server. EBOF (Ethernet Bunch of Flash) is a new type of high-density and high-performance storage server based on Ethernet as the underlying network transmission technology. It mainly accesses and manages the storage NVMe (Non-Volatile Memory Express, non-volatile memory host controller interface specification) Flash SSD (solid-state drive) through NOF (NVMe over Fabric) connection. The storage server includes but is not limited to a network card and a solid-state drive. The network card is a computer hardware designed to allow the storage server to communicate on a computer network. The solid-state drive (Solid State Disk or Solid State Drive, abbreviated as SSD), also known as a solid-state drive, is a hard disk made of a solid-state electronic storage chip array. The solid-state drive includes a controller memory buffer (Controller Memory Buffer, CMB). The controller memory buffer CMB is the read-write storage buffer inside the solid-state drive, which maps the internal storage space DDR (Double Data Rate) of the SSD to the physical address space of the host through the BAR (Base Address Registers) space of PCIe.

[0052] The host here refers to the computer that communicates with the storage server. The host also has a network interface card (NIC) for communicating with the NIC on the storage server. Specifically, the host sends data operation commands to the storage server via its NIC, and the storage server receives the data operation commands sent by the host via its NIC. The data operation commands carry input and output data. The data operation commands can be data read commands or data write commands, and different data operation commands carry different input and output data.

[0053] Step 104 : Send the input and output data to the solid state drive through the network card according to the data operation command.

[0054] Specifically, the network card sends the input and output data it carries to the solid-state drive according to the data operation command. In the prior art, the network card needs to forward data through the central processing unit (CPU). In this application, after the network card receives the data operation command sent by another host, it sends the input and output data it carries directly to the solid-state drive according to the data operation command, completely bypassing the central processing unit (CPU) and eliminating the need for CPU processing, greatly saving CPU resource consumption.

[0055] Step 106 : operating the controller memory buffer according to the input and output data through the solid state drive.

[0056] Specifically, after receiving the input and output data sent by the network card, the solid-state drive analyzes the input and output data to obtain an analysis result, and then operates the controller memory buffer based on the analysis result. For example, if the input and output data is data carried by a data read command, the solid-state drive reads data from the controller memory buffer based on the input and output data. For another example, if the input and output data is data carried by a data write command, the solid-state drive writes data from the controller memory buffer based on the input and output data. In other words, the storage server directly communicates with the solid-state drive through the network card, eliminating the need for the central processing unit (CPU) to perform data transmission operations or memory copy operations, greatly saving CPU resource consumption.

[0057] For example, as shown in Figure 1-A, Figure 1-A shows a data flow diagram of the data processing method in the prior art. The storage server in Figure 1-A includes a network card, a central processing unit CPU and a solid-state drive SSD. The network card receives a data operation command sent by another host, and sends the data carried by the data operation command to the central processing unit CPU through the network card. The central processing unit CPU sends the data to the solid-state drive SSD. That is to say, in the data processing method in the prior art, each data movement must pass through the central processing unit CPU, thereby increasing power consumption.

[0058] As shown in Figure 1-B, Figure 1-B shows a data flow diagram of the data processing method. The storage server in Figure 1-B includes a network card and a solid-state drive SSD. The solid-state drive SSD includes a controller memory buffer CMB. The network card receives a data operation command sent by another host, and directly sends the data carried by the data operation command to the solid-state drive SSD through the network card. The solid-state drive SSD operates on the internal controller memory buffer CMB according to the carried data, completely bypassing the central processing unit CPU. There is no need for the CPU to perform data transmission operations or memory copy operations, which greatly saves CPU resources.

[0059] In the above data processing method, the host-side data is directly transmitted to the network card of the storage server through the network card, and the data is directly transmitted to the solid-state drive through the network card. The entire data transmission process completely bypasses the central processing unit (CPU) of the storage server. There is no need for the CPU to perform data transmission operations or memory copy operations, which greatly saves CPU resource consumption.

[0060] In one embodiment, the solid state drive further includes a controller, a flash memory device, and an internal direct random access memory, wherein the internal direct random access memory includes a controller memory buffer.

[0061] In addition to the controller memory buffer (CMB), the solid-state drive (SSD) also includes a controller, a flash memory device, and internal direct random access memory (DRAM). The DRAM includes the controller memory buffer (CMB). The controller in the SSD is used to control the SSD, the flash memory device can be a non-volatile medium used to store data, and the DRAM is the internal memory inside the SSD that directly exchanges data with the controller. It can be read and written at any time (except when refreshed) and is very fast, and is usually used as a temporary data storage medium.

[0062] For example, as shown in FIG2-A, FIG2-A shows a schematic diagram of the internal structure of a solid-state drive in one embodiment. The solid-state drive SSD includes the following modules: an SSD controller, a NAND flash memory device, and an internal direct random access memory (DRAM) including a CMB. In operation, the SSD controller can communicate with the host via a bus. For example, an SSD controller using the Peripheral Component Interconnect Express (PCI Express or PCle) bus standard can further communicate with the DRAM device via a double data rate (DDR) bus, and connect to the NAND flash memory device via a physical interface.

[0063] In one embodiment, as shown in FIG2 , when the data operation command is a data read command, the input and output data are address information, and the controller memory buffer is operated according to the input and output data by the solid-state drive, including:

[0064] Step 202: Receive address information through the controller and send the address information to the internal direct random access memory.

[0065] Step 204 : determining the target address corresponding to the controller memory buffer according to the address information through the internal direct random access memory.

[0066] Step 206 : Read the target data from the target address of the controller memory buffer through the internal direct random access memory.

[0067] When the data operation command is a data read command, the input and output data carried by the data read command is address information. The address information here refers to information related to the address where the read data is located, including address blocks, internal address information, etc. Specifically, the solid-state drive receives the address information sent by the network card through the controller and sends the address information to the internal direct random access memory. The internal direct random access memory determines the target address corresponding to the controller memory buffer based on the address information and obtains the target data from the target address. In other words, the data is read from the controller memory buffer in the solid-state drive.

[0068] In one embodiment, as shown in FIG3 , the method further includes:

[0069] Step 302: Send the target data to the controller via the internal direct random access memory.

[0070] Step 304: Send the target data to the network card via the controller with a read completion message.

[0071] Step 306: Return the read completion message to the host via the network card.

[0072] Specifically, after successfully reading the target data from the target address in the controller's memory buffer through the internal direct random access memory, the internal direct access memory sends the target data to the controller, and the controller sends the target data to the network card in the form of a read completion message. After receiving the read completion message, the network card returns the read completion message to the host. Among them, RDMA remote direct memory access technology can be used as a protocol between the host and the storage server. That is to say, after successfully reading the target data from the controller's memory buffer in the internal direct random access memory, it is necessary to inform the host with a read completion message, and then the read completion message is generated by the controller and transmitted to the host through the network card.

[0073] In one embodiment, as shown in FIG4 , the controller memory buffer includes at least one buffer, and reading target data from a target address in the controller memory buffer through an internal direct random access memory includes:

[0074] Step 402: Determine a first target buffer in at least one buffer according to a target address through an internal direct random access memory.

[0075] Step 404: Read the target data from the first target buffer via the internal direct random access memory.

[0076] When the controller memory buffer CMB includes at least one buffer, after determining the target address, the internal direct random access memory may determine a first target buffer among the multiple buffers based on the target address, and the internal direct random access memory reads the target data from the first target buffer. Each buffer in the controller memory buffer is associated with an address, and the corresponding first target buffer can be determined based on the target address.

[0077] In one embodiment, as shown in FIG5 , when the data operation command is a data write command, the input and output data are the data to be written and the corresponding write address information, and the controller memory buffer is operated according to the input and output data by the solid-state drive, including:

[0078] Step 502: Receive the data to be written and the corresponding write address information through the controller, and send the data to be written and the corresponding write address information to the internal direct random access memory.

[0079] Step 504 : determining the to-be-written address corresponding to the controller memory buffer according to the write address information through the internal direct random access memory.

[0080] Step 506 : Write the data to be written into the address to be written corresponding to the controller memory buffer via the internal direct random access memory.

[0081] Among them, when the data operation command is a data write command, the data write command is used to instruct the data to be written. The input and output data carried by the data write command are the data to be written and the corresponding write address information. The write address information is information related to the address to be written, including the address block to be written, etc.

[0082] Specifically, after the controller receives the data to be written and the corresponding address information sent by the network card, the controller sends the data to be written and the corresponding address information to the internal direct random access memory. The internal direct random access memory determines the address to be written in the controller memory buffer according to the address information. Further, the internal direct random access memory writes the data to be written to the address to be written in the controller memory buffer, realizes data writing, and stores the data in the controller memory buffer.

[0083] In one embodiment, as shown in FIG6 , the method further includes:

[0084] Step 602 : Obtain the written data from the controller memory buffer via the internal direct random access memory, and send the written data to the flash memory device.

[0085] Step 604: Store the written data in the flash memory device, generate a write completion message, and send it to the controller.

[0086] Step 606: Send a write completion message to the network card through the controller.

[0087] Step 608: Return the write completion message to the host via the network card.

[0088] Once the data is successfully written to the controller memory buffer, it needs to return to the host to inform the host that the data has been successfully written to the SSD controller memory buffer. Since the controller memory buffer is a temporary storage memory, the SSD controller can read the data from the controller memory buffer and write it to the flash memory device.

[0089] Specifically, the internal direct random access memory reads the written data from the controller memory buffer and sends the written data to the flash memory device for storage. After receiving the written data, the flash memory device stores the written data and generates a corresponding write completion message.

[0090] Furthermore, the flash memory device sends the generated write completion message to the network card through the controller. After receiving the write completion message, the network card returns the write completion message to the host to inform the host that the data writing has been completed.

[0091] In this way, the controller memory buffer of the solid-state drive can be used as a read and write data buffer for the storage server, rather than using the local memory and cache of the EBOF when the input and output data passes through the I / O path of the storage server and the flash memory device, thereby avoiding the reduction of memory bandwidth due to memory congestion.

[0092] In one embodiment, as shown in FIG7 , the controller memory buffer includes at least one buffer, and writing the data to be written to the address to be written corresponding to the controller memory buffer via the internal direct random access memory includes:

[0093] Step 702: Determine a second target buffer from at least one buffer according to the address to be written through the internal direct random access memory.

[0094] Step 704 : Write the data to be written into the second target buffer via the internal direct random access memory.

[0095] When the controller memory buffer CMB includes at least one buffer, upon receiving the address to be written, the internal direct random access memory determines a matching second target buffer from the at least one buffer based on the address to be written, and then writes the data to be written into the second target buffer. Each buffer in the controller memory buffer is associated with an address, and the corresponding second target buffer can be determined based on the address to be written.

[0096] In one embodiment, the controller includes a first register and a second register, and the first register and the second register are respectively used to describe different attribute information of the controller memory buffer.

[0097] In one embodiment, the first register defines the location of the controller memory buffer, and the first attribute information corresponding to the first register is set to indicate that the controller supports the controller memory buffer.

[0098] In one embodiment, the second register defines the size of the controller memory buffer, and the second attribute information corresponding to the second register is set to indicate that the controller supports the controller memory buffer.

[0099] Among them, there are two registers in the solid-state drive controller, namely the first register and the second register, which describe different basic information of the controller memory buffer. The first register can be CMBLOC (Controller Memory Buffer Location, referring to the location information of the storage area), and the second register can be CMBSZ (Controller Memory Buffer Size, referring to the size information of the storage area).

[0100] The first register defines the location of the controller memory buffer. If the controller does not support the controller memory buffer (CAP.CMBS), this attribute is retained. If the controller supports the controller memory buffer and CMBMSC.CRE is cleared to "0", this attribute should be cleared to 0h. In this application, the first attribute information corresponding to the first register is set to indicate that the controller supports the controller memory buffer before operations on the controller memory buffer can be performed.

[0101] The second register defines the size of the controller memory buffer. If the controller memory buffer function is not supported, or if the controller supports the controller memory buffer (CAP.CMBS) and CMBMSC.CRE is cleared to "0", this attribute should be cleared to 0h. In this application, the second attribute information corresponding to the second register is set to indicate that the controller supports the controller memory buffer in order to operate the controller memory buffer.

[0102] In one embodiment, as shown in FIG8 , sending input and output data to a solid-state drive through a network card according to a data operation command includes:

[0103] Step 802: Send the input and output data to the high-speed serial computer expansion bus standard switching unit through the network card according to the data operation command.

[0104] Step 804 : Send the input and output data to the solid state drive via a high-speed serial computer expansion bus standard switching unit.

[0105] Specifically, the host transmits input and output data directly to the storage server's network card through the network card, and then directly completes the data transmission with the solid-state drive through the storage server's computer expansion bus standard (PCIe) switching unit. Furthermore, the high-speed serial computer expansion bus standard switching unit sends the input and output data to the solid-state drive. In other words, the data transmission between the network card in the storage server and the solid-state drive must be completed through the high-speed serial computer expansion bus standard switching unit, eliminating the need for the CPU to perform data transmission operations or memory copy operations, greatly saving CPU resources.

[0106] It should be understood that, although the various steps in the above flow chart are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the above flow chart may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these sub-steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0107] In one embodiment, as shown in FIG9 , a data processing device 900 is provided. The device is applied to a storage server. The storage server includes a network card and a solid-state drive. The solid-state drive includes a controller memory buffer. The device includes a receiving module 902 , a sending module 904 , and an operating module 906 , wherein:

[0108] The receiving module 902 is configured to receive a data operation command sent by the host through the network card, where the data operation command carries input and output data.

[0109] The sending module 904 is used to send the input and output data to the solid state drive through the network card according to the data operation command.

[0110] The operation module 906 is configured to operate the controller memory buffer according to the input and output data through the solid state drive.

[0111] In one embodiment, the solid state drive further includes a controller, a flash memory device, and an internal direct random access memory, wherein the internal direct random access memory includes a controller memory buffer.

[0112] In one embodiment, when the data operation command is a data read command, the input and output data is address information. The operation module 906 receives the address information through the controller, sends the address information to the internal direct random access memory, determines the target address corresponding to the controller memory buffer according to the address information through the internal direct random access memory, and reads the target data from the target address in the controller memory buffer through the internal direct random access memory.

[0113] In one embodiment, the operation module 906 sends the target data to the controller via the internal direct random access memory, sends the target data to the network card via the controller as a read completion message, and returns the read completion message to the host via the network card.

[0114] In one embodiment, the controller memory buffer includes at least one buffer, the operation module 906 determines a first target buffer in the at least one buffer according to a target address through an internal direct random access memory, and reads target data from the first target buffer through the internal direct random access memory.

[0115] In one embodiment, when the data operation command is a data write command, the input and output data are the data to be written and the corresponding write address information. The operation module 906 receives the data to be written and the corresponding write address information through the controller, sends the data to be written and the corresponding write address information to the internal direct random access memory, determines the address to be written corresponding to the controller memory buffer according to the write address information through the internal direct random access memory, and writes the data to be written to the address to be written corresponding to the controller memory buffer through the internal direct random access memory.

[0116] In one embodiment, the operation module 906 obtains the written data from the controller memory buffer through the internal direct random access memory, sends the written data to the flash memory device, stores the written data through the flash memory device, and generates a write completion message, sends it to the controller, sends the write completion message to the network card through the controller, and returns the write completion message to the host through the network card.

[0117] In one embodiment, the controller memory buffer includes at least one buffer, and the operation module 906 determines a second target buffer from the at least one buffer according to the address to be written through the internal direct random access memory, and writes the data to be written into the second target buffer through the internal direct random access memory.

[0118] In one embodiment, the controller includes a first register and a second register, and the first register and the second register are respectively used to describe different attribute information of the controller memory buffer.

[0119] In one embodiment, the first register defines the location of the controller memory buffer, and the first attribute information corresponding to the first register is set to indicate that the controller supports the controller memory buffer.

[0120] In one embodiment, the second register defines the size of the controller memory buffer, and the second attribute information corresponding to the second register is set to indicate that the controller supports the controller memory buffer.

[0121] In one embodiment, the sending module 904 sends the input and output data to the high-speed serial computer expansion bus standard switching unit according to the data operation command through the network card, and sends the input and output data to the solid-state hard disk through the high-speed serial computer expansion bus standard switching unit. For the specific definition of the data processing device, please refer to the definition of the data processing method above, which will not be repeated here. The various modules in the above-mentioned data processing device can be implemented in whole or in part by software, hardware and their combination. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above-mentioned modules.

[0122] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be shown in Figure 10. The computer device includes a processor, a memory, a network interface, and a database connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer-readable instructions, and a database. The internal memory provides an environment for the operation of the operating system and computer-readable instructions in the non-volatile storage medium. The database of the computer device is used to store input and output data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer-readable instructions are executed by the processor, a data processing method is implemented.

[0123] Those skilled in the art will understand that the structure shown in FIG10 is merely a block diagram of a portion of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0124] In one embodiment, a computer device is provided, comprising a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor. When the processor executes the computer-readable instructions, the following steps are implemented: receiving a data operation command sent by a host through a network card, the data operation command carrying input and output data; sending the input and output data to a solid-state drive through the network card according to the data operation command; and operating a controller memory buffer through the solid-state drive according to the input and output data.

[0125] In one embodiment, the solid state drive further includes a controller, a flash memory device, and an internal direct random access memory, wherein the internal direct random access memory includes a controller memory buffer.

[0126] In one embodiment, when the data operation command is a data read command, the input and output data is address information, and the processor also implements the following steps when executing the computer-readable instruction: receiving the address information through the controller, sending the address information to the internal direct random access storage, determining the target address corresponding to the controller memory buffer according to the address information through the internal direct random access memory, and reading the target data from the target address in the controller memory buffer through the internal direct random access memory.

[0127] In one embodiment, when the processor executes the computer-readable instructions, it further implements the following steps: sending the target data to the controller through the internal direct random access memory, sending the target data to the network card as a read completion message through the controller, and returning the read completion message to the host through the network card.

[0128] In one embodiment, the controller memory buffer includes at least one buffer, and when the processor executes the computer-readable instructions, it also implements the following steps: determining a first target buffer in at least one buffer according to a target address through an internal direct random access memory, and reading target data from the first target buffer through the internal direct random access memory.

[0129] In one embodiment, when the data operation command is a data write command, the input and output data are the data to be written and the corresponding write address information. When the processor executes the computer-readable instruction, the following steps are also implemented: receiving the data to be written and the corresponding write address information through the controller, sending the data to be written and the corresponding write address information to the internal direct random access memory, determining the address to be written corresponding to the controller memory buffer according to the write address information through the internal direct random access memory, and writing the data to be written to the address to be written corresponding to the controller memory buffer through the internal direct random access memory.

[0130] In one embodiment, when the processor executes the computer-readable instructions, it also implements the following steps: obtaining the written data from the controller memory buffer through the internal direct random access memory, sending the written data to the flash memory device, storing the written data through the flash memory device, and generating a write completion message, sending it to the controller, sending the write completion message to the network card through the controller, and returning the write completion message to the host through the network card.

[0131] In one embodiment, the controller memory buffer includes at least one buffer, and when the processor executes the computer-readable instructions, it also implements the following steps: determining a second target buffer from at least one buffer according to the address to be written through the internal direct random access memory, and writing the data to be written to the second target buffer through the internal direct random access memory.

[0132] In one embodiment, the controller includes a first register and a second register, and the first register and the second register are respectively used to describe different attribute information of the controller memory buffer.

[0133] In one embodiment, the first register defines the location of the controller memory buffer, and the first attribute information corresponding to the first register is set to indicate that the controller supports the controller memory buffer.

[0134] In one embodiment, the second register defines the size of the controller memory buffer, and the second attribute information corresponding to the second register is set to indicate that the controller supports the controller memory buffer.

[0135] In one embodiment, when the processor executes the computer-readable instructions, it also implements the following steps: sending the input and output data to the high-speed serial computer expansion bus standard switching unit through the network card according to the data operation command, and sending the input and output data to the solid-state hard disk through the high-speed serial computer expansion bus standard switching unit.

[0136] In one embodiment, one or more non-volatile computer-readable storage media storing computer-readable instructions are provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by one or more processors, the following steps are implemented: receiving a data operation command sent by a host through a network card, the data operation command carries input and output data, sending the input and output data to a solid-state drive through the network card according to the data operation command, and operating a controller memory buffer according to the input and output data through the solid-state drive.

[0137] In one embodiment, the solid state drive further includes a controller, a flash memory device, and an internal direct random access memory, wherein the internal direct random access memory includes a controller memory buffer.

[0138] In one embodiment, when the data operation command is a data read command, the input and output data is address information, and the processor also implements the following steps when executing the computer-readable instruction: receiving the address information through the controller, sending the address information to the internal direct random access storage, determining the target address corresponding to the controller memory buffer according to the address information through the internal direct random access memory, and reading the target data from the target address in the controller memory buffer through the internal direct random access memory.

[0139] In one embodiment, when the processor executes the computer-readable instructions, it further implements the following steps: sending the target data to the controller through the internal direct random access memory, sending the target data to the network card as a read completion message through the controller, and returning the read completion message to the host through the network card.

[0140] In one embodiment, the controller memory buffer includes at least one buffer, and when the processor executes the computer-readable instructions, it also implements the following steps: determining a first target buffer in at least one buffer according to a target address through an internal direct random access memory, and reading target data from the first target buffer through the internal direct random access memory.

[0141] In one embodiment, when the data operation command is a data write command, the input and output data are the data to be written and the corresponding write address information. When the processor executes the computer-readable instruction, the following steps are also implemented: receiving the data to be written and the corresponding write address information through the controller, sending the data to be written and the corresponding write address information to the internal direct random access memory, determining the address to be written corresponding to the controller memory buffer according to the write address information through the internal direct random access memory, and writing the data to be written to the address to be written corresponding to the controller memory buffer through the internal direct random access memory.

[0142] In one embodiment, when the processor executes the computer-readable instructions, it also implements the following steps: obtaining the written data from the controller memory buffer through the internal direct random access memory, sending the written data to the flash memory device, storing the written data through the flash memory device, and generating a write completion message, sending it to the controller, sending the write completion message to the network card through the controller, and returning the write completion message to the host through the network card.

[0143] In one embodiment, the controller memory buffer includes at least one buffer, and when the processor executes the computer-readable instructions, it also implements the following steps: determining a second target buffer from at least one buffer according to the address to be written through the internal direct random access memory, and writing the data to be written to the second target buffer through the internal direct random access memory.

[0144] In one embodiment, the controller includes a first register and a second register, and the first register and the second register are respectively used to describe different attribute information of the controller memory buffer.

[0145] In one embodiment, the first register defines the location of the controller memory buffer, and the first attribute information corresponding to the first register is set to indicate that the controller supports the controller memory buffer.

[0146] In one embodiment, the second register defines the size of the controller memory buffer, and the second attribute information corresponding to the second register is set to indicate that the controller supports the controller memory buffer.

[0147] In one embodiment, when the processor executes the computer-readable instructions, it also implements the following steps: sending the input and output data to the high-speed serial computer expansion bus standard switching unit through the network card according to the data operation command, and sending the input and output data to the solid-state hard disk through the high-speed serial computer expansion bus standard switching unit.

[0148] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing related hardware through computer-readable instructions, and the computer-readable instructions can be stored in a non-volatile computer-readable storage medium. When the computer-readable instructions are executed, they may include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0149] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0150] The above embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A data processing method, the method being applied to a storage server, the storage server comprising a network card and a solid state drive, the solid state drive comprising a controller memory buffer, comprising: Receiving a data operation command sent by a host through the network card, the data operation command carrying input and output data; Sending the input and output data to the solid state drive through the network card according to the data operation command; and The controller memory buffer is operated according to the input and output data by the solid state drive.

2. The method according to claim 1, characterized in that: The solid state drive also includes a controller, a flash memory device, and an internal direct random access memory, wherein the internal direct random access memory includes the controller memory buffer.

3. The method according to claim 2, characterized in that When the data operation command is a data read command, the input / output data is address information, and the operating the controller memory buffer according to the input / output data through the solid state drive includes: receiving the address information through the controller, and sending the address information to the internal direct random access memory; Determining, by the internal direct random access memory, a target address corresponding to the controller memory buffer according to the address information; and Target data is read from the target address of the controller memory buffer through the internal direct random access memory.

4. The method according to claim 3, characterized in that: The method further comprises: sending the target data to the controller via the internal direct random access memory; Sending the target data to the network card via the controller with a read completion message; and The read completion message is returned to the host through the network card.

5. The method according to claim 3, characterized in that: The controller memory buffer includes at least one buffer, and the reading of target data from the target address of the controller memory buffer through the internal direct random access memory includes: determining, by the internal direct random access memory, a first target buffer among the at least one buffer according to the target address; and The target data is read from the first target buffer through the internal direct random access memory.

6. The method according to claim 2, characterized in that When the data operation command is a data write command, the input / output data is the data to be written and the corresponding write address information, and the operation on the controller memory buffer according to the input / output data by the solid state drive includes: receiving the data to be written and the corresponding write address information through the controller, and sending the data to be written and the corresponding write address information to the internal direct random access memory; Determining, by the internal direct random access memory, an address to be written corresponding to the controller memory buffer according to the write address information; and The data to be written is written into the address to be written corresponding to the controller memory buffer through the internal direct random access memory.

7. The method according to claim 6, characterized in that The method further comprises: Obtaining written data from the controller memory buffer through the internal direct random access memory, and sending the written data to the flash memory device; The written data is stored by the flash memory device, and a write completion message is generated and sent to the controller; Sending the write completion message to the network card through the controller; and The write completion message is returned to the host through the network card.

8. The method according to claim 6, characterized in that The controller memory buffer includes at least one buffer, and the step of writing the to-be-written data to the to-be-written address corresponding to the controller memory buffer through the internal direct random access memory includes: Determining a second target buffer from the at least one buffer according to the address to be written by the internal direct random access memory; and The to-be-written data is written into the second target buffer through the internal direct random access memory.

9. The method according to claim 2, characterized in that: The controller includes a first register and a second register, and the first register and the second register are respectively used to describe different attribute information of the controller memory buffer.

10. The method according to claim 9, characterized in that The first register defines a location of the controller memory buffer, and first attribute information corresponding to the first register is set as the controller supporting the controller memory buffer.

11. The method according to claim 9, characterized in that The second register defines the size of the controller memory buffer, and the second attribute information corresponding to the second register is set as the controller supporting the controller memory buffer.

12. The method according to claim 1, characterized in that The sending the input and output data to the solid state drive according to the data operation command through the network card includes: Sending the input and output data to a high-speed serial computer expansion bus standard switching unit through the network card according to the data operation command; and The input and output data are sent to the solid state hard disk via the high-speed serial computer expansion bus standard switching unit.

13. The method according to claim 1, characterized in that The operating the controller memory buffer according to the input and output data through the solid state drive includes: In response to the input / output data being data carried by a read command, data is read from a controller memory buffer according to the input / output data through the solid state drive.

14. The method according to claim 1, characterized in that The operating the controller memory buffer according to the input and output data through the solid state drive includes: In response to the input / output data being data carried by a data write command, data is written from a controller memory buffer according to the input / output data through the solid state drive.

15. The method according to claim 3, characterized in that The address information includes address block information and internal address information.

16. The method according to claim 6, characterized in that The write address information includes an address block to be written that is related to the write address.

17. The method according to claim 9, characterized in that The first register is CMBLOC, and / or the second register is CMBSZ.

18. A data processing device, characterized in that: The device is applied to a storage server, the storage server includes a network card and a solid state hard disk, the solid state hard disk includes a controller memory buffer, and includes: A receiving module, used for receiving a data operation command sent by a host through the network card, wherein the data operation command carries input and output data; a sending module, configured to send the input and output data to the solid state drive through the network card according to the data operation command; and An operation module is used to operate the controller memory buffer according to the input and output data through the solid state drive.

19. A server comprising a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor, characterized in that: When the processor executes the computer-readable instructions, the steps of the method according to any one of claims 1 to 17 are implemented.

20. One or more non-volatile computer-readable storage media storing computer-readable instructions, which, when executed by one or more processors, cause the one or more processors to perform the steps of the method of claims 1 to 17.

Images