Configurable multifunctional interference cancellation device implementation architecture

Abstract

The present application relates to the technical field of electromagnetic compatibility, radio frequency and digital signal processing, and provides a configurable multifunctional interference cancellation device implementation architecture. The present application solves the problem of how to configure a multifunctional combinable interference cancellation function device. The architecture comprises an ARM core, an FPGA core, a multi-channel zero intermediate frequency chip, a multi-channel radio frequency link, and a radio frequency coupling link which are connected in sequence. The FPGA core is further connected to the multi-channel radio frequency link and the radio frequency coupling link. The ARM core is used for system control and parameter calculation, and the FPGA core is used for signal processing. The multi-channel zero intermediate frequency chip cooperates with the multi-channel radio frequency link to generate and transmit a radio frequency signal and to receive a radio frequency signal. The radio frequency coupling link is used for the coupling and radio frequency modulation process of a radio frequency signal. Different interference cancellation links are formed by means of software configuration of the architecture. According to the present application, a plurality of different interference cancellation links can be configured on the basis of unified hardware, and therefore, the architecture can be widely used in various scenarios requiring interference cancellation functions.

Description

A configurable multifunctional interference cancellation device implementation architecture

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application number 202311724070.7, filed on December 14, 2023, entitled “A Configurable Multifunctional Interference Cancellation Device Implementation Architecture,” which is incorporated herein by reference in its entirety. Technical Field

[0003] The present application belongs to the field of electromagnetic compatibility, radio frequency and digital signal processing technology, and specifically is a configurable multifunctional interference cancellation device implementation architecture. Background Art

[0004] With the development of information technology, the demand for information exchange is also increasing, and the number of RF transceiver devices installed on the same information platform is also increasing. Limited platform size and spectrum resources inevitably cause mutual coupling interference between RF sensors through antennas. When there are only a few RF sensors, traditional filtering methods can be used to achieve transmit and receive isolation. However, when a large number of RF sensors are used simultaneously, especially when their frequency bands are close or overlapping, RF interference cannot be eliminated with traditional methods.

[0005] To address this type of RF interference, those skilled in the art have proposed interference cancellation solutions based on adaptive filtering technology. After years of research, interference cancellation has evolved into a variety of technical approaches, including RF interference cancellation, digital interference cancellation, and adaptive near-field nulling. While these approaches differ in their implementation, their core goal is to construct appropriate adaptive filters to cancel out interfering signals.

[0006] With the rapid development of integrated circuit technology, software-defined radio (SDR) architectures are increasingly being used in the field of radio communications. This software-centric architecture builds a universal radio platform, provides a signal processing framework for algorithm encapsulation, and offers a user interface, enabling different functions to be implemented through software control rather than hardware modifications.

[0007] Because the various technologies derived from interference cancellation share similar core concepts, implementing configurable, multifunctional interference cancellation equipment within a software-defined radio (SDR) architecture has become a more reasonable option. Therefore, those skilled in the art have begun designing related architectures, hoping to implement different interference cancellation functions through software configuration, and even to combine different interference cancellation functions for a more effective interference cancellation effect.

[0008] Summary of the Invention

[0009] Based on the current status of the background technology, the purpose of this application is to provide an interference cancellation device implementation architecture that has multi-functionality and high multiplexing characteristics, and enables multiple interference cancellation capabilities to be configured or combined on demand; the architecture of this application can configure a variety of different interference cancellation links on the basis of unified hardware, and therefore can be widely used in a variety of scenarios that require interference cancellation functions.

[0010] This application uses the following technical solutions to achieve the purpose:

[0011] A configurable multifunctional interference cancellation device implementation architecture comprises an ARM core, an FPGA core, a multi-channel zero-IF chip, a multi-channel radio frequency link, and a radio frequency coupling link, all connected in sequence. The FPGA core is also connected to the multi-channel radio frequency link and the radio frequency coupling link. The ARM core is used for system control and parameter calculation, and the FPGA core is used for signal processing. The multi-channel zero-IF chip cooperates with the multi-channel radio frequency link to generate and transmit radio frequency signals, as well as to receive radio frequency signals. The radio frequency coupling link is used for radio frequency signal coupling and radio frequency modulation. Different interference cancellation links are formed through software configuration of each component in the architecture.

[0012] Furthermore, the ARM core is used for interference cancellation link configuration and adaptive filtering calculation;

[0013] The ARM core configures the interference cancellation link as follows: receiving the interference cancellation configuration requirements issued by the control computer, calculating the link construction method of the hardware resources of the multi-functional interference cancellation device; configuring the FPGA core and the multi-channel zero-IF chip via a high-speed bus, and configuring the multi-channel RF link and the RF coupling link via a serial data line;

[0014] The adaptive filtering calculation process of the ARM core is as follows: initiating sampling of the useful signal and the reference signal, completing the timing synchronization of the useful signal and the reference signal through the autocorrelation algorithm; obtaining the adaptive filtering coefficient through the adaptive filtering algorithm, and sending it to the FPGA core for execution.

[0015] Furthermore, the FPGA core is used for data acquisition and as an adaptive filter; the data acquisition process cooperates with the ARM core to sample the useful signal and the reference signal; the adaptive filter is composed of a delay device, an FIR filter and an adder; the FPGA core is used to perform the following process:

[0016] The FPGA core receives the adaptive filter coefficients sent by the ARM core, configures the delay for the delay device, configures the adaptive filter coefficients for the FIR filter, and configures the signal index involved in the addition for the adder; the useful signal and the reference signal pass through the delay device and the FIR filter, and then pass through the adder to synthesize the canceled signal according to the configuration of the hardware link, and then output it to the outside.

[0017] Furthermore, the multi-channel zero-IF chip is used to configure frequency and bandwidth parameters under the control of the FPGA core, and the specific process is: converting the output baseband signal into a radio frequency signal for transmission, and converting the received radio frequency signal into a baseband signal;

[0018] The multi-channel RF link includes a preamplifier link corresponding to the received RF signal and a power amplifier corresponding to the transmitted RF signal; the multi-channel RF link is used to: amplify the received RF signal and suppress the noise coefficient of the RF signal; amplify the transmitted RF signal to make it meet the power requirements of RF interference cancellation.

[0019] Furthermore, the RF coupling link is used to: construct an auxiliary receiving channel through coupling during the digital interference cancellation process, construct an auxiliary transmitting branch during the RF interference cancellation process, complete the modulation and elimination of the RF signal during the RF interference cancellation process, and serve as a direct channel for adaptive nulling and digital interference cancellation functions.

[0020] In summary, due to the adoption of this technical solution, the beneficial effects of this application are as follows:

[0021] The interference cancellation device implementation architecture proposed in this application can be directly configured as an RF interference cancellation link based on an auxiliary transmitting branch, an RF interference cancellation link based on RF amplitude and phase adjustment, a digital interference cancellation link based on an auxiliary receiving branch, a digital interference cancellation link based on a baseband signal, and a beam adaptive near-field nulling interference cancellation link.

[0022] The architecture of the present application therefore has the ability to construct multiple interference cancellation links, and through specific configuration, different interference cancellation functions can be realized, which can be combined to form a stronger interference cancellation effect, achieving multi-functionality and high multiplexing characteristics, and is extremely suitable for application in various scenarios requiring interference cancellation. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG1 is a schematic diagram showing the principle of the implementation architecture of the interference cancellation device of the present application;

[0024] FIG2 is a schematic diagram of the basic unit structure of a multi-channel radio frequency link;

[0025] Figure 3 is a schematic diagram of the basic source structure of the RF coupling link;

[0026] FIG4 is a schematic diagram of a radio frequency interference cancellation link based on an auxiliary transmission branch;

[0027] FIG5 is a schematic diagram of a radio frequency interference cancellation link based on radio frequency amplitude and phase adjustment;

[0028] FIG6 is a schematic diagram of a digital interference cancellation link based on an auxiliary receiving branch;

[0029] FIG7 is a schematic diagram of a digital interference cancellation link based on baseband signals;

[0030] FIG8 is a schematic diagram of a beam-adaptive near-field nulling interference cancellation link. DETAILED DESCRIPTION

[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0032] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0033] Example 1

[0034] A configurable multifunctional interference cancellation device implementation architecture is shown in Figure 1. The architecture comprises an ARM core, an FPGA core, multiple zero-IF chips, a multi-channel RF link, and an RF coupling link, all connected in sequence. The FPGA core is also connected to the multi-channel RF link and the RF coupling link. The ARM core is used for system control and parameter calculation, while the FPGA core is used for signal processing. The multiple zero-IF chips cooperate with the multi-channel RF link to generate and transmit RF signals, as well as receive RF signals. The RF coupling link is used for RF signal coupling and RF modulation. Different interference cancellation links are formed through software configuration of each component in the architecture.

[0035] This embodiment will introduce the details of each component of the above architecture in detail. In this embodiment, the number of multi-channel zero-IF chips and the number of channels of the multi-channel RF link can be adjusted according to actual needs.

[0036] First, the ARM core can realize interference cancellation link configuration and adaptive filtering calculation functions.

[0037] The steps for configuring the interference cancellation link function are as follows:

[0038] (1) Accepting interference cancellation configuration requirements issued by the control computer, which may include specific parameters such as the type of interference cancellation to be applied and the number of links to be configured;

[0039] (2) A link construction method for calculating the hardware resources of a multifunctional interference cancellation device;

[0040] (3) Configure the FPGA core and multi-channel zero-IF chips through a high-speed bus, and configure the multi-channel RF link and RF coupling link through a serial data line.

[0041] The steps of adaptive filtering calculation function are as follows:

[0042] (1) Initiate sampling of the useful signal and the reference signal;

[0043] (2) Achieve timing synchronization between the useful signal and the reference signal through the autocorrelation algorithm;

[0044] (3) using an adaptive filtering algorithm such as a recursive least squares method or a least mean square algorithm to obtain adaptive filtering coefficients;

[0045] (4) Send the adaptive filter coefficients to the FPGA core for execution.

[0046] In this embodiment, the FPGA core implements data acquisition and adaptive filtering. The data acquisition function cooperates with the ARM core to sample the useful signal and the reference signal. The adaptive filter is composed of a delay, an FIR filter, and an adder. Its functional implementation steps are as follows:

[0047] (1) The FPGA core receives the adaptive filter coefficients sent by the ARM core, configures the delay to the delayer, configures the filter coefficients to the FIR filter, and configures the signal index involved in the addition to the adder;

[0048] (2) The useful signal and the reference signal pass through a time delay device and an FIR filter, and are synthesized into a canceled signal by an adder according to the configuration of the hardware link, and then output to the outside.

[0049] In this embodiment, the multi-channel zero-IF chip is controlled by the FPGA core to configure its frequency, bandwidth and other related parameters. Its functions are as follows:

[0050] (1) Convert the output baseband signal into a radio frequency signal for transmission;

[0051] (2) Convert the received RF signal into a baseband signal.

[0052] In this embodiment, the multi-channel radio frequency link includes a preamplifier link for receiving signals and a power amplifier for transmitting signals, which functions as follows:

[0053] (1) Amplify the received signal and suppress the noise coefficient;

[0054] (2) Amplify the transmitted signal to meet the power requirements of radio frequency interference cancellation.

[0055] The basic unit of a multi-channel RF link is shown in FIG2 . A multifunctional interference cancellation device may include multiple basic units of RF links.

[0056] In this embodiment, the functions of the radio frequency coupling link include:

[0057] (1) Constructing auxiliary receiving channels by coupling in the process of digital interference cancellation;

[0058] (2) Constructing auxiliary transmission branches during the RF interference cancellation process;

[0059] (3) Complete the modulation and elimination of RF signals during the RF interference cancellation process;

[0060] (4) Serves as a direct channel for adaptive nulling and digital interference cancellation functions.

[0061] The basic unit of the radio frequency coupling link is shown in FIG3 . A multifunctional interference cancellation device may include multiple basic units of the radio frequency coupling link.

[0062] Example 2

[0063] Based on Example 1, the architecture of this application can implement different interference cancellation functions through software configuration. This embodiment introduces in detail the specific methods of five different configurations.

[0064] 1. Radio Frequency Interference Cancellation Link Based on Auxiliary Transmitter Branch

[0065] As shown in Figure 4, in this link, the FPGA core collects the transmitted baseband signal and the baseband signal received through the receiving link, calculates the weight of the adaptive filter, and assigns it to the auxiliary transmitting branch. After being converted into an RF signal by multiple zero-IF chips, it is amplified by an amplifier and then coupled to the receiving channel through a directional coupler to complete the elimination of the transmitted RF signal.

[0066] 2. RF Interference Cancellation Link Based on RF Amplitude and Phase Adjustment

[0067] As shown in Figure 5, in this link, the FPGA core collects the transmitted baseband signal and the baseband signal received through the receiving link, calculates the weight of the adaptive filter, and configures it to the vector modulator of the RF coupling link. The RF signal coupled from the transmitting channel is modulated in amplitude and phase by the vector modulator and then coupled to the receiving channel, completing the interference cancellation process.

[0068] 3. Digital Interference Cancellation Link Based on Auxiliary Receive Branch

[0069] As shown in Figure 6, in this link, the RF coupling link couples the transmitted RF signal to the auxiliary receiving channel through a directional coupler, and calculates the adaptive filtering weights together with the received RF signal. The weights are then configured to the adaptive filter in the FPGA core to complete the interference cancellation process, and the results are then output to the interfered device for subsequent processing.

[0070] 4. Digital Interference Cancellation Link Based on Baseband Signals

[0071] As shown in Figure 7, in this link, the FPGA core collects the transmitted baseband signal and the baseband signal received through the receiving link, calculates the weight of the adaptive filter, and configures it to the adaptive filter in the FPGA core to complete the process of canceling the interference signal in the received baseband signal.

[0072] 5. Beam-Adaptive Near-Field Nulling Interference Cancellation Link

[0073] As shown in Figure 8, in this link, the FPGA core collects the transmitted baseband signal and the baseband signal received through the receiving link, calculates the weights of the adaptive filter, and configures it to perform amplitude and phase modulation operations on the transmitting array. This creates a null in the electric field reaching the receiver during transmission, completing the interference elimination process.

Claims

1. A configurable multifunctional interference cancellation device implementation architecture, the architecture comprising an ARM core, an FPGA core, a multi-channel zero intermediate frequency chip, a multi-channel radio frequency link and a radio frequency coupling link connected in sequence, the FPGA core is also connected to the multi-channel radio frequency link and the radio frequency coupling link; the ARM core is used for system control and parameter calculation, and the FPGA core is used for signal processing; the multi-channel zero intermediate frequency chip cooperates with the multi-channel radio frequency link to generate and transmit radio frequency signals, and receive radio frequency signals; the radio frequency coupling link is used for the coupling and radio frequency modulation process of radio frequency signals; different interference cancellation links are formed by software configuration of each component in the architecture.

2. A configurable multifunctional interference cancellation device implementation architecture according to claim 1, wherein: The ARM core is used for interference cancellation link configuration and adaptive filtering calculation; The configuration process of the ARM core for the interference cancellation link is: receiving the interference cancellation configuration requirements issued by the control computer, calculating the link construction method of the hardware resources of the multi-functional interference cancellation device; configuring the FPGA core and the multi-channel zero intermediate frequency chip through the high-speed bus, and configuring the multi-channel radio frequency link and the radio frequency coupling link through the serial data line; The adaptive filtering calculation process of the ARM core is: initiating sampling of the useful signal and the reference signal, completing the timing synchronization of the useful signal and the reference signal through the autocorrelation algorithm; obtaining the adaptive filtering coefficient through the adaptive filtering algorithm, and sending it to the FPGA core for execution.

3. A configurable multifunctional interference cancellation device implementation architecture according to claim 2, wherein: The FPGA core is used for data acquisition and as an adaptive filter; the data acquisition process cooperates with the ARM core to sample the useful signal and the reference signal; The adaptive filter is composed of a delay device, a FIR filter and an adder; the FPGA core is used to perform the following process: The FPGA core receives the adaptive filter coefficients sent by the ARM core, configures the delay for the delay device, configures the adaptive filter coefficients for the FIR filter, and configures the signal index participating in the addition for the adder; the useful signal and the reference signal pass through the delay device and the FIR filter, and then through the adder, synthesize the canceled signal according to the configuration of the hardware link, and then output it to the outside.

4. A configurable multifunctional interference cancellation device implementation architecture according to claim 1, wherein: The multi-channel zero intermediate frequency chip is used to configure the frequency and bandwidth parameters under the control of the FPGA core. The specific process is: converting the output baseband signal into a radio frequency signal for transmission, and converting the received radio frequency signal into a baseband signal; The multi-channel RF link includes a preamplifier link corresponding to the received RF signal and a power amplifier corresponding to the transmitted RF signal; the multi-channel RF link is used to: amplify the received RF signal and suppress the noise coefficient of the RF signal; amplify the transmitted RF signal to meet the power requirements of RF interference cancellation.

5. A configurable multifunctional interference cancellation device implementation architecture according to claim 1, wherein: The RF coupling link is used to: construct an auxiliary receiving channel by coupling in the process of digital interference cancellation, construct an auxiliary transmitting branch in the process of RF interference cancellation, complete the modulation and elimination of RF signals in the process of RF interference cancellation, and serve as a direct channel for adaptive nulling and digital interference cancellation functions.

6. A configurable multifunctional interference cancellation device implementation architecture according to claim 1, wherein: Through software configuration of the architecture, a radio frequency interference cancellation link based on the auxiliary transmission branch is formed; In this link, the FPGA core collects the transmitted baseband signal and the baseband signal received through the receiving link, calculates the weight of the adaptive filter, and configures it to the auxiliary transmitting branch; after being converted into a radio frequency signal by the multi-channel zero intermediate frequency chip, it is amplified by the amplifier and then coupled to the receiving channel through a directional coupler to complete the elimination of the transmitted radio frequency signal.

7. A configurable multifunctional interference cancellation device implementation architecture according to claim 1, wherein: Through software configuration of the architecture, an RF interference cancellation link based on RF amplitude and phase adjustment is formed; In this link, the FPGA core collects the transmitted baseband signal and the baseband signal received through the receiving link, calculates the weight of the adaptive filter, and configures it to the vector modulator of the RF coupling link. The RF signal coupled from the transmitting channel is modulated in amplitude and phase by the vector modulator and then coupled to the receiving channel to complete the interference cancellation process.

8. A configurable multifunctional interference cancellation device implementation architecture according to claim 1, wherein: Through software configuration of the architecture, a digital interference cancellation link based on the auxiliary receiving branch is formed; In this link, the RF coupling link couples the transmitted RF signal to the auxiliary receiving channel through a directional coupler, and calculates the adaptive filtering weights together with the received RF signal, and then configures the weights to the adaptive filter in the FPGA core to complete the interference cancellation process, and then outputs the results to the interfered device for subsequent processing.

9. A configurable multifunctional interference cancellation device implementation architecture according to claim 1, wherein: Through software configuration of the architecture, a digital interference cancellation link based on baseband signals is formed; In this link, the FPGA core collects the transmitted baseband signal and the baseband signal received through the receiving link, calculates the weight of the adaptive filter, and configures it to the adaptive filter in the FPGA core to complete the cancellation process of the interference signal in the received baseband signal.

10. The configurable multifunctional interference cancellation device implementation architecture according to claim 1, wherein: Through software configuration of the architecture, a beam-adaptive near-field null-stuck interference cancellation link is formed; In this link, the FPGA core collects the transmitted baseband signal and the baseband signal received through the receiving link, calculates the weight of the adaptive filter, and configures it to the transmitting array for amplitude and phase modulation operations, so that the electric field reaching the receiver position when the transmitting array transmits forms a null, completing the interference elimination process.

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