Silicon bridge module integrated with passive device, and manufacturing method for silicon bridge module

Abstract

Provided in the present invention is a silicon bridge module integrated with a passive device. The silicon bridge module comprises a substrate, a first insulating layer, which is arranged on a first surface of the substrate, a capacitor, which is arranged on a surface of the first insulating layer, a second insulating layer, which is arranged on a surface of the capacitor and exposes at least part of an electrode of the capacitor, a first metal interconnection layer, which is arranged on a surface of the second insulating layer and is electrically connected to the capacitor, and an external pad, which is arranged on the outermost layer of the first metal interconnection layer and is electrically connected to the first metal interconnection layer, wherein the first metal interconnection layer comprises one or more layers of conductive lines and an insulating medium arranged between the conductive lines, and an inductive device is integrated in the first metal interconnection layer. The silicon bridge module achieves the integration of an inter-chip interconnection line and a passive device, integrates processing functions for signals or power distribution networks and achieves high-speed signal transmission, improves the integration degree of a system, reduces the packaging volume, and can be applied in the field of heterogeneous integrated products, e.g., chiplets.

Description

Silicon bridge module with integrated passive devices and manufacturing method thereof Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a silicon bridge module integrating passive devices and a manufacturing method thereof. Background Art

[0002] With the rapidly increasing demand for higher-performance and more versatile chips in electronic devices, and with integrated circuit manufacturing processes approaching the physical limits of size, Moore's Law has reached a bottleneck, ushering in the chip industry into a "post-Moore era." Simply relying on feature size reduction is no longer sufficient to meet the demand for continued improvement in chip performance. Against this backdrop, achieving systematic integration of multiple chips through advanced packaging has become a key approach to improving chip performance.

[0003] Among heterogeneous chip integration methods, embedded silicon bridges can reduce package area, lower the difficulty and cost of package processing, and enable high-density interconnection between chips, making them a mainstream advanced packaging solution. However, existing silicon bridges only enable planar interconnection and fail to consider vertical communication. Furthermore, existing silicon bridges fail to consider signal or power transmission processing requirements, such as filtering and decoupling. Consequently, there are no implementations for introducing passive components such as capacitors and inductors into embedded silicon bridges.

[0004] Passive components also play a crucial role in power and signal transmission within the package. For example, heterogeneous integration requires a robust power delivery network (PDN) to ensure stable operation of each chip. However, these passive components are often integrated as discrete components within the integrated circuit, limiting the overall area and volume reduction potential of heterogeneous chip integration. Furthermore, they typically require long trace lengths, which can lead to strong parasitic effects and thus limit the overall performance and stability of the package.

[0005] Summary of the Invention

[0006] In order to address some or all of the problems in the prior art, the present invention provides, in a first aspect, a silicon bridge module with integrated passive components. This module utilizes wafer-level processing to achieve three-dimensional integration of a silicon bridge and passive components. Furthermore, a TSV structure is integrated within the three-dimensional silicon bridge to achieve vertical interconnection of power or signals, thereby improving system integration and facilitating highly reliable communication between high-performance chips. The silicon bridge module comprises:

[0007] a substrate, a first surface of which is provided with a first insulating layer;

[0008] a capacitor, which is arranged on the surface of the first insulating layer;

[0009] a second insulating layer disposed on a surface of the capacitor but exposing at least a portion of the electrodes of the capacitor;

[0010] a first metal interconnection layer, which is disposed on a surface of the second insulating layer and includes one or more layers of conductive lines and an insulating medium disposed between the conductive lines, wherein the capacitor is electrically connected to the first metal interconnection layer;

[0011] an inductor device integrated into the metal interconnect layer; and

[0012] The external pad is arranged on the outermost layer of the first metal interconnection layer and is electrically connected to the first metal interconnection layer.

[0013] Furthermore, the capacitor is a deep trench capacitor, which is arranged in a deep trench of the substrate, and the deep trench capacitor includes a first electrode layer, a dielectric layer and a second electrode layer, wherein the first electrode layer and the second electrode layer are electrically connected to the first metal interconnection layer.

[0014] Furthermore, the capacitor is a planar capacitor, which is arranged on the surface of the insulating layer and includes a first electrode layer, a dielectric layer and a second electrode layer, wherein the first electrode layer and the second electrode layer are electrically connected to the first metal interconnection layer.

[0015] Furthermore, the silicon bridge module further includes a through silicon via (TSV), which passes through the substrate and has a first end electrically connected to the first metal interconnection layer and a second end exposed to a second surface of the substrate opposite to the first surface thereof.

[0016] Furthermore, the silicon bridge module also includes a second metal interconnection layer, which is arranged on the second surface of the substrate and includes one or more layers of conductive lines and an insulating medium arranged between the conductive lines. The second end of the silicon through-via is electrically connected to the second metal interconnection layer.

[0017] A second aspect of the present invention provides a method for manufacturing the aforementioned silicon bridge module, comprising:

[0018] Depositing a first insulating layer on the surface of the silicon wafer to form a capacitor, wherein the capacitor includes a first electrode layer, a dielectric layer and a second electrode layer;

[0019] Depositing a second insulating layer on the surface of the second electrode layer and opening windows to lead out the first electrode layer and the second electrode layer;

[0020] forming a first metal interconnection layer on a surface of the second insulating layer, wherein the first metal interconnection layer includes an inductor coil structure;

[0021] Prepare external pads on the surface of the first metal interconnection layer; and

[0022] The back side of the silicon wafer is thinned and cut into individual silicon bridges.

[0023] Further, depositing a first insulating layer and forming a capacitor includes:

[0024] Etching a deep silicon trench on a first surface of the silicon wafer;

[0025] Depositing a first insulating layer on the first surface of the silicon wafer and the surface of the deep silicon trench; and

[0026] The deep silicon trench is filled with a first electrode, a dielectric material and a second electrode in sequence.

[0027] Further, depositing a first insulating layer and forming a capacitor includes:

[0028] Depositing a first insulating layer on the surface of the silicon wafer;

[0029] preparing a first electrode layer and a portion of the first metal interconnection layer on the surface of the first insulating layer;

[0030] Depositing an intermediate insulating layer on the surface of the first electrode layer and the circuit, but exposing at least a portion of the surface of the first electrode layer for depositing a dielectric material;

[0031] Opening windows in the intermediate insulating layer to lead out the first electrode layer and the external pads of the circuit; and

[0032] A second electrode layer and a portion of the circuits of the first metal interconnection layer are formed on the intermediate insulating layer.

[0033] Furthermore, the manufacturing method further comprises:

[0034] forming a through silicon via on the silicon wafer, wherein a first end of the through silicon via is electrically connected to the first metal interconnection layer; and / or

[0035] The second surface of the silicon wafer is ground and thinned to expose the through silicon via, and a second metal interconnection layer is formed on the second surface of the silicon wafer, wherein the second end of the through silicon via is electrically connected to the second metal interconnection layer.

[0036] A third aspect of the present invention provides a packaging structure, which includes the silicon bridge module as described above.

[0037] The present invention provides a silicon bridge module with integrated passive devices. This structure, fabricated through wafer-level processing, achieves the integrated integration of inter-chip interconnects and passive components. While enabling high-speed signal transmission, it also integrates processing functions for signal or power transmission networks, improving system integration and saving packaging volume. Furthermore, the module is compatible with existing packaging processes and is technologically feasible. The silicon bridge module can be applied to heterogeneous integrated products such as chiplets. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more detailed description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings depict only typical embodiments of the present invention and are not to be considered as limiting the scope thereof. In the drawings, for clarity, identical or corresponding components will be represented by the same or similar reference numerals.

[0039] FIG1 is a schematic structural diagram of a silicon bridge module with integrated passive devices according to an embodiment of the present invention;

[0040] FIG2 is a schematic structural diagram of a silicon bridge module with integrated passive devices according to another embodiment of the present invention;

[0041] FIG3 shows a schematic structural diagram of a silicon bridge module with integrated passive devices according to yet another embodiment of the present invention;

[0042] FIG4 shows a schematic structural diagram of a silicon bridge module with integrated passive devices according to yet another embodiment of the present invention;

[0043] 5a to 5d are schematic structural diagrams respectively showing different packaging structures of silicon bridge modules according to different embodiments of the present invention;

[0044] FIG6 is a schematic flow chart showing a method for manufacturing a silicon bridge module with integrated passive devices according to an embodiment of the present invention;

[0045] 7a to 7e are schematic diagrams showing a process of manufacturing a silicon bridge module with integrated passive devices according to an embodiment of the present invention;

[0046] 8a to 8e are schematic diagrams showing a process of manufacturing a silicon bridge module with integrated passive devices according to yet another embodiment of the present invention;

[0047] 9a to 9e are schematic diagrams showing a process of manufacturing a silicon bridge module with integrated passive devices according to yet another embodiment of the present invention; and

[0048] 10 a to 10 e are schematic process diagrams showing a method for manufacturing a silicon bridge module with integrated passive devices according to yet another embodiment of the present invention. DETAILED DESCRIPTION

[0049] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that the various embodiments can be implemented without one or more of the specific details or with other alternative and / or additional methods, materials, or components. In other cases, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the inventive aspects of the present invention. Similarly, for the purpose of explanation, specific quantities, materials, and configurations are described to provide a comprehensive understanding of the embodiments of the present invention. However, the present invention is not limited to these specific details. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0050] In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in various places in this specification are not necessarily all referring to the same embodiment.

[0051] It should be noted that the embodiments of the present invention describe the process steps in a specific order. However, this is only for the purpose of illustrating the specific embodiment and does not limit the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to the process.

[0052] In view of the fact that existing silicon bridges do not consider integrating passive devices into the silicon bridge, the passive devices often need to be integrated in the form of discrete devices, which in turn causes disadvantages such as high space occupancy and large parasitic effects. The present invention provides a silicon bridge module with integrated passive devices, which integrates the integrated passive devices into the silicon bridge through a three-dimensional stacking method, thereby realizing the integrated integration of high-density interconnected silicon bridges and silicon-based integrated passive devices.

[0053] Specifically, a silicon bridge module with integrated passive devices includes a substrate, a first insulating layer disposed on a first surface of the substrate, a capacitor disposed on the surface of the first insulating layer, a second insulating layer disposed on the surface of the capacitor but exposing at least a portion of the capacitor's electrodes, a first metal interconnect layer disposed on the surface of the second insulating layer and electrically connected to the capacitor, and an external pad disposed on the outermost layer of the first metal interconnect layer and electrically connected to the first metal interconnect layer. In some embodiments of the present invention, the silicon bridge module further includes a through-silicon via (TSV) penetrating the substrate and electrically connected to the first metal interconnect layer, and / or a second metal interconnect layer disposed on the second surface of the substrate and electrically connected to the TSV.

[0054] In an embodiment of the present invention, the capacitor may be a deep trench capacitor or a planar capacitor. The silicon bridge module may have different structures based on different capacitor types and whether there are through silicon vias.

[0055] Figures 1 to 4 illustrate the structures of different silicon bridge modules according to various embodiments of the present invention. The silicon bridge module shown in Figure 1 utilizes deep trench capacitors without TSVs; the silicon bridge module shown in Figure 2 utilizes deep trench capacitors with TSVs; the silicon bridge module shown in Figure 3 utilizes planar capacitors without TSVs; and the silicon bridge module shown in Figure 4 utilizes planar capacitors with TSVs.

[0056] The structure and manufacturing method of each silicon bridge module will be further described below with reference to the drawings of each embodiment.

[0057] The silicon bridge module shown in Figure 1 includes a substrate 101, a first insulating layer 121, a second insulating layer 122, a deep trench capacitor 131, a first metal interconnect layer 141, an inductor 107, and an external pad 105. The deep trench capacitor 131 is arranged in a deep silicon trench on the first surface of the substrate 101, and includes a first electrode layer 1311, a dielectric layer 1312, and a second electrode layer 1313. The deep trench capacitor 131 is isolated from the substrate 101 by the first insulating layer 121. In one embodiment of the present invention, the substrate 101 is made of silicon. In one embodiment of the present invention, the first metal interconnect layer 141 includes one or more layers of conductive lines and an insulating medium provided between the conductive lines. The inductor 107 is integrated into the first metal interconnect layer 141. In one embodiment of the present invention, the inductor includes an inductor coil structure.

[0058] The silicon bridge module shown in Figure 2 has a substantially identical structure to the silicon bridge module shown in Figure 1 , differing only in that it further includes a through-silicon via (TSV) 106. The TSV 106 extends through the substrate 101, with a first end electrically connected to the first metal interconnect layer 141 and a second end exposed to the second surface of the substrate 101. For example, the second end may be provided with an external bonding pad electrically connected thereto, or a second metal interconnect layer 142. Similarly, the second metal interconnect layer 142 includes one or more layers of conductive circuitry and an insulating medium disposed between the conductive circuitry.

[0059] The silicon bridge module shown in Figure 3 differs from the silicon bridge module shown in Figure 1 in its capacitor type. It includes a substrate 101, a first insulating layer 121, a second insulating layer 122, an intermediate insulating layer 123, a planar capacitor 132, a first metal interconnect layer 141, an inductor 107, and an external pad 105. The planar capacitor 132 is disposed on the surface of the first insulating layer 121 and includes a first electrode layer 1321, a dielectric layer 1322, and a second electrode layer 1323. As shown, the first electrode layer 1321 is disposed on the surface of the first insulating layer 121, but does not cover the entire first insulating layer 121. The surface of the first insulating layer not provided with the first electrode layer can simultaneously form a portion of the first metal interconnect layer's circuitry. The dielectric layer 1322 is disposed on the surface of the first electrode layer 1321, but does not cover the entire first electrode layer, to facilitate the extraction of the first electrode layer. The second electrode layer 1323 is disposed on the surface of the dielectric layer 1322 and has substantially the same dimensions as the dielectric layer 1322. Similarly, part of the circuits of the first metal interconnection layer may also be formed simultaneously around the second electrode layer 1323 .

[0060] The silicon bridge module shown in FIG4 has a substantially identical structure to the silicon bridge module shown in FIG3 , differing only in that it further includes a through-silicon via (TSV) 106. The TSV 106 penetrates the substrate 101, with a first end electrically connected to the first metal interconnect layer 141 and a second end exposed to the second surface of the substrate 101. For example, the second end may be provided with an external pad electrically connected thereto, or with the second metal interconnect layer 142.

[0061] As described above, various silicon bridge modules can be applied to fan-out packaging or FCBGA packaging structures using embedded substrates. Figures 5a to 5d respectively show schematic structural diagrams of different packaging structures including silicon bridge modules according to different embodiments of the present invention. Figures 5a and 5b respectively show the application of a silicon bridge module 001 without a through-silicon via structure in a fan-out packaging and an FCBGA using an embedded substrate. As shown in the figure, the silicon bridge module can be electrically connected to the chip and circuit in the packaging structure directly or through a rewiring structure. Figures 5c and 5d respectively show the application of a silicon bridge module 002 with a through-silicon via structure in a fan-out packaging and an FCBGA using an embedded substrate. As shown in the figure, the silicon bridge module with through-silicon vias can further realize the vertical connection of chips and other devices in the packaging structure.

[0062] FIG6 is a flow chart showing a method for manufacturing a silicon bridge module with integrated passive devices according to an embodiment of the present invention. As shown in FIG6 , the method for manufacturing the silicon bridge module includes:

[0063] First, in step 601, a first insulating layer is deposited on the surface of a silicon wafer;

[0064] Next, in step 602, a capacitor is formed on the surface of the first insulating layer, wherein the capacitor includes a first electrode layer, a dielectric layer, and a second electrode layer;

[0065] Next, in step 603, a second insulating layer is deposited on the surface of the second electrode layer of the capacitor, and a window is opened to lead out the first electrode and the second electrode of the capacitor;

[0066] Next, in step 604, a first metal interconnection layer is formed. The first metal interconnection layer is formed on the surface of the second insulating layer, wherein the first metal interconnection layer includes an inductor coil structure;

[0067] Next, in step 605, an external pad is prepared. An external pad is prepared on the surface of the first metal interconnection layer; and

[0068] Finally, in step 606, the wafer is cut. The back side of the silicon wafer is thinned and cut to obtain individual silicon bridges.

[0069] In one embodiment of the present invention, the silicon bridge module has through-silicon vias and / or a second metal interconnection layer. Therefore, during the preparation process, it is also necessary to perform processes such as through-silicon via etching, insulation layer deposition, filling and planarization in the silicon wafer, and finally form a second metal interconnection layer on the second surface of the silicon wafer after the through-silicon vias are exposed.

[0070] Figures 7a to 7e illustrate a process diagram of a method for manufacturing a silicon bridge module using deep trench capacitors and without through silicon vias. As shown in the figure, the method for manufacturing a silicon bridge module using deep trench capacitors and without through silicon vias includes:

[0071] First, as shown in FIG7 a , a deep silicon trench is etched on the first surface of the silicon wafer 101 and a first insulating layer 121 is deposited. Subsequently, a first electrode layer 1311 , a High K dielectric material 1312 and a second electrode layer 1313 are sequentially filled to form a deep trench capacitor 131 .

[0072] Next, as shown in FIG7 b , a second insulating layer 122 is deposited to cover the second electrode layer, and a window is opened on the second insulating layer to realize the extraction of the first electrode layer and the second electrode layer;

[0073] Next, as shown in FIG7 c , multiple layers of interconnects and dielectric layers are alternately prepared to form a first metal interconnect layer 141 , wherein an inductor coil structure 107 may be introduced into the interconnects, and external pads 105 are prepared on the surface of the interconnects to facilitate subsequent connection with the chip.

[0074] Next, as shown in FIG7 d , the second surface of the silicon wafer is thinned; and

[0075] Finally, as shown in FIG7 e , the chip is cut to prepare a single silicon bridge.

[0076] Figures 8a to 8e illustrate a process diagram of a method for manufacturing a silicon bridge module using deep trench capacitors and having through silicon vias. As shown in the figure, the method for manufacturing a silicon bridge module using deep trench capacitors and having through silicon vias includes:

[0077] First, as shown in FIG8 a , a deep silicon trench is etched on the first surface of the silicon wafer 101 and a first insulating layer 121 is deposited. Subsequently, a first electrode layer 1311 , a High K dielectric material 1312 and a second electrode layer 1313 are sequentially filled to form a deep trench capacitor 131 .

[0078] Next, as shown in FIG8 b , etching of the through silicon via 106 , deposition of the second insulating layer 122 , filling and planarization processes are performed to form a through silicon via;

[0079] Next, as shown in FIG8c , windows are opened on the second insulating layer to allow the first electrode layer and the second electrode layer to be led out. Multiple layers of interconnects and dielectric layers are then alternately formed on the surface of the second insulating layer to form a first metal interconnect layer 141. An inductor coil structure 107 may be introduced into the interconnects, and external pads 105 are formed on the surface of the interconnects to facilitate subsequent connection to the chip.

[0080] Next, as shown in FIG8 d , a temporary bonding plate 003 is provided on the surface of the first metal interconnect layer, and the second surface of the silicon wafer is thinned to expose the through-silicon vias, and a second metal interconnect structure 142 is formed on the second surface of the silicon wafer or an external pad is formed at the end surface of the through-silicon vias; and

[0081] Finally, as shown in FIG8 e , the temporary bonding plate is removed and the chip is cut to prepare a single silicon bridge.

[0082] Figures 9a to 9e illustrate a process diagram of a method for manufacturing a silicon bridge module using planar capacitors and without through-silicon vias. As shown in the figure, the method for manufacturing a silicon bridge module using planar capacitors and without through-silicon vias includes:

[0083] First, as shown in FIG9 a , a first insulating layer 121 is deposited on the first surface of the silicon wafer 101 , and a first electrode layer 1321 and a portion of circuits in the same stack as the first electrode layer are prepared;

[0084] Next, as shown in FIG9 b , an intermediate insulating layer 123 and a High K dielectric material 1322 are deposited, wherein the High K dielectric material is embedded in the intermediate insulating layer. Then, windows are opened in the intermediate insulating layer to realize the extraction of the first electrode layer and interlayer interconnection. A second electrode layer 1323 is formed to form a planar capacitor 132, and interconnection lines are formed in the same stack layer with the second electrode layer.

[0085] Next, as shown in FIG9 c , a second insulating layer 122 is deposited to cover the second electrode layer, and a window is opened in the second insulating layer to realize the extraction of the second electrode layer. Then, multiple layers of interconnection lines and dielectric layers are alternately formed to form a first metal interconnection layer 141. Inductor coil structures 107 can be introduced into the interconnection lines, and external bonding pads 105 are formed on the surface of the interconnection lines to facilitate subsequent connection with the chip.

[0086] Next, as shown in FIG9 d , the second surface of the silicon wafer is thinned; and

[0087] Finally, as shown in FIG9e , the chip is cut to produce a single silicon bridge.

[0088] Figures 10a to 10e are schematic diagrams showing a process of manufacturing a silicon bridge module using planar capacitors and having through-silicon vias. As shown in the figure, the method of manufacturing a silicon bridge module using planar capacitors and having through-silicon vias includes:

[0089] First, as shown in FIG10 a , etching of the through silicon via 106 , deposition of the first insulating layer 121 , filling and planarization processes are performed on the first surface of the silicon wafer 101 to form the through silicon via;

[0090] Next, as shown in FIG10 b , a first electrode layer 1321 and a portion of the circuit in the same stack as the first electrode layer are formed on the surface of the first insulating layer. Then, an intermediate insulating layer 123 and a High K dielectric material 1322 are deposited, wherein the High K dielectric material is embedded in the intermediate insulating layer. Then, a window is opened in the intermediate insulating layer to realize the extraction of the first electrode layer and interlayer interconnection. A second electrode layer 1323 is formed to form a planar capacitor 132, and interconnection circuits in the same stack as the second electrode layer are formed.

[0091] Next, as shown in FIG10c , a second insulating layer 122 is deposited to cover the second electrode layer, and a window is opened in the second insulating layer to realize the extraction of the second electrode layer. Then, multiple layers of interconnection lines and dielectric layers are alternately formed to form a first metal interconnection layer 141. Inductor coil structures 107 can be introduced into the interconnection lines, and external bonding pads 105 are formed on the surface of the interconnection lines to facilitate subsequent connection with the chip.

[0092] Next, as shown in FIG10d , a temporary bonding plate 003 is provided on the surface of the first metal interconnect layer, and the second surface of the silicon wafer is thinned to expose the through-silicon vias, and a second metal interconnect structure 142 is formed on the second surface of the silicon wafer or an external pad is formed at the end surface of the through-silicon vias; and

[0093] Finally, as shown in FIG10 e , the temporary bonding plate is removed and the chip is cut to prepare a single silicon bridge.

[0094] The present invention provides a silicon bridge module with integrated passive devices. A silicon bridge structure with integrated passive devices is prepared through wafer-level technology, realizing the integrated integration of inter-chip interconnection lines and passive devices. While achieving high-speed signal transmission, it integrates the processing function of the signal or power transmission network, thereby improving the system integration and saving the packaging volume.

[0095] Although various embodiments of the present invention have been described above, it should be understood that they are presented by way of example only and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications, and variations may be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely in accordance with the appended claims and their equivalents.

Claims

1. A silicon bridge module with integrated passive devices, characterized in that: include: A substrate, a first surface of which is provided with a first insulating layer; A capacitor, which is arranged on the surface of the first insulating layer; A second insulating layer, which is disposed on the surface of the capacitor but exposes at least a portion of the electrodes of the capacitor; A first metal interconnection layer, which is disposed on the surface of the second insulating layer and includes one or more layers of conductive lines and an insulating medium disposed between the conductive lines, and the capacitor is electrically connected to the first metal interconnection layer; an inductor device integrated into the metal interconnect layer; and An external pad is disposed on the outermost layer of the first metal interconnection layer and is electrically connected to the first metal interconnection layer.

2. The silicon bridge module according to claim 1, characterized in that: The capacitor is a deep trench capacitor, which is disposed in a deep trench of the substrate, and includes a first electrode layer, a dielectric layer and a second electrode layer, wherein the first electrode layer and the second electrode layer are electrically connected to the first metal interconnection layer.

3. The silicon bridge module according to claim 1, characterized in that: The capacitor is a planar capacitor, which is arranged on the surface of the first insulating layer and includes a first electrode layer, a dielectric layer and a second electrode layer, wherein the first electrode layer and the second electrode layer are electrically connected to the first metal interconnection layer.

4. The silicon bridge module according to claim 1, characterized in that: It also includes a through silicon via, which passes through the substrate, and has a first end electrically connected to the first metal interconnection layer, and a second end exposing a second surface of the substrate opposite to the first surface thereof.

5. The silicon bridge module according to claim 4, characterized in that: It also includes a second metal interconnection layer, which is arranged on the second surface of the substrate and includes one or more layers of conductive lines and an insulating medium arranged between the conductive lines. The second end of the silicon through hole is electrically connected to the second metal interconnection layer.

6. A method for manufacturing a silicon bridge module according to any one of claims 1 to 5, characterized in that: Includes steps: Depositing a first insulating layer on the surface of the silicon wafer to form a capacitor, wherein the capacitor includes a first electrode layer, a dielectric layer and a second electrode layer; Depositing a second insulating layer on the surface of the second electrode layer, and opening windows to lead out the first electrode layer and the second electrode layer; forming a first metal interconnection layer on the surface of the second insulating layer, wherein the first metal interconnection layer includes an inductor coil structure; Preparing an external pad on the surface of the first metal interconnection layer; as well as The silicon wafer is back-thinned and cut into individual silicon bridges.

7. The manufacturing method according to claim 6, characterized in that: Depositing a first insulating layer and forming a capacitor comprises the following steps: Etching a deep silicon trench on a first surface of the silicon wafer; Depositing a first insulating layer on the first surface of the silicon wafer and the surface of the deep silicon trench; as well as A first electrode, a dielectric material and a second electrode are sequentially filled in the deep silicon trench.

8. The manufacturing method according to claim 6, characterized in that: Depositing a first insulating layer and forming a capacitor comprises the following steps: Depositing a first insulating layer on the surface of the silicon wafer; Prepare a first electrode layer and a part of the circuit of the first metal interconnection layer on the surface of the first insulating layer; Depositing an intermediate insulating layer on the first electrode layer and the circuit surface, but exposing at least a portion of the surface of the first electrode layer to deposit a dielectric material; Opening windows in the intermediate insulating layer to lead out the first electrode layer and the external pads of the circuit; as well as A second electrode layer and a portion of the lines of the first metal interconnection layer are formed on the intermediate insulating layer.

9. The manufacturing method according to claim 6, characterized in that: Also includes the steps: forming a through silicon via on the silicon wafer, wherein a first end of the through silicon via is electrically connected to the first metal interconnection layer; and / or The second surface of the silicon wafer is ground and thinned to expose the through silicon via, and a second metal interconnection layer is formed on the second surface of the silicon wafer, and the second end of the through silicon via is electrically connected to the second metal interconnection layer.

10. A packaging structure, characterized in that: It comprises the silicon bridge module as claimed in any one of claims 1 to 5.

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