High-speed serdes transmitter module, programmable logic chip and test method

Abstract

A high-speed SerDes transmitter module, a programmable logic chip and a test method. The module comprises a parallel-serial conversion circuit, an output drive circuit, a three-state gate circuit and a swing measurement circuit; the parallel-serial conversion circuit is used for receiving parallel data, and carrying out parallel-serial conversion on the parallel data, so as to output a serial signal; the output drive circuit is used for receiving and outputting the serial signal; on the basis of an external control signal, the three-state gate circuit is used for controlling the state of an input end of the output drive circuit; the swing measurement circuit is controlled by the external control signal to measure an output swing of the output drive circuit. Using the solution of the present invention can rapidly measure the swings of high-speed SerDes transmitters, and effectively reduce the usage of ATE.

Description

High-speed SerDes transmitter module, programmable logic chip, and test method

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 15, 2023, with application number 202311738808.5 and invention name “High-speed SerDes transmitter module, programmable logic chip, and test method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the technical field of radio frequency output swing measurement, and in particular to a high-speed SerDes transmitter module, a programmable logic chip, and a testing method. Background Art

[0003] Field Programmable Gate Arrays (FPGAs) are in high demand in applications such as aviation, industry, servers, and edge computing, requiring support for diverse protocols. High-speed SerDes (SERializer / DESerializer) is a critical resource within FPGAs and serves as the physical layer of the protocol. The TX (Transmitter) is the transmitter of a SerDes circuit. Its traditional architecture, shown in Figure 1, primarily consists of a clock generation module, a parallel-to-serial conversion module, and an output driver. The parallel-to-serial conversion module converts parallel data into serial data, which is then transmitted via the output driver. The clock generation module provides the operating clock for the parallel-to-serial conversion module.

[0004] One of the metrics TX focuses on is output swing. Because variations can occur during the tape-out process, batch testing is performed before shipment to screen out defective products with substandard output swing and improve overall shipment yield. TX output swing batch testing is performed using ATE (Automatic Test Equipment). ATE, an automatic tester for integrated circuits (ICs), is used to verify the functional integrity of integrated circuits. It is the final step in IC manufacturing and ensures IC quality. ATE testing costs are directly proportional to test time, so reducing ATE machine usage time can reduce testing costs.

[0005] As shown in Figure 2, the ATE tool reads two complementary signals from the output driver off-chip—the positive voltage signal txp and the negative voltage signal txn—to derive the differential swing of TX. During chip probing (CP), the ATE tool cannot directly measure the wafer. Instead, the probes in the probe card must contact the pads or bumps on the wafer to establish an electrical connection with the chip, thereby achieving electrical performance testing.

[0006] Traditional batch testing of TX output swing requires ATE equipment to connect to the TXP and TXN terminals and obtain data through the instrument, which is time-consuming and costly. Furthermore, with the continuous advancement of packaging technology, 2.5D packaging is increasingly being used in FPGAs. In 2.5D packaging, the TX pins lack a bump on the CP, making CP testing of TX swing parameters impossible. Summary of the Invention

[0007] The embodiments of the present invention provide a high-speed SerDes transmitter module, a programmable logic chip, and a testing method, which can realize rapid measurement of the swing amplitude of the high-speed SerDes transmitter and effectively save the use of an ATE machine.

[0008] On the one hand, an embodiment of the present invention provides a high-speed SerDes transmitter module, the module comprising: a parallel-to-serial conversion circuit, an output drive circuit, a tri-state gate circuit, and a swing test circuit;

[0009] The parallel-to-serial conversion circuit is used to receive parallel data, perform parallel-to-serial conversion on the parallel data, and output a serial signal;

[0010] The output driving circuit is used to receive and output the serial signal;

[0011] The tri-state gate circuit is used to control the state of the input terminal of the output drive circuit according to an external control signal;

[0012] The swing amplitude test circuit is controlled by the external control signal to complete the test of the output swing amplitude of the output drive circuit.

[0013] Optionally, the swing amplitude test circuit includes: a voltage dividing unit, a switch unit, and a comparator connected to the voltage dividing unit and the switch unit respectively;

[0014] The voltage dividing unit is used to generate a reference voltage and input the reference voltage to an input terminal of the comparator;

[0015] The switch unit is used to control the connection or disconnection between the other input terminal of the comparator and the output terminal of the output driving circuit according to the external control signal.

[0016] Optionally, the voltage dividing unit includes a plurality of voltage dividing branches, and the plurality of voltage dividing branches form a voltage dividing array for generating a plurality of reference voltages of different magnitudes.

[0017] Optionally, the output drive circuit includes a first output terminal and a second output terminal;

[0018] The first output terminal is used to output a first signal;

[0019] The second output terminal is used to output a second signal;

[0020] The first signal and the second signal are differential signals.

[0021] Optionally, the switch unit includes: a first switch and a second switch;

[0022] The first switch is used to control the connection and disconnection between the first output terminal of the output drive circuit and the comparator;

[0023] The second switch is used to control the connection and disconnection between the second output terminal of the output drive circuit and the comparator.

[0024] Optionally, the swing amplitude of the output drive circuit is a voltage range.

[0025] Optionally, the external control signal includes a first control signal and a second control signal;

[0026] The first control signal is used to enable the swing test circuit and the tri-state gate circuit and control the switch unit to be closed in the test mode, and to disable the swing test circuit and the tri-state gate circuit and control the switch unit to be opened in the working mode;

[0027] The second control signal is used to adjust the reference voltage output by the voltage dividing unit.

[0028] On the other hand, an embodiment of the present invention further provides a programmable logic chip, the programmable logic chip comprising: a logic control circuit, and the high-speed SerDes transmitter module described above;

[0029] The logic control circuit is used to control the high-speed SerDes transmitter module to enter the test mode and receive the level signal output by the high-speed SerDes transmitter module; after the test is completed, control the high-speed SerDes transmitter module to exit the test mode.

[0030] Optionally, in the test mode, the logic control circuit controls the swing test circuit to compare the voltage output by the output drive circuit with reference voltages of different sizes, and determines the swing of the output drive circuit based on the received level signals corresponding to the reference voltages of different sizes.

[0031] On the other hand, an embodiment of the present invention further provides a high-speed SerDes transmitter swing test method, wherein the high-speed SerDes transmitter includes an output drive circuit, and the method includes:

[0032] Setting a swing test circuit in the high-speed SerDes transmitter module;

[0033] Controlling the high-speed SerDes transmitter module to enter a test mode;

[0034] Inputting a test signal to the high-speed SerDes transmitter module, adjusting a reference voltage input to the swing test circuit, and obtaining a reference voltage before and after a level signal output by the swing test circuit jumps;

[0035] The swing of the high-speed SerDes transmitter module is determined according to the reference voltage.

[0036] The high-speed SerDes transmitter module, programmable logic chip, and testing method provided by embodiments of the present invention implement built-in testing of the output swing of the high-speed SerDes transmitter through a built-in test circuit for TX output swing. The testing process eliminates the need to contact and measure the two output terminals of the output driver, saving the use of ATE equipment and reducing costs. Furthermore, the method is applicable to testing chips in various packages. For example, even in 2.5D packages where the TX output pins do not have a CP bump, testing can be completed. This present invention offers greater applicability.

[0037] Furthermore, by fully leveraging the characteristics of programmable logic chips like FPGAs, the logic control of test functions can be implemented directly using programmable logic resources. For example, during the final test (FT) batch testing phase after chip packaging, the control program is burned into the FPGA. The FPGA array then controls the TX to enter swing test mode, obtains the corresponding range of TX output swing, and feeds the results back to the ATE machine. This testing process reduces the time the ATE machine spends testing the output voltage of the output driver circuit, improving test efficiency and saving costs compared to existing solutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a block diagram of the structure of a traditional TX;

[0039] Figure 2 is a schematic diagram of ATE machine testing TX swing;

[0040] FIG3 is a schematic structural diagram of a high-speed SerDes transmitter module provided in an embodiment of the present invention;

[0041] FIG4 is a schematic structural diagram of a swing test circuit according to an embodiment of the present invention;

[0042] FIG5 is a schematic structural diagram of a programmable logic chip provided in an embodiment of the present invention;

[0043] 6 is a schematic diagram of a structure of a TX output swing test using a programmable logic chip and an ATE machine provided in an embodiment of the present invention;

[0044] 7 is a schematic diagram of the structure of the prior art using an ATE machine to perform a TX output swing test;

[0045] 8 is another structural diagram of performing a TX output swing test using a programmable logic chip and an ATE machine according to an embodiment of the present invention;

[0046] FIG9 is a flow chart of a high-speed SerDes transmitter swing test method provided by the present invention. DETAILED DESCRIPTION

[0047] The principles and spirit of the present invention will be described below with reference to the exemplary embodiments shown in the accompanying drawings. It should be understood that these embodiments are described only to enable those skilled in the art to better understand and implement the present invention, and are not intended to limit the scope of the present invention in any way.

[0048] To address the problems of traditional batch testing of TX output swing, which requires an ATE machine to be connected to the TXP and TXN terminals of a TX module and obtain data through an instrument, resulting in long testing time and high cost, the present invention proposes a high-speed SerDes transmitter module, FPGA chip, and testing method. This method can quickly measure the TX swing without the need for an ATE machine to test the TX output terminal, thus saving testing time and cost.

[0049] FIG3 is a schematic structural diagram of a high-speed SerDes transmitter module provided in an embodiment of the present invention.

[0050] In this embodiment, the high-speed SerDes transmitter module 300 includes: a parallel-to-serial conversion circuit 301, an output drive circuit 302, a tri-state gate circuit 303, and a swing test circuit 304.

[0051] The parallel-to-serial conversion circuit 301 is used to receive parallel data, perform parallel-to-serial conversion on the parallel data, and output a serial signal;

[0052] The output driving circuit 302 is used to receive and output the serial signal;

[0053] The tri-state gate circuit 303 is used to control the state of the input terminal of the output drive circuit 302 according to the external control signal;

[0054] The swing test circuit 304 is configured to test the output swing of the output driving circuit according to the external control signal.

[0055] The tri-state gate circuit 303 has three output states: high level, low level, and high impedance. When its enable terminal EN is active, the tri-state gate circuit 303 outputs a normal "0" or "1." When the enable terminal EN is inactive, the output terminal of the tri-state gate circuit 303 is in a high-impedance state, i.e., a floating state, thereby disconnecting the output driver circuit 302.

[0056] By utilizing the aforementioned characteristics of the tri-state gate circuit 303, during testing, the enable terminal EN is controlled to be valid (e.g., pulled high). At this time, the output driver circuit 302 is controlled by the tri-state gate circuit, and the swing test circuit 304 operates. By inputting a test signal into the tri-state gate, the level states of the two complementary signals txp and txn output by the output driver circuit 302 are changed. The swing detection circuit 304 detects the signal txp or txn and outputs the test result Rslt.

[0057] When the high-speed SerDes transmitter module 300 is in working mode, the enable terminal EN of the tri-state gate circuit 303 is controlled to be invalid (for example, it is pulled low), the output terminal of the tri-state gate circuit 303 is suspended, and the swing test circuit 304 is disconnected, which does not affect the normal operation of the output drive circuit 302.

[0058] FIG4 is a schematic diagram showing the structure of a swing test circuit according to an embodiment of the present invention.

[0059] The swing test circuit 304 includes the following units: a voltage divider unit 341, a switch unit 342, and a comparator 343 connected to the voltage divider unit 341 and the switch unit 342 respectively.

[0060] The voltage divider unit 341 is used to generate a reference voltage and input it to one input terminal of the comparator 343;

[0061] The switch unit 342 is used to control the other input terminal of the comparator 343 to be connected to or disconnected from the output terminal of the output driving circuit 302 in FIG. 3 according to the external control signal.

[0062] 3 and 4 , the output driver circuit 302 generally includes a first output terminal and a second output terminal, wherein the first output terminal outputs a first signal txp, and the second output terminal outputs a second signal txn, wherein the first signal txp and the second signal txn are differential signals.

[0063] Accordingly, the switch unit 342 may include a first switch S1 and a second switch S2. The first switch S1 is used to control the connection and disconnection between the first output terminal of the output drive circuit 302 and the comparator 343; the second switch S2 is used to control the connection and disconnection between the second output terminal of the output drive circuit 302 and the comparator 343.

[0064] In a specific application, the voltage dividing unit 341 needs to generate a plurality of reference voltages of different magnitudes, which can be achieved by using two voltage dividing resistors R1 and R2 connected in series.

[0065] In a non-limiting embodiment, the voltage dividing unit 341 can change the reference voltage by designing one of the voltage dividing resistors, such as R1, as a variable resistor and adjusting the size of the variable resistor.

[0066] In another non-limiting embodiment, a plurality of voltage dividing branches may be provided to form a voltage dividing array, thereby generating a plurality of reference voltages of different magnitudes.

[0067] In practical applications, testing the TX output swing only requires checking whether it reaches a certain threshold, without having to measure its specific value. Therefore, the solution of the present invention can fully meet this requirement, determining the corresponding upper and lower swing ranges of the TX output terminals through testing.

[0068] The principle of implementing output swing testing using the high-speed SerDes transmitter module 300 will be described in detail below with reference to FIG. 3 and FIG. 4 .

[0069] When the circuit is in swing test mode, the first switch S1 is turned on and the second switch S2 is turned off. A test signal is input to the output driver circuit 302 via the tri-state gate circuit 303. At this time, the comparator 343 compares the output signal txp at the first output terminal of the output driver circuit 302 with the reference voltage vref. If the output signal txp is greater than vref, the comparator 343 outputs a high signal Rslt; otherwise, the comparator outputs a low signal Rslt.

[0070] By adjusting the size of the reference voltage vref through the control signal Rctrl, the reference voltage corresponding to the jump of the output signal txp of the first output terminal, that is, the jump from high level to low level, and the jump from low level to high level, can be found. The swing range of the first output terminal can be determined. The accuracy of this range can be set according to application requirements, and this requirement can be met by designing the adjustment accuracy of the voltage divider unit 341.

[0071] Assume that the adjustment accuracy of the control signal Rctrl for the reference voltage vref is 10mV. When the reference voltage vref is 800mV, the output signal Rslt of the comparator 343 is high. When the voltage of vref is 810mV, the output signal Rslt of the comparator 343 is low. This indicates that the voltage value of the output signal txp at the first output terminal of the output driver circuit 302 falls within the range of [800mV, 810mV]. That is, the output swing of the first output terminal of the output driver circuit 302 is [800mV, 810mV].

[0072] Similarly, the second switch S2 is turned on and the first switch S1 is turned off, and the output signal txn of the second output terminal of the output driving circuit 302 is compared with the reference voltage vref. The principle is similar to the above and will not be repeated here.

[0073] When the TX is in a normal operating mode, the first switch S1 and the second switch S2 are both disconnected, which does not affect the normal operation of the TX.

[0074] It should be noted that the external control signal may include a first control signal and a second control signal, wherein:

[0075] The first control signal is used to enable the swing test circuit and the tri-state gate circuit and control the switch unit to be closed in the test mode, and to disable the swing test circuit and the tri-state gate circuit and control the switch unit to be opened in the working mode;

[0076] The second control signal is used to adjust the reference voltage output by the voltage dividing unit.

[0077] Furthermore, a test signal may be included. The first control signal, the second control signal, and the test signal may be implemented by a logic control circuit according to corresponding control logic, which is not limited in this embodiment of the present invention.

[0078] The high-speed SerDes transmitter module 300 may further include a clock circuit (not shown in the figure) to provide a working clock for the parallel-to-serial conversion circuit 301 .

[0079] Accordingly, an embodiment of the present invention further provides a programmable logic chip, as shown in FIG5 , wherein the programmable logic chip 500 includes: a logic control circuit 501 and the high-speed SerDes transmitter module 300 described in the previous embodiment.

[0080] The logic control circuit 501 is used to control the high-speed SerDes transmitter module 300 to enter the test mode and receive the level signal output by the high-speed SerDes transmitter module 300; after the test is completed, the logic control circuit 501 controls the high-speed SerDes transmitter module 300 to exit the test mode.

[0081] 3 and 5 , the logic control circuit 501 controls the swing test circuit 304 to compare the voltage output by the output drive circuit 302 with reference voltages of different sizes in the test mode, and determines the swing of the output drive circuit 302 based on the received level signals corresponding to the reference voltages of different sizes.

[0082] The programmable logic device in the embodiment of the present invention may include, but is not limited to, FPGA, PSOC (Programmable System-on-Chip), etc.

[0083] The above logic control circuit 501 can be directly implemented using corresponding programmable logic resources.

[0084] By using this programmable logic chip, the TX output swing can be tested quickly, reducing the usage time of the ATE machine.

[0085] As shown in Figure 6, during the FT batch test phase, the ATE program is burned into the FPGA. The FPGA array then controls the TX to enter swing test mode, obtains the corresponding range of the TX output swing, and feeds the result back to the ATE machine. This test process reduces the time it takes the ATE machine to read the voltage values ​​of the test output signals TXP and TXN.

[0086] Figure 7 shows a schematic diagram of the structure of a TX output swing test using an ATE machine in the prior art. In the prior art, the ATE machine is required to continuously read the voltage values ​​of the output signals txp and txn at the test output terminals.

[0087] From the above comparison, it can be seen that, compared with the existing solution shown in FIG7 , the solution of the present invention shown in FIG6 does not require the ATE machine to read the voltage values ​​of the output signals txp and txn of the test output terminals. The FPGA array only needs to send the test results to the ATE machine, thereby effectively saving costs and improving test efficiency.

[0088] Similarly, the present invention's solution can also be used during the chip probing (CP) phase. As shown in Figure 8, swing measurement can be achieved without probing the CP bump at the two output terminals, enabling early screening of defective products and saving FT testing and packaging costs. The testing process is identical to the aforementioned FT testing. The ATE machine burns the control program into the FPGA, then controls the TX array to enter swing test mode, obtains the corresponding TX output swing range, and feeds the results back to the ATE machine. This process eliminates the need to protrude the two output pins.

[0089] It should be noted that the TX described in the above embodiments includes the high-speed SerDes transmitter module provided by the embodiments of the present invention.

[0090] It can be seen that the solution of the present invention can not only improve test efficiency and save costs, but also is not affected by the chip packaging structure. Even for the packaging situation where the TX output pin does not lead out the CP bump, the test can be completed.

[0091] Accordingly, an embodiment of the present invention further provides a high-speed SerDes transmitter swing test method, as shown in FIG9 , which is a flow chart of the method, including the following steps:

[0092] Step 901, setting a swing test circuit in the high-speed SerDes transmitter module;

[0093] Step 902: Control the high-speed SerDes transmitter module to enter a test mode;

[0094] Step 903: Input a test signal to the high-speed SerDes transmitter module, adjust the reference voltage input to the swing test circuit, and obtain the reference voltage before and after the level signal output by the swing test circuit jumps;

[0095] Step 904: Determine the swing of the high-speed SerDes transmitter module according to the reference voltage.

[0096] In specific implementations, the modules / units included in the various devices and products described in the above embodiments may be software modules / units or hardware modules / units, or may be partially software modules / units and partially hardware modules / units.

[0097] For example, for each device or product applied to or integrated into a chip, each module / unit contained therein may be implemented in the form of hardware such as circuits, or at least some of the modules / units may be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units may be implemented in the form of hardware such as circuits; for each device or product applied to or integrated into a chip module, each module / unit contained therein may be implemented in the form of hardware such as circuits, and different modules / units may be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least some of the modules / units may be implemented in the form of software programs. The element can be implemented in the form of a software program, which runs on the processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the terminal, the various modules / units contained therein can be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or different components in the terminal, or, at least some modules / units can be implemented in the form of a software program, which runs on the processor integrated inside the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits.

[0098] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A high-speed SerDes transmitter module, characterized in that: The module includes: a parallel-to-serial conversion circuit, an output drive circuit, a tri-state gate circuit, and a swing amplitude test circuit; The parallel-to-serial conversion circuit is used to receive parallel data, perform parallel-to-serial conversion on the parallel data, and output a serial signal; The output driving circuit is used to receive and output the serial signal; The tri-state gate circuit is used to control the state of the input terminal of the output drive circuit according to an external control signal; The swing test circuit is controlled by the external control signal to complete the test of the output swing of the output drive circuit.

2. The high-speed SerDes transmitter module according to claim 1, characterized in that: The swing amplitude test circuit comprises: a voltage dividing unit, a switch unit, and a comparator connected to the voltage dividing unit and the switch unit respectively; The voltage dividing unit is used to generate a reference voltage and input the reference voltage to an input terminal of the comparator; The switch unit is used to control the connection or disconnection between the other input terminal of the comparator and the output terminal of the output driving circuit according to the external control signal.

3. The high-speed SerDes transmitter module according to claim 2, characterized in that: The voltage division unit includes a plurality of voltage division branches, and the plurality of voltage division branches form a voltage division array for generating a plurality of reference voltages of different magnitudes.

4. The high-speed SerDes transmitter module according to claim 2, characterized in that: The output drive circuit includes a first output terminal and a second output terminal; The first output terminal is used to output a first signal; The second output terminal is used to output a second signal; The first signal and the second signal are differential signals.

5. The high-speed SerDes transmitter module according to claim 4, characterized in that: The switch unit comprises: a first switch and a second switch; The first switch is used to control the connection and disconnection between the first output terminal of the output drive circuit and the comparator; The second switch is used to control the connection and disconnection between the second output terminal of the output driving circuit and the comparator.

6. The high-speed SerDes transmitter module according to claim 2, characterized in that: The swing amplitude of the output drive circuit is a voltage range.

7. The high-speed SerDes transmitter module according to any one of claims 2 to 6, characterized in that: The external control signal includes a first control signal and a second control signal; The first control signal is used to enable the swing test circuit and the tri-state gate circuit in the test mode and control the switch unit to close, and to disable the swing test circuit and the tri-state gate circuit in the working mode and control the switch unit to open; The second control signal is used to adjust the reference voltage output by the voltage dividing unit.

8. A programmable logic chip, characterized in that: The programmable logic chip comprises: a logic control circuit, and a high-speed SerDes transmitter module according to any one of claims 1 to 6; The logic control circuit is used to control the high-speed SerDes transmitter module to enter the test mode and receive the level signal output by the high-speed SerDes transmitter module; after the test is completed, the high-speed SerDes transmitter module is controlled to exit the test mode.

9. The programmable logic chip according to claim 8, characterized in that: In the test mode, the logic control circuit controls the swing test circuit to compare the voltage output by the output drive circuit with reference voltages of different sizes, and determines the swing of the output drive circuit according to the received level signals corresponding to the reference voltages of different sizes.

10. A high-speed SerDes transmitter swing test method, wherein the high-speed SerDes transmitter includes an output drive circuit, characterized in that: The method comprises: Setting a swing test circuit in the high-speed SerDes transmitter module; Controlling the high-speed SerDes transmitter module to enter a test mode; Input a test signal to the high-speed SerDes transmitter module, adjust the reference voltage input to the swing test circuit, and obtain the reference voltage before and after the level signal output by the swing test circuit jumps; The swing amplitude of the high-speed SerDes transmitter module is determined according to the reference voltage.

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