NAND flash memory, memory and electronic device

Abstract

An NAND flash memory, a memory, and an electronic device. When simultaneously reading on the same plane data of a plurality of pages, the NAND flash memory allows the saturation current of each page to be different from each other and / or the time for reading the data of each page to be different from each other, so that the data recorded by each page is different from each other, the total currents of a reading circuit are different from each other, and the voltage reduction speeds of discharge capacitors are different from each other. When reading the data of the plurality of pages, the NAND flash memory can use a voltage comparison unit for detecting the relationship between the voltages of the discharge capacitors and a comparison voltage, so as to accurately read the data recorded by each page, avoiding confusion between the read data and the pages.

Description

NAND flash memory, memory and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on December 12, 2023, with application number 202311706589.2 and application name “A NAND flash memory, memory and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the technical field of memory chips, and in particular to a NAND flash memory, a memory and an electronic device. Background Art

[0003] NAND (non-and) flash memory is a non-volatile memory device that uses NAND gates to store data. NAND flash memory offers advantages such as high storage density, fast data read and write speeds, low power consumption, and a long lifespan. It is widely used in various electronic devices, such as solid-state drives (SSDs), universal serial bus (USB) flash drives, memory cards, and mobile devices.

[0004] Reading and writing data are the most typical scenarios in NAND flash memory applications. Data reading (read operations) is the most important use case for users, so improving NAND memory's read performance and power consumption is of great significance. NAND memory read operations can be divided into precharge, evaluation, and discharge processes. The latency of each process has been continuously reduced, reaching extreme values, as manufacturers improve their process technology, circuit design, and manufacturing capabilities. However, with the iteration and upgrade of NAND memory media, the reduction in read latency has gradually slowed, resulting in NAND memory being unable to meet the low power and high performance requirements of future storage scenarios. Summary of the Invention

[0005] To address the aforementioned issues, embodiments of the present application provide a NAND flash memory, a memory, and an electronic device. When simultaneously reading data from multiple pages on the same page, the saturation current for each page is varied and / or the time required to read the data from each page is varied. This allows accurate reading of the data recorded on each page and avoids confusion between the read data and the pages. Furthermore, the present application provides a memory and an electronic device corresponding to the NAND flash memory.

[0006] To this end, the following technical solutions are adopted in the embodiments of the present application:

[0007] In a first aspect, an embodiment of the present application provides a NAND flash memory, comprising: a voltage control unit, comprising a plurality of first output ports and a plurality of second output ports, the plurality of first output ports being configured to output a first electrical signal, and the plurality of second output ports being configured to output a second electrical signal; a NAND array, comprising a plurality of sub-blocks, each sub-block comprising a plurality of pages, the plurality of pages being electrically connected to the plurality of first output ports, respectively, for reading or writing data upon receiving the first electrical signal; an asynchronous unit, electrically connected between the plurality of first output ports and the plurality of sub-blocks, or electrically connected to gates of sub-block selection transistors in the plurality of pages of the plurality of sub-blocks and gates of dual-gate MOS transistors in the plurality of pages of the plurality of sub-blocks, for, when simultaneously reading data from target dual-gate MOS transistors of the plurality of pages, making the saturation currents of the target dual-gate MOS transistors for simultaneously reading the plurality of pages different, and / or making the conduction time of the respective pages for simultaneously reading the plurality of pages different; and a plurality of discharge capacitors C SO The first ends of the multiple discharge capacitors are respectively electrically connected to the multiple second output ports, and the second ends of the multiple discharge capacitors are grounded; the voltage comparison unit includes multiple input ports, the multiple input ports are respectively electrically connected to the multiple second output ports, and is used to compare the voltages received by the multiple input ports with the comparison voltage and output the comparison result.

[0008] In this embodiment, the NAND memory reads data of multiple pages at the same time on the same surface, and the saturation current of each page can be made different and / or the time of reading the data of each page can be made different, so that the data recorded on each page is different and the total current of the reading circuit is different, so that the discharge capacitor C SO When NAND flash memory reads data from multiple pages, the voltage comparison unit can be used to detect the discharge capacitor C SO The relationship between the voltage and the comparison voltage can be used to accurately read the data recorded in each page and avoid confusion between the read data and the page.

[0009] In one embodiment, the discharge capacitor is in a discharging state when the data recorded by the target dual-gate MOS transistor of the page electrically connected to the discharge capacitor is "1"; the discharge capacitor is in a charging state when the data recorded by the target dual-gate MOS transistor of the page electrically connected to the discharge capacitor is "0".

[0010] In this embodiment, when the data recorded by the target dual-gate MOS transistor is "1," the circuit between the target dual-gate MOS transistor and the discharge capacitor is connected, allowing the discharge capacitor to discharge, thereby reducing the voltage of the discharge capacitor. When the data recorded by the target dual-gate MOS transistor is "0," the circuit between the target dual-gate MOS transistor and the discharge capacitor is disconnected, allowing the discharge capacitor to be charged, thereby maintaining the voltage of the discharge capacitor. The voltage comparison unit can accurately read the data recorded on each page based on the voltages of the multiple discharge capacitors at different times, thereby avoiding confusion between the read data and the page.

[0011] In one embodiment, the voltage comparison unit is specifically configured to compare the voltages received by the multiple input ports at multiple latch time points with the comparison voltages to obtain multiple sub-output results. The NAND flash memory further includes a decoding unit configured to compare the multiple sub-output results with a preset result to determine whether the data recorded by the target dual-gate MOS transistors of each page of the multiple pages read simultaneously is "0" or "1." The preset result records that the sub-output results at different latch time points correspond to the data recorded by the multiple target dual-gate MOS transistors read simultaneously.

[0012] In this embodiment, because the saturation currents of the target dual-gate MOS transistors for multiple pages being read simultaneously are different, or the time taken to read the data for each page is different, the voltage comparison unit detects different voltages on the multiple discharge capacitors at different times. The decoding unit can compare the voltages of the multiple discharge capacitors at different times with the data recorded by the target dual-gate MOS transistors according to its pre-stored table, thereby accurately reading the data recorded on each page and avoiding confusion between the read data and the page.

[0013] In one embodiment, the relationship between the number M of the plurality of latching time points and the number N of pages read simultaneously is: M≥(2 N -1); M and N are positive integers greater than or equal to 2.

[0014] In this embodiment, the number M of latching time points set by the voltage comparison unit shall not be less than (2 N -1), to avoid insufficient latching time, which results in failure to distinguish the voltages of multiple discharge capacitors when the target dual-gate MOS transistors that simultaneously read multiple pages record different data.

[0015] In one embodiment, there is at least one latching time point between different discharge durations; the discharge duration refers to the duration for the voltage of the discharge capacitor electrically connected to the target dual-gate MOS transistor of multiple pages read simultaneously to drop to the comparison voltage.

[0016] In one embodiment, when the on-times of the pages of the simultaneously reading multiple pages are different, the time difference between the on-times of two adjacent pages is less than or equal to the time duration for the voltage of the discharge capacitor to drop to the comparison voltage.

[0017] In this embodiment, when the asynchronous unit makes the reading time of each page different, the delayed time is less than or equal to the time length for the voltage of the discharge capacitor to drop to the comparison voltage, thereby avoiding completely asynchronous reading of the two pages.

[0018] In one embodiment, the voltage control unit is further configured to electrically connect the plurality of first output ports to the plurality of second output ports respectively when outputting the first electrical signal and the second electrical signal is stopped.

[0019] In this embodiment, after the voltage control unit stops outputting the first electrical signal and the second electrical signal, each first output port can be electrically connected to a second output port to form a reading loop, so that the discharge capacitor C SO Discharge to read data.

[0020] In one embodiment, the voltage control unit is further configured to convert the current of the second output port from a first value to a second value.

[0021] In this embodiment, after the plurality of first output ports are electrically connected to the plurality of second output ports respectively, the voltage control unit can change the current value of the second output port to reduce the current flowing into the NAND array 420 to protect the NAND array.

[0022] In a second aspect, an embodiment of the present application provides a memory comprising: a circuit board, at least one NAND flash memory as may be implemented in the first aspect, wherein the NAND flash memory is fixed and electrically connected to the circuit board for storing data.

[0023] In a third aspect, an embodiment of the present application provides an electronic device, comprising: at least one memory as may be implemented in the second aspect, and at least one processor, the processor being electrically connected to the at least one memory and configured to write data into the at least one memory and / or read data from the at least one memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The following is a brief introduction to the drawings required for describing the embodiments or prior art.

[0025] FIG1 is a schematic structural diagram of a dual-gate MOS transistor of a NAND memory in the related art;

[0026] FIG2 is a schematic diagram of the structure of a NAND memory in the related art;

[0027] FIG3 is a schematic diagram of a path for reading data from page 1 of sub-block 0 in a NAND memory in the related art;

[0028] FIG4 is a schematic diagram of the structure of a first NAND memory provided in an embodiment of the present application;

[0029] FIG5 is a diagram of a discharge capacitor C in a reading circuit provided in an embodiment of the present application. SO Schematic diagram of the relationship between the voltage drop rate and the current;

[0030] FIG6 is a schematic diagram of the structure of a second NAND memory provided in an embodiment of the present application;

[0031] FIG. 7 is a diagram of a discharge capacitor C in a read circuit provided in an embodiment of the present application. SO Schematic diagram of the relationship between the voltage drop rate and the current;

[0032] FIG8 is a schematic diagram of the structure of a third NAND memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0034] The term "and / or" as used herein describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. The symbol " / " as used herein indicates that the related objects are in an "or" relationship, for example, A / B means either A or B.

[0035] The terms "first" and "second" in this specification and claims are used to distinguish different objects rather than to describe a specific order of objects. For example, "first response message" and "second response message" are used to distinguish different response messages rather than to describe a specific order of response messages.

[0036] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0037] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more, for example, multiple processing units means two or more processing units, etc.; multiple elements means two or more elements, etc.

[0038] NAND memory uses a dual-gate transistor design. Traditional metal-oxide-semiconductor field-effect transistors (MOSFETs) include a source, drain, gate, and body. The storage cell inside NAND adds a floating gate to the insulating layer of the traditional MOS tube to store charge. By applying a large voltage difference between the gate and the base, electrons or holes can be injected into the floating gate to achieve write and erase operations. The amount of stored charge will change the transistor threshold voltage V TH . Different threshold voltage V TH Represents the storage of different information states, so each memory cell stores one or more bits of data. When the voltage applied to the gate is greater than the threshold voltage V TH When the channel is inverted, if there is a voltage difference between the source and drain at this time, a current path will be formed. Otherwise, there will be no current path. Based on this, the threshold voltage V of the transistor can be determined. TH size, you can read the stored data.

[0039] Figure 1 is a schematic diagram of the structure of a dual-gate MOS transistor of a NAND memory in the related art. As shown in Figure 1, NAND memory can change the threshold voltage V of the dual-gate MOS transistor by using the amount of charge stored on the floating gate. TH NAND memory has a read voltage V applied to the gate. read After that, if the voltage V read Greater than the threshold voltage V formed by the charge in the floating gate TH When the voltage V read Greater than the threshold voltage V TH When the dual-gate MOS tube of the storage unit is in the on state, it means that the data recorded in the storage unit is "1". On the contrary, when the reading voltage V read Less than the threshold voltage V TH When the dual-gate MOS tube of the storage unit is in the off state, it indicates that the data recorded in the storage unit is "0".

[0040] In NAND memory, read operations are performed on a "page" basis. A page typically contains multiple memory cells. When performing a read operation in NAND memory, the word line (WL) of the target page is first selected and connected to the source output (SO) node via a bit line (BL).

[0041] As shown in FIG2 , the NAND memory includes a read circuit. The voltage control unit of the read circuit applies a suitable read voltage V to BL. read When a voltage is applied to BL, the charge state of the memory cell will affect the voltage on BL. If the charge state of the memory cell forms a threshold voltage V TH Greater than the read voltage V on BL read When the read voltage V read The reading circuit changes according to the reading voltage V on BL read The NAND memory detects the change of the discharge capacitor C and amplifies and encodes the changed voltage to output the data information in a detected manner. SO The voltage change can quickly read and transmit the data in the storage unit.

[0042] The process of reading a single page of NAND memory can be divided into a precharge phase, an evaluation phase, and a discharge phase.

[0043] During the pre-charge process, the voltage control unit charges WL and BL, so that the discharge capacitor C at the BL and SO nodes SO The voltage formed is V BL and V SO , and V BL <V SO .

[0044] During the evaluation process, due to the discharge capacitance C at the SO node SO The voltage V SO Greater than BL voltage V BL If the memory cell is in the on state (data is "1"), the discharge capacitor C SO It will discharge and discharge to the discharge capacitor C SO The voltage V SO Less than the comparison voltage V THSA If the memory cell is in the off state (data is “0”), the discharge capacitor C SO Will not discharge, discharge capacitor C SO The voltage V SO Will always be greater than the comparison voltage V THSA The voltage comparison unit inside the NAND memory can obtain the discharge capacitance C at the SO node at a "latch" time point. SO The voltage V SO and through the voltage V SO Compare with voltage V THSAThe voltage comparison unit saves the read data and stores it in the data temporary storage area.

[0045] During the discharge process, the voltage control unit discharges WL and BL to complete the read operation.

[0046] On the same plane, NAND memory needs to read data from multiple pages serially. As shown in Figure 3, taking the data of page 1 of sub-block 0 as an example, when the NAND memory needs to read the target storage cell, the voltage output by the boost and voltage control circuit is applied to each WL after being processed by the row address decoder. The sub-block select transistor is applied with a positive voltage Vpass to turn it on, allowing the BL to access the storage cell under sub-block 0. At the same time, the other non-selected sub-block select transistors are set to a low voltage (such as 0V) to prevent the non-selected sub-block select transistors from turning on and interfering with the read results.

[0047] The WL2 voltage where the target memory cell is located applies a read voltage V read After that, the memory cell on WL2 can be activated and selected for reading. The gates of other memory cells are set to a high voltage V pass , so that the transistors in series on other sub-blocks are turned on to ensure that the conduction state of the entire sub-block is determined by the conduction state of the read memory cell. If the data written to the target memory cell is "0", it indicates that the threshold voltage V TH Greater than the read voltage V read , the target memory cell is in the off state, and the memory cell string is close to no current passing through. If the data written to the target memory cell is "1", it indicates that the threshold voltage V TH Greater than the read voltage V read , the target memory cell is in the on state, and a current flows through the memory cell string. Let the current be I cell After the NAND memory finishes reading page 1, it discharges WL and BL. If the NAND memory needs to read the page on sub-block 1, it will repeat the above process, only turning off sub-block select transistor 0 and turning on sub-block select transistor 1.

[0048] When NAND memory performs a read operation, different planes and different logical units (logical unit number, LUN) can operate independently. This means that in a NAND memory chip, multiple planes and multiple LUNs can perform read operations at the same time. In the same plane, different pages can be read in a serial reading manner. Serial reading means reading pages one by one in sequence, rather than reading multiple pages at the same time. When NAND memory reads a page, it needs to recharge and discharge BL to read the data. However, the repeated charge and discharge process limits the read performance and increases the read power consumption. If two sub-blocks are turned on at the same time, the currents of the two sub-blocks are close to the same, and the voltage V of the node SO is SO If the slopes of the decrease are close to the same, it is possible that "01" and "10" cannot be distinguished, resulting in confusion between the read data and the page.

[0049] In order to solve the shortcomings existing in the related art, the embodiments of the present application provide a new NAND memory, storage and electronic device. In order to increase the speed of reading data, NAND memory can add an asynchronous unit. The asynchronous unit can make the saturation current of each page different, the time to read the data of each page different, the saturation current of each page different, and the time to read the data of each page different. NAND memory reads data of multiple pages at the same time on the same surface, and can make the saturation current of each page different and / or the time to read the data of each page different, so that the data recorded on each page is different, the total current of the reading circuit is different, and the discharge capacitor C SO When NAND flash memory reads data from multiple pages, it can use the voltage comparison unit to detect the discharge capacitor C at multiple latch time points. SO The relationship between the voltage and the comparison voltage is used to accurately read the data recorded on each page and avoid confusion between the read data and the page. The asynchronous unit below can be also called "current limiting unit", "time control unit" and "current limiting and time control unit" according to its function.

[0050] FIG4 is a schematic diagram of the structure of the first NAND memory provided in an embodiment of the present application. As shown in FIG4 , the NAND memory 400 includes a read circuit 410, a NAND array 420, and a current limiting unit 430. The CMOS circuit 410 includes a voltage control unit 411, a voltage comparison unit 412, a data cache unit 413, a decoding unit 414, and a plurality of discharge capacitors C SO The NAND array 420 includes a plurality of sub-blocks.

[0051] The voltage control unit 411 includes multiple first output ports and multiple second output ports. The multiple first output ports are connected to each sub-block of the NAND array 420 via wiring. The wiring between the voltage control unit 411 and the multiple sub-blocks is referred to as "BL." Each sub-block includes multiple sub-block select transistors. The drain of each sub-block select transistor is connected to a BL, and the source of each sub-block select transistor is connected in series with the dual-gate MOS transistors of multiple storage cells. The gate of each dual-gate MOS transistor of each storage cell is connected to an external read unit via wiring. The wiring between the gate of each dual-gate MOS transistor of each storage cell and the external read unit is referred to as "WL."

[0052] The plurality of second output ports of the voltage control unit 411 are respectively connected to the plurality of input ports of the voltage comparison unit 412. SO One end of each of the discharge capacitors C is connected to the line between the second output port of the voltage control unit 411 and the input port of the voltage comparison unit 412. SO The other end of the discharge capacitor C SO A node connected between the second output port of the voltage control unit 411 and the input port of the voltage comparison unit 412 is an SO node.

[0053] The voltage control unit 411 is used to convert the power provided by the power supply into a suitable voltage, and finely regulate the voltage applied to WL, such as reading the voltage V read , through the voltage V pass etc., for BL, WL and discharge capacitor C SO When the NAND memory 400 is reading data, the voltage control unit 411 provides a voltage to the discharge capacitor C in the pre-charging stage. SO The voltage of the SO node is charged and controlled. During the evaluation phase, the power supply can be stopped and the line where the SO node is located is connected to a BL to form a reading loop. The voltage of the SO node can be clamped to prevent it from being too low.

[0054] In the embodiment of the present application, the voltage control unit 411 applies a voltage VBL to each BL of the NAND array 420, and applies a voltage VSO to each input port of the voltage comparison unit 412 of the read circuit 410, and VSO>VBL. After the plurality of first output ports are electrically connected to the plurality of second output ports, the voltage control unit 411 can change the current value of the second output port, converting the current of the second output port from the first value to the second value. The voltage control unit 411 changes the discharge capacitor C SO The current during discharge reduces the current flowing into the NAND array 420 , thereby protecting the NAND array 420 .

[0055] Read circuit 410 may also include a read unit configured to parse an input address signal and determine the index, page, block, or other location information of the target memory cell to be operated. The read unit transmits the parsed location information to NAND array 420, activating the sub-block select transistors within the corresponding sub-blocks in NAND array 420 and thereby activating the circuitry corresponding to the target memory cell. Furthermore, address decoding unit 413 is configured to generate appropriate operation signals based on the parsed location information and the target memory cell selection result to control charging, discharging, erasing, or other related operations of the target memory cell.

[0056] In an embodiment of the present application, when the NAND array 420 simultaneously performs a read operation on storage cells managed by more than one sub-block, the read unit can simultaneously parse more than one input address information and transmit more than one parsed position to the NAND array 420 to control the selection gate of more than one target storage cell.

[0057] The current limiting unit 430 can be set between each BL and each sub-block, or set at the gate of the sub-block selection tube and the gate of the dual-gate MOS tube of each storage unit within each sub-block, and is used to control the gate voltage, threshold voltage, resistance value of the series resistor, resistance value of the equivalent resistor, etc. of the dual-gate MOS tube of the storage unit of each page to limit the saturation current of each page, so that the saturation current of each page is different. The saturation current refers to the saturation current of the dual-gate MOS tube of each storage unit of the page, the sub-block selection tube where the page is located, the BL and the discharge capacitor C SO The current in the reading circuit.

[0058] Take the NAND flash memory 400 as an example to read data from memory cells of two pages simultaneously, let the two pages be page 0 and page 1. Assume that the memory cells of page 0 are connected to sub-block select transistor 0 and BL0, the memory cells of page 1 are connected to sub-block select transistor 1 and BL1, and the saturation current I of the dual-gate MOS transistor of the memory cells of page 0 is cell0 Greater than the saturation current I of the dual-gate MOS transistor of the memory cell on page 1 cell1 .

[0059] During the evaluation process, if the data of the memory cell of page 0 is "1" and the data of the memory cell of page 1 is "1", the dual-gate MOS transistor of the memory cell of page 0 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell0 , and the dual-gate MOS transistor of the memory cell of page 1 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell1 Therefore, the total current in the reading circuit when the data is "11" is Icell0 +I cell1 .

[0060] If the data of the memory cell of page 0 is "1" and the data of the memory cell of page 1 is "0", the dual-gate MOS transistor of the memory cell of page 0 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell0 , and the dual-gate MOS transistor of the memory cell of page 1 is in the off state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. Therefore, the total current on the reading circuit when the data is "10" is I cell0 .

[0061] If the data of the memory cell of page 0 is "0" and the data of the memory cell of page 1 is "1", the dual-gate MOS transistor of the memory cell of page 0 is in the off state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is 0, and the dual-gate MOS transistor of the memory cell of page 1 is in the on state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is the saturation current I cell1 Therefore, the total current in the reading circuit when the data is “01” is I cell1 .

[0062] If the data in the memory cells of page 0 is "0" and the data in the memory cells of page 1 is "0", the dual-gate MOS transistors of the memory cells of page 0 are in the off state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistors is zero. Similarly, the dual-gate MOS transistors of the memory cells of page 1 are in the off state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistors is zero. Therefore, the total current in the read circuit when the data is "00" is zero.

[0063] In the embodiment of the present application, the total current on the reading circuit is different, and the discharge capacitor C SO The voltage from the voltage V SO Drop to the comparison voltage V THSA As shown in Figure 5, the total current on the reading circuit is I cell0 +I cell1 , I cell0 , I cell1 and 0. The total current on the reading circuit when the data is "11" is I cell0 +I cell1 , discharge capacitor C SO The voltage drops fastest and has the largest slope. cell0 Greater than the saturation current I cell1 , so the discharge capacitance C when the data is "10" SOThe voltage drop rate is greater than the discharge capacitance C when the data is "01". SO The voltage drop rate, that is, the discharge capacitance C when the data is "10" SO The slope of the voltage change is greater than the discharge capacitance C when the data is "01". SO The slope of the voltage change. When the data is "00", the total current on the reading circuit is 0, and the discharge capacitor C SO The voltage remains unchanged.

[0064] The voltage comparison unit 412 is used to receive the discharge capacitor C SO The discharge capacitor voltage V SO , and compare the discharge capacitor voltage V SO Compare with voltage V THSA In the embodiment of the present application, the voltage comparison unit 412 can set M latch time points. The relationship between the number M of multiple latch time points and the number N of pages read simultaneously is: M≥(2 N -1); M and N are positive integers greater than or equal to 2.

[0065] The NAND flash memory 400 can be divided into single level cell (SLC), multi level cell (MLC), triple level cell (TLC), quad level cell (QLC), etc. according to the number of bits stored in the storage cell.

[0066] SLC is a type of flash memory where each memory cell can only store one bit (0 or 1). When SLC reads a page of data, a read voltage V is applied to the memory cell. read , so the relationship between the number M of latching time points set by the voltage comparison unit 412 and the number N of pages read simultaneously is: M≥(2 N -1).

[0067] Each memory cell of MLC can store multiple bits, usually 2 bits. When MLC reads data of a page, it applies X1 read voltage V to the memory cell. read , so the relationship between the number M of latching time points set by the voltage comparison unit 412 and the number N of pages read simultaneously is: M≥(2 N -1)×X1, where X1 is 1 or 2. The value of X1 depends on the type of page being read.

[0068] Each memory cell of TLC can store more bits, usually 3 bits. When TLC reads a page of data, a read voltage of X2 is applied to the memory cell. read, so the relationship between the number M of latching time points set by the voltage comparison unit 412 and the number N of pages read simultaneously is: M≥(2 N -1)×X2, where X2 is 1, 2, 3, or 4. The value of X2 depends on the type of page being read.

[0069] Each memory cell of QLC can store more bits, usually 4 bits. When QLC reads a page of data, a read voltage of X3 is applied to the memory cell. read , so the relationship between the number M of latching time points set by the voltage comparison unit 412 and the number N of pages read simultaneously is: M≥(2 N -1)×X3, where X3 is 1, 2, 3, 4, 5, 6, 7, or 8. The value of X3 depends on the type of page being read.

[0070] The voltage comparison unit 412 is used to compare the voltage V SO and a specific comparison voltage V THSA In one embodiment of the present application, the voltage comparison unit 412 can detect the comparison result at each latch time point and input the comparison result to the data cache unit 413. In one embodiment, the voltage comparison unit 412 determines the discharge capacitor voltage V at a latch time point. SO Greater than the comparison voltage V THSA In another case, the voltage comparison unit 412 determines the voltage V of the discharge capacitor at a latch time point. SO Equal to or less than the comparison voltage V THSA When , the output is "pass".

[0071] There is at least one latch time point between different discharge time points. The discharge time point refers to the time it takes for the voltage of the discharge capacitor electrically connected to the target dual-gate MOS transistor of multiple pages read simultaneously to drop to the comparison voltage. Preferably, the first latch time point among the M latch time points can be set to the discharge capacitor C when the data is "11". SO The voltage drops to the comparison voltage V THSA The Mth latch time point among the M latch time points can be set to the discharge capacitor C when the data is "01". SO The voltage drops to the comparison voltage V THSA The 2nd to N-1st latch time points among the M latch time points are between the first latch time point and the Mth latch time point.

[0072] As shown in FIG5 , the voltage comparison unit 412 sets three latch time points. The first latch time point can be set to the discharge capacitor C when the data is “11”. SO The voltage drops to the comparison voltage V THSA The second latch time point can be set to the discharge capacitor C when the data is "10". SO The voltage drops to the comparison voltage V THSA The third latch time point can be set to the discharge capacitor C when the data is "01". SO The voltage drops to the comparison voltage V THSA time point.

[0073] The results output by the voltage comparison unit 412 are shown in Table 1. When the data is "11", the voltage comparison unit 412 outputs "pass" at the first latch time point, outputs "pass" at the second latch time point, and outputs "pass" at the third latch time point. When the data is "10", the voltage comparison unit 412 outputs "fail" at the first latch time point, outputs "pass" at the second latch time point, and outputs "pass" at the third latch time point. When the data is "01", the voltage comparison unit 412 outputs "fail" at the first latch time point, outputs "fail" at the second latch time point, and outputs "pass" at the third latch time point. When the data is "00", the voltage comparison unit 412 outputs "fail" at the first latch time point, outputs "fail" at the second latch time point, and outputs "fail" at the third latch time point.

[0074] Table 1 Output results of voltage comparison unit for different data at three latch time points

[0075] The data cache unit 413 is coupled to the voltage comparison unit 412 and is used to store the results of multiple latches by the voltage comparison unit 412 and to transmit data to the decoding unit 414. In the embodiment of the present application, the data cache unit 413 temporarily caches the data read by the NAND flash memory 400 from the NAND array 420 so that the read data can be subsequently transmitted to the host or processor. The decoding unit 414 is coupled to the data cache unit 413 and is used to read the comparison results of the voltage comparison unit 412 cached in the data cache unit 413 and, based on the comparison results, analyze whether the data of each page is "0" or "1".

[0076] The decoding unit 414 is used to calculate and process the results of multiple latches of the data storage unit 413, so as to obtain the original data of the read storage unit. In the embodiment of the present application, the decoding unit 414 pre-stores the preset results of Table 1, and can define that when the comparison results of the three latch time points are all "pass", the data of page 0 is "1", and the data of page 1 is "1". The NAND flash memory 400 can define that when the comparison result of the first latch time point is "fail", and the comparison results of the second latch time point and the third latch time point are "pass", the data of page 0 is "1", and the data of page 1 is "0". The NAND flash memory 400 can define that when the comparison results of the first latch time point and the second latch time point are "fail", and the comparison result of the third latch time point is "pass", the data of page 0 is "0", and the data of page 1 is "1". The NAND flash memory 400 can define that when the comparison results of the three latch time points are all "fail", the data of page 0 is "0", and the data of page 1 is "0".

[0077] The decoding unit 414 receives three results, all of which are "pass", and the output data is "11". The decoding unit 414 receives the first result as "fail", and the second and third results are both "pass", and the output data is "10". The decoding unit 414 receives the first and second results as "fail", and the third result is "pass", and the output data is "01". The decoding unit 414 receives three results, all of which are "fail", and the output data is "00". Alternatively, if "pass" is regarded as logic "1" and "fail" as logic "0", the result of the first page is the logical OR operation of the first and second latch results, and the result of the second page is the logical OR operation of the first and third latch results.

[0078] In the embodiment of the present application, when the NAND flash memory 400 reads multiple pages of the same plane at the same time, the saturation current of the dual-gate MOS transistor of the storage unit of each page can be changed to make the saturation current of each page different, so that the data recorded on each page is different, the total current of the reading circuit is different, and the discharge capacitor C SO When the NAND flash memory 400 reads data from multiple pages, the voltage comparison unit can be used to detect the discharge capacitor C at multiple latch time points. SO The relationship between the voltage and the comparison voltage can be used to accurately read the data recorded in each page and avoid confusion between the read data and the page.

[0079] FIG6 is a schematic diagram of the structure of the second NAND memory provided in an embodiment of the present application. As shown in FIG6 , compared with the structure of NAND memory 400 , the structure of NAND memory 600 replaces the current limiting unit 430 with a time control unit 630 .

[0080] The timing control unit 630 is used to stagger the discharge time of each page, such as by changing the read voltage V read By means of the application time, adjusting the time when different pages start to enter the evaluation phase by adding additional switches, etc., the storage cells of each page can enter the evaluation phase and read data at different times. In the embodiment of the present application, the timing control unit 630 can be connected to each sub-block selection tube, and by sending a control signal to the sub-block selection tube, the sub-block selection tube is turned on to enable the storage cells of the pages corresponding to different sub-blocks to read data at different times. Optionally, the NAND memory 600 can set a switch tube on each WL. The timing control unit 630 is connected to each switch tube respectively, and by sending a control signal to the switch tube, the switch tube is turned on to enable the storage cells of different pages to read data at different times.

[0081] Take the NAND flash memory 400 as an example to read data from two pages of memory cells at the same time, let the two pages be page 0 and page 1. Assume that the memory cells of page 0 are connected to sub-block select transistor 0 and BL0, and the memory cells of page 1 are connected to sub-block select transistor 1 and BL1. The saturation current I of the dual-gate MOS transistors of the memory cells of the two pages is cell The same, and the dual-gate MOS transistors of the memory cells of the two pages apply a read voltage V read The time difference is a set time T. The length of the set time T is equal to or less than the time it takes for the memory cell of page 0 to read data.

[0082] During the evaluation process, the timing control unit 630 first turns on the sub-block selection transistors where page 0 is located, and after waiting for the set time T, turns on the sub-block selection transistors where page 1 is located. If the data of the storage cells of page 0 is "1" and the data of the storage cells of page 1 is "1", the dual-gate MOS transistors of the storage cells of page 0 are in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistors is the saturation current I cell , and the dual-gate MOS transistor of the memory cell of page 1 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell Therefore, the total current in the reading circuit when the data is "11" is from I cell After time T, it becomes 2I cell .

[0083] If the data of the memory cell of page 0 is "1" and the data of the memory cell of page 1 is "0", the dual-gate MOS transistor of the memory cell of page 0 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell , and the dual-gate MOS transistor of the memory cell of page 1 is in the off state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. Therefore, the total current on the reading circuit when the data is "10" is always I cell .

[0084] If the data of the memory cell of page 0 is "0" and the data of the memory cell of page 1 is "1", the dual-gate MOS transistor of the memory cell of page 0 is in the off state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is 0, and the dual-gate MOS transistor of the memory cell of page 1 is in the on state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is the saturation current I cell Therefore, the total current in the reading circuit when the data is "01" is I cell .

[0085] If the data in the memory cells of page 0 is "0" and the data in the memory cells of page 1 is "0", the dual-gate MOS transistors of the memory cells of page 0 are in the off state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistors is zero. Similarly, the dual-gate MOS transistors of the memory cells of page 1 are in the off state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistors is zero. Therefore, the total current in the read circuit when the data is "00" is always zero.

[0086] The total current on the reading circuit is different, the discharge capacitor C SO The voltage from the voltage V SO Drop to the comparison voltage V THSA As shown in Figure 7, the total current on the reading circuit when the data is "11" is I cell When the discharge capacitor C SO The voltage drops faster and has a larger slope. When the data is "11", the total current in the reading circuit becomes 2I cell When the discharge capacitor C SO The voltage drop speed increases, and the slope increases on the original basis. When the data is "10", the total current on the reading circuit is always I cell , so the discharge capacitor C SO The voltage drop rate remains unchanged, and the slope remains unchanged. When the total current on the reading circuit is 0 when the data is "01", the discharge capacitor C SOThe voltage remains unchanged. The total current in the reading circuit when the data is "01" becomes I cell When the discharge capacitor C SO The voltage starts to drop, and the speed of drop is the same as that of the discharge capacitor C when the data is "10". SO The voltage drops at the same speed and has the same slope. When the data is "00", the total current on the reading circuit is 0, and the discharge capacitor C SO The voltage remains unchanged.

[0087] The voltage comparison unit 612 sets three latch time points. The first latch time point can be set to the discharge capacitor C when the data is "11". SO The voltage drops to the comparison voltage V THSA The second latch time point can be set to the discharge capacitor C when the data is "10". SO The voltage drops to the comparison voltage V THSA The third latch time point can be set to the discharge capacitor C when the data is "01". SO The voltage drops to the comparison voltage V THSA time point.

[0088] The results output by the voltage comparison unit 612 are shown in Table 2. When the data is "11", the voltage comparison unit 612 outputs "pass" at the first latch time point, outputs "pass" at the second latch time point, and outputs "pass" at the third latch time point. When the data is "10", the voltage comparison unit 612 outputs "fail" at the first latch time point, outputs "pass" at the second latch time point, and outputs "pass" at the third latch time point. When the data is "01", the voltage comparison unit 612 outputs "fail" at the first latch time point, outputs "fail" at the second latch time point, and outputs "pass" at the third latch time point. When the data is "00", the voltage comparison unit 612 outputs "fail" at the first latch time point, outputs "fail" at the second latch time point, and outputs "fail" at the third latch time point.

[0089] Table 2 Output results of voltage comparison unit for different data at three latch time points

[0090] The decoding unit 614 pre-stores the preset results of Table 2, and can define that when the comparison results of the three latch time points are all "pass", the data of page 0 is "1", and the data of page 1 is "1". The NAND flash memory 600 can define that when the comparison result of the first latch time point is "fail", and the comparison results of the second latch time point and the third latch time point are "pass", the data of page 0 is "1", and the data of page 1 is "0". The NAND flash memory 600 can define that when the comparison results of the first latch time point and the second latch time point are "fail", and the comparison result of the third latch time point is "pass", the data of page 0 is "0", and the data of page 1 is "1". The NAND flash memory 600 can define that when the comparison results of the three latch time points are all "fail", the data of page 0 is "0", and the data of page 1 is "0".

[0091] Decoding unit 614 receives three results, all of which are "pass," and outputs "11." Decoding unit 614 receives the first result, "fail," and the second and third results, all of which are "pass," and outputs "10." Decoding unit 614 receives the first and second results, all of which are "fail," and the third result, all of which are "pass," and outputs "01." Decoding unit 614 receives three results, all of which are "fail," and outputs "00."

[0092] In the embodiment of the present application, the NAND flash memory 600 can change the time of reading the data recorded by the storage unit of each page for multiple pages of the same surface at the same time, so that the data recorded on each page is different, the total current of the reading circuit is different, and the discharge capacitor C SO When the NAND flash memory 600 reads data from multiple pages, the voltage comparison unit can be used to detect the discharge capacitor C at multiple latch time points. SO The relationship between the voltage and the comparison voltage can be used to accurately read the data recorded in each page and avoid confusion between the read data and the page.

[0093] FIG8 is a schematic diagram of the structure of the third NAND memory provided in an embodiment of the present application. As shown in FIG8 , compared with the structure of NAND memory 400 , the structure of NAND memory 800 replaces the current limiting unit 430 with a current limiting time control unit 830 .

[0094] The current limiting and timing control unit 830 has the functions of the current limiting unit 430 and the timing control unit 630, and is used to limit the saturation current of each page, making the saturation current of each page different, and stagger the discharge time of each page, so that the storage cells of each page can read data at different times.

[0095] Taking the NAND flash memory 800 as an example, in which data of storage cells in four pages are read simultaneously, the four pages are assumed to be page 0, page 1, page 2, and page 3.

[0096] The current limiting timing control unit 830 can make all or part of the saturation currents of the dual-gate MOS transistors of the memory cells of the four pages different, and can make all or part of the time for applying the read voltage to the dual-gate MOS transistors of the memory cells of the four pages different. For example, the current limiting timing control unit 830 can make the saturation current of the dual-gate MOS transistors of the memory cells of page 0 the same as the saturation current of the dual-gate MOS transistors of the memory cells of page 1, make the saturation current of the dual-gate MOS transistors of the memory cells of page 2 the same as the saturation current of the dual-gate MOS transistors of the memory cells of page 3, and can make the saturation current of the dual-gate MOS transistors of the memory cells of page 0 different from the saturation current of the dual-gate MOS transistors of the memory cells of page 2. The current limiting control unit 830 allows the dual-gate MOS transistors of the memory cells of page 0 to apply the read voltage at the same time as the dual-gate MOS transistors of the memory cells of page 2, allows the dual-gate MOS transistors of the memory cells of page 1 to apply the read voltage at the same time as the dual-gate MOS transistors of the memory cells of page 3, and allows the dual-gate MOS transistors of the memory cells of page 0 to apply the read voltage at different times than the dual-gate MOS transistors of the memory cells of page 1. This application does not provide examples of other situations.

[0097] Assume that the saturation current of the dual-gate MOS tube of the memory cell of the four pages is I cell0 >I cell1 >I cell2 >I cell3 The time when the dual-gate MOS transistors of the memory cells of the four pages apply the read voltage is sequentially different by a set time T.

[0098] During the evaluation process, the current limiting and time control unit 830 first turns on the sub-block selection transistors for page 0, waits for a set time T, and then turns on the sub-block selection transistors for page 1. This process continues in this way until the sub-block selection transistors for page 1 are turned on.

[0099] If the data of the storage cells of the four pages is "1111", the dual-gate MOS transistor of the storage cell of page 0 is in the on state, and the current flowing through the channel between the source and the drain of the dual-gate MOS transistor is the saturation current I cell0 , the dual-gate MOS transistor of the memory cell of page 1 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell1, the dual-gate MOS transistor of the memory cell of page 2 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell2 The dual-gate MOS transistor of the memory cell on page 3 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell3 Therefore, the total current in the reading circuit when the data is "1111" changes to I cell0 , I cell0 +I cell1 , I cell0 +I cell1 +I cell2 and I cell0 +I cell1 +I cell2 +I cell3 .

[0100] If the data of the storage cells of the four pages is "1110", the dual-gate MOS transistor of the storage cell of page 0 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell0 , the dual-gate MOS transistor of the memory cell of page 1 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell1 , the dual-gate MOS transistor of the memory cell of page 2 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell2 , the dual-gate MOS transistor of the memory cell on page 3 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. Therefore, the total current in the read circuit when the data is "1110" changes in sequence to I cell0 , I cell0 +I cell1 and I cell0 +I cell1 +I cell2 .

[0101] If the data of the storage cells of the four pages is "1101", the dual-gate MOS transistor of the storage cell of page 0 is in the on state, and the current flowing through the channel between the source and the drain of the dual-gate MOS transistor is the saturation current I cell0 , the dual-gate MOS transistor of the memory cell of page 1 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell1The dual-gate MOS transistor of the memory cell on page 2 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the memory cell on page 3 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell3 Therefore, the total current in the read circuit when the data is "1101" changes to I cell0 , I cell0 +I cell1 and I cell0 +I cell1 +I cell3 .

[0102] If the data of the storage cells of the four pages is "1100", the dual-gate MOS transistor of the storage cell of page 0 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell0 , the dual-gate MOS transistor of the memory cell of page 1 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell1 , the dual-gate MOS transistor of the memory cell on page 2 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the memory cell on page 3 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. Therefore, the total current in the read circuit when the data is "1100" changes in sequence to I cell0 and I cell0 +I cell1 .

[0103] If the data of the storage cells of the four pages is "1011", the dual-gate MOS transistor of the storage cell of page 0 is in the on state, and the current flowing through the channel between the source and the drain of the dual-gate MOS transistor is the saturation current I cell0 The dual-gate MOS transistor of the memory cell on page 1 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the memory cell on page 2 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell2 The dual-gate MOS transistor of the memory cell on page 3 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell3 Therefore, the total current on the read circuit when the data is "1011" changes to I cell0 , I cell0 +I cell2 and I cell0 +I cell2 +Icell3 .

[0104] If the data of the storage cells of the four pages is "1010", the dual-gate MOS transistor of the storage cell of page 0 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell0 The dual-gate MOS transistor of the memory cell on page 1 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the memory cell on page 2 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell2 , the dual-gate MOS transistor of the memory cell on page 3 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. Therefore, the total current in the read circuit when the data is "1010" changes to I cell0 and I cell0 +I cell2 .

[0105] If the data of the storage cells of the four pages is "1001", the dual-gate MOS transistor of the storage cell of page 0 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell0 The dual-gate MOS transistor of the memory cell on page 1 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the memory cell on page 2 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the memory cell on page 3 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell3 Therefore, the total current in the reading circuit when the data is "1001" changes to I cell0 and I cell0 +I cell3 .

[0106] If the data of the storage cells of the four pages is "1000", the dual-gate MOS transistor of the storage cell of page 0 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell0, the dual-gate MOS transistor of the memory cell on page 1 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the memory cell on page 2 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the memory cell on page 3 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. Therefore, the total current in the read circuit when the data is "1000" is always I cell0 .

[0107] If the data of the storage cells of the four pages are "0111", the dual-gate MOS transistor of the storage cell of page 0 is in the on state, and the current flowing through the channel between the source and the drain of the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the storage cell of page 1 is in the on state, and the current flowing through the channel between the source and the drain of the dual-gate MOS transistor is the saturation current I cell1 , the dual-gate MOS transistor of the memory cell of page 2 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell2 The dual-gate MOS transistor of the memory cell on page 3 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell3 Therefore, the total current in the reading circuit when the data is "0111" changes to I cell1 , I cell1 +I cell2 and I cell1 +I cell2 +I cell3 .

[0108] If the data of the storage cells of the four pages are "0110", the dual-gate MOS transistor of the storage cell of page 0 is in the on state, and the current flowing through the channel between the source and the drain of the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the storage cell of page 1 is in the on state, and the current flowing through the channel between the source and the drain of the dual-gate MOS transistor is the saturation current I cell1 , the dual-gate MOS transistor of the memory cell of page 2 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell2 , the dual-gate MOS transistor of the memory cell on page 3 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. Therefore, the total current in the read circuit when the data is "0110" changes to I cell1 , and I cell1 +I cell2 .

[0109] If the data of the storage cells of the four pages are "0101", the dual-gate MOS transistor of the storage cell of page 0 is in the on state, and the current flowing through the channel between the source and the drain of the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the storage cell of page 1 is in the on state, and the current flowing through the channel between the source and the drain of the dual-gate MOS transistor is the saturation current I cell1 The dual-gate MOS transistor of the memory cell on page 2 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the memory cell on page 3 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell3 Therefore, the total current in the reading circuit when the data is "0101" changes to I cell1 and I cell1 +I cell3 .

[0110] If the data of the storage cells of the four pages are "0100", the dual-gate MOS transistor of the storage cell of page 0 is in the on state, and the current flowing through the channel between the source and the drain of the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the storage cell of page 1 is in the on state, and the current flowing through the channel between the source and the drain of the dual-gate MOS transistor is the saturation current I cell1 , the dual-gate MOS transistor of the memory cell on page 2 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the memory cell on page 3 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. Therefore, the total current in the reading circuit when the data is "0100" is always I cell2 .

[0111] If the data of the storage cells of the four pages are "0011", the dual-gate MOS transistor of the storage cell of page 0 is in the on state, and the current flowing through the channel between the source and the drain of the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the storage cell of page 1 is in the on state, and the current flowing through the channel between the source and the drain of the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the storage cell of page 2 is in the on state, and the current flowing through the channel between the source and the drain of the dual-gate MOS transistor is the saturation current I cell2 The dual-gate MOS transistor of the memory cell on page 3 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I cell3 Therefore, the total current on the read circuit when the data is "0011" changes to I cell2 and I cell2 +I cell3 .

[0112] If the data of the storage cells of the four pages is "0001", the dual-gate MOS transistor of the storage cell of page 0 is in the on state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the storage cell of page 1 is in the on state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the storage cell of page 2 is in the on state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the storage cell of page 3 is in the on state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is the saturation current I cell3 Therefore, the total current in the reading circuit when the data is “0001” is always I cell3 .

[0113] If the data of the memory cells in the four pages is "0000", the dual-gate MOS transistors of the memory cells in page 0 are in the on-state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistors is zero. The dual-gate MOS transistors of the memory cells in page 1 are in the on-state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistors is zero. The dual-gate MOS transistors of the memory cells in page 2 are in the on-state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistors is zero. The dual-gate MOS transistors of the memory cells in page 3 are in the on-state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistors is zero. Therefore, the total current in the read circuit when the data is "0000" is always zero.

[0114] The total current on the reading circuit is different, the discharge capacitor C SO The voltage from the voltage V SO Drop to the comparison voltage V THSA The slopes of the discharge capacitors are different. The larger the total current, the smaller the discharge capacitance C. SO The greater the slope of the voltage change. The voltage comparison unit 812 can detect the comparison results of multiple latch time points and input the multiple comparison results into the data cache unit 813. The data cache unit 813 temporarily caches the data read by the NAND flash memory 800 from the NAND array 820 so that the read data can be subsequently transmitted to the host or processor. The decoding unit 814 can read the comparison results of the voltage comparison unit 812 cached in the data cache unit 813 and, based on the comparison results, analyze whether the data of each page is "0" or "1".

[0115] In the embodiment of the present application, the NAND flash memory 800 can change the saturation current of the dual-gate MOS transistor of the storage unit of each page for multiple pages on the same plane at the same time, so that the saturation current of each page is different, and change the time of reading the data recorded by the storage unit of each page, so that the data recorded on each page is different, the total current of the reading circuit is different, and the discharge capacitor C is discharged. SO When the NAND flash memory 800 reads data from multiple pages, the voltage comparison unit can be used to detect the discharge capacitor C at multiple latch time points. SO The relationship between the voltage and the comparison voltage can be used to accurately read the data recorded in each page and avoid confusion between the read data and the page.

[0116] An embodiment of the present application provides a memory device comprising a circuit board and at least one NAND flash memory. The NAND flash memory device is fixed to and electrically connected to the circuit board and is used to store data. The NAND flash memory device may be the NAND flash memory device shown in Figures 4-8. Because the memory device comprises the NAND flash memory device shown in Figures 4-8, the memory device has all or at least some of the advantages of NAND flash memory. The memory device may be an SSD, a USB flash drive, a memory card, a mobile device, or the like.

[0117] An embodiment of the present application provides an electronic device comprising at least one memory and at least one processor. The at least one processor is electrically connected to the at least one memory and is configured to write data into the at least one memory and / or read data from the at least one memory. Since the memory comprises NAND flash memory as shown in Figures 4 to 8, the electronic device has all or at least some of the advantages of NAND flash memory. The electronic device may be a smartphone, a laptop, a tablet computer, a desktop computer, a server, a storage system, a base station, an unmanned aircraft, an outdoor cabinet, and the like.

[0118] The number, positional relationship, type, and shape of the various components of the memory provided in the embodiments of this application are not limited to the above-described embodiments. Any technical solution implemented under the principles of this application is within the scope of protection of this solution. Any technical solution combining one or more embodiments or illustrations in the specification in an appropriate manner is within the scope of protection of this solution.

[0119] The number, positional relationship, type, and shape of the components of the electronic device provided in the embodiments of this application are not limited to the above-described embodiments. Any technical solution implemented under the principles of this application is within the scope of protection of this solution. Any one or more embodiments or illustrations in the specification, combined in an appropriate manner, are within the scope of protection of this solution.

[0120] Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present application. Those skilled in the art should understand that, although the present application has been described in detail with reference to the aforementioned embodiments, the technical solutions described in the aforementioned embodiments may be modified or some of the technical features thereof may be replaced with equivalents. However, such modifications or replacements do not deviate from the spirit and scope of the technical solutions in the various embodiments of the present application.

Claims

1. A NAND flash memory (400, 600, 800), characterized in that: include: A voltage control unit (411, 611, 811), comprising a plurality of first output ports and a plurality of second output ports, wherein the plurality of first output ports are all used to output a first electrical signal, and the plurality of second output ports are all used to output a second electrical signal; A NAND array (420, 620, 820), comprising a plurality of sub-blocks, each sub-block comprising a plurality of pages, the plurality of pages being electrically connected to the plurality of first output ports respectively, and being used to read or write data when receiving the first electrical signal; An asynchronous unit (430, 630, 830), electrically connected between the plurality of first output ports and the plurality of sub-blocks, or electrically connected to the gates of the sub-block selection tubes in the plurality of pages of the plurality of sub-blocks and the gates of the dual-gate MOS tubes in the plurality of pages of the plurality of sub-blocks, for making the saturation currents of the target dual-gate MOS tubes for simultaneously reading the plurality of pages different, and / or making the conduction time of each page for simultaneously reading the plurality of pages different; Multiple discharge capacitors (C SO ), the first ends of the plurality of discharge capacitors are electrically connected to the plurality of second output ports respectively, and the second ends of the plurality of discharge capacitors are grounded; The voltage comparison unit (412, 612, 812) comprises a plurality of input ports, wherein the plurality of input ports are electrically connected to the plurality of second output ports respectively, and is used for comparing the magnitudes of the voltages received by the plurality of input ports with the comparison voltage, and outputting the comparison result.

2. The NAND flash memory according to claim 1, wherein: The discharge capacitor is in a discharging state when the data recorded by the target dual-gate MOS transistor of the page electrically connected to the discharge capacitor is "1"; the discharge capacitor is in a charging state when the data recorded by the target dual-gate MOS transistor of the page electrically connected to the discharge capacitor is "0".

3. The NAND flash memory according to claim 1 or 2, characterized in that: The voltage comparison unit is specifically used to compare the voltages received by the multiple input ports at multiple latch time points with the comparison voltage to obtain multiple sub-output results; The NAND flash memory further includes: A decoding unit (414, 614, 814) is used to compare the multiple sub-output results with a preset result to determine whether the data recorded by the target dual-gate MOS transistor of each page of the multiple pages read simultaneously is "0" or "1"; the preset result records the sub-output results at different latching time points corresponding to the data recorded by the multiple target dual-gate MOS transistors read simultaneously.

4. The NAND flash memory according to claim 3, characterized in that: The relationship between the number M of the plurality of latching time points and the number N of pages read simultaneously is: M≥(2 N -1); M and N are positive integers greater than or equal to 2.

5. The NAND flash memory according to claim 3 or 4, characterized in that: There is at least one latching time point between different discharge durations; the discharge duration refers to the duration for the voltage of the discharge capacitor electrically connected to the target dual-gate MOS tubes of multiple pages read simultaneously to decrease to the comparison voltage.

6. The NAND flash memory according to any one of claims 1 to 5, characterized in that: When the on-times of the pages of the plurality of pages read simultaneously are different, the time difference between the on-times of two adjacent pages is less than or equal to the time duration for the voltage of the discharge capacitor to decrease to the comparison voltage.

7. The NAND flash memory according to any one of claims 1 to 6, characterized in that: The voltage control unit is further configured to electrically connect the plurality of first output ports to the plurality of second output ports respectively when outputting the first electrical signal and the second electrical signal is stopped.

8. The NAND flash memory according to claim 7, wherein: The voltage control unit is further used to convert the current of the second output port from a first value to a second value.

9. A memory, characterized in that: include: Circuit Boards, At least one NAND flash memory according to any one of claims 1 to 8, wherein the NAND flash memory is fixed to and electrically connected to the circuit board for storing data.

10. An electronic device, characterized in that: include: at least one memory as claimed in claim 9, At least one processor is electrically connected to the at least one memory and is used to write data into the at least one memory and / or read data from the at least one memory.

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