Communication method and related apparatus

Abstract

The present application provides a communication method and a related apparatus, which can improve the decoding performance. The method comprises: acquiring a check matrix of a target SC-LDPC code, wherein the check matrix has M rows and N columns, the value of elements is 0 or 1, the check matrix of the target SC-LDPC code comprises a second matrix composed of an i-th row to an (i+(Z+1)*m-1)-th row among the M rows and a 0th column to an (n-1)-th column among the N columns, the second matrix is obtained by sequentially arranging, on the basis of rows, (Z+1) third matrixes having m rows and n columns, Z third matrixes are present among the (Z+1) third matrixes, and the number K of elements 1 comprised in the Z third matrixes and the number L of elements 1 comprised in the second matrix meet the following relation: K / L=Z*z%; and encoding information bits on the basis of the check matrix of the target SC-LDPC code to obtain a first SC-LDPC codeword.

Description

Communication method and related device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 15, 2023, with application number 202311739096.9 and application name “Communication Methods and Related Devices,” the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a communication method and related devices. Background Art

[0003] Low-density parity check (LDPC) codes are linear block codes with a sparse parity check matrix. LDPC codes not only offer excellent performance approaching the Shannon limit, but also feature low decoding complexity and a flexible structure, making them a research hotspot in the field of channel coding in recent years. Quasi-cyclic low-density parity check (QC-LDPC) codes, a type of structured LDPC code, have been successfully applied in certain communication systems, such as the new radio access technology (NR) of fifth-generation (5G) communication systems, due to their simple description, ease of construction, and space-saving storage.

[0004] However, the QC-LDPC code in the 5G-NR standard currently suffers from an error floor and limited decoding parallelism. This results in low decoding performance in practical applications, making it difficult to meet the encoding and decoding requirements of future communication systems for high-reliability and high-throughput services. Summary of the Invention

[0005] The present application provides a communication method and related devices to improve decoding performance.

[0006] In a first aspect, the present application provides a communication method that can be applied to a first communication device. For example, the first communication device can be a terminal device or a network device, or a component configured in the terminal device or network device (such as a chip, a chip system, etc.), or a logic module or software that can implement all or part of the functions of the terminal device or network device, which is not limited by the present application.

[0007] Exemplarily, the method includes: obtaining a check matrix of a target spatially coupled low-density parity check (spatially coupled LDPC, SC-LDPC) code, wherein the check matrix of the target SC-LDPC code is obtained from a preset check matrix of the SC-LDPC code based on a target code rate and a length of information bits; encoding the information bits based on the check matrix of the target SC-LDPC code to obtain a first SC-LDPC codeword.

[0008] In example 1, the check matrix of the target SC-LDPC code is a portion intercepted from the check matrix of the preset SC-LDPC code based on the target code rate and the length of the information bits.

[0009] In which, the number of rows of the check matrix of the preset SC-LDPC code is M, the number of columns is N, and the value of the elements in the check matrix of the preset SC-LDPC code is 0 or 1, or the number of rows of the check matrix of the target SC-LDPC code is M, the number of columns is N, and the value of the elements in the check matrix of the target SC-LDPC code is 0 or 1.

[0010] In Example 2, a check matrix for a preset SC-LDPC code is included in a first mapping relationship, which indicates a correspondence between at least one code rate, at least one information bit length, and at least one check matrix for a preset SC-LDPC code. That is, the check matrix for the target SC-LDPC code is determined based on the target code rate, the information bit length, and the first mapping relationship.

[0011] The number of rows and columns of the check matrix of the target SC-LDPC code is M, and the value of the elements in the check matrix of the target SC-LDPC code is 0 or 1.

[0012] In combination with Example 1 and Example 2, the first matrix consisting of the 0th to (M-1)th rows in the M rows and the 0th to (n-1)th columns in the N columns includes a second matrix with ((Z+1)*m) rows and n columns, and the elements of the jth to (j+n-1)th columns in the N columns are obtained by cyclically shifting the first matrix downward by ((j / n)*m) rows; the second matrix is ​​a matrix consisting of the i-th to (i+(Z+1)*m-1)th rows in the first matrix, and the other elements in the first matrix except the second matrix are all 0, and the second A matrix is ​​obtained by arranging (Z+1) third matrices with m rows and n columns in sequence, wherein there are Z third matrices among the (Z+1) third matrices, and the number K of elements 1 included in the Z third matrices and the number L of elements 1 included in the second matrix satisfy the following relationship: K / L=Z*z%, K / L≤50%, (LK)≥(K / Z), or the number of remaining elements 1 in the second matrix except the K elements 1 included in the Z third matrices is greater than or equal to the number of elements 1 included in at least one third matrix among the Z third matrices.

[0013] The above Z is an integer greater than 0, z is an integer less than or equal to 100*R, or z is an integer less than or equal to 100*(1-R), R is the target code rate or the maximum code rate supported by the preset SC-LDPC code check matrix, or the minimum code rate, i is an integer greater than or equal to 0 and less than or equal to (M-(Z+1)*m), j=n, 2*n,…,y*n; (y+1)=N / n, M is divisible by m, and n, m, and y are all integers greater than 1.

[0014] Based on this method, the first communication device (device for encoding) encodes the information bits by obtaining the check matrix of the target SC-LDPC code to obtain the first SC-LDPC codeword, and the second communication device (device for decoding) also uses the check matrix of the target SC-LDPC code to decode the first SC-LDPC codeword. Since the multiple second matrices included in the check matrix of the target SC-LDPC code have coupling characteristics, better error performance can be obtained. In addition, the check matrix of the target SC-LDPC code increases the decoding parallelism, which can achieve fast decoding and obtain better decoding performance.

[0015] In combination with the first aspect, in certain implementations of the first aspect, the first SC-LDPC codeword includes Q groups of coding bits, each group of coding bits in the Q groups of coding bits includes a group of information bits and a group of check bits, each group of information bits in the Q groups of information bits includes A information bits, and each group of check bits in the Q groups of check bits includes B check bits, where A and B are integers greater than 0, and Q = N / n.

[0016] In combination with the first aspect, in some possible implementations of the first aspect, the method further includes: reordering the Q groups of coded bits included in the first SC-LDPC codeword to obtain a second SC-LDPC codeword; interleaving and modulating the second SC-LDPC codeword to obtain multiple modulation symbols; and sending the multiple modulation symbols.

[0017] The Q groups of information bits and the Q groups of check bits included in the second SC-LDPC codeword satisfy any of the following characteristics:

[0018] The Q group of information bits are located before the Q group of check bits;

[0019] The q groups of coded bits serving as decoding starting points among the Q groups of coded bits are located before the other groups of coded bits;

[0020] The q groups of coded bits serving as decoding starting points in the Q groups of coded bits are located before the other groups of coded bits, and the information bits in each group of coded bits are located before the check bits; or,

[0021] The q groups of coded bits in the Q groups of coded bits that serve as decoding starting points are located before the other groups of coded bits, and the information bits in the q groups of coded bits are located before the check bits in the q groups of coded bits, where q is an integer greater than 0 and less than or equal to Q.

[0022] Exemplarily, the positions of the other groups of coding bits in the second SC-LDPC codeword are arranged in ascending order according to the first distance, where the first distance refers to the number of coding bit groups between each group of coding bits in the other groups of coding bits and the q groups of coding bits in the first SC-LDPC codeword.

[0023] Exemplarily, the information bits in the other group of coded bits are located before the check bits in the other group of coded bits.

[0024] Optionally, the reordering of the Q groups of coded bits to obtain a second SC-LDPC codeword includes: using a first row-column interleaver to interleave the first SC-LDPC codeword to obtain the second SC-LDPC codeword, where the number of rows of the first row-column interleaver is Q and the number of columns is (A+B).

[0025] Here, interleaving refers to the process of inputting the first SC-LDPC codeword into the first row-column interleaver by row, and then reading out the first SC-LDPC codeword by column.

[0026] Optionally, the reordering of the Q groups of coded bits to obtain a second SC-LDPC codeword includes: based on a decoding method of the first SC-LDPC codeword, reordering the Q groups of coded bits to obtain the second SC-LDPC codeword.

[0027] Example 1: The decoding method is bidirectional sliding window decoding, and the q groups of coded bits are the first group of coded bits and the Qth group of coded bits in the first SC-LDPC codeword.

[0028] Example 2: The decoding method is parallel sliding window decoding, q is an integer greater than 2 and less than or equal to Q, and the q group of bits is a coding bit group in the Q group of bits that serves as a decoding starting point.

[0029] It can be understood that the above decoding method can be indicated by the second communication device (for example, the decoding device) to the first communication device.

[0030] Optionally, the interleaving and modulating the second SC-LDPC codeword to obtain multiple modulation symbols includes: using a second row-column interleaver to interleave the second SC-LDPC codeword to obtain a third SC-LDPC codeword, the number of rows of the second row-column interleaver is P, the number of columns is D, D = ceil((A+B)*Q / P), and P is the modulation order; mapping P consecutive bits in the third SC-LDPC codeword to a modulation symbol to obtain multiple modulation symbols, where ceil() represents rounding up.

[0031] In a second aspect, the present application provides a communication method that can be applied to a second communication device. For example, the second communication device can be a terminal device or a network device, or a component configured in the terminal device or network device (such as a chip, a chip system, etc.), or a logic module or software that can implement all or part of the functions of the terminal device or network device, which is not limited by the present application.

[0032] Exemplarily, the method includes: receiving multiple modulation symbols; demodulating and processing the multiple modulation symbols to obtain a first SC-LDPC codeword; obtaining a check matrix of a target SC-LDPC code, wherein the check matrix of the target SC-LDPC code is obtained from a preset check matrix of the SC-LDPC code based on a target code rate and a length of information bits; decoding the first SC-LDPC codeword based on the check matrix of the target SC-LDPC code to obtain the information bits.

[0033] For the description of the check matrix of the target SC-LDPC code and the check matrix of the preset SC-LDPC code, please refer to the description of the first aspect above and will not be repeated here.

[0034] Based on this method, the first communication device (for example, a decoding device) demodulates and processes the received modulation symbols to obtain a first SC-LDPC codeword, and uses the check matrix of the target SC-LDPC code that encodes the information bits on the first communication device side to decode the first SC-LDPC codeword. Since the multiple second matrices of the check matrix of the target SC-LDPC code obtained by the first communication device and the second communication device have coupling characteristics, better error performance can be obtained. At the same time, the check matrix of the target SC-LDPC code increases the decoding parallelism, which can achieve fast decoding and obtain better decoding performance.

[0035] In combination with the second aspect, in some possible implementations of the second aspect, the demodulating and processing the multiple modulation symbols to obtain a first SC-LDPC codeword includes: demodulating the multiple modulation symbols to obtain a third SC-LDPC codeword, the third SC-LDPC codeword including (Q*A) information bits and (Q*B) check bits; performing deinterleaving processing on the third SC-LDPC codeword to obtain a second SC-LDPC codeword, the second SC-LDPC codeword including Q groups of information bits and Q groups of check bits, each group of information bits in the Q groups of information bits including A information bits, each group of check bits in the Q groups of check bits including B check bits, A and B are integers greater than 0, Q=N / n; reordering the Q groups of information bits and Q groups of check bits in the second SC-LDPC codeword to obtain the first SC-LDPC codeword, the first SC-LDPC codeword including Q groups of coding bits, each group of coding bits in the Q groups of coding bits including a group of information bits and a group of check bits.

[0036] Deinterleaving is the inverse of interleaving. For example, a second row-column interleaver is used to deinterleave the third SC-LDPC codeword to obtain a second SC-LDPC codeword. The second row-column interleaver has P rows and D columns, where D = ceil((A+B)*Q / P), and P is the modulation order. Deinterleaving the third SC-LDPC codeword involves inputting the third SC-LDPC codeword into the second row-column interleaver by column and reading out the second SC-LDPC codeword by row.

[0037] In combination with the second aspect, in some possible implementations of the second aspect, the reordering of the Q groups of information bits and Q groups of check bits in the second SC-LDPC codeword to obtain the first SC-LDPC codeword includes: using a first row-column interleaver to deinterleave the second SC-LDPC codeword to obtain the first SC-LDPC codeword, the number of rows of the first row-column interleaver being Q, and the number of columns being (A+B).

[0038] It can be understood that the above-mentioned sorting manner may be indicated by the first communication device (for example, the encoding device) to the second communication device.

[0039] In combination with the first and second aspects, in some implementations, the K elements 1 included in the fourth matrix are uniformly distributed among the L elements 1 included in the fifth matrix, the fourth matrix is ​​the sum of the Z third matrices, and the fifth matrix is ​​the sum of the (Z+1) third matrices.

[0040] In other words, the K elements 1 included in the fourth matrix are uniformly selected (or selected at equal intervals) from the L elements 1 included in the fifth matrix.

[0041] Optionally, the K elements 1 may be randomly selected from the L elements 1.

[0042] Exemplarily, the fifth matrix includes at least K elements 1 with different numbers of rows and columns, and the elements 1 included in the fourth matrix belong to the at least K elements 1 with different numbers of rows and columns.

[0043] Exemplarily, the fifth matrix includes at least K' elements 1 with different numbers of rows and columns, and the fourth matrix includes at least K' elements 1 with different numbers of rows and columns, where K' is an integer greater than 0 and less than K.

[0044] In combination with the first and second aspects, in certain implementations, the elements 1 included in each of the Z third matrices are evenly distributed among the K elements 1 included in the fourth matrix.

[0045] In other words, the elements 1 included in each of the Z third matrices are uniformly selected (or selected at equal intervals) from the L elements 1 included in the fourth matrix.

[0046] Optionally, the elements 1 included in each of the Z third matrices are randomly selected from the L elements 1 included in the fourth matrix, and the elements 1 included in any two third matrices have different positions in the fourth matrix.

[0047] In a third aspect, the present application provides a communication device including modules or units for implementing the method in any of the above aspects and any possible implementation of any of the aspects. It should be understood that each module or unit can implement the corresponding function by executing a computer program.

[0048] In a fourth aspect, the present application provides a communication device, comprising a processor, wherein the processor is configured to execute the method described in any of the above aspects and any possible implementation of any of the aspects.

[0049] The apparatus may further include a memory for storing instructions and data. The memory is coupled to the processor, and when the processor executes the instructions stored in the memory, the method described in the above aspects may be implemented.

[0050] The apparatus may further include a communication interface, where the communication interface is used for the apparatus to communicate with other devices. Exemplarily, the communication interface may be a transceiver, a circuit, a bus, a module, or other types of communication interfaces.

[0051] In a fifth aspect, the present application provides a chip system comprising at least one processor for supporting the implementation of the functions involved in any of the above aspects and any possible implementation of any aspect, for example, receiving or processing the data and / or information involved in the above method.

[0052] In one possible design, the chip system further includes a memory, which is used to store program instructions and data, and the memory is located inside or outside the processor.

[0053] The chip system can be composed of chips, or can include chips and other discrete devices.

[0054] In a sixth aspect, the present application provides a computer-readable storage medium comprising a computer program, which, when executed on a computer, enables the computer to implement the method in any of the above aspects and any possible implementation of any of the aspects.

[0055] In the seventh aspect, the present application provides a computer program product, which includes: a computer program (also referred to as code, or instructions), which, when executed, enables a computer to execute the method in any of the above aspects and any possible implementation of any aspect.

[0056] In an eighth aspect, the present application provides a communication system comprising the aforementioned first communication device and a second communication device. The first communication device is configured to execute the method of the aforementioned first aspect and any possible implementation thereof, and the second communication device is configured to execute the method of the aforementioned second aspect and any possible implementation thereof.

[0057] It should be understood that the third to eighth aspects of the present application correspond to the technical solutions of the first or second aspect of the present application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] FIG1 is a schematic diagram of the architecture of a communication system applicable to the method provided in an embodiment of the present application;

[0059] FIG2 is a schematic diagram of signal processing provided by an embodiment of the present application;

[0060] FIG3 is a schematic flow chart of a communication method provided in an embodiment of the present application;

[0061] 4 to 6 are schematic diagrams of a method for selecting K elements 1 according to an embodiment of the present application;

[0062] 7 to 9 are schematic diagrams of the connection relationship between multiple variable nodes and multiple check nodes provided in embodiments of the present application;

[0063] FIG10 is a schematic diagram of a first SC-LDPC codeword provided in an embodiment of the present application;

[0064] FIG11 is a schematic diagram of an interleaving process provided in an embodiment of the present application;

[0065] FIG12 is a schematic diagram of a method for determining a third SC-LDPC codeword provided in an embodiment of the present application;

[0066] 13 and 14 are schematic block diagrams of devices provided in embodiments of the present application. DETAILED DESCRIPTION

[0067] The technical solution in this application will be described below with reference to the accompanying drawings.

[0068] To facilitate understanding of the embodiments of the present application, the following points are first explained:

[0069] First, in the embodiments of the present application, prefixes such as "first" and "second" are used only to facilitate the distinction and description of different things belonging to the same name category, and do not restrict the order, size, or quantity of things. For example, "first communication device" and "second communication device" are simply different devices, and do not limit the number of devices or the priority relationship; for another example, "first SC-LDPC codeword" and "second SC-LDPC codeword" are simply different codewords, and there is no size or priority relationship between the two.

[0070] Second, the “sending” and “receiving” in the embodiments of the present application indicate the direction of signal transmission. For example, “sending multiple modulation symbols to the second communication device” can be understood as the destination end of the multiple modulation symbols being the second communication device, which can include direct sending through the air interface, and also includes indirect sending through the air interface by other units or modules. “Receiving multiple modulation symbols from the first communication device” can be understood as the source end of the multiple modulation symbols being the first communication device, which can include direct receiving from the first communication device through the air interface, and also includes indirect receiving from the first communication device through the air interface from other units or modules. “Sending” can also be understood as the “output” of the chip interface, and “receiving” can also be understood as the “input” of the chip interface.

[0071] In other words, sending and receiving can be performed between devices, for example, between the second communication device and the first communication device; it can also be performed within the device, for example, sending or receiving between components, modules, chips, software modules or hardware modules within the device through a bus, wiring or interface.

[0072] It is understood that before information is sent from the source to the destination, it may undergo necessary processing, such as encoding and modulation. After receiving the information from the source, the destination may also perform corresponding processing, such as decoding and demodulation, to interpret the valid information from the source. Similar expressions in this application can be understood similarly and will not be repeated here.

[0073] Third, in the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship, but does not exclude the situation where the previous and next associated objects are in an "and" relationship. The specific meaning can be understood in conjunction with the context. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can represent: a, b, c; a and b; a and c; b and c; or a and b and c. Where a, b, c can be single or multiple.

[0074] Fourth, the tables in the embodiments of the present application are only examples. The values ​​of the information in each table are only examples and can be configured as other values, which are not limited by the present application. The tables do not limit the scope of protection of the present application. For example, appropriate deformation adjustments can be made based on the tables in the above text, such as splitting, merging, etc. For another example, the parameter names shown in the titles of the tables can also use other names that can be understood by the communication device, and the values ​​or representations of the parameters can also use other values ​​or representations that can be understood by the communication device. For another example, when implementing the above tables, other data structures can also be used, such as arrays, queues, containers, stacks, linear lists, pointers, linked lists, trees, graphs, structures, classes, heaps, hash tables or hash tables.

[0075] Fifth, in the embodiments of the present application, descriptions such as "when...", "in the case of...", "if" and "if" all mean that the device (such as the first device or the second device) will make corresponding processing under certain objective circumstances. It does not limit the time, and does not require the device (such as the network device or the terminal device) to have a judgment action when implementing it, nor does it mean that there are other limitations.

[0076] Sixth, the predefined in this application can be understood as: define, predefine, store, pre-store, pre-negotiate, pre-configure, solidify, or pre-burn.

[0077] The technical solutions provided in this application can be applied to various communication systems, such as: long term evolution (LTE) system, LTE frequency division duplex (FDD) system, LTE time division duplex (TDD) system, sidelink (SL) communication system, world-wide interoperability for microwave access (WiMAX) communication system, fifth generation (5G) mobile communication system or new radio access technology (NR), satellite communication system, etc. Among them, the 5G mobile communication system can include non-standalone (NSA) and / or standalone (SA) networking.

[0078] The technical solution provided in this application can also be applied to future communication systems, such as the sixth generation (6G) mobile communication system, etc. This application does not limit this.

[0079] In this application, a radio access network (RAN) device is a device with wireless transceiver capabilities. It can provide wireless communication services and connect terminals to a wireless network. It can be a node in a radio access network, referred to as a RAN node.

[0080] In one possible scenario, a RAN node can be a base station (BS), an evolved NodeB (eNodeB), a transmission reception point (TRP), a home evolved NodeB (HNB), a wireless fidelity (Wi-Fi) access point (AP), a mobile switching center, a next-generation NodeB (gNB) in a 5G mobile communication system, a next-generation NodeB in a 6G mobile communication system, or a base station in a future mobile communication system. A RAN node can also be a device that performs base station functions in device-to-device (D2D) communication systems, vehicle-to-everything (V2X) communication systems, machine-to-machine (M2M) communication systems, and Internet of Things (IoT) communication systems. A RAN node can also be a RAN node in a non-terrestrial network (NTN), meaning that the RAN node can be deployed on a high-altitude platform or satellite. A RAN node can be a macro base station, a micro base station, an indoor base station, a relay node, a donor node, or a radio controller in a cloud radio access network (CRAN) scenario, or a node in an open radio access network (O-RAN or ORAN) scenario. Alternatively, a RAN node can be a server, a wearable device, a vehicle, or an onboard device. For example, a RAN node in V2X technology can be a roadside unit (RSU). Of course, a RAN node can also be a node in the core network.

[0081] In another possible scenario, multiple RAN nodes collaborate to assist the terminal in achieving wireless access, and different RAN nodes respectively implement part of the functions of the base station. For example, the RAN node can be a centralized unit (CU), a distributed unit (DU), a CU-control plane (CP), a CU-user plane (UP), or a radio unit (RU). The CU and DU can be set separately, or they can be included in the same network element, such as a baseband unit (BBU). The RU can be included in a radio frequency device or radio frequency unit, such as a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH).

[0082] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meanings. For example, in the ORAN system, CU may be referred to as Open CU (O-CU), DU may be referred to as Open DU (O-DU), CU-CP may be referred to as Open CU-CP (O-CU-CP), CU-UP may be referred to as Open CU-UP (O-CU-UP), and RU may be referred to as Open RU (O-RU).

[0083] Among them, any unit among CU (or CU-CP, CU-UP), DU and RU can be implemented by a software module, a hardware module, or a combination of a software module and a hardware module. That is, the wireless access network device in this application can be a virtualized device, for example, implemented by general hardware and instantiated virtualization functions, or by dedicated hardware and instantiated virtualization functions. Among them, the general hardware can be a server, such as a cloud server.

[0084] The terminal device in this application may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent or user device.

[0085] The terminal device may be a device that provides voice / data connectivity to users, such as a handheld device or vehicle-mounted device with wireless connection function. At present, some examples of terminal devices may include: mobile phones, tablet computers, computers with wireless transceiver functions (such as laptops, PDAs, etc.), mobile internet devices (MIDs), virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, drones, wireless terminals in remote medical care, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication functions, computing devices or other processing devices connected to wireless modems, vehicle-mounted devices, wearable devices, terminal devices in 5G networks or future evolved public land mobile communication networks (PLMNs). Mobile network, PLMN) terminal equipment, etc.

[0086] Wearable devices, also known as wearable smart devices, are a general term for wearable devices that use wearable technology to intelligently design and develop wearable devices for daily wear, such as glasses, gloves, watches, clothing, and shoes. Wearable devices are portable devices that are worn directly on the body or integrated into the user's clothing or accessories. Wearable devices are not just hardware devices, but also achieve powerful functions through software support, data interaction, and cloud interaction. In a broad sense, wearable smart devices include those that are fully functional, large in size, and can achieve full or partial functions without relying on smartphones, such as smart watches or smart glasses, as well as those that only focus on a certain type of application function and need to be used in conjunction with other devices such as smartphones, such as various smart bracelets and smart jewelry for vital sign monitoring.

[0087] Furthermore, terminal devices can also be end devices in IoT systems. IoT is a crucial component of future information technology development. Its primary technical feature is connecting objects to the internet through communication technologies, thereby enabling intelligent networks that interconnect humans and machines, and objects and things. IoT technology, for example, utilizes narrowband (NB) technology to achieve massive connectivity, deep coverage, and power-saving terminals.

[0088] In addition, terminal devices can also include sensors such as smart printers, train detectors, and gas stations. Their main functions include collecting data (part of the terminal devices), receiving control information and downlink data from network devices, and sending electromagnetic waves to transmit uplink data to network devices.

[0089] The terminal device in this application may be a virtualized device, for example, implemented by general-purpose hardware and instantiated virtualization functions, or by dedicated hardware and instantiated virtualization functions. The general-purpose hardware may be a server, for example, a cloud server.

[0090] It should be understood that the present application does not limit the specific forms of the wireless access network device and the terminal device.

[0091] Figure 1 is a schematic diagram of the architecture of a communication system 100 applicable to the method provided in an embodiment of the present application. As shown in Figure 1 , the communication system 100 includes a radio access network 10 and a core network 20. Optionally, the communication system 100 may also include the Internet 30. The radio access network 10 may include at least one radio access network device (such as 110a and 110b in Figure 1 ) and at least one terminal (such as 120a-120j in Figure 1 ).

[0092] Terminals can connect to radio access network equipment wirelessly, and radio access network equipment can connect to the core network wirelessly or via wired connections. Core network equipment and radio access network equipment can be independent, distinct physical devices, or they can integrate the core network equipment's functions and the radio access network equipment's logical functions into the same physical device. Alternatively, a single physical device can integrate some core network equipment functions and some radio access network equipment functions. Terminals and radio access network equipment can connect to each other via wired or wireless connections.

[0093] Wireless access network devices and terminals, wireless access network devices, and terminals can communicate through authorized spectrum, unauthorized spectrum, or both. They can communicate through spectrum below 6 gigahertz (GHz), spectrum above 6 GHz, or both. The embodiments of this application do not limit the spectrum resources used for wireless communications.

[0094] The wireless access network device may be a base station deployed in the air, such as a satellite base station 110a; or a base station deployed indoors, such as a micro base station or an indoor station 110b.

[0095] The terminal can be a terminal deployed in the air, such as the helicopter or drone 120i in Figure 1; it can also be a terminal deployed on the ground, such as the mobile phones 120a, 120e, 120f and 120j, vehicle 120b, computer 120g, printer 120h, etc. in Figure 1.

[0096] Wireless access network equipment and terminals can be fixed or mobile. For example, they can be deployed on land, indoors or outdoors, handheld or vehicle-mounted; on water; or in the air on aircraft, balloons, and satellites.

[0097] The roles of radio access network devices and terminals can be relative. For example, the helicopter or drone 120i in Figure 1 can be configured as a mobile base station. For devices 120j accessing the radio access network 10 via 120i, 120i is a base station; however, for 110a, 120i is a terminal. That is, communication between 110a and 120i occurs via a wireless air interface protocol. Of course, communication between 110a and 120i can also occur via an interface protocol between radio access network devices. In this case, 120i is also a base station relative to 110a. Therefore, radio access network devices and terminals can be collectively referred to as communication devices. 110a, 110b, and 120a-120j in Figure 1 can be referred to as communication devices having their respective corresponding functions, such as communication devices having base station functions or communication devices having terminal functions.

[0098] It should be understood that FIG1 is only a schematic diagram, and the communication system may further include other devices, such as wireless relay devices and wireless backhaul devices, which are not shown in FIG1 .

[0099] To facilitate understanding of the embodiments of the present application, the processing process at the physical layer is briefly described below with reference to FIG2 .

[0100] It should be understood that the signal processing process shown in FIG2 can be performed by a network device or a terminal device, and this application does not limit this.

[0101] As shown in FIG2 , when transmitting information data, communication device #1 (e.g., the access network device or terminal device shown in FIG1 ) can divide the information data from the upper layer (e.g., the media access control (MAC) layer) into multiple transport blocks (TBs) according to the transport block size supported by the system, and send a packet to each transport block a0, a1, a2, a3, ..., a A-1 Add CRC check p0, p1, p2, p3, ..., p L-1 Get the sequence b0,b1,b2,b3,…,b B-1 , where B=A+L, a0, a1, a2, a3,…, a A-1 Also called the payload of the transport block. If the transport blocks b0, b1, b2, b3, .., b B-1 If the size exceeds the maximum code block length, the transport block needs to be divided into several code blocks (CBs). Each code block may include several bits in the transport block and a CRC checksum of these bits, for example, a 24-bit CRC checksum. Padding bits may also be included in the code block to ensure that the code block length meets the block length requirement. For example, in the case of LPDC coding, the code block length must be an integer multiple of the expansion factor.

[0102] Communication device #1 may perform channel coding on each code block, for example, using LDPC coding, to obtain a corresponding coded code block. The information bits in this application are referred to as the aforementioned code blocks. Each coded code block may include multiple information bits in the code block before encoding and parity bits generated by encoding, which are collectively referred to as coded bits in this application. The sequence of multiple coded bits is referred to as a coded bit sequence.

[0103] Communication device #1 may store the coded bit sequence in a circular buffer of communication device #1 for rate matching. Communication device #1 may select a segment of coded bits from the circular buffer, interleave them, modulate them, map them into modulation symbols, and transmit a signal carrying the modulation symbols.

[0104] In the embodiments of the present application, the length of the coded bit sequence may refer to the length of the bit sequence output after the transport block is segmented and LDPC encoded. More specifically, after segmenting and LDPC encoding, the transport block is stored in a circular buffer. Bit data of a specified length is then continuously read from a specified location in the buffer, with padding bits automatically skipped.

[0105] After demodulating and deinterleaving the received modulated symbols, communication device #2 (e.g., the access network device or terminal device shown in Figure 1) may store the soft values ​​of the received coded bits in the corresponding locations in the soft information buffer. If retransmissions occur, communication device #2 combines the soft values ​​of the coded bits from each retransmission and stores them in the soft information buffer. This merging refers to combining the soft values ​​of the coded bits received twice if the positions of the coded bits are the same.

[0106] Communication device #2 can directly decode all soft values ​​in the soft information buffer, for example, by LDPC decoding, to obtain a corresponding information sequence. The information sequence obtained by channel decoding can be sent to an upper layer (for example, a MAC layer).

[0107] It should be understood that the process by which communication device #2 processes the received modulation symbols to obtain an information sequence can be regarded as the inverse process of the process by which communication device #1 processes the information data to be sent to obtain a coded bit sequence. In particular, communication device #1 and communication device #2 can use wireless technology or wired technology to communicate, or optical communication, optical disc reading, or hard disk reading. For example, when communication device #1 sends a signal, communication device #1 is a sending device, and in this embodiment of the application, the sending end device can be called an encoding device; when communication device #2 receives a signal, communication device #2 is a receiving device, and in this embodiment of the application, the receiving end device can be called a decoding (or decoding) device. For example, communication device #1 can be the first communication device in this application, and communication device #2 can be the second communication device in this application.

[0108] To facilitate understanding, we first briefly introduce the relevant concepts involved in this application.

[0109] 1. Codeword: The source input is a sequence of binary 0s and 1s. This information sequence is divided into fixed-length message packets, each of which is denoted as u and consists of f information bits. The encoder converts each message packet u into a binary d-dimensional vector v (where d > f) according to a predetermined rule. This d-dimensional vector v is called the codeword or code vector for message packet u, and its bit length is d.

[0110] 2. Block code: Each message packet has f information bits, which means it can carry 2 f Different messages, each message corresponds to a codeword, that is, there are 2 f Code words. 2 f A set of vectors consisting of codewords is called a block code.

[0111] 3. Linear block code: In a block code, there is a one-to-one correspondence between all messages h and codewords v. That is, any different message must correspond to a different codeword. This is called a linear block code, denoted as a linear (d, f) code. A (d, f) linear block code can be understood as encoding a message sequence of length f into a code of length d.

[0112] Mathematically, a (d, f) linear code is an f-dimensional subspace of the vector space composed of all binary n-dimensional vectors, that is, f linearly independent code words (g1, g2... g f ), so that each codeword in the (d, f) linear code can be represented by a linear combination of these f vectors, that is, v = u1g1+…+u k g f , its matrix expression is as follows:

[0113] Among them, bold lowercase letters represent vectors, bold uppercase letters represent matrices, u=(u0,u1…,u f-1 ) is the message sequence, v=(v0,v1…,v d-1 ) is the encoded codeword, G is called the generator matrix of the code set, which consists of k linearly independent d-dimensional vectors, where the elements are 0 or 1.

[0114] The check matrix H is the inverse matrix of the generator matrix in the binary sense, that is, H(uG) T = 0. During decoding, error detection and correction can be achieved by relying on this verification relationship.

[0115] 4. Interleaving: This is a method of permuting the order of bits, also known as permutation, to combat sudden interference. After interleaving, previously clustered bursts of interference are reduced to random, individual interferences, facilitating decoding.

[0116] 5. LDPC code: This is a linear block code with a sparse parity check matrix. Its characteristic is that the LDPC code's parity check matrix has a low density of nonzero elements (i.e., the number of nonzero elements is small compared to the number of rows and columns). The sparsity of the LDPC code's parity check matrix results in a large minimum distance and reduces decoding complexity. The error correction capability of this code is very close to the theoretical maximum (i.e., the Shannon limit).

[0117] 6. QC-LDPC code: A subclass of LDPC. The parity check matrix of QC-LDPC is obtained by expanding a base matrix.

[0118] As a type of structured LDPC code, the QC-LDPC code is well used in certain communication systems, such as 5G NR, due to its advantages such as simple description, easy construction, and storage space saving.

[0119] However, due to the problems of QC-LDPC in the 5G-NR standard in short code design and error floor, such as poor decoding performance of short codes with length less than 128, and error floor of codewords of arbitrary length occurring at block error rate (BLER) = 10 -6 In addition, when pursuing high throughput, it is necessary to increase decoding parallelism. Due to the large input size of LDPC long code decoding and the extremely high scheduling complexity, the decoder is prone to routing congestion. To avoid routing congestion, the decoder input length needs to be within the range of 1000-2000 bits. Limiting the code length causes the coding gain to drop by at least 0.6 decibels. At the same time, the number of decoding iterations and the length of decoding soft information need to be significantly reduced to increase the decoding rate, which results in a coding gain drop of at least 0.8dB. Therefore, the current QC-LDPC code check matrix is ​​difficult to meet the high reliability and high throughput coding requirements of 5.5G / 6G services.

[0120] In view of this, an embodiment of the present application proposes a communication method and related devices, in which the first communication device and the second communication device complete encoding and decoding through the check matrix of the SC-LDPC code, and the sub-check matrices of the check matrix of the SC-LDPC code have coupling characteristics, which can obtain better error performance. In addition, compared with the check matrix of the QC-LDPC code, the check matrix of the SC-LDPC code increases the decoding parallelism, which can achieve fast decoding to obtain better decoding performance.

[0121] The method provided in the embodiment of the present application is described in detail below in conjunction with Figure 3. The method 300 can be applied to the communication system shown in Figure 1, but the embodiment of the present application is not limited thereto.

[0122] In the flowchart shown in Figure 3, the method is described from the perspective of interaction between communication devices. However, the present application does not limit the execution subject of the method. For example, the first communication device in Figure 3 can be a terminal device or a network device, or it can also be a component configured in the terminal device or the network device (such as a chip, a chip system, etc.), or it can also be a logic module or software that can realize all or part of the functions of the terminal device or the network device; for another example, the second communication device in Figure 3 can be a terminal device or a network device, or it can also be a component configured in the terminal device or the network device (such as a chip, a chip system, etc.), or it can also be a logic module or software that can realize all or part of the functions of the terminal device or the network device.

[0123] FIG3 is a schematic flow chart of a method 300 for generating a check matrix according to an embodiment of the present application. As shown in FIG3 , the method 300 may include steps S301 to S308. Each step in the method 300 is described in detail below.

[0124] S301: A first communication device obtains a check matrix of a target SC-LDPC code.

[0125] In a possible implementation, the target SC-LDPC code check matrix is ​​extracted from a preset SC-LDPC code check matrix based on a target code rate and a length of information bits.

[0126] In which, the number of rows of the check matrix of the preset SC-LDPC code is M, the number of columns is N, and the value of the elements in the check matrix of the preset SC-LDPC code is 0 or 1; or, the number of rows of the check matrix of the target SC-LDPC code is M, the number of columns is N, and the value of the elements in the check matrix of the preset SC-LDPC code is 0 or 1.

[0127] In another possible implementation, the check matrix of the target SC-LDPC code is determined based on a target code rate, a length of information bits, and a first mapping relationship.

[0128] Among them, the first mapping relationship indicates the correspondence between at least one code rate, at least one information bit length, and at least one SC-LDPC code check matrix; the number of rows of the target SC-LDPC code check matrix is ​​M, the number of columns is N, the values ​​of the elements in the target SC-LDPC code check matrix are 0 or 1, and M and N are both integers greater than 1.

[0129] In the above two possible implementations, the 0th to (M-1)th rows in the M rows and the 0th to (n-1)th columns in the N columns constitute a first matrix, and the elements from the jth to (j+n-1)th columns in the N columns are obtained by cyclically shifting the first matrix downward by ((j / n)*m) rows; the first matrix includes a second matrix with ((Z+1)*m) rows and n columns, the second matrix is ​​a matrix consisting of the i-th to (i+(Z+1)*m-1)th rows in the first matrix, all elements in the first matrix except the second matrix are 0, Z is an integer greater than 0, i is an integer greater than or equal to 0 and less than or equal to (M-(Z+1)*m), j=n, 2*n, ..., y*n; (y+1)=N / n, M is divisible by m, and n, m, and y are all integers greater than 1.

[0130] In which, the above-mentioned second matrix is ​​obtained by arranging (Z+1) third matrices with m rows and n columns in sequence, there are Z third matrices in the (Z+1) third matrices, and the number K of elements 1 included in the Z third matrices and the number L of elements 1 included in the first matrix satisfy the following relationship: K / L=Z*z%, K / L≤50%, (LK)≥(K / Z), or, the number of remaining elements 1 in the second matrix except the K elements 1 included in the Z third matrices is greater than or equal to the number of elements 1 included in at least one third matrix among the Z third matrices.

[0131] z is an integer less than or equal to 100*R, or z is an integer less than or equal to 100*(1-R). It should be understood that when M and N are the number of rows and columns of the check matrix of the target SC-LDPC code, respectively, R is the target code rate, or R is the maximum code rate or minimum code rate supported by the check matrix of the SC-LDPC code included in the above-mentioned first mapping relationship; when M and N are the number of rows and columns of the check matrix of the preset SC-LDPC code, respectively, R is the maximum code rate or minimum code rate supported by the check matrix of the preset SC-LDPC code.

[0132] The above-mentioned second matrix is ​​obtained by arranging (Z+1) third matrices with m rows and n columns in sequence. It can be understood that the second matrix is ​​composed of (Z+1) third matrices with m rows and n columns. That is, the second matrix starts with the 0th row of the second matrix, and the matrix composed of elements in every m rows is called a third matrix, resulting in a (Z+1) third matrix.

[0133] It is understood that the length of the information bits can be replaced by the target code length. For example, the check matrix of the target SC-LDPC code is determined based on the target code rate, the length of the information bits, and a first mapping relationship, where the first mapping relationship indicates a correspondence between at least one code rate, at least one code length, and at least one check matrix of the SC-LDPC code.

[0134] In the target SC-LDPC check matrix in the present application, the elements from the jth column to the (j+n-1th)th column in the N columns are obtained by cyclically shifting the first matrix downward by ((j / n)*m) rows. Since the position range of non-elements in the first matrix is ​​known, the position range of non-zero elements in the check matrix of the target SC-LDPC can be obtained, so the check matrix of the target SC-LDPC code has lower decoding scheduling complexity.

[0135] Optionally, the Z third matrices are summed to obtain a fourth matrix, and the Z+1 third matrices are summed to obtain a fifth matrix, wherein the K elements included in the fourth matrix are evenly distributed among the L elements 1 included in the fifth matrix.

[0136] It can be understood that the fifth matrix has the same number of rows and columns as the fourth matrix (the number of rows is m and the number of columns is n).

[0137] It should be noted that, in the present application, summing multiple matrices refers to summing multiple matrices modulo 2, for example, summing the Z third matrices modulo 2.

[0138] The meaning of uniform distribution is introduced through the following example. For example, the K elements 1 included in the fourth matrix are arranged in sequence according to the order of the matrix columns to obtain a second list, and the length of the second list is K; similarly, the L elements 1 included in the fifth matrix are arranged in sequence according to the order of the matrix columns to obtain a first list, and the length of the first list is L. Three adjacent elements 1 are randomly selected from the second list, and the positions of these three adjacent elements 1 in the fourth matrix are determined. For example, the positions of the three elements 1 in the fourth matrix are (m1, n1), (m2, n2) and (m3, n3). Then, the positions of the three elements 1 at positions (m1, n1), (m2, n2) and (m3, n3) in the fifth matrix are determined in the first list: position 1, position 2, position 3, and the number of elements 1 included between position 1 and position 2 is the same as the number of elements 1 included in positions 2 and 3. It should be understood that the elements 1 included in the fifth matrix and the fourth matrix can also be arranged in rows.

[0139] In other words, the K elements 1 included in the fourth matrix are uniformly selected from the L elements 1 included in the fifth matrix. The uniform selection method is described below with reference to FIG4 and FIG5.

[0140] As shown in (a) and (b) in Figure 4 and (a) and (b) in Figure 5, the fifth matrix has 4 rows and 4 columns, and includes 8 elements 1; if 4 elements 1 need to be evenly selected from the 8 elements 1 included in the fifth matrix, then 4 elements 1 need to be included in the fourth matrix.

[0141] Example 1: Arrange the eight elements 1 in the fifth matrix in columns and number them sequentially, and the fifth matrix shown in (a) and (b) in FIG. 4 can be obtained.

[0142] For the fifth matrix shown in (a) in FIG4 , element 1 is selected starting from number ①, and an element 1 is selected every other element 1. Then, the numbers corresponding to the elements 1 selected in sequence are ①, ③, ⑤, and ⑦ respectively; in the fifth matrix, the unselected elements 1 are updated to elements 0, and the fourth matrix shown in (a) in FIG4 can be obtained.

[0143] As shown in the fifth matrix in (b) of FIG4 , element 1 is selected starting from number ②, and an element 1 is selected every other element 1. Then, the numbers corresponding to the elements 1 selected in sequence are ②, ④, ⑥, and ⑧ respectively. In the fifth matrix, the unselected elements 1 are updated to element 0, and the fourth matrix shown in (b) of FIG4 can be obtained.

[0144] Example 2: Arrange the eight elements 1 in the fifth matrix in rows and number them sequentially, and the fifth matrix shown in (a) and (b) in FIG5 can be obtained.

[0145] Similarly, as shown in the fifth matrix (a) in FIG5 , element 1 is selected starting from number ①, and an element 1 is selected every other element 1. Then, the numbers corresponding to the elements 1 selected in sequence are ①, ③, ⑤, and ⑦ respectively; in the fifth matrix, the unselected elements 1 are updated to elements 0, and the fourth matrix shown in FIG5 (a) can be obtained.

[0146] As shown in the fifth matrix in (b) of FIG5 , element 1 is selected starting from number ②, and an element 1 is selected every other element 1. Then, the numbers corresponding to the elements 1 selected in sequence are ②, ④, ⑥, and ⑧ respectively. In the fifth matrix, the unselected elements 1 are updated to element 0, and the fourth matrix shown in (b) of FIG5 can be obtained.

[0147] It can be understood that the present application does not limit the selection method of the K elements 1 included in the fourth matrix. For example, the K elements 1 can be randomly selected; for another example, when the fifth matrix includes at least K elements 1 with different row numbers and column numbers, the K elements 1 can be randomly selected from the fifth matrix including at least K elements 1 with different row numbers and column numbers, or when the fifth matrix includes at least K' (K' is an integer greater than 0 and less than K) elements 1 with different row numbers and column numbers, the K elements 1 include the at least K' (K' is an integer greater than 0 and less than K) elements 1 with different row numbers and column numbers.

[0148] It should be noted that when K elements are uniformly selected from L elements, if x = L / K and x is an integer, one element 1 can be selected from the L elements every (x-1) element 1 to obtain L elements 1; if x = L / K and x is not an integer, one element 1 can be selected from the L elements every (x-1) element 1 to obtain L elements 1. Select one element 1 from the elements 1, and then randomly or evenly select from the remaining elements 1 element 1, and get L elements 1. Among them, Indicates rounding up.

[0149] Exemplarily, a method of selecting K elements 1 from L elements 1 is described below with reference to FIG. 6 .

[0150] As shown in FIG6(a), the fifth matrix has four rows and four columns. The fifth matrix includes eight elements 1, and the eight elements 1 include multiple groups of elements 1. Each group of elements 1 includes four elements 1 with different numbers of rows and columns. In the fifth matrix shown in FIG6, elements 1 identified by the same number belong to the same group.

[0151] In example 1, if it is necessary to randomly select 4 elements 1 from the 8 elements 1 included in the fifth matrix, then a group of elements 1 may be randomly selected from the 8 elements as the elements 1 included in the fourth matrix.

[0152] As shown in (a) of FIG6 , the fifth matrix includes three groups of elements 1, and the number of rows and columns of the four elements 1 included in each group of elements 1 are different. If the group of elements 1 identified by number ① is used as the four elements 1 to be selected, the fourth matrix shown in (b) of FIG6 can be obtained; if the group of elements 1 identified by number ② is used as the four elements 1 to be selected, the fourth matrix shown in (c) of FIG6 can be obtained; if the group of elements 1 identified by number ③ is used as the four elements 1 to be selected, the fourth matrix shown in (d) of FIG6 can be obtained.

[0153] Example 2: If it is necessary to randomly select 6 elements 1 from the 8 elements 1 included in the fifth matrix, then a group of elements 1 can be randomly selected from the 8 elements, and two elements 1 can be randomly selected or uniformly selected from the remaining elements 1 except the selected group of elements 1 as the elements 1 included in the fourth matrix.

[0154] Example 3: If it is necessary to randomly select 2 elements 1 from the 8 elements 1 included in the fifth matrix, then a group of elements 1 can be randomly selected from the 8 elements, and two elements 1 can be randomly selected or evenly selected from the group of elements 1 as the elements 1 included in the fourth matrix.

[0155] Optionally, the elements 1 included in each of the Z third matrices are evenly distributed among the K elements 1 included in the fourth matrix.

[0156] Similarly, if Z=2, a third matrix #1 and a third matrix #2 can be obtained. The elements 1 included in the third matrix #1 are arranged in sequence according to the order of the matrix columns to obtain a list 1 of length K1 (K1 is an integer greater than 0 and less than K); the elements 1 included in the third matrix 2 are arranged in sequence according to the order of the matrix columns to obtain a list 2 of length K2 (K2=K-K1); any two elements 1 are selected from list 2, but it is necessary to ensure that the positions of the elements selected from list 1 in list 1 are the same as the positions of the elements selected from list 2 in list 2, for example, both are located at position 1 and position 2 in the list. If the positions of the two elements 1 taken from list 1 in the third matrix 1 are (ml, nl) and (m2, n2), respectively, and the positions of the two elements 1 taken from list 2 in the third matrix 2 are (m3, n3) and (m4, n4), respectively, then the positions of the four elements located at positions (ml, nl), (m2, n2), (m3, n3), and (m4, n4) in the fourth matrix in the second list are determined: position 1, position 2, position 3, position 4, and the element 1 included between position 1 and position 3 is the same as the element 1 included between position 2 and position 4. It should be understood that the elements 1 included in the third matrix 1, the third matrix 2, and the fourth matrix can also be arranged in rows.

[0157] Optionally, the elements 1 included in each of the Z third matrices are randomly distributed among the K elements 1 included in the fourth matrix.

[0158] In other words, after determining the K elements 1 and the value of Z, the encoding device or decoding device may divide the K elements 1 into Z groups, and the number of elements 1 included in each group may be the same or different. If the K elements 1 are obtained in a row (or column) arrangement, and each group includes multiple elements 1, the elements 1 included in each group may be continuous or discontinuous when there are K elements 1.

[0159] S302: The first communication device encodes information bits based on a check matrix of the target SC-LDPC code to obtain a first SC-LDPC codeword.

[0160] The length of the information bits is the length of the information bits used to determine the parity check matrix of the target SC-LDPC code.

[0161] In one possible implementation, the preset check matrix of the SC-LDPC code or the check matrix of the target SC-LDPC code may also be determined by the following steps 1 to 4. It should be understood that steps 1 to 4 may be performed by the encoding device or the decoding device.

[0162] Step 1: Based on the code rate R and the length l of the information bits, determine a matrix 1. The number of rows in the matrix 1 is a, the number of columns is b, the values ​​of the elements in the matrix 1 are 0 or 1, and the matrix 1 includes Y elements 1, R = 1-a / b, l = k*b, k is an integer greater than 0, and a, b, and Y are all integers greater than 1.

[0163] If each row of matrix 1 corresponds to a check node and each column corresponds to a variable node, an element 0 in matrix 1 indicates that the corresponding variable node and check node are not connected, and an element 1 in matrix 1 indicates that the corresponding variable node and check node are connected. In other words, each element 1 in matrix 1 corresponds to an edge, and each edge connects the variable node corresponding to the column containing the element 1 with the check node corresponding to the row containing the element 1. Since matrix 1 contains Y elements 1, matrix 1 contains Y edges.

[0164] In one possible implementation, the above-mentioned determination of matrix 1 based on the code rate R and the length l of the information bit includes: determining matrix 5 based on the code rate R and the length l of the information bit, the number of rows of the matrix is ​​(a / D), the number of columns is (b / D), and the matrix 5 includes (Y / D) edges, where D is an integer greater than 1; and using a quasicycle (QC) algorithm to expand matrix 5 to obtain the above-mentioned matrix 1, where D is the expansion coefficient.

[0165] The above matrix 1 can be understood as the fifth matrix in this application.

[0166] Step 2: Based on matrix 1, obtain a matrix 2 and Z matrices 3. The matrix 2 and the Z matrices 3 have the same number of rows and columns, and the number of rows is a and the number of columns is b. The sum of the matrix 2 and the Z matrices 3 is matrix 1.

[0167] Among them, matrix 2 is the corresponding matrix after matrix 1 removes W edges out of Y edges, each matrix 3 in the Z matrices 3 includes at least one edge, at least one edge belongs to the W edges, and any two matrices in the Z matrices 3 include different edges, W / Y=Z*z%.

[0168] In a possible implementation, the W edges may be selected at equal intervals (or uniformly selected) from the Y edges, or in other words, the W elements 1 are selected at equal intervals from the Y elements 1 included in the matrix 1 .

[0169] The specific selection method can refer to the relevant description in Figures 4 and 5 above, which will not be repeated here.

[0170] In a possible implementation, the elements 1 included in each matrix 3 are selected at equal intervals (or uniformly selected) from the W elements 1. The specific selection method can be referred to the relevant description in FIG6 above, which will not be repeated here.

[0171] The above matrix 2 and the Z matrices 3 can be understood as the (Z+1) third matrices in this application. Among them, the Z matrices 3 can be understood as the Z third matrices in this application.

[0172] Step 3: Based on matrix 2 and Z matrices 3, a matrix 4 is obtained. The number of rows of matrix 4 is ((Z+1)*a) and the number of columns is (b*F).

[0173] The matrix 4 is a matrix obtained by arranging the matrix 2 and the Z matrices 3 in rows. The present application does not limit the arrangement order of the matrix 2 and the Z matrices 3. It should be understood that the arrangement order of the matrix 2 and the Z matrices 3 can be predefined. Three arrangement orders are listed below:

[0174] Example 1: If matrix 2 is recorded as H2, the Z matrices 3 are recorded as: H 31 , H 32 ,…,H 3Z , matrix 4 is recorded as: H4. H4 satisfies:

[0175] Example 2: If matrix 2 is recorded as H2, the Z matrices 3 are recorded as: H 31 , H 32 ,…,H 3Z , matrix 4 is recorded as: H4. H4 satisfies:

[0176] Example 3: If matrix 2 is recorded as H2, the Z matrices 3 are recorded as: H 31 , H 32 ,…,H 3Z , matrix 4 is recorded as: H4. H4 satisfies:

[0177] Step 4: Determine the coupling chain length k, and place the k matrices 4 in sequence according to a preset method to obtain the check matrix of the SC-LDPC code.

[0178] In the parity check matrix of the SC-LDPC code, all positions except the k matrices 4 are 0.

[0179] The number of columns in the parity check matrix of this SC-LDPC code is k times the number of columns in matrix 3, and the number of rows is (k + Z) times the number of rows in matrix 3. For example, if matrix 3 has 5 columns, the number of columns in the parity check matrix of this SC-LDPC code is 5*k. For another example, if matrix 3 has 3 rows, the number of columns in the parity check matrix of this SC-LDPC code is 3*(k + Z).

[0180] In one possible implementation, step 4 may include: using the QC algorithm to expand matrix 4 to obtain matrix 5, where the number of rows of matrix 5 is ((Z+1)*a*F), the number of columns is (b*F), and F is the expansion coefficient; determining the coupling chain length k; placing matrix 5 in sequence according to preset positions to obtain the check matrix of the SC-LDPC code.

[0181] The above matrix 4 and matrix 5 can be understood as the second matrix in this application.

[0182] The following describes the process of obtaining the parity check matrix for an SC-LDPC code, taking as an example the number of check nodes a = 3, the number of variable nodes b = 6, and the number of edges Y = 12 included in matrix 1, with reference to Figures 7 to 9. It should be understood that matrix 1 is a matrix expanded by the QC algorithm.

[0183] As shown in Figure 7, the three check nodes are numbered sequentially to obtain check node a1, check node a2, and check node a3. The six variable nodes are numbered sequentially to obtain variable node b1, variable node b2, variable node b3, variable node b4, variable node b5, and variable node b6. Among them, a1 is connected to b1, b2, b4, and b5 respectively; a2 is connected to b1, b3, b4, and b6 respectively; and a3 is connected to b2, b3, b5, and b6 respectively, resulting in 12 edges.

[0184] Based on the three check nodes, six variable nodes, and the connection relationship between the check nodes and the variable nodes shown in Figure 7, we can obtain matrix 1, which is denoted as H1:

[0185] Among them, the matrix 1 includes 12 elements 1.

[0186] Taking R = 0.4 and z = 25 as an example, based on the relationship between W and Y: W / Y = Z*z%, we can get W = 6. By disconnecting six edges at equal intervals from the 12 edges shown in Figure 7, for example, disconnecting a1 and b1, a1 and b2, a2 ​​and b3, a1 and b4, a1 and b5, and a2 and b6, we can obtain the connection diagram of the variable nodes and check nodes shown in Figure 8.

[0187] Based on the three check nodes, six variable nodes, and the connection relationship between the check nodes and the variable nodes shown in Figure 8, we can obtain matrix 2, which is denoted as H2:

[0188] Matrix 2 includes 6 elements 1. H2 can be understood as the remaining third matrices in the (Z+1) third matrices in this application except for the Z third matrices.

[0189] Taking Z=2 as an example, three edges are selected at equal intervals from the six edges disconnected in Figure 7: the line between a1 and b1, the line between a2 and b3, and the line between a1 and b5 is disconnected, and a connection diagram of the variable nodes and the check nodes as shown in (a) in Figure 9 can be obtained; three edges are selected at equal intervals from the six edges disconnected in Figure 7: the line between a1 and b2, the line between a1 and b4, and the line between a2 and b6, and a connection diagram of the variable nodes and the check nodes as shown in (b) in Figure 9 can be obtained.

[0190] Based on the three check nodes, six variable nodes, and the connection relationship between the check nodes and the variable nodes shown in (a) and (b) of Figure 9, two matrices 3 can be obtained, which are denoted as H 31 and H 32 :

[0191] Each matrix 3 includes 6 elements 1. 31 and H 32 It can be understood as Z third matrices in this application.

[0192] Based on the above matrix 2 and the two matrices 3, we can get matrix 4, which is recorded as H4:

[0193] The matrix 4 includes 12 elements 1, which is the same number as the elements 1 included in the matrix 1. The matrix 4 can be understood as the second matrix in this application.

[0194] For example, when the coupling chain length k=3, the check matrix of the SC-LDPC code can be obtained, which is denoted as H5:

[0195] Among them, H2, H 31 、H 32 The number of rows and columns are the same; "0" represents an all-0 matrix, and the number of rows is the same as the number of rows of H2, and the number of columns is the same as the number of columns of H2; the matrix composed of the elements in the first column can be understood as the first matrix in this application.

[0196] Optionally, the first communication device encodes information of length l based on the check matrix of the target SC-LDPC code to obtain a first SC-LDPC codeword, including: the first communication device divides the information bits of length l into Q (Q = N / n) groups; and encodes Q groups of information bits based on the check matrix of the target SC-LDPC code to obtain a first SC-LDPC codeword including Q groups of coded bits, each group of coded bits in the Q groups of coded bits including a group of information bits and a group of check bits.

[0197] Each group of information bits includes at least one information bit, and the number of information bits included in any two groups of information bits in the Q groups of information bits is the same or different.

[0198] Exemplarily, when the number of information bits included in the Q groups of information bits is the same, each group of information bits includes A (A=l / Q) information bits, and each group of check bits in the Q groups of check bits includes B (B=nl / Q) check bits, where A and B are integers greater than 0.

[0199] It can be understood that the A information bits can be arranged continuously.

[0200] It can also be understood that in each of the Q groups of coded bits, the information bits precede the check bits. In other words, when the first communication device encodes the Q groups of information bits, each group of information bits corresponds to the first A columns of each first matrix.

[0201] Exemplarily, if the Q groups of coding bits in the first SC-LDPC codeword are numbered consecutively starting from 1, then any check bit in the qth group of coding bits in the Q groups of coding bits has a check relationship with at least one group of coding bits in the consecutive p groups of coding bits before the qth group of coding bits, q is an integer greater than 1 and less than Q, and p is an integer greater than 0 and less than p.

[0202] It can be understood that the consecutive p groups of coded bits before the qth group of coded bits refer to the q-1th group of coded bits to the qpth group of coded bits.

[0203] The following takes Q=4, A=4, B=2 as an example (i.e., the first SC-LDPC codeword includes 4 groups of coding bits, each group of coding bits includes 4 information bits and 2 check bits) and introduces the first SC-LDPC codeword in conjunction with Figure 10.

[0204] As shown in Figure 10, the first SC-LDPC codeword is: 101011 010100 100101 011010. Among them, the first group of information bits in the first group of coded bits is: 1010, and the first group of parity bits is: 11; the second group of information bits in the second group of coded bits is: 0101, and the second group of parity bits is: 00; the third group of information bits in the third group of coded bits is: 1001, and the third group of parity bits is: 01; and the fourth group of information bits in the fourth group of coded bits is: 0110, and the fourth group of parity bits is: 10.

[0205] Exemplarily, when q=3 and p=2, any check bit 01 in the third group of coded bits has a check relationship with at least one group of coded bits in the second group of coded bits (010100) and the third group of coded bits (100101).

[0206] Optionally, after S302 , the method 300 may further include: S303 to S305 .

[0207] S303: The first communication device reorders the Q groups of coded bits in the first SC-LDPC codeword to obtain a second SC-LDPC codeword.

[0208] The second SC-LDPC codeword includes Q groups of information bits and Q groups of parity bits, and a positional relationship between the Q groups of information bits and the Q groups of parity bits in the second SC-LDPC codeword satisfies any one of the following features 1 to 5:

[0209] Feature 1: Q groups of information bits are located before Q groups of check bits.

[0210] In combination with the first SC-LDPC codeword shown in FIG10 , the second SC-LDPC codeword may be: 1010 0101 1001 0110 11 00 01 10.

[0211] Feature 2: Among the Q groups of coded bits, the q groups of coded bits that serve as the decoding starting point are located before the other groups of coded bits.

[0212] Combined with the first SC-LDPC codeword shown in Figure 10, when q=2 and the decoding starting points are the first group of coded bits and the fourth group of coded bits respectively, the second SC-LDPC codeword can be: 1010 11 0110 10 0101 00 1001 01, or: 11 1010 10 0110 01 1001 10 0110.

[0213] Feature 3: Among the Q groups of coded bits, the q groups of coded bits that serve as decoding starting points are located before the other groups of coded bits, and the information bits in each group of coded bits are located before the check bits.

[0214] Optionally, the information bits in the other groups of coded bits in feature 3 are located before the check bits in the other groups of coded bits.

[0215] With reference to the first SC-LDPC codeword shown in FIG10 , when q=2 and the decoding starting points are the first group of coded bits and the fourth group of coded bits respectively, the second SC-LDPC codeword may be: 1010 11 0110 10 0101 00 1001 01.

[0216] Feature 4: The q groups of coded bits serving as decoding starting points among the Q groups of coded bits are located before the other groups of coded bits, and the information bits among the q groups of coded bits are located before the check bits among the q groups of coded bits.

[0217] With reference to the first SC-LDPC codeword shown in FIG10 , when q=2 and the decoding starting points are the first group of coded bits and the fourth group of coded bits respectively, the second SC-LDPC codeword may be: 1010 0110 11 10 1001 01 0110 10.

[0218] Or, feature 5, the information bits in the q groups of coded bits that serve as the decoding starting point are located before the information bits in other groups of coded bits, the check bits in the q groups of coded bits are located before the check bits in other groups of coded bits, and the information bits in the Q groups of coded bits are located before the check bits.

[0219] With reference to the first SC-LDPC codeword shown in FIG10 , when q=2 and the decoding starting points are the first group of coded bits and the fourth group of coded bits respectively, the second SC-LDPC codeword may be: 1010 0110 0101 1001 11 10 00 01.

[0220] The other groups of coded bits are the remaining groups of coded bits in the Q groups of coded bits except the q groups of coded bits. In other words, the other groups of coded bits are the coded bit groups in the Q groups of coded bits that are not used as decoding starting points.

[0221] Optionally, the positional relationship between the above-mentioned other groups of coding bits satisfies: the other groups of coding bits are arranged in ascending order according to the first distance, and the first distance refers to the number of coding bit groups between each group of coding bits in the other groups of coding bits and the q groups of coding bits in the first SC-LDPC codeword.

[0222] In other words, the r group of code bits adjacent to the q group of code bits in the other groups of code bits are located before the s group of code bits not adjacent to the q group of code bits in the other groups of code bits, the y group of code bits adjacent to the r group of code bits in the s group of code bits are located before the w group of code bits not adjacent to the r group of code bits in the s group of code bits, and so on, until all the Q groups of code bits are arranged. Where s, r, y, and w are all integers greater than or equal to 0 and less than Q.

[0223] Exemplarily, if the first SC-LDPC codeword uses the 1st group of coded bits and the Qth group of coded bits as the starting points for decoding, then the (2t-1)th group of coded bits in the Q group of information bits of the second SC-LDPC codeword is the tth group of coded bits in the Q group of coded bits in the first SC-LDPC codeword, and the tth group of coded bits in the Q group of coded bits of the second SC-LDPC codeword is the (Q-t+1)th group of coded bits in the Q group of information bits in the first SC-LDPC codeword, t=1, 2,..., ceil(Q / 2), where ceil() indicates rounding up.

[0224] In one possible implementation, the first communication device reorders Q groups of coded bits in the first SC-LDPC codeword to obtain a second SC-LDPC codeword, including: the first communication device uses a first row-column interleaver to interleave the first SC-LDPC codeword to obtain the second SC-LDPC codeword, where the number of rows of the first row-column interleaver is Q and the number of columns is (A+B).

[0225] The following takes the first SC-LDPC codeword shown in FIG10 as an example and describes the process of obtaining the second SC-LDPC by using the first row-column interleaver in combination with FIG11 .

[0226] As shown in Figure 11, given that Q = 4 and A + B = 6, the first row-column interleaver has 4 rows and 6 columns. The 24 bits in the first SC-LDPC codeword are written sequentially from left to right into the second row-column interleaver. The bits in each column are then read out from top to bottom, resulting in the following second SC-LDPC codeword: 1010 0101 1001 0110 1001 1010. In the second SC-LDPC codeword obtained using the first row-column interleaver, all information bits precede all parity bits.

[0227] In another possible implementation, the first communication device reorders the Q groups of coded bits in the first SC-LDPC to obtain a second SC-LDPC codeword, including: the first communication device reorders the Q groups of coded bits based on the decoding method of the first SC-LDPC codeword to obtain the second SC-LDPC codeword.

[0228] The decoding methods include bidirectional sliding window decoding and parallel sliding window decoding. Bidirectional sliding window decoding means that the second communication device performs sliding window decoding from the first and last coded bit groups of the first SC-LDPC codeword to the intermediate coded bit groups. Parallel sliding window decoding means that the second communication device performs sliding window decoding from multiple coded bit groups among the Q groups of coded bits included in the first SC-LDPC codeword.

[0229] Optionally, the decoding method is bidirectional sliding window decoding, and the q groups of coded bits are the first group of coded bits and the Qth group of coded bits in the first SC-LDPC codeword.

[0230] Exemplarily, the first communication device may cyclically shift the first SC-LDPC codeword backward by the length of one group of coded bits to place the Qth group of coded bits and the first group of coded bits before other coded bit groups.

[0231] This application does not limit the order of arrangement of the two groups of coding bits as the starting point of decoding. For example, the first group of coding bits may be located before the fourth group of coding bits, or the fourth group of coding bits may be located before the first group of coding bits.

[0232] Optionally, when the decoding mode is parallel sliding window decoding, q is an integer greater than 2 and less than or equal to Q, and the q groups of coded bits are the q groups of coded bits serving as decoding starting points among the Q groups of coded bits.

[0233] It can be understood that the starting point of the parallel sliding window decoding may be indicated by the second communication device to the first communication device; or the starting point of the parallel sliding window decoding may be predefined.

[0234] Exemplarily, the decoding starting point predefined by the protocol or indicated by signaling may be: one or more bit positions. The one or more bit positions may be determined by a bit length, which may be the distance from the start bit of the SC-LDPC codeword or the distance from the end bit of the SC-LDPC codeword; or, the one or more bit positions may be determined by a ratio, which may be a ratio relative to the code length, for example, half the code length or a quarter of the code length.

[0235] This application does not limit the arrangement order of multiple groups of coding bits that serve as the starting point of decoding. For example, the multiple groups of coding bits are the first group of coding bits and the third group of coding bits. The first group of coding bits may be located before the fourth group of coding bits, or the fourth group of coding bits may be located before the first group of coding bits.

[0236] S304: The first communication device interleaves and modulates the second SC-LDPC codeword to obtain multiple modulation symbols.

[0237] Interleaving refers to processing the second SC-LDPC codeword using a row-column interleaver, that is, writing the second SC-LDPC codeword into the row-column interleaver by row and reading the written second SC-LDPC codeword by column.

[0238] Modulation refers to the process of mapping every P consecutive bits of all the bits included in the second SC-LDPC codeword to a modulation symbol, and each bit in the second SC-LDPC codeword must be mapped, and each bit can only be mapped once. P is the modulation order, which is related to the modulation method. For example, 256 quadrature amplitude modulation (QAM) is used to modulate the third SC-LDPC codeword, P = 8; or, 64QAM is used to modulate the third SC-LDPC codeword, P = 6. For the relevant description of obtaining the modulation order based on the modulation method, please refer to the existing description and will not be repeated here. It should be understood that the first communication device also uses other modulation methods (for example, phase shift keying modulation, etc.) to modulate the second SC-LDPC codeword.

[0239] It should be noted that in S304, when the Q groups of coded bits in the first SC-LDPC are reordered, the position of the important bits in the second SC-LDPC is related to the reliability of the bit subchannel in the multiple bits corresponding to each symbol of the selected modulation mode. For example, if the reliability of the first bits in the multiple bits corresponding to each symbol is higher and the reliability of the following bits is lower, then the important bits in the Q groups of coded bits need to be arranged before the unimportant bits; or if the reliability of the first bits in the multiple bits corresponding to each symbol is lower and the reliability of the following bits is higher, then the important bits in the Q groups of coded bits need to be arranged after the unimportant bits. In other words, the arrangement order of the Q groups of coded bits in the second SC-LDPC codeword is determined based on the selected modulation mode.

[0240] In one possible implementation, the above-mentioned first communication device interleaves and modulates the second SC-LDPC codeword, including: the first communication device can use a second row-column interleaver to interleave the second SC-LDPC codeword to obtain a third SC-LDPC codeword; map consecutive P bits in the second SC-LDPC codeword to a modulation symbol to obtain multiple modulation symbols.

[0241] The third SC-LDPC codeword includes (Q*A) information bits and (Q*B) check bits. The number of rows of the second row-column interleaver is P, and the number of columns is D=ceil((A+B)*Q / P).

[0242] It can be understood that each bit in the first SC-LDPC codeword can only be mapped to one modulation symbol. In other words, different modulation symbols in the above multiple modulation symbols have different bits mapped to them.

[0243] The following takes the modulation mode of 256QAM as an example, and combines the first SC-LDPC codeword shown in Figure 12 to introduce the process of obtaining the third SC-LDPC through interleaving and modulation.

[0244] As shown in Figure 12, the modulation order corresponding to 256QAM is P = 8, and D = ceil((4+2)*4 / 8) = 3, resulting in a second row-column interleaver with 8 rows and 3 columns. If the four groups of coded bits in the first SC-LDPC codeword shown in Figure 10 are reordered, the resulting second SC-LDPC codeword is: 1010 0101 1001 0110 11 00 01 10. The second SC-LDPC codeword is then interleaved using a row-column interleaver with 8 rows and 3 columns. That is, the 24 bits in the second SC-LDPC codeword are sequentially written into the row-column interleaver from left to right, and the bits in each column are then read out from top to bottom. The resulting third SC-LDPC codeword is: 10000001 00101101 11111100.

[0245] Afterwards, the first communication device uses 256QAM to modulate the third SC-LDPC codeword obtained based on the method shown in Figure 11 to obtain three modulation symbols, where 10000001 corresponds to one symbol, 00101101 corresponds to one symbol, and 11111100 corresponds to one symbol.

[0246] For 256QAM, each modulation symbol corresponds to eight bit channels. Among these eight bit channels, the reliability of the bit channels at the front is higher than that of the bit channels at the back. Because the important bits in the second SC-LDPC codeword are arranged first, by modulating the third SC-LDPC codeword, the important bits can be modulated onto bit channels with higher reliability.

[0247] In an embodiment of the present application, the Q groups of coded bits in the first SC-LDPC codeword are reordered, and the relatively important bits in the Q groups of coded bits are arranged before the unimportant bits to obtain a second SC-LDPC, and then the second SC-LDPC is interleaved and modulated. In this way, the important bits in the first SC-LDPC codeword can be mapped to the bits with higher reliability among the P bits corresponding to the modulation symbols, thereby improving the decoding performance.

[0248] S305: The first communication device sends a plurality of modulation symbols to the second communication device. Correspondingly, the second communication device receives the plurality of modulation symbols from the first communication device.

[0249] Optionally, after S305 , the method 300 may further include: S306 to S308 .

[0250] S306: The second communication device demodulates and deinterleaves the multiple modulation symbols to obtain a second SC-LDPC codeword.

[0251] Demodulation is the inverse of modulation, demodulating multiple modulated symbols into multiple bits. Deinterleaving is the inverse of interleaving, writing the demodulated bits column by column into a row-column interleaver and reading the written bits row by row. Therefore, this process will not be further described here.

[0252] For the description of the second SC-LDPC codeword, please refer to the relevant description above and will not be repeated here.

[0253] S307: The second communication device reorders the second SC-LDPC codeword to obtain a first SC-LDPC codeword.

[0254] The process shown in S307 is the reverse process of the above-mentioned S303.

[0255] It can be understood that the first communication device can indicate the arrangement method of obtaining the second SC-LDPC codeword from the first SC-LDPC codeword to the second communication device, so that the second communication device can restore the first SC-LDPC codeword based on the indicated arrangement method after obtaining the second SC-LDPC codeword.

[0256] For the description of the first SC-LDPC codeword, please refer to the relevant description above and will not be repeated here.

[0257] In one possible implementation, the second communication device may use a first row-column interleaver to deinterleave the second SC-LDPC codeword to obtain the first SC-LDPC codeword, where the number of rows of the first row-column interleaver is Q and the number of columns is (A+B).

[0258] In another possible implementation, the second communication device may reorder the Q groups of information bits and Q groups of check bits included in the second SC-LDPC codeword based on the decoding method of the first SC-LDPC codeword to obtain the first SC-LDPC codeword.

[0259] S308: The second communication device decodes the first SC-LDPC codeword based on the check matrix of the target SC-LDPC code to obtain an information ratio.

[0260] Optionally, after S308, the method 300 further includes S309: the second communication device obtains a check matrix of the target SC-LDPC code, and decodes the first SC-LDPC codeword based on the check matrix of the target SC-LDPC code.

[0261] The process of the second communication device obtaining the check matrix of the target SC-LDPC code can refer to the relevant description in S301 above and will not be repeated here. It should be noted that the target code rate and information bit length of the check matrix used by the second communication device to obtain the target SC-LDPC code can be indicated to the second communication device by the first communication device.

[0262] In an embodiment of the present application, a first communication device (for example, an encoding device) encodes information bits by obtaining a check matrix of a target SC-LDPC code to obtain a first SC-LDPC codeword, and a decoding device also uses the check matrix of the target SC-LDPC code to decode the first SC-LDPC codeword. Since the sub-check matrices of the check matrix of the target SC-LDPC code obtained by the first communication device and the decoding device have coupling characteristics, better error performance can be obtained. At the same time, the check matrix of the target SC-LDPC code increases the decoding parallelism, can achieve fast decoding, and can obtain better decoding performance.

[0263] The above describes in detail the method provided in the embodiment of the present application, and the following describes in detail the device provided in the embodiment of the present application in conjunction with Figures 13 and 14.

[0264] Figures 13 and 14 are schematic diagrams of possible devices provided by embodiments of the present application. These devices can be used to implement the functions of the first communication device or the second communication device in the above method embodiments, thereby also achieving the beneficial effects of the above method embodiments.

[0265] FIG13 is a schematic block diagram of an apparatus according to an embodiment of the present application. As shown in FIG13 , the apparatus 1300 includes a processing module 1310 , and optionally, the apparatus 1300 may further include a transceiver module 1320 .

[0266] One possible design is that the device 1300 is used to implement the function of the first communication device in the method embodiment shown in FIG. 3 .

[0267] Exemplarily, the processing module 1310 is used to: obtain a check matrix of a target SC-LDPC code, where the check matrix of the target SC-LDPC code is obtained from a check matrix of a preset SC-LDPC code based on a target code rate and the length of information bits; encode the information bits based on the check matrix of the target SC-LDPC code to obtain a first SC-LDPC codeword.

[0268] Optionally, the processing module 1310 is further used to: reorder the Q groups of coded bits to obtain a second SC-LDPC codeword; and interleave and modulate the second SC-LDPC codeword to obtain multiple modulation symbols; the transceiver module 1320 is used to: send the multiple modulation symbols.

[0269] Optionally, the processing module 1310 is further used to: use a first row-column interleaver to interleave the first SC-LDPC codeword to obtain the second SC-LDPC codeword, and the number of rows of the first row-column interleaver is Q, and the number of columns is (A+B).

[0270] Optionally, the processing module 1310 is further configured to: reorder the Q groups of coded bits based on a decoding method of the first SC-LDPC codeword to obtain the second SC-LDPC codeword.

[0271] A more detailed description of the transceiver module 1310 and the processing module 1320 can be directly obtained by referring to the relevant description in the embodiment shown in FIG3 , and is not repeated here.

[0272] Another possible design is that the device 1300 is used to implement the function of the second communication device in the method embodiment shown in FIG. 3 .

[0273] Exemplarily, the transceiver module 1320 is used to: receive multiple modulation symbols; the processing module 1310 is used to: demodulate and process the multiple modulation symbols to obtain a first SC-LDPC codeword; obtain a check matrix of a target SC-LDPC code, the check matrix of the target SC-LDPC code is obtained from a preset check matrix of a SC-LDPC code based on a target code rate and the length of the information bit; and decode the first SC-LDPC codeword based on the check matrix of the target SC-LDPC code to obtain the information bit.

[0274] Optionally, the processing module 1310 is also used to: demodulate the multiple modulation symbols to obtain a third SC-LDPC codeword, wherein the third SC-LDPC codeword includes (Q*A) information bits and (Q*B) check bits; and, perform deinterleaving processing on the third SC-LDPC codeword to obtain a second SC-LDPC codeword, wherein the second SC-LDPC codeword includes Q groups of information bits and Q groups of check bits, Q = N / n.

[0275] Optionally, the processing module 1310 is further used to: use a first row-column interleaver to deinterleave the second SC-LDPC codeword to obtain the first SC-LDPC codeword, and the number of rows of the first row-column interleaver is Q, and the number of columns is (A+B).

[0276] Optionally, the processing module 1310 is further configured to: reorder the Q groups of information bits and the Q groups of check bits based on a decoding method of the first SC-LDPC codeword to obtain the first SC-LDPC codeword.

[0277] A more detailed description of the transceiver module 1310 and the processing module 1320 can be directly obtained by referring to the relevant description in the embodiment shown in FIG3 , and is not repeated here.

[0278] It should be noted that device 1300 may include a sending module but not a receiving module. Alternatively, device 1300 may include a receiving module but not a sending module. This may depend on whether the above-mentioned solution executed by device 1300 includes both sending and receiving actions. It is understood that because device 1300 has communication functionality, it can also be referred to as a communication device.

[0279] FIG14 is another schematic block diagram of an apparatus provided in an embodiment of the present application. As shown in FIG14 , apparatus 1400 includes one or more processors 1410. The processor 1410 may be a general-purpose processor or a dedicated processor. For example, it may be a baseband processor or a central processing unit. The baseband processor may be used to process communication protocols and communication data, and the central processing unit may be used to control the apparatus (e.g., the first communication apparatus, the second communication apparatus, or the chip), execute software programs, and process data of the software programs.

[0280] Optionally, in one design, the processor 1410 may include a program (also referred to as code or instructions), which may be executed on the processor 1410 to cause the apparatus 1400 to perform the method performed by the first communication device or the second communication device in the above method embodiment. In another possible design, the apparatus 1400 includes a circuit (not shown in FIG. 14 ) configured to implement the functions of the first communication device or the second communication device in the above method embodiment.

[0281] Exemplarily, the processor 1410 may be configured to execute a computer program or instruction in a memory to implement the steps performed by the first communication device or the second communication device in the method embodiment shown in any one of the embodiments shown in FIG. 3 .

[0282] Optionally, the device 1400 may include one or more memories 1420 on which programs (sometimes also referred to as codes or instructions) are stored. The programs can be run on the processor 1410, so that the device 1400 executes the method executed by the first communication device or the second communication device in the above embodiment.

[0283] Optionally, the processor 1410 and / or the memory 1420 may include an artificial intelligence (AI) module, which is used to implement AI-related functions. The AI ​​module may be implemented through software, hardware, or a combination of software and hardware. For example, the AI ​​module may include a wireless intelligent controller (RIC) module. For example, the AI ​​module may be a near real-time RIC or a non-real-time RIC.

[0284] Optionally, data may be stored in the processor 1410 and / or the memory 1420. The processor and memory may be provided separately or integrated together.

[0285] Optionally, the device 1400 may further include a communication interface 1430. The processor 1410 may also be sometimes referred to as a processing unit, which controls the device (e.g., the first communication device or the second communication device). The communication interface 1430 may also be sometimes referred to as a transceiver unit, a transceiver, a transceiver circuit, or a transceiver, etc., which is used to implement the transceiver function of the device.

[0286] Optionally, the apparatus 1400 further includes a communication interface 1430. The processor 1410 and the communication interface 1430 are coupled to each other. It is understood that the communication interface 1430 may be a transceiver or an input / output interface.

[0287] It is understandable that, since the device 1400 has a communication function, it can also be called a communication device.

[0288] When apparatus 1400 is used to implement the method of FIG3 , processor 1410 is used to perform the functions of the processing unit described above, and communication interface 1430 is used to perform the functions of the transceiver module described above. Whether communication interface 1430 is used for sending or receiving can be determined by whether it is used to perform a sending action or a receiving action in the solution implemented by apparatus 1400.

[0289] When the device 1400 is a chip implemented in a first communication device, the chip implements the functions of the first communication device in the above method embodiment. The chip of the first communication device receives a signal from another module (such as a radio frequency module or antenna) in the first communication device, and the signal may be sent from the second communication device to the first communication device; or the chip of the first communication device sends a signal to another module (such as a radio frequency module or antenna) in the first communication device, and the signal may be sent from the first communication device to the second communication device.

[0290] When the device 1400 is a chip used in a second communication device, the chip implements the functions of the second communication device in the above method embodiment. The chip of the second communication device receives a signal from another module (such as a radio frequency module or antenna) in the second communication device, and the signal may be sent from the first communication device to the second communication device; or the chip of the second communication device sends a signal to another module (such as a radio frequency module or antenna) in the second communication device, and the signal may be sent from the second communication device to the first communication device.

[0291] It is understood that when the device 1400 is a first communication device or a second communication device, the communication interface 1430 may be a transceiver, specifically including a transmitter and a receiver, where the transmitter is used to transmit signals and the receiver is used to receive signals. When the device 1400 is a chip used in the first communication device or the second communication device, the communication interface 1430 may be an input / output circuit, where the input circuit can be used for receiving and the output interface can be used for transmitting.

[0292] It should be noted that the above method embodiments can be applied to or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by hardware integrated logic circuits in the processor or by software instructions.

[0293] The processor may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0294] The steps of the method disclosed in the embodiments of this application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium well-known in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above method.

[0295] The memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0296] The present application also provides a computer-readable medium having a computer program stored thereon, which implements the functions of the above-mentioned method embodiment when executed by a computer.

[0297] The present application also provides a computer program product comprising instructions, which implements the functions of the above method embodiments when executed by a computer.

[0298] The methods provided in the above embodiments can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, they can be implemented in whole or in part in the form of a computer program product. The computer program product may include one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated therein. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic disk), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state disk (SSD)).

[0299] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0300] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0301] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0302] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0303] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0304] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk, or an optical disk.

[0305] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A communication method, characterized in that: include: Obtain a check matrix of a target spatially coupled low-density parity check SC-LDPC code, wherein the check matrix of the target SC-LDPC code is obtained from a check matrix of a preset SC-LDPC code based on a target code rate and a length of information bits; the number of rows of the check matrix of the preset SC-LDPC code is M, the number of columns is N, and the value of the element in the check matrix of the preset SC-LDPC code is 0 or 1, or the number of rows of the check matrix of the target SC-LDPC code is M, the number of columns is N, and the value of the element in the check matrix of the target SC-LDPC code is 0 or 1; Among them, the first matrix composed of the 0th to (M-1)th rows in M ​​rows and the 0th to (n-1)th columns in N columns includes a second matrix with ((Z+1)*m) rows and n columns, the elements of the jth to (j+n-1)th columns in N columns are obtained by cyclically shifting the first matrix downward by ((j / n)*m) rows, the second matrix is ​​a matrix composed of the i-th to (i+(Z+1)*m-1)th rows in the first matrix, and all elements in the first matrix except the second matrix are 0, the second matrix is ​​obtained by arranging (Z+1) third matrices with m rows and n columns in sequence by rows, there are Z third matrices in the (Z+1) third matrices, and the number K of elements 1 included in the Z third matrices is the same as the number K of elements 1 included in the second matrix. The number L of elements 1 satisfies the following relationship: K / L=Z*z%, (LK)≥(K / Z), or, the number of remaining elements 1 in the second matrix except the K elements 1 included in the Z third matrices is greater than or equal to the number of elements 1 included in at least one of the Z third matrices; Z is an integer greater than 0, z is an integer less than or equal to 100*R, or z is an integer less than or equal to 100*(1-R), R is the target code rate or the maximum code rate or minimum code rate supported by the check matrix of the preset SC-LDPC code, i is an integer greater than or equal to 0 and less than or equal to (M-(Z+1)*m), j=n, 2*n, ..., y*n; (y+1)=N / n, M is divisible by m, and n, m, and y are all integers greater than 1; The information bits are encoded based on a check matrix of the target SC-LDPC code to obtain a first SC-LDPC codeword.

2. The method according to claim 1, characterized in that The K elements 1 included in the fourth matrix are uniformly distributed in the L elements 1 included in the fifth matrix, the fourth matrix is ​​the sum of the Z third matrices, and the fifth matrix is ​​the sum of the (Z+1) third matrices.

3. The method according to claim 2, characterized in that The elements 1 included in each of the Z third matrices are evenly distributed among the K elements 1 included in the fourth matrix.

4. The method according to any one of claims 1 to 3, characterized in that The first SC-LDPC codeword includes Q groups of coding bits, each group of coding bits in the Q groups of coding bits includes a group of information bits and a group of check bits, each group of information bits in the Q groups of information bits includes A information bits, and each group of check bits in the Q groups of check bits includes B check bits, A and B are integers greater than 0, and Q=N / n.

5. The method according to claim 4, characterized in that The method further comprises: The Q groups of coded bits are reordered to obtain a second SC-LDPC codeword, wherein the Q groups of information bits and the Q groups of check bits included in the second SC-LDPC codeword satisfy any of the following characteristics: The Q group of information bits are located before the Q group of check bits; The q groups of coded bits in the Q groups of coded bits, which are used as the decoding starting point, are located before the other groups of coded bits; The q groups of coded bits in the Q groups of coded bits that are used as decoding starting points are located before the other groups of coded bits, and the information bits in each group of coded bits are located before the check bits; or, The q groups of coded bits in the Q groups of coded bits that are used as decoding starting points are located before the other groups of coded bits, and the information bits in the q groups of coded bits are located before the check bits in the q groups of coded bits, and q is an integer greater than 0 and less than or equal to Q; Interleaving and modulating the second SC-LDPC codeword to obtain multiple modulation symbols; The plurality of modulation symbols are transmitted.

6. The method according to claim 5, characterized in that The positions of the other groups of coding bits in the second SC-LDPC codeword are arranged in ascending order according to the first distance, and the first distance refers to the number of coding bit groups between each group of coding bits in the other groups of coding bits and the q groups of coding bits in the first SC-LDPC codeword.

7. The method according to claim 5, characterized in that The information bits in the other groups of coded bits are located before the check bits in the other groups of coded bits.

8. The method according to any one of claims 5 to 7, characterized in that The reordering of the Q groups of coded bits to obtain a second SC-LDPC codeword includes: A first row-column interleaver is used to interleave the first SC-LDPC codeword to obtain the second SC-LDPC codeword, wherein the number of rows of the first row-column interleaver is Q, and the number of columns is (A+B).

9. The method according to any one of claims 5 to 7, characterized in that The reordering of the Q groups of coded bits to obtain a second SC-LDPC codeword includes: Based on the decoding method of the first SC-LDPC codeword, the Q groups of coded bits are reordered to obtain the second SC-LDPC codeword.

10. The method according to claim 9, characterized in that The decoding method is bidirectional sliding window decoding, and the q groups of coded bits are the first group of coded bits and the Qth group of coded bits in the first SC-LDPC codeword.

11. The method according to claim 9, characterized in that The decoding method is parallel sliding window decoding, q is an integer greater than 2 and less than or equal to Q, and the q groups of coded bits are the coded bit groups in the Q groups of coded bits that serve as the decoding starting point.

12. A communication method, characterized in that: include: receiving a plurality of modulation symbols; Demodulating and processing the multiple modulation symbols to obtain a first SC-LDPC codeword; Obtain a check matrix of a target SC-LDPC code, wherein the check matrix of the target SC-LDPC code is obtained from a check matrix of a preset SC-LDPC code based on a target code rate and a length of information bits; the number of rows of the check matrix of the preset SC-LDPC code is M, the number of columns is N, and the value of the element in the check matrix of the preset SC-LDPC code is 0 or 1, or the number of rows of the check matrix of the target SC-LDPC code is M, the number of columns is N, and the value of the element in the check matrix of the target SC-LDPC code is 0 or 1; Among them, the first matrix composed of the 0th to (M-1)th rows in M ​​rows and the 0th to (n-1)th columns in N columns includes a second matrix with ((Z+1)*m) rows and n columns, the elements of the jth to (j+n-1)th columns in the N columns are obtained by cyclically shifting the first matrix downward by ((j / n)*m) rows, the second matrix is ​​a matrix composed of the i-th to (i+(Z+1)*m-1)th rows in the first matrix, and all elements in the first matrix except the second matrix are 0, the second matrix is ​​obtained by arranging (Z+1) third matrices with m rows and n columns in sequence by rows, there are Z third matrices in the (Z+1) third matrices, and the number K of elements 1 included in the Z third matrices is the same as the number K of elements 1 included in the second matrix. The number L of elements 1 satisfies the following relationship: K / L=Z*z%, (LK)≥(K / Z), or, the number of remaining elements 1 in the second matrix except the K elements 1 included in the Z third matrices is greater than or equal to the number of elements 1 included in at least one of the Z third matrices; Z is an integer greater than 0, z is an integer less than or equal to 100*R, or z is an integer less than or equal to 100*(1-R), R is the target code rate or the maximum code rate or minimum code rate supported by the check matrix of the preset SC-LDPC code, i is an integer greater than or equal to 0 and less than or equal to (M-(Z+1)*m), j=n, 2*n,..., y*n; (y+1)=N / n, M is divisible by m, and n, m, and y are all integers greater than 1; The first SC-LDPC codeword is decoded based on the check matrix of the target SC-LDPC code to obtain the information bits.

13. The method according to claim 12, characterized in that The K elements 1 included in the fourth matrix are uniformly distributed in the L elements 1 included in the fifth matrix, the fourth matrix is ​​the sum of the Z third matrices, and the fifth matrix is ​​the sum of the (Z+1) third matrices.

14. The method according to claim 13, characterized in that The elements 1 included in each of the Z third matrices are evenly distributed in the K elements 1 included in the fourth matrix.

15. The method according to any one of claims 12 to 14, characterized in that The first SC-LDPC codeword includes Q groups of coding bits, each group of coding bits in the Q groups of coding bits includes a group of information bits and a group of check bits, each group of information bits in the Q groups of information bits includes A information bits, and each group of check bits in the Q groups of check bits includes B check bits, A and B are integers greater than 0, and Q=N / n.

16. The method according to claim 15, characterized in that The demodulating and processing the multiple modulation symbols to obtain a first SC-LDPC codeword includes: Demodulating the multiple modulation symbols to obtain a third SC-LDPC codeword, wherein the third SC-LDPC codeword includes (Q*A) information bits and (Q*B) check bits; Performing deinterleaving processing on the third SC-LDPC codeword to obtain a second SC-LDPC codeword, wherein the second SC-LDPC codeword includes Q groups of information bits and Q groups of check bits; The Q groups of information bits and the Q groups of check bits in the second SC-LDPC codeword are reordered to obtain the first SC-LDPC codeword.

17. The method according to claim 16, characterized in that The Q groups of information bits and the Q groups of check bits in the second SC-LDPC codeword satisfy any of the following characteristics: The Q group of information bits are located before the Q group of check bits; The q group of coded bits in the Q group of coded bits, which are used as the decoding starting point, are located before the other groups of coded bits; The q groups of coded bits in the Q groups of coded bits that are used as decoding starting points are located before the other groups of coded bits, and the information bits in each group of coded bits are located before the check bits; or, The q groups of coded bits in the Q groups of coded bits that are used as decoding starting points are located before the other groups of coded bits, and the information bits in the q groups of coded bits are located before the check bits in the q groups of coded bits.

18. The method according to claim 17, characterized in that The positions of the other groups of coding bits in the second SC-LDPC codeword are arranged in ascending order according to the first distance, and the first distance refers to the number of coding bit groups between each group of coding bits in the other groups of coding bits and the q groups of coding bits in the first SC-LDPC codeword.

19. The method according to claim 17, characterized in that The information bits in the other groups of coded bits are located before the check bits in the other groups of coded bits.

20. The method according to any one of claims 16 to 19, characterized in that The reordering of the Q groups of information bits and the Q groups of check bits in the second SC-LDPC codeword to obtain the first SC-LDPC codeword includes: The second SC-LDPC codeword is deinterleaved using a first row-column interleaver to obtain the first SC-LDPC codeword, wherein the first row-column interleaver has Q rows and (A+B) columns.

21. The method according to any one of claims 16 to 19, characterized in that The reordering of the Q groups of information bits and the Q groups of check bits in the second SC-LDPC codeword to obtain the first SC-LDPC codeword includes: Based on a decoding method for the first SC-LDPC codeword, the Q groups of information bits and the Q groups of check bits are reordered to obtain the first SC-LDPC codeword.

22. A communication device, characterized in that: The method comprises a module for implementing the method according to any one of claims 1 to 11; or the method comprises a module for implementing the method according to any one of claims 12 to 21.

23. A communication device, characterized in that: The device comprises a processor, configured to enable the communication device to implement the method according to any one of claims 1 to 11 by executing a computer program and / or a logic circuit, or enable the communication device to implement the method according to any one of claims 12 to 21.

24. The device according to claim 23, characterized in that The system also includes a memory for storing a computer program and / or a configuration file of the logic circuit.

25. The device according to claim 23 or 24, characterized in that A communication interface is also included for inputting and / or outputting signals.

26. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 11 is executed, or the method according to any one of claims 12 to 21 is executed.

27. A computer program product, characterized in that The invention comprises a computer program. When the computer program is executed, the method according to any one of claims 1 to 11 is executed, or the method according to any one of claims 12 to 21 is executed.

28. A communication system, characterized in that: The method comprises a first communication device and a second communication device, wherein the first communication device is used to implement the method according to any one of claims 1 to 11, and the second communication device is used to implement the method according to any one of claims 12 to 21.

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