An electronic device for calculating a reciprocal of an input value, or calculating a square root of the input value

Abstract

An electronic calculation circuit for performing a mathematical operation on an input value to calculate an output value by calculating the output value as a reciprocal of the input value, or calculating the output value as a square root of the input value. The electronic calculation circuit comprises a memristive crossbar array (203d) comprising at least three memristors (211d, 212d, 213d) operatively arranged in series and configured to be programmed by a respective memristor value; and at least two inputs operatively connected to two of the at least three memristors (211d, 212d, 213d).

Description

[0001]AN ELECTRONIC DEVICE FOR CALCULATING A RECIPROCAL OF AN INPUTVALUE, OR CALCULATING A SQUARE ROOT OF THE INPUT VALUE TECHNICAL FIELD The embodiments herein relate to an electronic device and a method forcalculating a reciprocal of an input value, or calculating a square root of the input value. A corresponding computer program and a computer program carrier are also disclosed. BACKGROUND Signal processing algorithms include many arithmetic operations, ranging from simple operations like addition and subtraction to the more complicated ones like division calculation. Examples of Use Cases:There are many use cases, which require calculation of different mathematicaloperations. Some of these applications are listed below: ^Reciprocal calculation is a fundamental operation in many signal processingalgorithms. Some examples are: oBeam power calculation and beam selection in the wireless communicationsystems oCholesky decompositiono to realize the activation functions in Machine Learning and NeuralNetwork. The activation function decides whether a neuron in the corresponding neural network should be activated or not. Examples of activation functions are Sigmoid function and Hyperbolic tangent (Tanh), which include reciprocal calculation. oTo realize divisiono Mean calculationo SQRT calculation^ Mean squared error (MSE) is a very useful operation, which is usedo to define loss functions for Machine Learning and Deep Learningapplications,o to evaluate the quality of an estimator or predictor,o as the selection criterion in the estimation and optimization problems invarious applications, oto realize the method of least squares, which is a standard method of fittingstatistical estimates to observed data by minimizing the squared distances between them.^ Mean calculation is widely used ino data analysis, for example to find the distribution of a data set around itsmean, to calculate dispersion and skewness in a data set, and to get a general understanding of a set of data. oThere are many applications, which require calculation of different types ofmean e.g., weighted mean, harmonic mean, and mean squared. oFor example, in order to calculate the average power and energy of asignal at the transceivers in wireless communication systems.^ Norm calculation is widely used in the context of Machine Learning and DeepLearning. For example, for defining loss functions, for regularization methods inmachine learning, e.g., ridge and lasso regularization methods. Also, the vector norm is used to calculate the error between a prediction and an actual observation(label).^ Norm calculation is used to measure the size of vectors and matrices in manyapplications in which the largest / smallest vectors / matrices or the sorted list of them should be found.^ There are several matrix transformations like Gram-Schmidt, HouseholderTransform, etc., which need norm calculation of vectors.^ Root mean square is frequently used in various mathematical and scientificapplications. Some applications are to calculate the mean square value of a waveform to measure the amount of energy in it, to calculate the magnitude of an alternating current / voltage, to determine the power dissipation of a resistor, etc.^ Root mean square is also used to measure the variability of a data set.^ Euclidean distance calculation is needed in many MIMO detection algorithms inwireless communication systems. ^Euclidean distance calculation is needed in other applications to calculate thedistance between two point or two vectors, and consequently find the closest points / vectors together. ^SQRT calculation is required in most of the above-mentioned applications as wellas in the other use cases.Such arithmetic operations may be implemented in software but software implementation may not meet requirements for computational time by a certain application. Hardware implementation may be an option to reduce latency. However,hardware implementation of some of these operations such as calculation of reciprocal,division, square root (SQRT), different types of average / mean of numbers is very challenging. For example, a problem of prior art is that a computational complexity of thesophisticated mathematical functions increases significantly in case of fully parallel implementation. This makes the hardware implementation of such functions / algorithms very challenging and costly. Also, the traditional implementations of mathematical operations are not flexible interms of different inputs and parameters like a number of iterations, degree of parallelism,real or complex inputs, etc. SUMMARY Non-iterative implementation of the above-mentioned mathematical operations typically leads to low accuracy / performance while hardware cost and latency are increased in such traditional implementation approaches. One of the problems in the hardware implementation of mathematical functionsusing iterative methods, like the Newton–Raphson method, is that a higher number ofiterations reduces the throughput while it increases the hardware cost and latencysignificantly. On the other hand, a low number of iterations do not benefit from a goodaccuracy / performance.An objective of embodiments herein is to solve at least some of the drawbacksmentioned above. Embodiments herein disclose an electronic device and a method for calculating areciprocal of an input value, or calculating a square root of the input value. Specifically, embodiments herein disclose an electronic device comprising amemristive crossbar array. An analog memristive crossbar array, such as a 2-dimensionalarray, consists of M×N memristive devices, each of which can be programmed torepresent an m-bit binary value. According to a first aspect, the object is achieved by an electronic calculation circuitfor performing a mathematical operation on an input value to calculate an output value bycalculating the output value as a reciprocal of the input value, or calculating the output value as a square root of the input value. The electronic calculation circuit comprises a memristive crossbar array comprising: at least three memristors operatively arranged in series and configured to be programmed by a respective memristor value; and at least two inputs operatively connected to two of the at least three memristors. According to a second aspect, the object is achieved by a method, performed by anelectronic device, for performing a mathematical operation with an electronic calculation circuit on an input value to calculate an output value by calculating the output value as areciprocal of the input value, or calculating the output value as a square root of the inputvalue. The electronic calculation circuit comprises a first memristive crossbar arraycomprising at least three memristors operatively arranged in series and at least two inputs operatively connected to two of the at least three memristors. The method comprises configuring inputs of at least two of the at least threememristors. The method further comprises configuring values represented by the at least threememristors. The method further comprises applying the inputs to the at least three memristors tocalculate the output value. According to a third aspect, the object is achieved by an electronic device forperforming a mathematical operation on one or more input values to calculate an outputvalue. The electronic device comprises a first electronic calculation circuit according to thefirst aspect above and configured to perform a first mathematical operation on a first inputvalue based on the one or more input values to calculate a first output value by calculating the first output value as a reciprocal of the first input value, or calculating the first output value as a square root of the first input value. The first electronic calculation circuit comprises a first memristive crossbar array. The electronic device further comprises a second electronic calculation circuit comprising a second memristive crossbar array. The second electronic calculation circuit is configured to perform a second mathematical operation on a second input value based on the one or more input values to calculate a second output value. The output value of the electronic device is based on the second output value or based on the first output value or both. According to a further aspect, the object is achieved by a computer program comprising instructions, which when executed by a processor, causes the processor to perform actions according to any of the aspects above. According to a further aspect, the object is achieved by a carrier comprising the computer program of the aspect above, wherein the carrier is one of an electronic signal, an optical signal, an electromagnetic signal, a magnetic signal, an electric signal, a radio signal, a microwave signal, or a computer-readable storage medium. Since the electronic calculation circuit comprises the memristive crossbar array andsince the memristive devices consume much less power compared to traditional multiply accumulate (MAC) modules, such as digital MAC modules, the proposed PIM-based electronic calculation circuit has the potential of low power / energy consumption, which isa critical demand in many use cases (e.g., IoT devices). The lower power consumptionmay in turn lead to increased battery life for battery-powered devices such as mobilephones. The latency of the memristive-based electronic calculation circuit is only limited bythe read cycle of the crossbar arrays. The memristive-based electronic calculation circuit is computationally efficient sincethe computational complexity is reduced to O(1). This results in a significant reduction inhardware complexity of the filter. The memristive-based electronic electronic calculation circuit is fully flexible in termsof configuration. The memristive-based electronic calculation circuit supports processing of complex- valued input samples without any degradation in the throughput and performance. BRIEF DESCRIPTION OF THE DRAWINGS In the figures, features that appear in some embodiments are indicated by dashed lines. The various aspects of embodiments disclosed herein, including particular features and advantages thereof, will be readily understood from the following detailed description and the accompanying drawings, in which: Figure 1 is a block diagram schematically illustrating a crossbar array of memristors, Figure 2a is a block diagram schematically illustrating an electronic device forcalculating a reciprocal value according to embodiments herein, Figure 2b is a block diagram schematically illustrating an electronic device for calculating a reciprocal value according to some further embodiments herein, Figure 2c is a block diagram schematically illustrating an electronic device for calculating a square value according to some further embodiments herein,Figure 2d is a block diagram schematically illustrating an electronic device for calculating a reciprocal value according to some further embodiments herein, Figure 2e is a block diagram schematically illustrating an electronic device for calculating a reciprocal value according to some further embodiments herein, Figure 2f is a block diagram schematically illustrating an electronic device for calculating a reciprocal value according to some further embodiments herein, Figure 3a is a block diagram schematically illustrating an electronic device for calculating division according to some embodiments herein, Figure 3b is a block diagram schematically illustrating a crossbar array formultiplication, Figure 4a is a block diagram schematically illustrating an electronic device for calculating a square root value according to some embodiments herein, Figure 4b is a block diagram schematically illustrating a crossbar array forinitialisation of calculating a square root value according to some further embodiments herein, Figure 4c is a block diagram schematically illustrating an electronic device for calculating a square root value according to some further embodiments herein,Figure 5 is a flowchart illustrating embodiments of a method for performing amathematical operation,Figure 6 is a further flowchart illustrating embodiments of a method for performing amathematical operation, Figure 7a is a block diagram schematically illustrating an electronic device for calculating a mean square value according to some embodiments herein, Figure 7b is a block diagram schematically illustrating a crossbar array for calculating a sum square value according to some further embodiments herein, Figure 8 is a block diagram schematically illustrating an electronic device for calculating a mean square error value according to some embodiments herein, Figure 9 is a block diagram schematically illustrating an electronic device for calculating a root mean square value according to some embodiments herein, Figure 10a is a block diagram schematically illustrating an electronic device for calculating a weighted average value according to some embodiments herein, Figure 10b is a block diagram schematically illustrating a crossbar array for calculating a sum of weighted values according to some furtherembodiments herein, Figure 11a is a block diagram schematically illustrating an electronic device for calculating a harmonic mean value according to some embodiments herein, Figure 11b is a block diagram schematically illustrating a crossbar array for calculating a sum of values according to some further embodiments herein, Figure 12a is a block diagram schematically illustrating an electronic device for calculating a norm value according to some embodiments herein, Figure 12b is a block diagram schematically illustrating a crossbar array for calculating a sum of values according to some further embodiments herein, Figure 13a is a block diagram schematically illustrating an electronic device for calculating a Frobenius norm value according to some embodiments herein, Figure 13b is a block diagram schematically illustrating a crossbar array for calculating a trace value according to some further embodiments herein, Figure 14 is a diagram schematically illustrating an Euclidian distance, Figure 15a is a block diagram schematically illustrating an electronic device for calculating an Euclidian distance value according to some embodiments herein, Figure 15b is a block diagram schematically illustrating a crossbar array for calculating an Euclidian distance value according to some further embodiments herein, Figure 16a is a block diagram schematically illustrating an electronic device forcalculating an Euclidian distance value according to some embodiments herein, Figure 16b is a block diagram schematically illustrating a crossbar array for calculating a difference value according to some further embodimentsherein, Figure 16c is a block diagram schematically illustrating a crossbar array for calculating a square value according to some further embodiments herein, Figure 17 is a block diagram schematically illustrating a network node.Figure 18 is a block diagram schematically illustrating a wireless communicationsdevice. Figure 19 is a block diagram schematically illustrating a wireless communicationsystem. DETAILED DESCRIPTION Embodiments herein relate to electronic calculation circuits and electronic devicesfor mathematical operations. Mathematical operations are widely used in manyapplications as listed above. Some of these operations may be realized using Newton–Raphson’s method. TheNewton–Raphson’s method is an iterative method to estimate the output of a function,^(^), for a given input, ^^. This process can be mathematically expressed as where ^(^) and ^′(^) are the targeted function and its derivative, ^^ is the input value at^-th iteration, and ^ is the maximum number of iterations. Depending on the targetfunction and the required accuracy / performance, the number of iterations, ^, may bespecified. Also, in some cases, non-iterative implementation approaches may be employedto implement a sub-block of a complicated mathematical operation and then combine thesub-blocks to realize a more complex function.More specifically, embodiments herein relate to memristive-based electroniccalculation circuits for mathematical operations, i.e. to electronic calculation circuits formathematical operations implemented with crossbar arrays of memristors. A memristormay also be referred to as a memristive device. Analog memristive devices have emerged as a new technology for storing and processing information in analog domain. These devices make it possible to perform computations in a place where data is stored. Thisconcept is called in-memory computing (or processing in memory), which eliminates theneed for moving data from a memory to a processing unit. There are different types ofmemristive devices, which are differentiated with respect to the used materials, switching principles, device endurance, retention, etc. The main types of memristive devices include phase change memory (PCM), resistive random-access memory (ReRAM), spin-transfer torque magnetic RAM (STT-MRAM), ferroelectric memristive devices (FeRAM). Memristive devices may support a limited bit precision, attributed to the limited number ofconductance levels that may be reliably programmed in the device. For example, a PCMdevice may support around 50 conductance levels, meaning that it may represent around 6 bits. A number of memristor devices may be organized to form an analog crossbar array.Figure 1 illustrates an electronic calculation circuit 101 comprising a memristorcrossbar array 110 which computes MVM by calculating a dot-product of the input vectorapplied to crossbar rows (i.e., word lines) and every column of the crossbar (i.e., bit lines).The memristor crossbar array 110 is a two-dimensional array that comprises an M×Narray of memristors 111, 112, 121, 122, each of which may be programmed to representan m-bit binary value. A memristor is a tunable and programmable. The memristor may comprise a dielectric layer sandwiched by two electrodes. A unique feature of memristors is that the conductance depends on historical electrical signals, making them capable of working as nonvolatile memory. In addition, memristors may store multibit information with continuously tunable conductance, in contrast to binary states “0” and “1” in traditional digital storage systems, equipping them with higher bit density. Thus, the m-bit binary value of the memristor may be set or programmed by applying a current to the memristor.The binary value may depend on the amplitude of the current. Thus, an ^ × ^ matrix ofbinary words, G, may be represented by the memristor crossbar array 110 comprising^ × ^ memristors. The input to the memristor crossbar array 110 is an electronic inputsignal of multiple samples, such as a vector of ^ analog voltages, e.g., V, whichcorrespond to M binary values. Analog crossbar arrays comprise parallel conductors, such as metal lines, termedword lines and bit lines, respectively, as electrodes of the memristors. The word lines andbit lines may be perpendicular to each other. The memristors are formed at theintersections of word and bit lines. In embodiments herein input conductors 131 of theanalog crossbar array 110 corresponds to the word lines and output conductors 132 ofthe analog crossbar array 110 corresponds to the bit lines.The analog crossbar array 110 computes MVM by calculating the dot-product ofthe input vector applied to crossbar rows (i.e., word lines) and every column of the crossbar (i.e., bit lines), all performed in analog domain using Ohm’s law for multiplication and Kirchhoff’s law for accumulation. In Figure 1 the entries of a matrix G (an M×M matrix) are programmed to thememristive devices 111, 112, 121, 122 of the M×M crossbar array 110 while the inputvector V (an M×1 vector) is applied to the crossbar rows. Note that, the vector Vcorresponds to the actual input vector (Input 1, …, Input M), which may be converted toanalog voltages using one or more Digital to Analog Converter (DAC) modules 104illustrated in Figure 1. As a result, the following MVM may be realized using the illustratedcrossbar array 110,^, ^ = 1, … , ^ (2) where an output vector I is the output current of crossbar columns, which is equal tothe result of matrix-vector multiplication, i.e., I = G‧V. The output vector I may beconverted to the corresponding binary words using one or more Analog to DigitalConverter (ADC) modules 105 as shown in Figure 1. This conversion may be doneeither separately for each crossbar column (i.e., one ADC for each binary word) or in a time-multiplexed fashion and hence reduce ADC overhead (i.e., multiple bit lines mayshare one ADC 105).In this disclosure vectors and matrices are represented using capital boldface letters while their entries are shown using normal letters. Thus, when the electronic input signal is digital then the electronic calculation circuit101 further comprises the one or more DACs 104 adapted to convert the input signal ofmultiple samples to corresponding analog voltages V1, V2, … VN.In other words, when the input signal of the multiple samples is digital, the electroniccalculation circuit 101 may further comprise the DACs 104 configured to convert thedigital input signal of the multiple samples to the analog voltages. There may be one DAC 104 per input sample. In some other embodiments theremay be less than one DAC 104 per input sample as one DAC 104 may be shared amongseveral input samples by multiplexing. For example, two input samples may share the same DAC 104. Output signals will be extracted from the bit lines (columns in Figure 1) of thecrossbar array 110. If digital output values of the crossbar array 110 are needed then theoutputs of the crossbar array 110 may be converted to digital values. Thus, the electroniccalculation circuit 101 may further comprise the one or more ADCs 105 adapted toconvert the output samples, comprising analog output current, to corresponding digitaloutput values. In other words, the electronic calculation circuit 101 may further compriseADCs 105 configured to convert the output from the respective output conductor to adigital signal. If analog signals are needed in a next block in the processing chain, then the ADCs105 in the electronic device 101 may not be needed.Further, if the analog outputs are sent to another crossbar array, then they may beconverted to voltage signals, which may be done by a resistor.Embodiments herein relate to memristive-based electronic devices for mathematicaloperations. The memristive-based electronic devices for mathematical operations providehigh-throughput, high-performance, fully-parallel and flexible realization of several mathematical operations / functions using processing in memory (PIM). To this end, theparallel nature of analog crossbar arrays is employed to realize several mathematicalfunctions which leads to lower hardware cost, higher throughput, and lower latency compared to the traditional implementation approaches. Embodiments herein may comprise programming a set of memristive devices in acrossbar array with values which are determined by a target mathematicaloperation / function. Computations are performed using inherent properties of memristordevices, following Ohm’s law and Krichhoff’s current law, to generate an output of thetarget mathematical operation / function. ^Embodiments herein are based on PIM. Embodiments herein may be used toimplement one or more arithmetic functions by using one or more arrays ofmemristive devices. ^In some embodiments herein, a reciprocal calculation is realized according to theNewton–Raphson method using an array of memristive devices in the analogdomain. The reciprocal calculation may be employed to realize furthermathematical functions such as a square root (SQRT) function. In some otherembodiments herein the SQRT function is realized according to the Newton– Raphson method using an array of memristive devices in the analog domain. Thereciprocal or the SQRT function or both may be used to implement several othermathematical operations as will be described below. Since the electroniccalculation circuits for reciprocal and square root calculation according to embodiments herein may be based on the Newton-Raphson method they maytake advantage of memristive crossbar arrays since the required calculations for the Newton Raphson method for calculating the reciprocal or the square root comprise multiplication and addition which may be performed by crossbar arraysof memristors.^ The mathematical operation of the target function is converted to a vector-vectoror vector-matrix multiplication, which may be done in a parallel manner asdescribed below. Below this procedure will be described for each targeted functionin detail. ^Embodiments herein support also the most general cases. For example, in case offunctions which can receive real-valued and complex-valued inputs, both real andcomplex scenarios are realized. ^By realization of a complicated mathematical function using an array of memristivedevices, a computational complexity will be reduced to ^(1), which results in asignificant reduction in hardware complexity since the computations are donethrough inherent features of the memristive devices.^ Different embodiments herein may be realized using similar memristive devices.As a result, the different mathematical operations / functions may be combined withother mathematical operations / functions / computations within a single crossbar. Thus, multiple crossbar columns may be used to realize a certain function likereciprocal calculation, and another set of columns may be programmed to performanother computation, like mean calculation, and so on. These functions may worktogether in parallel. ^Embodiments herein may reduce the power / energy consumption, which in turnmay lead to increased battery life at a user equipment (UE) side. This is becausethe proposed schemes reduce the hardware complexity and also low-power memristive devices are employed to implement the target functions.Embodiments of a first electronic device 200 for performing a mathematicaloperation on an input value to calculate an output value by calculating the output value as a reciprocal of the input value, will be presented in relation to Figures 2a-2e. Embodiments of a second electronic device 400 for performing a mathematicaloperation on an input value to calculate an output value by calculating the output value asa square root of the input value will be presented in relation to Figures 4a-4c. The firstand second electronic devices 200, 400 may also be referred to as a first system ofelectronic calculation circuits 200 and a second system of electronic calculation circuits 400. Thus embodiments presented in relation to Figures 2a-2e and 4a-4c are forperforming a mathematical operation comprising either a calculation of an output value as a reciprocal of an input value or a calculation of the output value as a square root of the input value. In other words, the first electronic device 200 calculates the reciprocal of theinput, while second electronic device 400 calculates the square root of the input.Both the first and second electronic device 200, 400 comprise a memristivecrossbar array 203b, 203d, 203e, 430-1 which comprises at least three memristorsoperatively arranged in series and configured to be programmed by a respective memristor value. The memristive crossbar array 203b, 203d, 203e, 430-1 furthercomprises at least two inputs. The inputs to the at least three memristors and values ofthe at least three memristors may be configured based on a Newton-Raphson method forperforming the mathematical operation on the input value. In the following figures the memristors are programmed with memristor values,which are written near the memristors in the corresponding figure.PIM-based Reciprocal Calculation In many applications in wireless communication like Beam Power Calculation, Beam Selection, Cholesky Decomposition, which is used in MIMO Detection, etc. reciprocalcalculation of numbers is needed. Also, reciprocal calculation is highly required inMachine Learning (ML) for realizing the Activation Functions in neurons.The reciprocal operation may be realized using Newton–Raphson’s method. TheNewton–Raphson method is an iterative method which may be used to estimate an outputof a function, ^(^), for a given input, ^^. This process may be mathematically expressedas where ^(^) and ^′(^) are the targeted function and its derivative, ^^ is the inputvalue at ^-th iteration, and ^ is the maximum number of iterations. Depending on thetarget function and the required accuracy / performance, the number of iterations, ^, may be specified. One problem in the hardware implementation of mathematical functions usingNewton–Raphson method is that higher number of iterations reduces the throughput whileit increases the hardware cost and latency significantly. In embodiments herein theparallel nature of a memristive crossbar is employed to realize one or more mathematicalfunctions which leads to lower hardware cost, higher throughput, and lower latency compared to the traditional implementation approaches.Let’s consider the reciprocal operation, i.e.,^ ^ . In order to realize this operationusing Newton–Raphson method, the function ^(^) should be considered as where ^ is the input number, which we want to calculate the reciprocal of and ^^ is^ the output of reciprocal function, i.e., ^ , in the ^-th iteration. Having considered the concept of Newton–Raphson method in equation (4), an iterative process of reciprocal calculation may be expressed as ^^^^ = 2^^ − ^. ^ ^^, ^ = 1, … , ^ (5)where ^^and ^^^^are the output of the reciprocal function, i.e., ^ , in the ^-th and(^ + 1)-th iterations, respectively.In this process ^^ is an initial value, which may be obtained from a lookup table(LUT). It has been shown that a 4-bit LUT, which stores 16 initial values, results in a very good accuracy / performance. However, in order to improve the accuracy, a 6-bit LUT maybe used. In general, in case of an m-bit LUT, the first m bits of binary representation of ^may be used as the address of the LUT to generate the initial value, ^^.Embodiments of the first electronic device 200 for reciprocal calculation usingprocessing in memory (PIM) is illustrated in Figure 2a, which may include four blocks: ^A LUT 201, which may be used to store the initial values of the reciprocalcalculation as described above. ^A DAC 202, which may be used to convert the initial value, ^^, as well as the inputvalue to the corresponding analog values. ^A memristive-based reciprocal calculation circuit 203, which includes multiplememristors to realize the presented equations. ^An ADC 204, which is used to convert a final output to a corresponding digitalvalue. The LUT may be a digital LUT or an analog LUT e.g., using capacitors in analog domain. This means that the ADC / DACs are not mandatory.Some first embodiments of the reciprocal calculation circuit 203 using one iterationis shown in Figure 2b. In Figure 2b the reciprocal calculation circuit 203 comprises amemristive crossbar array 203b. This architecture realizes^ = 2 ^^ ^^ − ^. ^^, (6)where ^^ is the initial value and ^^ is the final result, i.e., ^^ ≈ 1 / ^.In Figure 2b the memristive crossbar array 203b comprises three memristors211b, 212b, 213b operatively arranged in series. The three memristors 211b, 212b, 213bare configured to be programmed by a respective memristor value. A first memristor 211bmay be configured with 1. A second memristor 212b may also be configured with 1. Athird memristor 213b may be configured with −^^^. The memristive crossbar array 203b of Figure 2b further comprises three inputs, one per memristor. A first input to the firstmemristor 211b may be ^^. A second input to the second memristor 212d may be ^^ anda third input to the third memristor 213d may be ^.The reciprocal calculation circuit 203 may further comprise DACs at every input tothe memristive crossbar array 203b. Likewise, the reciprocal calculation circuit 203 maycomprise ADCs at the output of the memristive crossbar array 203b. Also for the rest ofthe described embodiments below such DACs and ADCs may be used but are notillustrated nor described in the following. Since the value of ^^ may be stored in the LUT, it is also possible to store thesquare of the initial values (^^^) in the LUT as well. However, another solution to obtain ^^ ^ or −^^^is to employ a separate memristive-based multiplier 205 for this purpose, like the one shown in Figure 2c. For the above first embodiments it was assumed that the LUT 201 stores the squareof the initial values. However, it is possible to implement the same operation using adifferent architecture. To this end, the computations in equation (5) may be rewritten as^^ = ^^(2 − ^. ^^). (7)Some second embodiments of the memristive-based reciprocal calculation circuit203 for reciprocal calculation using one iteration is shown in Figure 2d. This architecturefollows equation (7), in which the LUT 201 may store the initial values but do not need tostore the square of the initial values (^^^). In Figure 2d a memristive crossbar array 203d-1 comprises three memristors211d, 212d, 213d operatively arranged in series. The three memristors 211d, 212d, 213d are configured to be programmed by a respective memristor value. A first memristor 211dmay be configured with 2. A second memristor 212d may also be configured with −^^^. Athird memristor 213d may be configured with ^^. The memristive crossbar array 203d ofFigure 2d further comprises two inputs. A first input to the first memristor 211d may be 1.A second input to the second memristor 212d may be ^.Thus, the memristive crossbar array 203b, 203d, 203e of the electronic reciprocal calculation circuit 203 comprises at least three memristors, such as the three memristors 211b, 212b, operatively arranged in series and configured to be programmed by a respective memristor value. The memristive crossbar array 203b, 203d, 203e further comprises at least two inputs. As mentioned above, in some embodiments herein thememristive crossbar array 203b, 203d, 203e comprises two or three inputs.In Figure 2d as well as in coming other figures, horizontal thick lines between someof the memristors represent current-to-voltage conversion with a current-to-voltageconverter 215, which may be implemented using a resistor. Thus, the memristivecrossbar array 203d may comprise multiple single-column crossbar sub-arrays 203d-1, 203d-2. At least two of the multiple single-column crossbar sub-arrays 203d-1, 203d-2 may be operatively connected via current-to-voltage converters. In some embodiments herein the multiple single-column crossbar sub-arrays 203d- 1, 203d-2 are two. There are several options to improve the accuracy of the reciprocal calculation. Oneoption is to increase the number of bits to represent ^, ^^, and ^^. This does not changethe presented architectures in Figure 2b and Figure 2d. Another solution to improve the accuracy is to increase the number of iterations. According to simulation results, twoiterations, i.e., ^ = 2, will result in a very good accuracy. To this end, the computations inequation (6) may be expanded as follows: By employing the presented architectures in Figure 2b or Figure 2d, the final result(i.e., ^^ ≈ 1 / ^) may be obtained in two crossbar read cycles. By repeating this process fora larger number of iterations, more accurate results may be obtained. However, adrawback of this scenario is that some of the memristors in the crossbar should be programmed twice and also the whole operation takes two crossbar read cycles.In order to solve these issues, the complete computations may be implemented atonce. By substituting equation (8) into equation (9) the final result of the reciprocalcalculation after two iterations, i.e., ^^ ≈ 1 / ^, may be obtained as,^^ = 4^ ^ ^ ^ ^ ^^ − 6^. ^^ + 4^ . ^^ − ^ . ^^ . (10)A memristive crossbar array 203e to realize the computations of equation (10) isshown in Figure 2e. In this architecture, the memristors are programmed only once with the depicted values and the input value, ^, is sent to the crossbar rows as shown inFigure 2e. As a result, the final output, ^^ ≈ 1 / ^, will be generated after only one readcycle of the memristive crossbar array 203e. A higher number of iterations (^ > 2) may berealized by following this idea. To this end, the computations in equations (6) may beexpanded for the desired ^ and then a corresponding structure of the crossbar may bespecified. Note that such a procedure may be done offline. Thus, the electronic calculation circuit 203 may be configured to calculate the reciprocal value of the input value based on two iterations of the Newton-Raphsonmethod. Then the memristive crossbar array 203e may comprise eight inputs and mayfurther comprise seven memristive crossbar sub-arrays operatively connected via six current-to-voltage converters. The seven memristive crossbar sub-arrays may comprise eighteen memristors and wherein a first crossbar sub-array 203e-1 is operatively connected to a seventh crossbar sub-array 203e-7 via a first current-to-voltage converter 221, a second crossbar sub-array 203e-2 is operatively connected to a third crossbar sub- array 203e-3 via a second current-to-voltage converter 222, the third crossbar sub-array 203e-3 is operatively connected to a fourth crossbar sub-array 203e-4 and a fifth crossbarsub-array 203e-5 via a third current-to-voltage converter 223 , the fourth crossbar sub-array 203e-4 is operatively connected to the seventh crossbar sub-array 203e-7 via a fourth current-to-voltage converter 224, the fifth crossbar sub-array 203e-5 is operatively connected to a sixth crossbar sub-array 203e-6 via a fifth current-to-voltage converter 225 and the sixth crossbar sub-array 203e-6 is operatively connected to the seventh crossbar sub-array 203e-7 via a sixth current-to-voltage converter 226. As may be seen in Figure 2e, in some embodiments herein at least a further two of the multiple single-column sub-arrays 203d-1, 203d-2 are arranged in parallel. It is possible to avoid reprogramming of the memristive crossbar array 203e in casea new input value is received. To this end, multiple memristive crossbar arrays 203f,203g, which are similar to the one in Figure 2e, may be considered such that each ofthem is programmed with a specific initial value, ^^. Since the memristive crossbar array203e in Figure 2e is not large and also the number of initial values is not large, e.g., 8 or16 initial values in case of 3-bit or 4-bit LUT, the hardware cost will be acceptable. On the other hand, in this case, the LUT is not needed anymore, which reduces the hardware cost. PIM-based Division One of the most challenging mathematical operations using hardware is division,which is needed in realization of various signal processing algorithms. A traditional way toperform division is to use off-the-shelf digital division circuitry, which have a high hardware cost. For high throughput and high numeric precision, embodiments herein are based ona PIM architecture to perform division.Figure 3a and Figure 3b illustrate embodiments herein wherein division isperformed by using a reciprocal operation according to the previously describedembodiments followed by a multiplication using a memristive crossbar array. For example,a dividend Y is to be divided by a divisor X. The reciprocal of X, i.e., 1 / X, may be calculated according to the previously described embodiments. The reciprocal of thedivisor, 1 / X, is then multiplied with Y.Figure 3a illustrates a first electronic calculation circuit 301 and a secondelectronic calculation circuit 302. The first electronic calculation circuit 301 calculatesthe reciprocal of X. The second electronic calculation circuit 302 calculates the multiplication of 1 / X with Y. In Figure 3b the input value to a memristor of a multiplying crossbar array of thesecond electronic calculation circuit 302 is configured with the value of the reciprocal ofthe divisor, 1 / X, and the value represented by the memristor is configured with the valueof the dividend Y. In order to improve the accuracy, as described above, a higher number of bits maybe used to represent X and Y, and a higher number of iterations may be used in thereciprocal calculation. PIM-based Square Root (SQRT) In many applications calculation of a square root of a number is needed. A simpleexample is to solve ^^ = ^. However, there are more complicated use cases in wirelesscommunication systems which require SQRT calculation, e.g., Cholesky decomposition in MIMO detection, Norm Calculation of the received Beam Power, etc. The SQRT operation may be realized using one or more calculation circuits, at least one of them comprising amemristive crossbar array configured based on the Newton–Raphson method. This leadsto a lower hardware cost, higher throughput, and lower latency compared to traditional implementation approaches. In order to calculate√^, the target function is defined as ^(^^) = ^ − ^ ^^, (11)where ^ is the input number, of which the square root is to be calculated, and ^^ isthe output of the SQRT function, i.e., , in the ^-th iteration.Having considered the concept of Newton–Raphson method in (3), the iterative process of SQRT calculation may be expressed as where ^^ and ^^^^ are the output of SQRT function, i.e., √^ , in the ^-th and (^ +1)-th iterations, respectively. An electronic device 400 to calculate √^ is illustrated in Figure 4a. A first actionmay be initialization, in which ^^ is an initial value. The initial value may be set to ^^ = ^,which result in a good accuracy / performance. Also, by choosing this initial value, there isno need for a lookup table to save the initial values. As a result, by substituting ^^ = ^ in(12), the output of the initialization step will be equal to The electronic device 400 may comprise an initialization calculation circuit 410. In some embodiments herein the initialization calculation circuit 410 comprises amemristive crossbar array 410-1 illustrated in Figure 4b. The memristive crossbar array410-1 comprises two memristors which are configured to be programmed by a respectivememristor value. A first memristor 411b of the memristive crossbar array 410-1 may beconfigured with 0,5. A second memristor 412b of the memristive crossbar array 410-1may also be configured 0,5. The memristive crossbar array 410-1 of Figure 4b furthercomprises two inputs. A first input 401b to the first memristor 411b and a second input402b to the second memristor 412b.A first input value to the first memristor 411 may be the input number, ^, of whichthe square root is to be calculated. A second input value to the second memristor 212dmay be 1.A reciprocal of the output of the initialization, ^^, may be calculated using the PIM-based reciprocal calculation circuit 200 above. Then an iteration of a SQRT calculation,which follows equation (12), may be calculated using embodiments of a square rootcalculation circuit 430 illustrated in Figure 4c. At the (i+1)-th iteration, a memristivecrossbar array 430-1 of the square root calculation circuit 430 receives the input number^ (^), the output of a previous iteration (^^) and its reciprocal (^^) to calculate the SQRT of ^ in (i+1)-th iteration as √^ = ^^^^ . (14)In some embodiments herein the memristive crossbar array 430-1 comprises twomemristive crossbar sub-arrays, such as a first memristive crossbar sub-array 431 anda second memristive crossbar sub-array 432. The memristive crossbar array 430-1may comprise three memristors in total which are configured to be programmed by arespective memristor value. The first memristive crossbar sub-array 431 may comprise afirst memristor 411c and a second memristor 412c. The first memristor 411c of thememristive crossbar array 430-1 may be configured with a value of 1. The secondmemristor 412c of the memristive crossbar array 410-1 may be configured with the inputnumber, ^, of which the square root is to be calculated.The second memristive crossbar sub-array 432 may comprise a third memristor 413c. The memristive crossbar array 430-1 of Figure 4c further comprises two externalinputs. A first input 401c to the first memristor 411c and a second input 402c to thesecond memristor 412c. Afirst input value to the first memristor 411c may be the output of a previousiteration (^^). A second input value to the second memristor 412c may be the reciprocal ofthe output of the previous iteration (1 / ^^). A third input value to the third memristor 413cmay be the output of the second memristor 412c of the first memristive crossbar sub-array 431. Depending on a required accuracy of the respective application, the square rootcalculation as well as the reciprocal calculation may be repeated similarly for (K-1) times,where K is the maximum number of iterations. For a certain application, an efficient valueof K may be obtained from simulations in advance and then a number of required blocks(i.e., iterative steps) in Figure 4a may be specified.Embodiments herein may be combined to implement an electronic device forperforming a mathematical operation on one or more input values to calculate an outputvalue. The electronic device may also be referred to as a system of electronic calculationcircuits and may besides the memristive crossbar arrays also comprise DACs and ADCs and LUTs and other suitable electronics. The mathematical operation may for example be one of: division, mean square, mean squared error, root mean square, weighted average, arithmetic mean, harmonic mean, vector norm, Frobenius norm of a matrix, or Euclidian distance. The electronic device 200, 400 comprises a first electronic calculation circuit203f, 301, 420 according to any of the embodiments described in relation to Figures 2a-2for 4a-4c. The first electronic calculation circuit 203f, 301, 420 is configured to perform afirst mathematical operation on a first input value based on the one or more input values to calculate a first output value by calculating the first output value as a reciprocal of the first input value, or calculating the first output value as a square root of the first inputvalue. The first electronic calculation circuit 203f, 301, 420 comprises a first memristivecrossbar array 203b, 203d, 203e. The electronic device 200, 400 comprises a second electronic calculation circuit203g, 302, 430 comprising a second memristive crossbar array 430-1. The secondelectronic calculation circuit 203g, 302, 430 is configured to perform a second mathematical operation on a second input value based on the one or more input values to calculate a second output value. The output value is based on the second output value or based on the first output value or both. The first electronic calculation circuit 203f, 301, 420 may be configured to calculatethe first output value as a reciprocal of the first input value The second electroniccalculation circuit 203g, 302, 430 may be configured to calculate the second output valueas a square root of the second input value. In some embodiments herein, e.g., as described above in relation to Figure 2f or 4a,the second electronic calculation circuit 203g, 302, 430 is according to any of theembodiments described in relation to Figures 2a-2f or 4a-4c. Specifically for embodiments related to Figure 2f, the second electronic calculationcircuit 203g, 302, 430 may be a copy of the first electronic calculation circuit 203f, 301,420 and the second electronic calculation circuit 203g, 302, 430 is then configured tocalculate a same mathematical operation as the first electronic calculation circuit 203f,301, 420. Further, the second input value may be the same as the first input value. Thenthe first electronic calculation circuit 203f, 301, 420 may be configured based on a first approximation of the output. For example, at least one memristor of the first crossbar array may be programmed with a first initial approximation of the output value. The second electronic calculation circuit 203g, 302, 430 may be configured basedon a second approximation of the output. The electronic device 200 may then be configured to select one of the first or thesecond electronic devices, which are operatively arranged in parallel, for performing the mathematical operation. At least one memristor of the second crossbar array may be programmed with asecond initial approximation of the output value. One multiplexer may be added to the design. Inputs to the multiplexer may be theoutput values of the different crossbars corresponding to different initial values and its output is the final output of the mathematical operation. In some other embodiments herein the first electronic calculation circuit 203f, 301, 420 is configured to calculate a first part of the mathematical operation on the one or more input values and the second electronic calculation circuit 203g, 302, 430 is configured to calculate a second part of the mathematical operation on the one or more input values. Then the second electronic calculation circuit 203g, 302, 430 may differ from the first electronic calculation circuit 203f, 301, 420. This is for example the case for the calculation of the square root as described above in relation to Figures 4a-4c but also for the calculations that will be described below. Thus, inputs to the memristors of the second memristive crossbar array and thevalues of the memristors of the second memristive crossbar array may be based on a second Newton-Raphson method for performing the second part of the mathematicaloperation, and the second Newton-Raphson method may differ from the first Newton-Raphson method in that the final iterative calculations differ. Figure 5 illustrates a flowchart of a method for performing a mathematical operationwith the electronic calculation circuit 203f, 301, 420 on an input value to calculate an output value by calculating the output value as a reciprocal of the input value, orcalculating the output value as a square root of the input value. The method may beiterative. As mentioned above, the electronic calculation circuit 203f, 301, 420 comprises thefirst memristive crossbar array 203b, 203e, 320, 330 comprising at least three memristors 211b, 212b, 213b operatively arranged in series and at least two inputs operatively connected to two of the at least three memristors 211b, 212b, 213b. In some embodiments herein the mathematical operation comprises a first mathematical operation on a first input value based on the input value to calculate a firstoutput value and a second mathematical operation on a second input value based on theinput value to calculate a second output value. The second input value may comprise thefirst output value. For example, the second input value may be the first output value.In some embodiments herein the first mathematical operation calculates the firstoutput value as a reciprocal of the first input value and the second mathematical operation calculates the second output value as a square root of the second input value. The mathematical operation may be one of: division, mean square, mean squarederror, root mean square, weighted average, arithmetic mean, harmonic mean, vectornorm, Frobenius norm of a matrix, or Euclidian distance. All these mathematicaloperations may be based on the reciprocal calculation or the square root calculation or both. The method may be performed by the electronic device 200, 400. The methodactions below may be taken in any suitable order. Action 500 The method comprises configuring inputs of at least two of the at least threememristors 211b, 212b, 213b. The three memristors 211b, 212b, 213b may be configuredaccording to the Newton Raphson method for performing the mathematical operation onthe input value described above. At least one memristor of the at least three memristors 211b, 212b, 213b may beconfigured with a static value. The at least one memristor may be pre-configured with thestatic value. In some embodiments herein the static value is any of 0,5, 1, or 2. A value ofat least one input to the crossbar array may equal the input value. Action 501 The method further comprises configuring values represented by the at least three memristors 211b, 212b, 213b. That is, the values represented by the at least three memristors 211b, 212b, 213b are programmed.A value represented by at least one memristor of the crossbar array may equal theinput value. In some embodiments herein a value of at least one memristor of the crossbar array equals an approximation of the output value. Avalue represented by at least one memristor of the crossbar array may equal asquare of an approximation of the output value. In some embodiments herein theapproximation of the output value is an intermediate output value based on the input value. Action 502 The method further comprises applying the inputs to the at least three memristors 211b, 212b, 213b to calculate the output value. Figure 6 illustrates a flowchart of a method for performing a mathematical operationwith the electronic calculation circuit 203f, 301, 420 on the input value to calculate theoutput value according to embodiments herein which complements the flowchart of Figure5. The method actions below may be taken in any suitable order. The method accordingto the flowchart of Figure 6 may be used for several complicated mathematical functions. Action 600 The method may comprise extracting the required mathematical operations torealize a specific function. The extracted computations of the targeted function can berealized using matrix or vector multiplications.Action 601 For each specific function, a corresponding matrix of coefficients, ʗ, may be extracted. Action 602 Astructure of the required crossbar arrays to realize the target function may bespecified. Action 603 The method may further comprise configuring the memristive devices of the electronic calculation circuit 203f, 301, 420. The memristive devices of the electroniccalculation circuit 203f, 301, 420 may be configured according to the matrix coefficients.Thus, the vector / matrix of coefficients will be programmed to the memristors of theelectronic calculation circuit 203f, 301, 420. Action 604 Then, the input samples may be sent to the DAC 202. The output voltage of theDAC 202 will be applied to the crossbar rows.Action 605 If digital output of the filter is needed, the analog signals which are generated at thecrossbar columns may be converted to binary values, e.g., using the ADC 204. Action 606 After a read cycle of the crossbar arrays, the generated signal(s) at the crossbarcolumn(s) will represent the output signal.This procedure will be repeated for the next sequence of input samples. If theparameters of the function / algorithm are changed for any reason, the crossbar may be programmed with a new vector / matrix of coefficients. Otherwise, there is no need to reprogram the crossbar array. Mean Square (MS) Calculation using PIMIn some applications, the mean square (MS) of a set of numbers, ^ , ^ = 1, … , needed. The MS value, is calculated as the arithmetic mean of the squares of the values, where ^ is the number of values in the input sequence.Figure 7a illustrates some embodiments to calculate the MS of ^ values. Areciprocal calculation block 701 in the left side of the block diagram, calculates the^ reciprocal of the number of values, ^, using the PIM-based reciprocal calculation circuit203 described above. Meanwhile the summation of the squares of the input values,∑^ ^^^ ^^ ^, may be calculated using a sum calculation block 702 comprising a memristivecrossbar array 702-1 shown in Figure 7b.The generated values by these two blocks may be multiplied together using amemristive-based multiplier 703, corresponding to the memristive-based multiplier 205of Figure 2c. The output of this multiplication , which will be the MS of all the input values. Mean Squared Error (MSE) Calculation using PIMMean squared error (MSE) or mean squared deviation (MSD) is widely used in theprocedure of estimating an unobserved quantity in wireless communication includingChannel Estimation, Adaptive Filter, System Identification, etc. Moreover, MSE is used todefine a loss functions for Machine Learning and Deep Learning applications. It may alsobe used to define MSE measures, the average of the squares of the errors, in which theerror is defined as the difference between the estimated values and the actual value. Another use case of the MSE is to evaluate predictors, which are used in machine learning algorithms (the predictor maps arbitrary inputs to some random variable). Thus, the MSE (MSD) is considered as a measure of the quality of an estimator, predictor, etc. In addition, the MSE (MSD) is also used in a method of least squares, which is astandard method of fitting statistical estimates to observed data by minimizing the squareddistances between them. The MSE (MSD) is defined mathematically as, where ^ is the vector of actual values, ^ is the vector of estimated / predicted values,and N is the number of samples in vectors ^ and ^. The computations in equation (16)may be rewritten as,^^^(^, ^) =1 [^^^^ + ^ ^^ − 2^^^^ + ^ ^^ + ^ ^^ − 2^ ^ ^^^^ + ⋯ + ^^ + ^^ − 2^^^^ +]. (17)Embodiments of a calculation circuit to compute MSE between two vectors of size Nis illustrated in Figure 8. An MSE calculation crossbar array 801 may include 4Nmemristors, which are programmed as depicted in Figure 8. After a read cycle, the outputsignal of crossbar column is sent to a memristive-based multiplier 802, which is like theone shown on Figure 2c. The other input of the multiplier is 1 / N, which is generated by areciprocal calculation block 803. The PIM-based reciprocal calculation block 803 inFigure 8 may be implemented as described above. Finally, the output of the PIM-basedmultiplier may represent the MSE of two vectors, i.e., ^^^(^, ^).PIM-based Root Mean Square (RMS) In some applications, the root mean square (RMS) of a set of numbers, ^^ , ^ =1, … , is needed. The RMS value, which is also known as the quadratic mean, iscalculated as the square root of the arithmetic mean of the squares of the values, where ^ is the number of values in the sequence.A PIM-based electronic circuit to calculate the RMS of ^ values is illustrated inFigure 9. A reciprocal calculation block 901 in the left side of the block diagram,^ calculates the reciprocal of the number of values, ^, using the above-described reciprocalcalculation circuit. Meanwhile the summation of the squares of the input values, ∑^ ^ ^^^ ^^,may be calculated using a sum square calculation block 902 comprising the above-described memristive crossbar array 702-1 of Figure 7b.The generated values by the previous two blocks may be multiplied together usingthe memristive-based multiplier 903. The output of this multiplication is^ ^∑^ ^^^ , whichwill be sent to a PIM-based SQRT calculation block 904 to generate the RMS of thevalues in the input sequence. The SQRT calculation block 904 may be realized using theabove-described square root calculation circuit 430. Average Calculation using PIM ^Weighted Average (WA)A weighted average is used in several applications including obtaining a weightedaverage of beam power for receiver beams at the receiver side. The weighted average of a set of numbers is the general case of average calculation. In this case, the numbers, X^, contribute unequally to the average of the set. The weighted average is defined as where ^ is the number of values in the set and ^^ is the weight corresponding tothe i-th input number in the set, ^^. ^Arithmetic Mean (AM)An elementary form of average calculation is the arithmetic mean, which is widely used in many applications like average power calculation of the UEs in wireless communication systems, data analysis, etc. Having considered the input set of numbers,^^, ^^, … , ^^, the arithmetic mean may be expressed as It may be seen that the arithmetic mean is a simplified case of the weightedaverage, where all the weights are equal to 1, i.e., ^^ = 1, ^ = 1, … , Figure 10a illustrates an architecture of an electronic device to implement bothweighted average (WA) and arithmetic mean (AM). First, a weighted summation of thenumbers in the input set, , may be calculated by using a memristive crossbararray 1001, details of which are shown in Figure 10b. Next, the reciprocal of the number^ of values, ^, is calculated using the above-described reciprocal calculation circuit 203.Then, the generated values by the previous two blocks may be multiplied together using amemristive-based multiplier 1002, for example corresponding to Figure 2c. The outputof this multiplication may be either weighted average (WA) or arithmetic mean (AM)depending on the value of the weights, ^^. One of the most commonly used application of this scheme is to calculate the average power consumption, which is needed in many use cases including wireless communications systems. Note that in some applications like wireless communication systems, the number ofvalues in the set is usually a power of two, i.e., ^ = 2^. In such cases, the division by ^may be performed with a much lower cost (almost zero cost) in the digital domain. To thisend, the PIM-based Reciprocal Circuit may be removed, and the output of the PIM-basedmultiplication block may be shifted to the right by ^ bit positions in the digital domain.Harmonic Mean (HM) Calculation using PIM An important type of numerical average is harmonic mean (HM). The harmonic mean necessarily includes all the entries in the input set of numbers and thus it considers all the aspect of the series (i.e., input set). Moreover, it allows a more significant weighting to be given to smaller values. The harmonic mean may be expressed as the reciprocal of the arithmetic mean ofthe reciprocals of the given set of input numbers, ^^, where ^ is the total numbers in the input set.Figure 11a illustrates a PIM-based architecture of an electronic device 1100 torealize the harmonic mean (HM). First, the reciprocal of all the numbers in the input ^ set,^^ , are calculated using a reciprocal calculation block 1101 comprising the above-described reciprocal calculation circuit 203. Next, these reciprocals may be addedtogether by using a memristive-based summation calculation block 1102, comprisinga memristive crossbar array 1102-1 shown in Figure 11b. Then, the result of theaddition,∑^ ^ ^^^^^ , may be sent to another reciprocal calculation block 1103, which^^ computes its reciprocal,Finally, the output of the reciprocal block may be multiplied by the number of values in the set, ^, using a memristive-based multiplier 1104, forexample corresponding to Figure 2c. As shown in Figure 11a, the output of thismultiplication is equal to the harmonic mean (HM). It is worth to mention that in case of ^ = 2, the following relation is valid betweenharmonic mean (HM), arithmetic mean (AM), and geometric mean (GM): ^^^ = ^^ × ^^, (22)where the geometric mean of two numbers is calculated as Thus, when two of the above-mentioned means are available, the relation inequation (22) may help to indirectly calculate the third mean. Vector Norm Calculation using PIM In many applications, it is required to compute the norm of a vector, which is a non-negative number. This is needed in wireless communication systems for Beam Selection,MIMO Detection, etc. Also, it is needed in ML and DL applications to define the LossFunction. The vector, ^ = [X^ , X^ , … , X^], may include complex or real-domain entries.Let’s consider the general case, in which the entries of the input vector, X, are complex numbers. There are different types of norms. However, one of the most commonly used is L-2 norm. The L-2 norm of a complex vector is defined as where ^^ is the conjugate transpose of vector ^. It may be said that thecomputation in equation (24) realizes the inner dot product of vector ^. The computation in (24) can be expanded as follows ‖^‖ = ^ℜ{^^}^ + ℑ{^^}^ + ℜ{^^}^+ℑ{^^}^ + ⋯ + ℜ{^^}^+ℑ{^^}^ , (25) and ℑ{^} are the real and imaginary parts of the entries, respectively.In case of a real-domain vector, the L-2 norm of vector ^ may be calculated as,‖^‖ = ^^^ + ^ ^ ^^ + ⋯ + ^^ . (26)Figure 12a illustrates a PIM-based architecture of an electronic device 1200 tocalculate the L-2 norm. First, the summation of the squares of real and imaginary parts ofthe input values (^ ^^^ and ^^^ ℑ{^^} ) may be calculated by a respectivesquare calculation block 1201, 1202 using the memristive-based crossbar array 702-1which is shown in Figure 7b. Next, these summations will be added together by using amemristive-based adder block 1203, comprising a memristive crossbar array 1203-1shown in Figure 12b. Then, the result of the addition will be sent to a PIM-based SQRTcalculation block 1204 as described above.Simplification: Depending on the use case, it is known in advance if the input vector is real orcomplex. As a result, the architecture in Figure 12a may be simplified as follows:^ In case of real-domain vector, the adder block 1203 is not needed. Thus, sumsquares are calculated and then the SQRT of the summation will be computed. Inthis case, the Sum Square of imaginary parts is not needed, which is illustrated bya dashed rectangle in Figure 12a.^ For a complex-domain vector, the summation of squares of real and imaginaryparts may be computed together using one crossbar. Therefore, the adder block1203 is not needed in this case. As a result, the architecture in Figure 12a may be simplified to two calculationblocks such that the first bock calculates the summation of squares and the second onecalculates the SQRT for the output of the first block. Frobenius norm Calculation of a matrix using PIM Above the norm calculation was described for a vector. Here the norm calculationfor a matrix is explained. The most important matrix norm which is not induced by a vectornorm is the Hilbert-Schmidt or Frobenius Norm. The Frobenius Norm is used to measurethe magnitude of a matrix, which is needed in many applications such as powercalculation of a signal, etc. The Frobenius Norm of an ^ × ^ matrix is defined as where ^^,^is the (i, j)-th entry of matrix ^. In order to calculate the Frobenius Normeffectively using the crossbar arrays, the equation (27) can be rewritten as‖^‖^ = ^trace where “trace” of a matrix is the sum of its diagonal elements. Figure 13a illustrates a PIM-based architecture of an electronic device 1200 tocalculate the Frobenius Norm of a matrix. First, the trace of ^. ^^ is calculated using atrace calculation block 1301 comprising a memristive crossbar array 1301-1 shown inFigure 13b, which is a crossbar of size 2^^ × 1. The memristors of this crossbar areprogrammed by the real and imaginary parts of the entries in the input matrix. Forexample, the first ^ memristors are programmed by the real part of the entries in the firstrow of ^ and the second ^ memristors are programmed by the imaginary part of theentries in the first row of ^. The input value to each crossbar row is the same as the value, which is already programmed to the corresponding memristor. After a read cycle,the output signal of the crossbar in Figure 13b will represent the trace of ^. ^^.Finally, the result of the crossbar 1301-1 is sent to a SQRT calculation block 1302as described above. The output of the SQRT block 1302 represents the Frobenius norm of the input matrix, i.e.,‖^‖^.The crossbar shown in Figure 13b may be replaced by either a crossbar array withmultiple columns, or multiple crossbars with smaller size than the one in Figure 13b. Forexample, if the size of the input matrix is larger than the size of available crossbars,multiple smaller crossbars may be used instead. In case of using multiple crossbar arrays,a memristive-based adder may be employed to do the summation of the output signals ofall crossbar columns. It is worth to mention that, in the proposed architecture in Figure 13b, thissummation is performed according to the Krichhoff’s current law without any extra circuitfor the adder.Euclidean Distance (ED) Calculation using PIM There are many applications in wireless communication systems like MIMO Detection, Beam Selection, Channel Estimation, etc., which require ED calculation. ^Two-Dimensional Euclidean Distance (2-D ED)Figure 14 shows the Euclidean distance between two points in a cartesian space,which can be calculated as ^^(^, ^) = ^(^^ − ^^)^ + (^^ − ^^)^ (29)where (^^, ^^) and (^^, ^^) are the Cartesian coordinates of the points ^^ and ^^,respectively. Figure 15a illustrates a PIM-based architecture of an electronic device 1500 tocalculate the Euclidean distance between two points, which follows the computation in equation (29). However, this architecture may be simplified in case of ED calculation between twopoints. To this end, equation (29) may be rewritten as The computation in (30) may be realized using eight memristors of a crossbararray 1501, which may be programmed as shown in Figure 15b, in combination with asquare root calculation circuit 1502.^ High-Dimensional Euclidean Distance (N-D ED)In general, the Euclidean distance can be calculated for points given by their coordinates in a higher-dimensional space, e.g., 3-dimensional space. Also, this conceptcan be used to find the Euclidean distance between two vectors, ^ = [^^, ^^, … , ^^] and^ = [^^, ^^, … , ^^] as follows, Figure 16a illustrates a PIM-based architecture of an electronic device 1600 tocalculate the Euclidean distance between two vectors ^ and ^.First, a distance between ^-th entries, ^ = 1, … , of two vectors are calculated inparallel using a memristive-based subtractor circuit 1601, comprising a memristivecrossbar array 1601-1 shown in Figure 16b. Next, the squares of the distances may becalculated using a memristive-based square calculation block 1602 comprising amemristive crossbar array 1602-1 which is shown in Figure 16c. Next, these squarevalues will be added together by using a memristive-based circuit 1603, comprising thememristive crossbar array of Figure 12b. Then, the result of the summation will be sent toa PIM-based SQRT calculation block 1604, which has been described above to obtainthe ED between two vectors ^ and ^.Note that, if the vector entries are complex values, then the square of L-2 norm of(^^ − ^^) should be calculated, i.e., ‖^^ − ^^‖^, instead of (^^ − ^^)^. The SQRT calculation blocks in Figure 15a, 15b, and 16a is illustrated by a dashedrectangle. The reason is that in some scenarios, the SQRT calculation block may beremoved as explained below. In many applications, and in particular when comparing distances between two points or vectors, it may be more convenient to omit the final square root in the computation of Euclidean distances. Thus, the calculated value resulting from thisomission is the square of the Euclidean distance, which is called the squared Euclideandistance. This can be expressed as a sum of squares:^^^(^, ^) = (^ − ^ ^ ^ ^^ ^) + (^^ − ^^) + ⋯ + (^^ − ^^) . (32) In addition to its application for distance comparison, the squared Euclideandistance in (32) is also used in the method of least squares, which is a standard methodof fitting statistical estimates to observed data by minimizing the squared distancesbetween them. Some advantages of PIM-based hardware accelerators for mathematical / arithmetic functions include: ^A fully parallel architecture for multiple arithmetic functions, which may achieve anultra-high throughput. ^The latency of embodiments herein is only limited by the read cycle of thecrossbar arrays, and it is not limited by the complexity of the function, number of inputs, etc. ^Since the memristive devices consume much lower power compared to traditionalmultiply accumulate (MAC) modules, the proposed PIM-based hardware accelerators have the potential of low power / energy consumption, which is a critical demand in many use cases (e.g., IoT devices). ^Embodiments herein support processing of complex-valued inputs in a similar wayas real-valued inputs without any degradation in the throughput and performanceof the electronic device. ^The presented PIM-based hardware accelerators are computationally efficientcompared to the traditional coding schemes since the computational complexity of embodiments herein is reduced to ^(1).^ Embodiments herein are scalable in terms of number of inputs, bit resolution, etc.^ Embodiments herein support serial, partial parallel, and fully parallelimplementation of different arithmetic functions while they enable a tradeoff between the achieved accuracy / performance and hardware cost. Figure 17 illustrates a network node 601 of a wireless communications network170, the network node 601 comprising any of the electronic calculation circuits disclosedabove or any of the electronic devices disclosed above.Figure 18 illustrates a wireless communications device 602 comprising any ofthe electronic calculation circuits disclosed above or any of the electronic devices disclosed above.The network node 601 and the wireless device 602 may be configured to performthe method actions of Figures 5 and 6 above.The embodiments herein may be implemented through a processor or one ormore processors, such as the processor 1704, 1804 of a processing circuitry in thenetwork node 601 and the wireless device 602 respectively and depicted in Figure 17 and18 together with computer program code for performing the functions and actions of theembodiments herein. The program code mentioned above may also be provided as a computer program product, for instance in the form of a data carrier carrying computerprogram code for performing the embodiments herein when being loaded into the networknode 601 and the wireless device 602 respectively. One such carrier may be in the formof a CD ROM disc. It is however feasible with other data carriers such as a memory stick. The computer program code may furthermore be provided as pure program code on aserver and downloaded to the network node 601 and the wireless device 602 respectively.The network node 601 and the wireless device 602 respectively may furthercomprise a memory 1702, 1802 comprising one or more memory units. The memorycomprises instructions executable by the processor in the network node 601 and thewireless device 602 respectively.The respective memory 1702, 1802 is arranged to be used to store e.g. information,data, configurations, and applications to perform the methods herein when beingexecuted in the network node 601 and the wireless device 602 respectively.In some embodiments, a computer program 1703, 1803 comprises instructions,which when executed by the at least one processor, cause the at least one processor ofthe network node 601 and the wireless device 602 respectively to perform the actionsabove. In some embodiments, a carrier 1705, 1805 comprises the computer program,wherein the carrier is one of an electronic signal, an optical signal, an electromagnetic signal, a magnetic signal, an electric signal, a radio signal, a microwave signal, or a computer-readable storage medium. The network node 601 and the wireless device 602 respectively may furthercomprise an input and output interface, I / O, 1706, 1806 configured to communicate withother devices. The input and output interface 1706, 1806 may comprise a receiver, such as a wireless receiver, (not shown) and a transmitter, such as a wireless transmitter, (not shown). Those skilled in the art will also appreciate that the units described above may refer to a combination of analog and digital circuits, and / or one or more processors configuredwith software and / or firmware, e.g., stored in the network node 601 and the wirelessdevice 602 respectively, that when executed by the respective one or more processorssuch as the processors described above. One or more of these processors, as well as the other digital hardware, may be included in a single Application-Specific Integrated Circuitry (ASIC), or several processors and various digital hardware may be distributed among several separate components, whether individually packaged or assembled into a system-on-a-chip (SoC). Figure 19 illustrates a wireless communications network 170 in whichembodiments herein may be implemented. The wireless communications network 170 may use a number of different technologies, such as Wi-Fi, Long Term Evolution (LTE), LTE-Advanced, 5G, New Radio (NR), Wideband Code Division Multiple Access (WCDMA), Global System for Mobile communications / enhanced Data rate for GSM Evolution (GSM / EDGE), Worldwide Interoperability for Microwave Access (WiMax), or Ultra Mobile Broadband (UMB), just to mention a few possible implementations. Embodiments herein relate to recent technology trends that are of particular interest in a 5G context. However, embodiments are also applicable in further development of other existing wireless communication systems suchas e.g., WCDMA and LTE and in future wireless communication systems, such as 6Gsystems. Network nodes operate in the wireless communications network 170 such as thenetwork node 601. The network node 601 provides radio coverage over a geographicalarea, a service area referred to as a cell 15, which may also be referred to as a beam or a beam group of a first radio access technology (RAT), such as 5G, LTE, Wi-Fi or similar.There may be more than one cell. For example, there may be a second cell 16 as well.The network node 601 may be a NR-RAN node, transmission and reception point e.g. abase station, a radio access node such as a Wireless Local Area Network (WLAN) access point or an Access Point Station (AP STA), an access controller, a base station, e.g. a radio base station such as a NodeB, an evolved Node B (eNB, eNode B), a gNB, a base transceiver station, a radio remote unit, an Access Point Base Station, a base station router, a transmission arrangement of a radio base station, a stand-alone access point or any other network unit capable of communicating with a wireless device within the service area depending e.g. on the radio access technology and terminology used. Therespective network node 601 may be referred to as a serving radio access node andcommunicates with a UE with Downlink (DL) transmissions to the UE and Uplink (UL) transmissions from the UE. A number of wireless communications devices operate in the wireless communication network 170, such as the wireless communications device 602. The wireless communications device 602 may be a mobile station, a non-accesspoint (non-AP) STA, a STA, a user equipment and / or a wireless terminal, thatcommunicate via one or more Access Networks (AN), e.g., RAN, e.g. via the networknode 601 to one or more core networks (CN) e.g. comprising a CN node 13, for examplecomprising an Access Management Function (AMF). It should be understood by the skilled in the art that “UE” is a non-limiting term which means any terminal, wireless communication terminal, user equipment, Machine Type Communication (MTC) device,Device to Device (D2D) terminal, or node e.g., smart phone, laptop, mobile phone,sensor, relay, mobile tablets or even a small base station communicating within a cell. When using the word "comprise" or “comprising” it shall be interpreted as non- limiting, i.e. meaning "consist at least of". The embodiments herein are not limited to the above-described preferredembodiments. Various alternatives, modifications and equivalents may be used.

Claims

CLAIMS1. An electronic calculation circuit (203, 430) for performing a mathematical operation onan input value to calculate an output value by calculating the output value as areciprocal of the input value, or calculating the output value as a square root of theinput value, wherein the electronic calculation circuit (203, 430) comprises a memristive crossbar array (203b, 203d, 203e, 430-1) comprising:at least three memristors (211b, 212b, 213b) operatively arranged in series and configured to be programmed by a respective memristor value; and at least two inputs operatively connected to two of the at least three memristors (211b, 212b, 213b).

2. The electronic calculation circuit (203, 430) according to claim 1, wherein the at leasttwo inputs and values of the at least three memristors (211b, 212b, 213b) are configured based on a Newton-Raphson method for performing the mathematical operation on the input value.

3. The electronic calculation circuit (203, 430) according to claim 1 or 2, wherein thememristive crossbar array (203b, 203d, 203e, 430-1) comprises two or three inputs.

4. The electronic calculation circuit (203, 430) according to any of the claims 1-3,wherein the memristive crossbar array (203d) comprises multiple single-columncrossbar sub-arrays (203d-1, 203d-2, 203e-1, … 203e-7) and wherein at least two ofthe multiple single-column crossbar sub-arrays (203d-1, 203d-2, 203e-1, … 203e-7) are operatively connected via current-to-voltage converters.

5. The electronic calculation circuit (203, 430) according to claim 4,wherein the multiple single-column crossbar sub-arrays (203d-1, 203d-2) are two.

6. The electronic calculation circuit (203) according to claim 4,wherein at least a further two of the multiple single-column sub-arrays (203d-1, 203d- 2, 203e-1, … 203e-7) are arranged in parallel.

7. The electronic calculation circuit (203) according to claim 6 configured to calculate thereciprocal value of the input value based on two iterations of the Newton-Raphsonmethod and wherein the memristive crossbar array (203e) comprises eight inputs andfurther comprises seven memristive crossbar sub-arrays operatively connected via sixcurrent-to-voltage converters, wherein the seven memristive crossbar sub-arrays comprise eighteen memristors and wherein a first crossbar sub-array (203e-1) is operatively connected to a seventh crossbar sub-array (203e-7) via a first current-to- voltage converter (221), a second crossbar sub-array (203e-2) is operatively connected to a third crossbar sub-array (203e-3) via a second current-to-voltage converter (222), the third crossbar sub-array (203e-3) is operatively connected to a fourth crossbar sub-array (203e-4) and a fifth crossbar sub-array (203e-5) via a thirdcurrent-to-voltage converter (223) , the fourth crossbar sub-array (203e-4) is operatively connected to the seventh crossbar sub-array (203e-7) via a fourth current- to-voltage converter (224), the fifth crossbar sub-array (203e-5) is operatively connected to a sixth crossbar sub-array (203e-6) via a fifth current-to-voltage converter (225) and the sixth crossbar sub-array (203e-6) is operatively connected to the seventh crossbar sub-array (203e-7) via a sixth current-to-voltage converter (226).

8. An electronic device (200, 400) for performing a mathematical operation on one ormore input values to calculate an output value, the electronic device (200, 400) comprising: a first electronic calculation circuit (203f, 301, 420) according to any of the claims 1-7 configured to perform a first mathematical operation on a first input value based on the one or more input values to calculate a first output value by calculatingthe first output value as a reciprocal of the first input value, or calculating the firstoutput value as a square root of the first input value, wherein the first electronic calculation circuit (203f, 301, 420) comprises a first memristive crossbar array (203b, 203d, 203e); anda second electronic calculation circuit (203g, 302, 430) comprising a second memristive crossbar array (430-1), wherein the second electronic calculation circuit (203g, 302, 430) is configured to perform a second mathematical operation on a second input value based on the one or more input values to calculate a second output value; wherein the output value is based on the second output value or based on the first output value or both.

9. The electronic device (200, 400) according to claim 8, wherein the second electroniccalculation circuit (203g, 302, 430) is according to any of the claims 1-7.

10. The electronic device (200) according to claim 9, wherein the second electroniccalculation circuit (203g, 302, 430) is a copy of the first electronic calculation circuit(203f, 301, 420) and the second electronic calculation circuit (203g, 302, 430) isconfigured to calculate a same mathematical operation as the first electronic calculation circuit (203f, 301, 420) and the second input value is the same as the firstinput value, and wherein the first electronic device (203f) is configured based on a first approximation of the output and the second electronic calculation circuit (203g, 302, 430) is configured based on a second approximation of the output, and whereinthe electronic device (200) is configured to select one of the first or the second electronic devices , which are operatively arranged in parallel, for performing the mathematical operation.

11. The electronic device (200, 400) according to claim 8 or 9, wherein the first electroniccalculation circuit (203f, 301, 420) is configured to calculate a first part of themathematical operation on the one or more input values and the second electroniccalculation circuit (203g, 302, 430) is configured to calculate a second part of themathematical operation on the one or more input values and wherein the second electronic calculation circuit (203g, 302, 430) differs from the first electronic calculationcircuit (203f, 301, 420).

12. The electronic device (200, 400) according to claim 11, wherein the first electroniccalculation circuit (203f, 301, 420) is configured to calculate the first output value as areciprocal of the first input value; wherein the second electronic calculation circuit (203g, 302, 430) is configured to calculate the second output value as a square root ofthe second input value.

13. The electronic device (200, 400) according to any of the claims 8-12, wherein themathematical operation is one of: division, mean square, mean squared error, root mean square, weighted average, arithmetic mean, harmonic mean, vector norm, Frobenius norm of a matrix, or Euclidian distance.

14. A network node (601) of a wireless communications network (170), the network node(601) comprising the electronic calculation circuit (203, 430) according to any of the claims 1-7 or the electronic device (200, 400) according to any of the claims 8-13.

15. A wireless communications device (602) comprising the electronic calculation circuit(203, 430) according to any of the claims 1-7 or the electronic device (200, 400)according to any of the claims 8-13.

16. A method, performed by an electronic device (200, 400), for performing amathematical operation with an electronic calculation circuit (203f, 301, 420) on an input value to calculate an output value by calculating the output value as a reciprocalof the input value, or calculating the output value as a square root of the input value,the electronic calculation circuit (203f, 301, 420) comprising a first memristivecrossbar array (203b, 203e, 320, 330) comprising at least three memristors (211b,212b, 213b) operatively arranged in series and at least two inputs operatively connected to two of the at least three memristors (211b, 212b, 213b), the methodcomprises: configuring (500) inputs of at least two of the at least three memristors (211b, 212b, 213b); configuring (501) values represented by the at least three memristors (211b, 212b, 213b); and applying (502) the inputs to the at least three memristors (211b, 212b, 213b)to calculate the output value.

17. The method according to claim 16, configuring (500) inputs and configuring (501)values represented by the at least three memristors (211b, 212b, 213b) based on a Newton-Raphson method for performing the mathematical operation on the inputvalue.

18. The method according to claim 16 or 17, wherein at least one memristor of the at leastthree memristors (211b, 212b, 213b) is configured with a static value.

19. The method according to claim 18, wherein the static value is any of 0,5, 1, or 2.

20. The method according to any of the claims 16-19, wherein a value of at least oneinput to the crossbar array equals the input value.

21. The method according to any of the claims 16-20, wherein a value represented by atleast one memristor of the crossbar array equals the input value.

22. The method according to any of the claims 16-21, wherein a value of at least onememristor of the crossbar array equals an approximation of the output value.

23. The method according to any of the claims 15-22, wherein a value represented by atleast one memristor of the crossbar array equals a square of an approximation of the output value.

24. The method according to claim 22 or 23, wherein the approximation of the outputvalue is an intermediate output value based on the input value.

25. The method according to any of the claims 16 to 24, wherein the mathematicaloperation comprises a first mathematical operation on a first input value based on theinput value to calculate a first output value and a second mathematical operation on a second input value based on the input value to calculate a second output value.

26. The method according to claim 24, wherein the second input value comprises the firstoutput value.

27. The method according to claim 25 or 26, wherein the first mathematical operationcalculates the first output value as a reciprocal of the first input value and the second mathematical operation calculates the second output value as a square root of the second input value.

28. The method according to any of claims 16-27, wherein the mathematical operation isone of: division, mean square, mean squared error, root mean square, weighted average, arithmetic mean, harmonic mean, vector norm, Frobenius norm of a matrix, or Euclidian distance.

29. The method according to any of claims 16-28, wherein the method is iterative.

30. A computer program (1703, 1803), comprising computer readable code units whichwhen executed on a computer causes the computer to perform the method according to any one of claims 16-29.

31. A carrier (1705, 1805) comprising the computer program according to the precedingclaim, wherein the carrier (1705, 1805) is one of an electronic signal, an optical signal, a radio signal and a computer readable medium.

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