Semiconductor device and display device

Abstract

The present invention provides a high-aperture-ratio display device. The present invention provides a high-definition display device. The display device includes a first to a third conductive layers, a first semiconductor layer, and a first and a second insulating layers. The first insulating layer has an island-like shape and includes a first surface located on the first conductive layer. The first surface is a part of a side surface of the first insulating layer, and includes two or more regions having different normal directions. The second conductive layer is located on the first insulation layer. The first semiconductor layer includes a first portion in contact with an upper surface of the first conductive layer, a second portion in contact with an upper surface of the second conductive layer, and a third portion in contact with a first surface of the first insulating layer. The second insulating layer covers the third portion. The third conductive layer covers the third portion via the second insulating layer.

Description

Semiconductor device and display device

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a transistor, and a display device including a transistor.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] One type of display device is a liquid crystal display device that uses liquid crystal elements as display elements. For example, active matrix liquid crystal display devices, in which pixel electrodes are arranged in a matrix and switching elements are connected to each pixel electrode, are used in a variety of devices such as smartphones, tablet terminals, monitors, televisions, and digital signage.

[0004] There are two types of LCD devices known, broadly classified as transmissive and reflective. The larger the effective light-emitting area ratio (also called aperture ratio) of a pixel in an LCD device, the brighter the display can be, which also leads to a reduction in power consumption, and therefore there is a demand for improving the aperture ratio.

[0005] For example, an active matrix liquid crystal display device is known that uses transistors having a metal oxide channel region as switching elements connected to each pixel electrode. Patent Document 1 discloses a liquid crystal display device that employs transistors using a metal oxide channel region to increase the aperture ratio.

[0006] JP 2018-189938 A

[0007] Another object of one embodiment of the present invention is to provide a transistor that can be miniaturized, a transistor with favorable electrical characteristics, a transistor with a short channel length, or a transistor with a small occupation area.

[0008] An object of one embodiment of the present invention is to provide a liquid crystal display device with a high aperture ratio, a high-resolution liquid crystal display device, a liquid crystal display device with low power consumption, a liquid crystal display device that can be driven at high speed, or a display device with high display quality.

[0009] An object of one embodiment of the present invention is to provide a transistor, a display device, an electronic device, or the like having a novel structure. Another object of one embodiment of the present invention is to provide a highly reliable transistor, a display device, an electronic device, or the like. An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0011] One embodiment of the present invention is a semiconductor device including a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer, a first insulating layer, and a second insulating layer. The first insulating layer has an island shape and a first surface located on the first conductive layer. The first surface is a part of a side surface of the first insulating layer and has two or more regions whose normal directions are different from each other. The second conductive layer is located on the first insulating layer. The first semiconductor layer has a first portion in contact with a top surface of the first conductive layer, a second portion in contact with a top surface of the second conductive layer, and a third portion in contact with the first surface of the first insulating layer. The second insulating layer covers the third portion of the first semiconductor layer. The third conductive layer covers the third portion of the first semiconductor layer via the second insulating layer.

[0012] In the above, the first surface of the first insulating layer preferably has two planes that intersect at right angles on the first conductive layer, or the first surface of the first insulating layer preferably has a curved shape on the first conductive layer.

[0013] In the above, it is preferable that the second insulating layer has an edge aligned with the third conductive layer.

[0014] In the above, it is preferable that the semiconductor device further includes a second semiconductor layer. Furthermore, it is preferable that the first insulating layer has a second surface that is another part of the side surface and is located on the first conductive layer. In this case, it is preferable that the second semiconductor layer has a fourth portion in contact with the second surface, and the second insulating layer covers the fourth portion of the second semiconductor layer. In this case, it is preferable that the second semiconductor layer has a fifth portion in contact with the top surface of the first conductive layer and a sixth portion in contact with the top surface of the second conductive layer.

[0015] In the above, it is preferable that the semiconductor device further includes a second semiconductor layer and a fourth conductive layer. Furthermore, it is preferable that the first insulating layer has a third surface that is another part of the side surface and is located on the fourth conductive layer. In this case, it is preferable that the second semiconductor layer has a fifth portion in contact with the upper surface of the fourth conductive layer, a sixth portion in contact with the upper surface of the second conductive layer, and a seventh portion in contact with the third surface. It is also preferable that the second insulating layer covers the seventh portion of the second semiconductor layer.

[0016] Another embodiment of the present invention is a display device including any one of the above semiconductor devices and a liquid crystal element. The liquid crystal element includes a part of the second conductive layer, liquid crystal, and a fifth conductive layer. The liquid crystal is located over the second conductive layer. The second conductive layer functions as a pixel electrode. The fifth conductive layer functions as a common electrode.

[0017] In the above, it is preferable to have a third insulating layer covering the second conductive layer, the third conductive layer, and the second insulating layer.

[0018] In the above, the second conductive layer preferably has a region that does not overlap with the first insulating layer, and the region preferably functions as a pixel electrode.

[0019] Another embodiment of the present invention is a display device including a first conductive layer, a third conductive layer, a first semiconductor layer, a first insulating layer, a second insulating layer, and a liquid crystal element. The first insulating layer has an island shape and a first surface that is part of a side surface and is located on the first conductive layer. The first semiconductor layer has a first portion in contact with a top surface of the first conductive layer, a third portion in contact with the first surface of the first insulating layer, and an eighth portion located on the first insulating layer. The second insulating layer covers the third portion of the first semiconductor layer. The third conductive layer covers the third portion of the first semiconductor layer via the second insulating layer. The liquid crystal element includes a part of the first semiconductor layer, liquid crystal, and a fifth conductive layer. The liquid crystal is located on the first semiconductor layer. A part of the first semiconductor layer functions as a pixel electrode. The fifth conductive layer functions as a common electrode.

[0020] In the above, the first semiconductor layer preferably has a ninth portion that does not overlap with the first insulating layer, and the ninth portion preferably functions as a pixel electrode.

[0021] According to one embodiment of the present invention, a transistor that can be miniaturized, a transistor with favorable electrical characteristics, a transistor with a short channel length, or a transistor with a small occupation area can be provided.

[0022] According to one embodiment of the present invention, a liquid crystal display device with a high aperture ratio, a high-resolution liquid crystal display device with low power consumption, a liquid crystal display device capable of high-speed operation, or a display device with high display quality can be provided.

[0023] According to one aspect of the present invention, it is possible to provide a transistor, a display device, an electronic device, etc. having a novel configuration. According to one aspect of the present invention, it is possible to provide a highly reliable transistor, a display device, an electronic device, etc. According to one aspect of the present invention, it is possible to at least alleviate at least one of the problems of the prior art.

[0024] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0025] FIGS. 1A to 1C are structural examples of semiconductor devices. FIGS. 2A to 2C are structural examples of semiconductor devices. FIGS. 3A and 3B are structural examples of semiconductor devices. FIGS. 4A to 4E are structural examples of semiconductor devices. FIGS. 5A to 5D2 are structural examples of semiconductor devices. FIGS. 6A to 6E are structural examples of semiconductor devices. FIGS. 7A to 7D are structural examples of semiconductor devices. FIGS. 8A to 8D are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 9A to 9C are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 10A and 10B are structural examples of display devices. FIGS. 11A and 11B are structural examples of display devices. FIGS. 12A and 12B are structural examples of display devices. FIGS. 13A and 13B are structural examples of display devices. FIGS. 14A and 14B are structural examples of display devices. FIGS. 15A and 15B are structural examples of display devices. FIGS. 16A and 16B are structural examples of display devices. Fig. 17A and Fig. 17B are configuration examples of a display device. Fig. 18A to Fig. 18C are configuration examples of a display device. Fig. 19A, Fig. 19C, and Fig. 19D are circuit diagrams of display devices. Fig. 19B is a timing chart. Fig. 20 is a block diagram of a touch panel module. Fig. 21A to Fig. 21C are configuration examples of a touch panel module. Fig. 22A to Fig. 22F are configuration examples of an electronic device. Fig. 23A to Fig. 23G are configuration examples of an electronic device.

[0026] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0027] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0028] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0029] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0030] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0031] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0032] Furthermore, in this specification, "electrically connected" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0033] In this specification, when two nodes are connected via an insulator such as a dielectric of a capacitive element, a gate insulating film of a transistor, or an interlayer insulating film, this is not considered to be an "electrical connection."

[0034] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0035] In this specification, the phrase "top surface shapes generally match" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0036] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0037] Embodiment 1 In this embodiment, a structural example of a semiconductor device according to one embodiment of the present invention will be described. Hereinafter, a structural example of a transistor will be described as an example of a semiconductor device.

[0038] A transistor according to one embodiment of the present invention includes a semiconductor layer, a gate insulating layer, a gate electrode, a first electrode, and a second electrode. The first electrode functions as one of a source electrode and a drain electrode, and the second electrode functions as the other.

[0039] The transistor is provided in a region including an end portion of an insulating layer provided in an island shape. More specifically, an insulating layer is provided to cover a portion of the first electrode, and a second electrode is provided on the insulating layer. The semiconductor layer has a portion in contact with a top surface of the first electrode, a portion in contact with a top surface of the second electrode, and a portion provided along a side surface of the insulating layer. A gate insulating layer is provided to cover the portion of the semiconductor layer provided along the side surface of the insulating layer, and a gate electrode is provided to cover the gate insulating layer.

[0040] The first electrode and the second electrode may be electrodes different from the semiconductor layer, or a part of the semiconductor layer may function as the first electrode or the second electrode.

[0041] In a transistor having the above structure, the source electrode and the drain electrode are located at different heights, and therefore, a current flows in the semiconductor layer in the height direction. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, or the like.

[0042] In the above-mentioned transistor, the source electrode, the semiconductor layer, and the drain electrode can be provided in a stacked manner, and therefore the occupied area can be significantly reduced compared to a so-called planar type transistor (which can also be called a lateral transistor, LFET (Lateral FET)), in which the semiconductor layer is arranged on a plane.

[0043] Furthermore, the semiconductor layer of the transistor is preferably provided over two or more regions of the surface of the insulating layer functioning as a spacer, the normal directions of which are different from each other. Specifically, the semiconductor layer may be provided over two or more adjacent planes or along a curved portion. By providing the semiconductor layer not only on one plane of the insulating layer but also on two or more planes or along a curved surface, the channel width can be increased while suppressing an increase in the area occupied by the transistor. In other words, a transistor with a large on-state current and a small size can be realized.

[0044] Furthermore, since the channel length of a transistor can be precisely controlled by the thickness of the insulating layer, the variation in channel length can be significantly reduced compared to planar transistors. Furthermore, by thinning the insulating layer, transistors with extremely short channel lengths can be fabricated. For example, transistors with channel lengths of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more, 7 nm or more, or 10 nm or more, can be fabricated. Therefore, transistors with extremely short channel lengths that could not be achieved using conventional exposure equipment for mass production of flat panel displays (e.g., minimum line widths of approximately 2 μm or 1.5 μm) can be realized. Furthermore, transistors with channel lengths of less than 10 nm can be fabricated without using the extremely expensive exposure equipment used in cutting-edge LSI technology.

[0045] As the semiconductor layer, a metal oxide (also referred to as an oxide semiconductor) film having semiconductor properties is preferably used because it can achieve both high performance and high productivity. In particular, a crystalline oxide semiconductor film is more preferable because it can provide high reliability.

[0046] A more specific example will be described below with reference to the drawings.

[0047] [Configuration Example] Fig. 1A shows a schematic top view of a semiconductor device having a transistor 10. Fig. 1B shows a schematic cross-sectional view corresponding to the cutting line A1-A2 in Fig. 1A, and Fig. 1C shows a schematic cross-sectional view corresponding to the cutting line B1-B2. Fig. 2A shows a schematic perspective view of the transistor 10. Note that in the schematic top view, some components (e.g., insulating layers) are not explicitly shown to make the view easier to see.

[0048] The transistor 10 is provided over an insulating layer 11 provided over a substrate (not shown). The transistor 10 includes a semiconductor layer 21, an insulating layer 22 functioning as a gate insulating layer, a conductive layer 23 functioning as a gate electrode, a conductive layer 24 functioning as one of a source electrode and a drain electrode, and a conductive layer 25 functioning as the other electrode. Note that the insulating layer 11 does not have to be provided if it is not necessary.

[0049] A conductive layer 24 is provided on the insulating layer 11, and an insulating layer 41 is provided covering a portion of the conductive layer 24. The insulating layer 41 functions as a spacer and has an island-like shape. The conductive layer 25 is provided on the insulating layer 41. The semiconductor layer 21 has a portion in contact with the top surface of the conductive layer 24, a portion in contact with the top surface of the conductive layer 25, a portion in contact with the side surface of the conductive layer 25, and a portion provided along the side surface of the insulating layer 41. Here, an example is shown in which the semiconductor layer 21 is provided in contact with the side surface of the insulating layer 41. The insulating layer 22 is provided covering at least the portion of the semiconductor layer 21 provided along the side surface of the insulating layer 41. The insulating layer 22 is provided covering not only the semiconductor layer 21 but also a portion of the top surface of the conductive layer 25 and a portion of the side surface of the insulating layer 41 where the semiconductor layer 21 is not provided. The conductive layer 23 is provided covering at least the portion of the semiconductor layer 21 provided along the side surface of the insulating layer 41 via the insulating layer 22. Here, an example is shown in which the conductive layer 23 and the insulating layer 22 are formed so that their top surface shapes are roughly the same.

[0050] Here, the conductive layer 25 and the insulating layer 41 are formed to have substantially the same top surface shape. For example, the conductive layer 25 and the insulating layer 41 can be formed by processing them using the same resist mask, which can simplify the manufacturing process of the transistor 10.

[0051] The insulating layer 41 functions as an interlayer insulating film or a spacer that insulates the conductive layer 24 from the conductive layer 25. Here, an example is shown in which the side surface of the insulating layer 41 is approximately perpendicular to the surface on which the insulating layer 41 is to be formed (the upper surface of the insulating layer 11 or the conductive layer 24), but this is not limiting. For example, the side surface of the insulating layer 41 may have a tapered shape. For example, the angle between the side surface of the insulating layer 41 and the surface on which the insulating layer 41 is to be formed can be 45 degrees or more and 90 degrees or less, preferably 60 degrees or more and 90 degrees or less, and more preferably 75 degrees or more and 90 degrees or less. Note that while the angle may be greater than 90 degrees, an angle of 90 degrees or less is preferable because it improves the coverage of the semiconductor layer 21, the insulating layer 22, and the like. When the angle between the side surface of the insulating layer 41 and the surface on which the insulating layer 41 is to be formed is 90 degrees, the thickness of the insulating layer 41 matches the channel length of the transistor 10.

[0052] Although various semiconductor materials can be used for the semiconductor layer 21, it is particularly preferable to use an oxide semiconductor containing a metal oxide. By using an oxide semiconductor formed under appropriate conditions, a transistor having both a high on-state current and an extremely low off-state current can be realized at low cost. Unless otherwise specified, a preferred configuration example in which an oxide semiconductor is used for the semiconductor layer 21 will be described below.

[0053] The conductive layer 24 and the conductive layer 25 are configured so that the semiconductor layer 21 contacts the upper surface of each of them. Therefore, when an oxide semiconductor is used for the semiconductor layer 21, the vicinity of the surface of the conductive layer 24 and the conductive layer 25 may be oxidized due to the influence of heat during or after the film formation process of the semiconductor film that becomes the semiconductor layer 21, and an insulating oxide film may be formed between the conductive layer 24 and the conductive layer 25 and the semiconductor layer 21, which may increase the contact resistance.

[0054] Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductive material for at least the uppermost portions of the conductive layers 24 and 25. In particular, it is preferable to use an oxide conductor that contains a conductive oxide. This can prevent an increase in contact resistance due to oxidation of the surfaces of the conductive layers 24 and 25.

[0055] A part of the conductive layer 24 can be used as one of the source wiring and the drain wiring. A part of the conductive layer 25 can be used as the other of the source wiring and the drain wiring. When one or both of the conductive layer 24 and the conductive layer 25 are used as wirings in this way, it is preferable that the conductive layer 24 and the conductive layer 25 have low electrical resistance. Therefore, it is preferable to use a material having higher conductivity than an oxide conductor, such as a metal, an alloy, or a nitride thereof. In particular, it is preferable that one or both of the conductive layer 24 and the conductive layer 25 have a stacked structure including a layer of the highly conductive material, and that the above-mentioned oxide conductor is used at least in the uppermost portion.

[0056] FIG. 2B shows a perspective view in which the conductive layer 23 and the insulating layer 22 are omitted from the perspective view shown in FIG. 2A . As shown in FIG. 2B , the semiconductor layer 21 is provided so as to cover the entire corners of the insulating layer 41 and the conductive layer 25. The portion of the semiconductor layer 21 provided along the side surface of the insulating layer 41 functions as a channel formation region of the transistor 10. The width of the portion of the semiconductor layer 21 provided along the insulating layer 41 in a direction perpendicular to the height direction is the channel width of the transistor 10. In FIG. 2B , the channel width direction is indicated by a dashed arrow. Therefore, in this configuration example, by utilizing the corners of the insulating layer 41, the occupied area of ​​the transistor 10 with the same channel width can be reduced compared to when the semiconductor layer 21 is provided only on the flat surface of the side surface of the insulating layer 41.

[0057] 2C shows a perspective view in which the semiconductor layer 21 is omitted from the perspective view shown in FIG. 2B. Furthermore, a hatched pattern is added to a region R of the side surface of the insulating layer 41 that contacts the semiconductor layer 21. The region of the conductive layer 25 that contacts the semiconductor layer 21 is also shown by a dashed line.

[0058] The semiconductor layer 21 is preferably provided across two or more regions of the side surface of the insulating layer 41 that have different normal directions. FIG. 2C illustrates an example in which the side surface of the insulating layer 41 has two adjacent planes. FIG. 2C illustrates two planes in the region R, with point P included in one plane and point Q included in the other plane. Furthermore, the normal vector n1 at point P and the normal vector n2 at point Q indicate different directions. When the two planes are perpendicular to each other, the two normal vectors (normal vector n1 and normal vector n2) are also perpendicular to each other. For example, the corner of the insulating layer 41 refers to the boundary between the plane including point P and the plane including point Q. FIG. 2C illustrates an example in which the corner of the insulating layer 41 is perpendicular in a planar view (i.e., the plane including point P and the plane including point Q are perpendicular to each other). As will be described later, the corner of the insulating layer 41 may be a curved surface.

[0059] The above-described structure allows a transistor to pass a large current and be miniaturized. By applying such a transistor to a pixel circuit of a display device, a display device with extremely high resolution can be realized. Furthermore, since the area occupied by the transistor applied to the pixel can be reduced, a display device with a high aperture ratio can be realized.

[0060] Fig. 3A shows a modification of the above. While the above example shows an example in which the insulating layer 22 and the conductive layer 23 are processed so that their top surface shapes are roughly the same, Fig. 3 shows an example in which such processing is not performed. The insulating layer 22 is provided so as to cover the conductive layer 25 in a region where the conductive layer 23 is not provided. Although not shown here, the insulating layer 22 may also be provided so as to cover the insulating layer 41, the conductive layer 24, the insulating layer 11, and the like in a region where the conductive layer 23 is not provided.

[0061] In the example shown in FIG. 3B, the insulating layer 41 has a laminated structure in which insulating layers 41a, 41b, and 41c are laminated in this order from the insulating layer 11 side.

[0062] The semiconductor layer 21 is provided in contact with a side surface of the insulating layer 41b. It is preferable to use an oxide insulating film for the insulating layer 41b. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated. Furthermore, it is preferable to provide an insulating layer 41c having oxygen barrier properties (oxygen barrier properties) on the insulating layer 41b. For example, it is preferable to use a film through which oxygen is less likely to diffuse (having a smaller oxygen diffusion coefficient) than the insulating layer 41b as the insulating layer 41c. This can prevent most of the oxygen contained in the insulating layer 41b from diffusing to the outside, which can prevent a shortage of oxygen supplied to the semiconductor layer 21. Furthermore, it is preferable to have a structure in which the insulating layer 41b is sandwiched between the insulating layers 41a and 41c having oxygen barrier properties. This can confine the oxygen contained in the insulating layer 41b in a region surrounded by the insulating layers 41a, 41c, and the semiconductor layer 21. This can prevent oxygen from being released and reduced during the process, thereby more efficiently supplying oxygen to the semiconductor layer 21.

[0063] Typical examples of the oxide insulating film that releases oxygen when heated include silicon oxide and silicon oxynitride.

[0064] As the insulating film having an oxygen barrier property, it is preferable to use an oxide, nitride, or oxynitride such as silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium aluminate, yttrium oxide, yttrium oxynitride, gallium oxide, or gallium-zinc oxide. In particular, silicon nitride and aluminum oxide are preferable because they can be used as a film that exhibits high oxygen barrier property at low cost.

[0065] The portion of the semiconductor layer 21 in contact with the insulating layer 41b is a region in which oxygen vacancies are reduced and can be said to be an i-type region. On the other hand, the portion not in contact with the insulating layer 41b is preferably an n-type region containing many carriers. For example, the portion of the semiconductor layer 21 in contact with the insulating layer 41b can be called a channel formation region, and the region outside that can be called a low-resistance region (also called a source region or a drain region).

[0066] Next, the shape of each component of the transistor 10 in a plan view and the positional relationship between the components will be described.

[0067] 4A shows a schematic top view of a transistor described below. The conductive layer 23 and the insulating layer 22 are omitted here to clearly show the positional relationship between the conductive layer 24, the conductive layer 25, the insulating layer 41, and the semiconductor layer 21. In addition, in FIG. 4A, a region 21AC that becomes a channel formation region is shown surrounded by a dashed line. More specifically, the region of the end of the insulating layer 41 and the conductive layer 25 that overlaps with the semiconductor layer 21 is shown as the region 21AC.

[0068] In the top view schematic diagrams shown below, including FIG. 4A, the insulating layer 22 and the conductive layer 23 need only cover at least the region 21AC that will become the channel formation region of the semiconductor layer 21, and the other regions can have any shape.

[0069] 4A and the other schematic top view diagrams shown below show an example in which the top surface shapes of the insulating layer 41 and the conductive layer 25 roughly match, but this is not limiting. The insulating layer 41 may have a region that is not covered by the conductive layer 25, or the conductive layer 25 may have a portion located outside the contour of the insulating layer 41.

[0070] Furthermore, in the top view schematic diagrams shown below, including FIG. 4A, only the hatching pattern of conductive layer 24 is shown differently from that shown in the cross-sectional schematic diagrams shown in FIG. 1B and the like, in order to make it easier to distinguish between conductive layer 24 and conductive layer 25.

[0071] 1A and other drawings show an example in which the semiconductor layer 21 is provided to cover the entire top surface of the conductive layer 24, but this is not limiting. The top view of FIG. 4A shows an example in which the semiconductor layer 21 covers a portion of the conductive layer 24. The conductive layer 24 has a region that is not covered by the semiconductor layer 21.

[0072] 4B shows an example in which the semiconductor layer 21 is located inside the end of the conductive layer 24. In the region where the conductive layer 24 and the conductive layer 25 overlap with each other via the insulating layer 41, there is a portion that does not overlap with the semiconductor layer 21. Furthermore, by varying only the shape of the semiconductor layer 21 in this way, transistors with different channel widths can be fabricated.

[0073] 4C shows an example in which semiconductor layer 21 has a region that overlaps neither conductive layer 24 nor conductive layer 25. As a result, in addition to the entire region of the side surface of insulating layer 41 that overlaps conductive layer 24, a region that does not overlap conductive layer 24 and overlaps semiconductor layer 21 can be used as region 21AC, thereby realizing a transistor with a large channel width.

[0074] 4D shows an example in which the shape of the semiconductor layer 21 is rectangular in a plan view. In this case, the areas of the two planes of the side surfaces of the insulating layer 41 that overlap with the semiconductor layer 21 are different. In this way, the shape of the semiconductor layer 21 is not limited to a square, and it can also be a rectangle with a large aspect ratio. By varying the shape of the semiconductor layer 21, transistors of various shapes can be fabricated, thereby increasing the degree of freedom in design.

[0075] 4E shows an example in which the corners of each component are curved rather than angular. In this case, semiconductor layer 21 is provided along the curved portion of the side surface of insulating layer 41, so region 21AC also has a portion that is arc-shaped in plan view. By making the side surface of insulating layer 41 on which region 21AC is provided curved, the gate electric field applied to semiconductor layer 21 is averaged, thereby achieving a highly reliable transistor.

[0076] In the above example, the semiconductor layer 21 is provided in a region including one corner of the side surface of the insulating layer 41, but a different example will be described below.

[0077] FIG. 5A shows an example in which the semiconductor layer 21 is provided to cover two corners of the insulating layer 41. Region 21AC has a U-shaped (square bracket) shape. FIG. 5B shows an example in which the semiconductor layer 21 is provided to cover three convex surfaces and one concave surface of the side surfaces of the insulating layer 41. The larger the area of ​​the side surfaces of the insulating layer 41 covered by the semiconductor layer 21, the larger the channel width of the transistor can be. Furthermore, the greater the number of corners of the insulating layer 41 in the region covered by the semiconductor layer 21, the larger the area of ​​the side surfaces of the insulating layer 41 covered by the semiconductor layer 21 can be. The shape of the region of the insulating layer 41 covered by the semiconductor layer 21 can be various shapes. For example, it can be a square, rectangle, circle, ellipse, or rectangle with rounded corners. It can also be a regular polygon, such as an equilateral triangle or a regular pentagon, or a polygon other than a regular polygon. Furthermore, the channel width can be increased by using a concave polygon, such as a star-shaped polygon, which is a polygon with at least one interior angle exceeding 180 degrees. Other shapes include polygons with rounded corners and curves that combine straight lines and curves.

[0078] 5C1 shows an example in which the insulating layer 41 and the conductive layer 25 have a shape that combines a circular portion and a rectangular portion in a plan view. Also, in FIG. 5C2, only the outline of the semiconductor layer 21 is shown by a dashed line. The semiconductor layer 21 is provided to cover the circular portion and a pair of straight portions of the side surface of the insulating layer 41 in a plan view. Therefore, the region 21AC has an arc-shaped portion and a pair of straight portions. By using such a shape, a transistor with a large channel width can be realized while occupying a small area.

[0079] 5D1 and 5D2 show examples in which the insulating layer 41 and the conductive layer 25 have annular portions in a planar view. In FIG. 5D2, only the outline of the semiconductor layer 21 is shown by a dashed line. As shown in FIG. 5D2, a circular opening is provided in the circular portion of the insulating layer 41 and the conductive layer 25, reaching the conductive layer 24. The semiconductor layer 21 is provided so as to cover the side surface of the insulating layer 41 located at the opening. With this configuration, a channel formation region can be provided not only on the outer outline of the insulating layer 41 but also on the side surface of the opening, thereby realizing a transistor with an even larger channel width than the example shown in FIG. 5C1.

[0080] Although the above describes an example of a transistor using one semiconductor layer, an example of a transistor using a plurality of semiconductor layers will be described below.

[0081] 6A shows a configuration including two semiconductor layers 21a and 21b. The semiconductor layers 21a and 21b are provided to cover two corners of the insulating layer 41 that overlap with the conductive layer 24. This forms two transistors: a transistor 10a having the semiconductor layer 21a and a transistor 10b having the semiconductor layer 21b. The transistors 10a and 10b share a source electrode and a drain electrode. The gate electrode may be shared by the transistors 10a and 10b, or different gate electrodes may be provided independently for each transistor.

[0082] Fig. 6D shows a circuit diagram corresponding to Fig. 6A. Here, an example is shown in which the transistors 10a and 10b share a gate electrode. In this way, the configuration shown in Fig. 6A has two transistors connected in parallel.

[0083] FIG. 6B shows a configuration including three semiconductor layers 21a, 21b, and 21c. Furthermore, the insulating layer 41 and the conductive layer 25 have two protruding portions (portions 41p and 41q) in a planar view. The portions 41p and 41q each have an area overlapping the conductive layer 24. The semiconductor layers 21a and 21b are provided to cover two corners of the portion 41p, respectively, and the semiconductor layers 21b and 21c are provided to cover two corners of the portion 41q, respectively. This results in transistors 10a, 10b, 10c, and 10d, each of which includes one of the semiconductor layers 21a, 21b, or 21c. The transistors 10b and 10c share the semiconductor layer 21b. Each of the four transistors shares a source electrode and a drain electrode. The gate electrode may be common to two or more of the four transistors, or different gate electrodes may be provided independently for each transistor.

[0084] Fig. 6E shows a circuit diagram corresponding to Fig. 6B. Here, an example is shown in which four transistors have a common gate electrode. As shown in Fig. 6E, the configuration shown in Fig. 6B has four transistors connected in parallel.

[0085] Fig. 6C is a modified example of Fig. 6B. Fig. 6C shows a configuration having four semiconductor layers (semiconductor layers 21a, 21b, 21c, and 21d), with transistors 10a, 10b, 10c, and 10d each having one of the semiconductor layers. Fig. 6C also shows an example in which conductive layer 25 and insulating layer 41 do not have protruding portions (portions 41p and 41q).

[0086] The conductive layer 25 and the insulating layer 41 have regions that overlap with the conductive layer 24. Of the four semiconductor layers, the semiconductor layers 21a and 21d located at the ends are provided so as to cover one of the two corners of the insulating layer 41 that overlap with the conductive layer 24. The semiconductor layers 21b and 21c are provided so as to cover the side surfaces of the insulating layer 41 that overlap with the conductive layer 24. The side surfaces of the insulating layer 41 that are covered by the semiconductor layers 21b and 21c are approximately planar.

[0087] Although the semiconductor layers 21a to 21d have the same shape and the channel widths of the transistors 10a and 10d are larger than those of the transistors 10b and 10c in this example, the present invention is not limited to this. The channel widths of the four transistors can also be made approximately the same by adjusting the shapes of the semiconductor layers 21a to 21d.

[0088] While the above example shows a configuration in which a plurality of transistors are connected in parallel, the following example will explain a configuration in which a plurality of transistors are connected in series.

[0089] The configuration shown in FIG. 7A is an example in which, instead of the conductive layer 24, two conductive layers (conductive layers 24a and 24b) and two semiconductor layers (semiconductor layer 21a and semiconductor layer 21b) are located below the insulating layer 41. In FIG. 7A , one corner of the insulating layer 41 and the conductive layer 25 overlaps with the conductive layer 24a and the semiconductor layer 21a, and the other corner overlaps with the conductive layer 24b and the semiconductor layer 21b. This forms a transistor 10a having the semiconductor layer 21a and a transistor 10b having the semiconductor layer 21b. The transistors 10a and 10b share one of the source electrode and the drain electrode, and the other is provided independently. The gate electrode may be provided in common to the transistors 10a and 10b, or different gate electrodes may be provided independently for each transistor.

[0090] 7C and 7D show circuit diagrams corresponding to FIG. 7A. Fig. 7C shows a case where the gate electrode of the two transistors is common, while Fig. 7D shows a case where the gate electrodes are provided independently. As shown in Fig. 7C and 7D, transistor 10a and transistor 10b are connected in series.

[0091] Although FIG. 7A shows an example in which two semiconductor layers, 21a and 21b, are provided, these may be combined into one semiconductor layer.

[0092] Fig. 7B is a modification of Fig. 7A. In Fig. 7B, of the four corners of the insulating layer 41 and the conductive layer 25, two adjacent corners overlap with the semiconductor layer 21a and the conductive layer 24a, and the other two corners overlap with the semiconductor layer 21b and the conductive layer 24b. This configuration makes it possible to reduce the occupied area compared to the example shown in Fig. 7A.

[0093] 7B, the semiconductor layer 21 a and the semiconductor layer 21 b may be integrated into a single semiconductor layer. With this configuration, the distance between the transistors can be made smaller than when two island-shaped semiconductor layers are used, thereby further reducing the occupied area.

[0094] [Regarding Components] <Substrate> The substrate on which a transistor is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides may also be used. Further, there are substrates in which a conductive layer or a semiconductor layer is provided on an insulating substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate. Alternatively, any of these substrates may be provided with elements. The elements provided on the substrate include capacitor elements, resistor elements, switch elements (including transistors), light-emitting elements, memory elements, and the like.

[0095] <Semiconductor Layer> The semiconductor layer 21 preferably contains a metal oxide (oxide semiconductor).

[0096] Examples of metal oxides that can be used for the semiconductor layer 21 include In oxide, Ga oxide, and Zn oxide. The metal oxide preferably contains at least In, Zn, Sn, or Al, and more preferably contains In or Zn.

[0097] The metal oxide preferably contains two or three elements selected from In, element M, and Zn. For example, In-M-Zn oxide, In-Zn oxide, In-M oxide, or M-Zn oxide can be used. The element M is a metal element or a metalloid element with a high bond energy with oxygen, for example, a metal element or a metalloid element with a bond energy with oxygen higher than that of indium. Examples of the element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The metal oxide preferably contains one or more of the above elements, and particularly preferably contains one or more selected from Al, Ga, Y, and Sn. Here, in this specification, the term "metal element" may also include a metalloid element.

[0098] The atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. Increasing the atomic ratio of indium in the metal oxide can increase the on-state current or field-effect mobility of a transistor. For example, the atomic ratio of metal elements in the In-M-Zn oxide may be In:M:Zn ratios of 1:1:1, 1:1:1.2, 2:1:3, 3:1:2, 4:2:3, 4:2:4.1, 5:1:3, and 5:1:6, as well as compositions in the vicinity thereof. Note that the term "composition in the vicinity" refers to a range of ±30% of the desired atomic ratio.

[0099] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed. For example, the atomic ratio of metal elements in the In-M-Zn oxide may have an In:M:Zn ratio of 1:3:2, 1:3:3, or 1:3:4, respectively, as well as compositions close to these.

[0100] The semiconductor layer 21 may be formed from, for example, In oxide, In—Zn oxide, In—Ga oxide, In—Sn oxide, In—Ti oxide, In—W oxide, In—Ga—Al oxide, In—Ga—Sn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, In—Al—Zn oxide, In—Ti—Zn oxide, In-W—Zn oxide, In—Ga—Sn—Zn oxide, In—Ga—Al—Zn oxide, etc. Alternatively, oxides not containing In may be formed from Ga oxide, Zn oxide, Ga—Zn oxide, Ga—Sn oxide, Al—Zn oxide, Al—Sn oxide, etc. Materials that do not contain Zn, such as indium oxide, are preferred because they enhance compatibility with LSI manufacturing processes. On the other hand, materials that contain Zn are preferred because they facilitate high crystallinity.

[0101] Note that the metal oxide may contain a metal element with a relatively large number of atoms instead of or in addition to indium. Since the greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be, the metal oxide containing a metal element with a large number of atoms may be able to increase the field-effect mobility of the transistor. For example, one or more metal elements belonging to the fifth period and the sixth period may be used. Specific examples include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu.

[0102] The metal oxide may also contain one or more nonmetallic elements, such as C, N, P, S, Se, F, Cl, Br, and H, which may enhance the field-effect mobility of the transistor.

[0103] The higher the content of elements that contribute to improving conductivity, such as In, the better the mobility and conductivity. Examples of high-mobility materials include oxide materials with atomic ratios of In:Ga:Zn = 4:3:2, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 4:1, In:Sn:Zn = 40:1:10, In:Sn:Zn = 20:1:10, In:Sn = 95:5, In:Sn = 90:10, and nearby oxide materials. On the other hand, examples of materials with lower mobility than the above-mentioned materials include oxide materials with atomic ratios of In:Ga:Zn of 1:3:2, 1:3:4, 2:2:1, 1:1:1, 1:1:2, and nearby oxide materials.

[0104] The metal oxide can be formed by sputtering or ALD. The sputtering method is preferred because it can reduce the impurity concentration. The ALD method is also preferred because it has excellent coverage. When forming a metal oxide by sputtering, the composition of the metal oxide after film formation may differ from the composition of the target. In particular, the zinc content in the metal oxide after film formation may decrease to about 50% compared to the target.

[0105] In this specification, the content of a metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if a metal oxide contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A, then Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ ) In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide (atomic number ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0106] For example, in the case of a metal oxide containing In, a transistor with a large on-current can be realized by increasing the In content.

[0107] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of threshold voltage fluctuation in a PBTS (Positive Bias Temperature Stress) test can be obtained. Furthermore, when using a metal oxide that contains Ga, it is preferable to make the Ga content lower than the In content. This makes it possible to realize a transistor with high mobility and high reliability.

[0108] On the other hand, by increasing the Ga content, a transistor with high reliability against light can be obtained. That is, a transistor with a small amount of variation in threshold voltage in a Negative Bias Temperature Illumination Stress (NBTIS) test can be obtained. Specifically, a metal oxide in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In has a larger band gap, and the amount of variation in threshold voltage of the transistor in the NBTIS test can be reduced.

[0109] Furthermore, by increasing the zinc content, the metal oxide becomes highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0110] The semiconductor layer 21 may have a stacked structure including two or more metal oxides. The two or more metal oxides included in the semiconductor layer 21 may have the same or substantially the same composition. By using a stacked structure of metal oxides with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. Note that a stacked structure in which two or more metal oxides with different compositions are stacked may also be used. Furthermore, by using the ALD method, it is also possible to form metal oxides whose compositions vary continuously in the thickness direction. This not only broadens the range of design options compared to when a film with a fixed composition is used, but also makes it possible to prevent the generation of interface states and the like between two layers with different compositions, thereby improving electrical properties and reliability.

[0111] When the semiconductor layer 21 has a two-layer structure, it is preferable to use a material with higher mobility (higher conductivity) in the second layer, i.e., the side closer to the gate electrode, than in the first layer. This allows for a transistor that is normally off and has a large on-current. This makes it possible to achieve both low power consumption and high performance. Alternatively, a material with higher mobility than in the second layer may be used in the first layer, i.e., the side in contact with the source electrode and drain electrode. This reduces the contact resistance between the semiconductor layer 21 and the source electrode or drain electrode, thereby reducing parasitic resistance and enabling a transistor with a large on-current.

[0112] Furthermore, when the semiconductor layer 21 has a three-layer structure, it is preferable to use a material for the second layer that has a higher mobility than the first and third layers, thereby realizing a transistor with a high on-current and high reliability.

[0113] When the semiconductor layer 21 has a stacked structure, all layers may be formed by the same deposition method, or different deposition methods may be used in combination. For example, the semiconductor layer 21 having a stacked structure may be formed by combining sputtering and ALD. Here, deposition methods such as sputtering may result in the formation of a mixed layer (also known as mixing) at the interface between the semiconductor layer and the surface on which it is formed. Therefore, by forming the first layer by ALD to suppress mixing and forming the second layer by sputtering to form a highly crystalline film, a transistor with both high reliability and excellent electrical characteristics can be realized. Furthermore, a three-layer structure in which the third layer is formed by ALD may also be formed. Furthermore, it is preferable to perform a heat treatment after forming a stacked film by combining ALD and sputtering. This may cause crystal growth from the layer formed by sputtering toward the layer formed by ALD, resulting in the formation of a highly crystalline semiconductor layer as a whole stacked film.

[0114] Furthermore, when the semiconductor layer 21 has a stacked structure, a high-mobility material may be used on the side in contact with the source electrode and the drain electrode. This reduces the contact resistance between the semiconductor layer 21 and the source electrode or the drain electrode, thereby realizing a transistor with a high on-current. In particular, in the case of a bottom-contact structure (a structure in which a semiconductor layer is provided on a source electrode and a drain electrode), the contact resistance may be relatively high compared to a top-contact structure (a structure in which a source electrode and a drain electrode are provided on a semiconductor layer), so it is preferable to use a high-mobility material on the side in contact with the source electrode and the drain electrode.

[0115] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 21. For example, a metal oxide layer having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 21, the defect level density in the semiconductor layer 21 can be reduced, and a highly reliable semiconductor device can be realized.

[0116] The higher the crystallinity of the metal oxide layer used in the semiconductor layer 21, the more the density of defect states in the semiconductor layer 21 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0117] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0118] A semiconductor device according to one embodiment of the present invention can be applied to, for example, a display device using a light-emitting element as a display element. To increase the emission luminance of a light-emitting element included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Because an OS transistor has a higher withstand voltage between the source and drain than a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, it is possible to increase the amount of current flowing through the light-emitting element and increase the emission luminance of the light-emitting element.

[0119] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor in a pixel circuit, the amount of current flowing through a light-emitting element can be precisely controlled. This allows for a larger number of gray levels in the pixel circuit. Furthermore, even if the electrical characteristics (e.g., resistance) of the light-emitting element fluctuate or vary, a stable current can flow.

[0120] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of the influence of manufacturing variations of light-emitting elements," and the like.

[0121] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0122] The semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors. For example, semiconductors made of simple elements or compound semiconductors can be used. Examples of semiconductors made of simple elements include Si (including single crystal, polycrystalline, microcrystalline, and amorphous) and Ge. Examples of compound semiconductors include GaAs and SiGe. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. These semiconductor materials may contain impurities as dopants.

[0123] Alternatively, the semiconductor layer 21 may be made of a material having a layered crystal structure. A material having a layered crystal structure has high in-plane electrical conductivity. Therefore, by using such a material having a layered crystal structure in the channel formation region, a transistor with a large on-state current can be provided. Examples of such a material include graphene, silicene, and chalcogenides. Examples of chalcogenides include chalcogenides of transition elements such as Mo, W, Hf, and Zr. In this case, examples of chalcogen elements include Group 16 elements such as S, Se, and Te.

[0124] The crystallinity of the semiconductor material used for the semiconductor layer 21 is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0125] <Gate Insulating Layer> The insulating layer 22 functions as a gate insulating layer of a transistor and can also be used as a dielectric layer of a capacitor element. When an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide insulating film for at least the film of the insulating layer 22 that is in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide can be used. Alternatively, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can also be used for the insulating layer 22. Furthermore, the insulating layer 22 may have a stacked structure, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0126] In this specification and the like, an oxynitride refers to a material containing more oxygen than nitrogen, and a nitride oxide refers to a material containing more nitrogen than oxygen.

[0127] Furthermore, the insulating layer 22 is preferably formed by laminating insulating materials made of high-k materials with a high dielectric constant, and preferably by using a laminate structure of a high-k material and a material with a higher dielectric strength than the high-k material. For example, the insulating layer 22 can be formed by laminating an insulating film (also referred to as ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order. Alternatively, the insulating layer 22 can be formed by laminating an insulating film (also referred to as ZAZA) in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in this order. Alternatively, the insulating film can be formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By using a laminate of insulators with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element can be suppressed.

[0128] Furthermore, a material exhibiting ferroelectricity may be used for the insulating layer 22. Examples of the material exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ (X is a real number greater than 0).

[0129] <Conductive Layer> The conductive layer 24 and the conductive layer 25 are in contact with the semiconductor layer 21. When an oxide semiconductor is used as the semiconductor layer 21, if an easily oxidized metal such as aluminum is used in the portion of the conductive layer 24 or the conductive layer 25 in contact with the semiconductor layer 21, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 24 or the conductive layer 25 and the semiconductor layer 21, preventing electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material for at least the portion of the conductive layer 24 and the conductive layer 25 in contact with the semiconductor layer 21.

[0130] It is preferable to use, for example, titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. as the conductive layers 24 and 25. These are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxidized, and are therefore preferable.

[0131] Alternatively, conductive oxides such as indium oxide, zinc oxide, In—Sn oxide, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide, and Ga—Zn oxide can be used. Conductive oxides containing indium are particularly preferred because of their high conductivity. Alternatively, oxide materials such as In—Ga—Zn oxide that can be used for the semiconductor layer 21 can also be used as a conductive layer by increasing the carrier concentration.

[0132] For example, the conductive layer 24 and the conductive layer 25 can be a single-layer structure of the above-mentioned conductive oxide film, a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are stacked in this order, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on a tungsten film, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on the above-mentioned conductive oxide film, or a two-layer structure in which the above-mentioned conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film.

[0133] The conductive layer 23 functions as a gate electrode and may be made of various conductive materials. For example, a metal element selected from Al, Cr, Cu, Ag, Pt, Ta, Ni, Ti, Mo, W, Hf, V, Nb, Mn, Mg, Zr, Be, In, Ru, Ir, Sr, La, or the like, or an alloy containing such a metal element, may be used. Alternatively, nitrides of the above metals or alloys, or oxides of the above metals or alloys, may be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel may be used. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may be used.

[0134] The conductive layer 23 may be made of the nitride or oxide that can be used for the conductive layers 24 and 25 .

[0135] Since the conductive layers 23, 24, and 25 also function as wiring, it is preferable to use a stack of low-resistance conductive materials. For example, the low-resistance conductive material that can be used for the conductive layer 23 described above can also be used for the lower layer of the conductive layers 24 and 25.

[0136] <Insulating Layer> The insulating layer 41b can be used as an interlayer insulating film. For example, it is preferably formed by a film formation method such as a sputtering method or a plasma CVD method. In particular, when a sputtering method is used, hydrogen gas is not used as a film formation gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 10 can be stabilized.

[0137] The insulating layer 41b is preferably an oxide insulating film because it is in contact with the channel formation region of the semiconductor layer 21. In particular, it is preferably an oxide insulating film that releases oxygen when heated. The oxide insulating film that can be used for the gate insulating layer can be used as the insulating layer 41b.

[0138] Furthermore, since the insulating layer 41b functions as an interlayer insulating layer, it is preferable to use a film formation method that allows film formation at a high film formation rate compared to other insulating layers. For example, the insulating layer 41 may be formed using TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC ２ H ５ ) ４ Alternatively, a silicon oxide film formed by plasma CVD using a silicon dioxide film containing SiO 2 may be used. This can improve productivity.

[0139] The insulating layers 41a and 41c are preferably made of a material that is less permeable to oxygen than the insulating layer 41b, i.e., has oxygen barrier properties. The insulating layers 41a and 41c can be made of the insulating films having oxygen barrier properties. In particular, silicon nitride or aluminum oxide is preferably used.

[0140] Alternatively, insulating layers 41 a and 41 c may be made of an insulating material containing the same element (e.g., silicon oxide) as insulating layer 41 b. In this case, an insulating film having a higher density than insulating layer 41 b, e.g., an insulating film having a slower etching rate, may be used.

[0141] The insulating layers 41 a and 41 c are preferably made of films that do not easily diffuse hydrogen. By sandwiching the insulating layer 41 b between the insulating layers 41 a and 41 c, which do not easily diffuse hydrogen, it is possible to prevent external hydrogen from being mixed into the insulating layer 41 b that contacts the semiconductor layer 21.

[0142] In particular, silicon nitride and silicon nitride oxide are suitable for use as the insulating layer 41a and the insulating layer 41c because they release little impurities (for example, water and hydrogen) and are less permeable to oxygen and hydrogen.

[0143] When the insulating layer 41 has a single layer structure, the above-mentioned materials that can be used for the insulating layer 41b or the materials that can be used for the insulating layer 41a or the insulating layer 41b can be applied.

[0144] The insulating layer 11 functions as a base insulating layer or an interlayer insulating layer. The insulating layer 11 may be made of an insulating material that can be used for the insulating layer 41b or the insulating layer 41a and the insulating layer 41c.

[0145] This concludes the description of the components.

[0146] [Manufacturing Method Example] An example of a manufacturing method of a transistor of one embodiment of the present invention will be described below. Here, as an example, the structure shown in FIG.

[0147] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using a sputtering method, a CVD method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD method, etc. CVD methods include a plasma enhanced chemical vapor deposition (PECVD) method and a thermal CVD (TCVD) method. One type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0148] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0149] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0150] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD, which uses heat, and photo-CVD (photo-CVD), which uses light. They can also be further classified into metal CVD (MCVD) and metal organic CVD, depending on the source gas used.

[0151] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, since the thermal CVD method does not use plasma, it is possible to minimize plasma damage to the workpiece. Furthermore, since the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0152] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0153] Unlike sputtering, CVD and ALD are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which have a faster film formation rate.

[0154] In the CVD method, a film of any composition can be formed by adjusting the flow rate ratio of the source gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0155] In the ALD method, a film of any composition can be formed by alternately introducing multiple different precursors. Alternatively, when multiple different precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor. Furthermore, as with the CVD method, a film with a continuously changing composition can be formed.

[0156] Furthermore, when processing the thin film that constitutes the semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0157] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0158] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0159] Dry etching, wet etching, sandblasting, and other methods can be used to etch thin films. Wet etching is primarily suitable for isotropic etching. On the other hand, dry etching can be used for both isotropic and anisotropic etching depending on the etching equipment and etching conditions.

[0160] 8A to 9C are cross-sectional views illustrating steps in a manufacturing method of a semiconductor device, which will be described below. The left side of each of FIGS. 8A to 9C is a cross-sectional view corresponding to A1-A2 in the top view of FIG. 1. The right side of each of FIGS. 8A to 9C is a cross-sectional view corresponding to B1-B2 in the top view of FIG. 1.

[0161] First, an insulating layer 11 is formed on a substrate (not shown).

[0162] The substrate may be a substrate having heat resistance sufficient to withstand at least a subsequent heat treatment. When an insulating substrate is used, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, an organic resin substrate, or the like may be used. Alternatively, a semiconductor substrate such as a single-crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium or gallium nitride, or an SOI substrate may be used.

[0163] An inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used as the insulating layer 11. The insulating layer 11 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. If the surface on which the insulating layer 11 is to be formed is not flat, a planarization process may be performed after the insulating layer 11 is formed so that the upper surface of the insulating layer 11 becomes flat.

[0164] Next, a conductive film is formed on the insulating layer 11, a resist mask is formed on the conductive film, and unnecessary portions of the conductive film are removed by etching to form a conductive layer 24 ( FIG. 8A ). The conductive film that becomes the conductive layer 24 can be formed by a film formation method such as a sputtering method, a CVD method, or an ALD method.

[0165] The conductive film that becomes the conductive layer 24 preferably has a layered structure in which a film containing a highly conductive metal or alloy and a film containing an oxide conductor are stacked thereon.

[0166] Subsequently, insulating layers 41a, 41b, and 41c are formed on the conductive layer 24 and the insulating layer 11 (FIG. 8B). The insulating layers 41a, 41b, and 41c may be formed by appropriate methods such as sputtering, CVD, MBE, PLD, and ALD. Here, it is preferable that the insulating layer 41b be an insulating film having a different composition or constituent elements from the insulating layers 41a and 41c.

[0167] Furthermore, since the thicknesses of insulating layers 41a, 41b, and 41c affect the channel length of the transistor, it is important to prevent variations in the thicknesses of insulating layers 41a, 41b, and 41c.

[0168] Since the insulating layer 41b is a film that will later come into contact with the semiconductor layer 21, it is preferable to use an oxide film that contains a large amount of oxygen to the extent that oxygen is released by heating and that contains a small amount of hydrogen. The insulating layer 41b can be formed by a film formation method such as a PECVD method, a sputtering method, or an ALD method, but is particularly preferably formed by a sputtering method. In particular, by forming the insulating layer 41b using a gas containing oxygen and not using a gas containing hydrogen as a film formation gas, the insulating layer 41b can be formed with an extremely small amount of hydrogen and an excess amount of oxygen. By forming the insulating layer 41b in this manner, oxygen can be supplied from the insulating layer 41b to the channel formation region of the semiconductor layer 21, thereby reducing oxygen vacancies.

[0169] Alternatively, a process for supplying oxygen to the insulating layer 41b may be performed after the insulating layer 41b is formed and before the insulating layer 41c is formed. Examples of a method for supplying oxygen to the insulating layer 41b include heat treatment in an oxygen atmosphere and plasma treatment in an oxygen atmosphere. Alternatively, oxygen may be supplied by forming an oxide film on the insulating layer 41b in an oxygen atmosphere by sputtering. The oxide film may then be removed. Alternatively, oxygen (including oxygen radicals, oxygen atoms, or oxygen ions) may be supplied by ion implantation, ion doping, plasma immersion ion implantation, or the like.

[0170] Subsequently, a conductive film 25f is formed on the insulating layer 41c (FIG. 8C). The conductive film 25f can be formed by a film formation method such as sputtering, CVD, MBE, PLD, or ALD.

[0171] Like the conductive layer 24, the conductive film 25f preferably has a layered structure in which a film containing a highly conductive metal or alloy and a film containing an oxide conductor are stacked thereon.

[0172] Next, unnecessary portions of the conductive film 25f, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a are removed by etching, and these are processed into islands (FIG. 8D), at which point a part of the conductive layer 24 is exposed.

[0173] When processing the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a, the conductive film 25f may be used as a hard mask. At this time, the conductive film 25f is first processed into an island shape using a resist mask. Then, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a can be etched in this order using the conductive film 25f as a mask. The resist mask may be removed after etching the conductive film 25f, during etching of the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a, or after etching is completed.

[0174] Alternatively, the conductive film 25f and the insulating layers 41c, 41b, and 41a may be processed using different resist masks. At this time, after the conductive film 25f, the insulating layers 41c, 41b, and 41a are processed, the conductive film 25f can be etched using different resist masks. Alternatively, after the conductive film 25f is etched, the insulating layers 41c, 41b, and 41a can be etched using different resist masks.

[0175] Subsequently, heat treatment may be performed. The heat treatment may be performed at a temperature of 250° C. to 650° C., preferably 300° C. to 500° C., and more preferably 320° C. to 450° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. By performing the heat treatment as described above, impurities such as water and hydrogen contained in the insulating layer 41 and the like can be reduced before the formation of a semiconductor film that becomes a semiconductor layer. The oxidizing gas may be N ２ O (nitrous oxide or dinitrogen monoxide), NO ２ (nitrogen dioxide), nitrogen oxides such as NO (nitric oxide), or O ２ (oxygen), O ３ A gas containing ozone or the like can be used.

[0176] Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, it is preferable that the amount of moisture contained in the gas used in the heat treatment be 1 ppb (0.001 ppm) or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the insulating layer 41 and the like as much as possible.

[0177] Next, a semiconductor film that will later become the semiconductor layer 21 is formed, and unnecessary portions are removed by etching to form the semiconductor layer 21 (FIG. 9A).

[0178] The semiconductor film is preferably formed by a film formation method with extremely high coverage so as to contact the side surface of the insulating layer 41. Typically, it is preferable to form the film by the ALD method. Note that even when the sputtering method is used, it is possible to form the film with a uniform thickness on the side surface of the insulating layer 41 by reducing the distance between the substrate surface and the sputtering target or by tilting the substrate surface and the surface of the sputtering target relatively.

[0179] Furthermore, during or after the formation of an oxide semiconductor film, a microwave treatment may be performed in an atmosphere containing oxygen to reduce the impurity concentration in the oxide semiconductor film. Examples of impurities include hydrogen and carbon. The microwave treatment may improve the crystallinity of the oxide semiconductor film in some cases. Here, the microwave treatment refers to a treatment using, for example, an apparatus having a power supply that generates high-density plasma using microwaves.

[0180] The semiconductor film is preferably a dense film with as few defects as possible. Furthermore, the semiconductor film is preferably a highly pure film with as little impurities as possible, such as hydrogen and water, as much as possible reduced. In particular, it is preferable to use a crystalline metal oxide film as the semiconductor film.

[0181] Furthermore, when forming a metal oxide film by sputtering, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film, resulting in a highly reliable transistor. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film, resulting in a transistor with a higher on-state current.

[0182] When a metal oxide film is formed by a sputtering method, a higher substrate temperature can result in a denser metal oxide film with higher crystallinity, whereas a lower substrate temperature can result in a lower crystallinity and higher electrical conductivity.

[0183] As a deposition condition for forming a metal oxide film by a sputtering method, the substrate temperature is preferably from room temperature to 250° C., more preferably from room temperature to 200° C., and even more preferably from room temperature to 140° C. For example, a substrate temperature of from room temperature to less than 140° C. is preferred because productivity is increased. Furthermore, by forming a metal oxide film at room temperature or without intentional heating, the crystallinity can be reduced.

[0184] When the ALD method is used to form a metal oxide film, it is preferable to use a film formation method such as a thermal ALD method or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it exhibits high step coverage and allows low-temperature film formation.

[0185] For example, when a metal oxide is used for the semiconductor layer 21, the semiconductor layer 21 can be formed by the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0186] For example, when forming an In—Ga—Zn oxide film, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0187] Examples of precursors that can be used that contain indium include triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.

[0188] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.

[0189] Furthermore, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0190] As the oxidizing agent, for example, ozone, oxygen, water, etc. can be used.

[0191] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, the order in which the source gases are flowed, etc. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form two or more films with different compositions continuously.

[0192] After the semiconductor film is formed, heat treatment can be performed to supply oxygen from the insulating layer 41b to the semiconductor film. Furthermore, the heat treatment can remove hydrogen in the semiconductor film and water adsorbed on the surface of the semiconductor film. The above description can be referred to for the heat treatment method.

[0193] Subsequently, the insulating layer 22 is formed to cover the conductive layer 24, the semiconductor layer 21, the conductive layer 25, etc. The insulating layer 22 is preferably formed to a uniform thickness along the side surface of the insulating layer 41, and therefore is preferably formed by a film formation method with high coverage. Specifically, it is preferable to use a film formation method such as the ALD method or the CVD method, with the ALD method being particularly preferable.

[0194] Next, a conductive film 23f is formed on the insulating layer 22 (FIG. 9B). After that, unnecessary portions of the conductive film 23f are removed by etching to form the conductive layer 23. Next, portions of the insulating layer 22 that are not covered by the conductive layer 23 are removed by etching (FIG. 9C).

[0195] The conductive film that becomes the conductive layer 23 is preferably formed by a film formation method with high coverage. Specifically, it is preferable to use a film formation method such as an ALD method or a CVD method, and it is particularly preferable to form the conductive layer 23 by using one or both of an ALD method and a thermal CVD method. Note that the conductive layer 23 may also be formed by a sputtering method.

[0196] Through the above steps, a transistor can be manufactured.

[0197] The above is a description of an example of the manufacturing method.

[0198] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0199] By applying the vertical transistor exemplified in Embodiment 1 to a liquid crystal display device, the aperture ratio can be significantly increased compared to a liquid crystal display device that applies a conventional horizontal transistor, thereby realizing a display device with low power consumption, a display device with increased maximum luminance, a display device with good viewing angle characteristics, a display device with high reliability, and the like.

[0200] More specifically, one embodiment of the present invention can realize a liquid crystal display device that combines extremely high definition and a high aperture ratio by applying a vertical transistor that can occupy an extremely small area to a pixel of the liquid crystal display device. Furthermore, the vertical transistor of one embodiment of the present invention can have a shorter channel length and can pass a large current compared to a conventional horizontal transistor. Therefore, by applying such a transistor to a display device, a liquid crystal display device that can be driven at high speed and has high display quality can be realized. Furthermore, the vertical transistor of one embodiment of the present invention has an extremely small leakage current in an off state despite its short channel length. Therefore, by applying the vertical transistor to a liquid crystal display device, a potential written to a pixel can be held for a long time, thereby reducing power consumption by displaying at a low frame rate.

[0201] It is preferable to use an oxide conductive film as a second electrode of a transistor provided over an insulating layer. When an oxide semiconductor film is used for a semiconductor layer, contact resistance between the semiconductor layer and the second electrode can be reduced. Furthermore, a light-transmitting oxide conductive film may be used for the second electrode, which also serves as a pixel electrode of a liquid crystal element.

[0202] However, when a horizontal transistor is used, it is necessary to provide a contact hole to connect the source or drain electrode of the transistor to the pixel electrode. Furthermore, depending on the transistor configuration, a contact hole is also used to connect the semiconductor layer to the source or drain electrode. The uneven shape of these contact holes causes the alignment of liquid crystal in the contact holes and their surrounding areas to become disordered, making them unusable for display. This is one of the reasons why the aperture ratio cannot be increased.

[0203] On the other hand, in one embodiment of the present invention, the second electrode of the transistor also serves as a pixel electrode, so that a contact hole is not needed, and therefore the aperture ratio can be increased.Furthermore, since an interlayer insulating layer is not needed between the semiconductor layer and the second electrode of the transistor, a structure in which the semiconductor layer and the second electrode are in contact with each other without a contact hole can be realized, and the aperture ratio can be further increased.

[0204] The liquid crystal element may have various configurations. Typically, a transmissive liquid crystal element may be used that employs a VA (Vertical Alignment) mode, an FFS (Fringe Field Switching) mode, an IPS (In-Plane Switching) mode, or the like. In addition to a transmissive liquid crystal element, a reflective or semi-transmissive liquid crystal element may also be used.

[0205] A more specific example will be described below with reference to the drawings.

[0206] [Configuration example of liquid crystal display device] Fig. 10A shows a schematic top view of a pixel 55 included in the liquid crystal display device exemplified below. Fig. 10B shows a schematic perspective view of the pixel. Note that some components (liquid crystal, common electrode, etc.) are omitted here.

[0207] The pixel 55 has three subpixels (subpixels 56R, 56G, and 56B). The subpixel 56R is a red subpixel, the subpixel 56G is a green subpixel, and the subpixel 56B is a blue subpixel. The subpixels 56R, 56G, and 56B have the same configuration except for the colored layers.

[0208] The subpixel 56R includes a transistor 10. The subpixel 56R also includes a part of the conductive layer 23, a part of the conductive layer 24, and a conductive layer 25. The conductive layer 23 also functions as a gate line, and the conductive layer 24 also functions as a signal line. The conductive layer 25 also functions as a pixel electrode.

[0209] 10B , conductive layer 24 and island-shaped insulating layer 41 are provided on insulating layer 11, and conductive layer 25 is provided on insulating layer 41. Semiconductor layer 21 has a portion in contact with the upper surface of conductive layer 24, a portion in contact with the side surface of insulating layer 41, and a portion in contact with the upper surface of conductive layer 25. Note that insulating layer 22, which functions as a gate insulating layer, and conductive layer 23 are omitted from FIG. 10B .

[0210] 10A and 10B, it is possible to achieve high-definition display devices. For example, by forming the wiring width of conductive layer 23 and conductive layer 24 and the spacing between two conductive layers 25 at the minimum processing dimensions, a display device with extremely high definition can be realized. For example, when the minimum processing dimension is 1.5 μm, the configuration shown in FIGS. 10A and 10B has a resolution of 2117 ppi and an aperture ratio (here, the ratio of the effective area of ​​the pixel electrode) of 44.7%, making it possible to realize a display device that combines a high aperture ratio and high definition.

[0211] 11A and 11B show an example of a pixel configuration that allows for even higher resolution. In this example, the width of conductive layer 24 is the same as the width of the thickest part of conductive layer 25. With this configuration, for example, when the minimum processing dimension is 1.5 μm, a display device with a resolution of 2822 ppi and an aperture ratio of 28.8% can be realized.

[0212] [Cross-sectional configuration examples] [Configuration example 1] Fig. 12A is a schematic cross-sectional view of a liquid crystal display device. Fig. 12A shows a cross section corresponding to the dashed dotted line C1-C2 shown in Fig. 10A. The display device shown in Fig. 12A has a transistor 10 and a liquid crystal element 30 between an insulating layer 11 and a substrate 12.

[0213] The transistor 10 includes a semiconductor layer 21, an insulating layer 22, a conductive layer 23, a conductive layer 24a, a conductive layer 24b, and a conductive layer 25. Here, an example is shown in which the conductive layer 24b is stacked over the conductive layer 24a, and the semiconductor layer 21 is in contact with the top surface of the conductive layer 24b. It is preferable to use a low-resistance conductive film for the conductive layer 24a and an oxide conductive film for the conductive layer 24b.

[0214] The liquid crystal element 30 includes a part of the conductive layer 25, a liquid crystal 31, and a conductive layer 32. The conductive layer 25 functions as a pixel electrode. The conductive layer 32 functions as a common electrode. A light-transmitting conductive film is preferably used for the conductive layer 25 and the conductive layer 32, and an oxide conductive film is preferably used.

[0215] Conductive layer 24a and conductive layer 24b are stacked on insulating layer 11, with island-shaped insulating layer 41 (insulating layers 41a, 41b, and 41c) covering portions of these, and conductive layer 25 is provided on insulating layer 41. Semiconductor layer 21 is provided in contact with the upper surface of conductive layer 24a, the side surface of insulating layer 41, and the upper surface of conductive layer 25. Insulating layer 22 is provided covering conductive layer 24b, semiconductor layer 21, conductive layer 25, insulating layer 11, etc., and conductive layer 23 is provided on insulating layer 22. Conductive layer 23 is provided to cover the portion of semiconductor layer 21 that is along insulating layer 41, via insulating layer 22. Note that insulating layer 11 may be a glass substrate.

[0216] An insulating layer 42 is provided to cover the conductive layer 23 and the insulating layer 22. The insulating layer 42 functions as a protective layer. The insulating layer 42 can be formed using the same insulating film as that used for the insulating layer 41a or the insulating layer 41b.

[0217] An alignment film 35a is provided to cover the insulating layer 42, and an insulating layer 54 functioning as a spacer is provided on the alignment film 35a. The insulating layer 54 is preferably provided in a portion that does not contribute to display. The insulating layer 54 can be provided in a portion overlapping with the conductive layer 24a, a portion overlapping with the conductive layer 23, or the like.

[0218] A colored layer 51, a light-shielding layer 52, an insulating layer 53, a conductive layer 32, and an alignment film 35b are provided on the surface of the substrate 12 facing the insulating layer 11. The alignment film 35b may have a portion in contact with the insulating layer 54.

[0219] The portion where the light-shielding layer 52 is provided becomes a non-light-emitting region. In one embodiment of the present invention, the light-shielding layer 52 can be provided in a region covering the transistor 10, the conductive layer 23, and the conductive layer 24. In one embodiment of the present invention, there is no contact hole connecting the pixel electrode and the transistor, so that the area of ​​the non-light-emitting region where the light-shielding layer 52 is provided can be significantly reduced compared to conventional embodiments.

[0220] The colored layer 51 can also be called a color filter, and converts light from a light source such as a backlight into light exhibiting a specific color. For example, by applying colored layers 51 corresponding to red, green, and blue to each pixel (sub-pixel) as the colored layer, a full-color display can be achieved. Note that providing pixels (sub-pixels) corresponding to colors such as yellow and white in addition to these three colors is preferable because it reduces power consumption.

[0221] Alternatively, blue or purple light may be used as the light source, and a color conversion material that converts the blue or purple light into another color (e.g., red, green, etc.) may be applied to the colored layer 51. The color conversion material may be a fluorescent material, a phosphorescent material, or a resin material in which quantum dots are dispersed. In this case, it is preferable that the colored layer 51 has a laminated structure of a color conversion material and a color filter from the backlight side so as to absorb light that has passed through the color conversion material.

[0222] The insulating layer 53 functions as an overcoat that prevents components contained in the colored layer 51 and the like from diffusing into the liquid crystal 31. The insulating layer 53 also functions as a planarizing film. The insulating layer 53 can be formed using a light-transmitting organic resin.

[0223] The substrate on which the insulating layer 11 is provided and the substrate 12 are bonded together by an adhesive layer (not shown) provided outside the display section. The distance between the substrates is controlled by an insulating layer 54 that functions as a spacer.

[0224] In one embodiment of the present invention, one of the source electrode and the drain electrode of the transistor 10 (specifically, the upper electrode) also serves as a pixel electrode of the liquid crystal element 30. With this structure, the manufacturing process can be significantly simplified and manufacturing costs can be reduced compared to when these electrodes are formed separately. Furthermore, the number of required interlayer insulating films can be reduced, which can reduce scattering of light from a backlight, improve power efficiency, and reduce power consumption.

[0225] Here, the pixel electrode of the liquid crystal element 30 is required to have high light-transmitting properties. Furthermore, the transistor 10 is required to have good electrical connection with the semiconductor layer 21 containing an oxide semiconductor. Therefore, by using a light-transmitting conductive metal oxide film for the conductive layer 25, not only can high light-transmitting properties be achieved but also good electrical connection with the oxide semiconductor can be achieved. Therefore, by using a light-transmitting conductive metal oxide film for the conductive layer 25, the conductive layer 25 can function as both one of the source electrode and drain electrode of the transistor 10 and as a pixel electrode.

[0226] Here, the liquid crystal element 30 is shown to be in a so-called VA mode, in which the pixel electrodes are disposed on the insulating layer 11 side and the common electrode is disposed on the substrate 12 side, and an electric field is applied parallel to the thickness direction of the liquid crystal 31. However, the method of arranging the electrodes is not limited to this, and a method of applying an electric field in a direction perpendicular to the thickness direction of the liquid crystal 31 may also be used.

[0227] The display device may be a normally black liquid crystal display device, for example, a transmissive liquid crystal display device employing a vertical alignment (VA) mode. As the vertical alignment mode, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, an advanced super view (ASV) mode, or the like may be used.

[0228] Furthermore, liquid crystal elements applying various modes can be used for the liquid crystal element 30. For example, in addition to the VA mode and the FFS mode, liquid crystal elements applying other modes such as the Twisted Nematic (TN) mode, the IPS mode, the ASM (Axially Symmetric Aligned Micro-cell) mode, the Optically Compensated Birefringence (OCB) mode, the Ferroelectric Liquid Crystal (FLC) mode, the Anti-Ferroelectric Liquid Crystal (AFLC) mode, the Electrically Controlled Birefringence (ECB) mode, and the Guest-Host mode can be used.

[0229] Here, a liquid crystal display device is a display device that controls the transmission or non-transmission of light by utilizing the optical modulation effect of polarized light and liquid crystals. The optical modulation effect of liquid crystals is controlled by an electric field (including a horizontal electric field, a vertical electric field, or an oblique electric field) applied to the liquid crystal. Liquid crystals that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, polymer liquid crystals, polymer-dispersed liquid crystals (PDLC), polymer network liquid crystals (PNLC), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, and the like, depending on the conditions. Furthermore, either positive or negative liquid crystals may be used as the liquid crystal material, and the optimal liquid crystal material may be used depending on the mode or design to be applied.

[0230] 12A, in the case of a transmissive liquid crystal display, a polarizing plate is provided on each of the outer surfaces of the substrate on which the insulating layer 11 is provided and the outer surface of the substrate 12. Furthermore, a backlight is provided outside the substrate on which the insulating layer 11 is provided. In this case, the substrate 12 side becomes the display surface side.

[0231] 12A shows a configuration in which the insulating layer 22 covers the upper surface of the conductive layer 25, but FIG. 12B shows an example in which the insulating layer 22 is processed so that its end coincides with that of the conductive layer 23. In this case, the insulating layer 22 is not provided between the conductive layer 25 and the liquid crystal 31 in the liquid crystal element 30, and therefore the strength of the electric field that the liquid crystal 31 receives from the conductive layer 25 can be increased. This is preferable because the driving voltage of the liquid crystal element 30 can be reduced.

[0232] [Configuration Example 2] FIG. 13A shows an example in which a conductive layer 36 is added to the configuration shown in FIG. 12A.

[0233] The conductive layer 36 is provided in a region overlapping with the liquid crystal element 30. The conductive layer 36 can be formed by processing the same conductive film as the conductive layer 24b. The conductive layer 36 has a function of transmitting visible light.

[0234] The conductive layer 36, the insulating layer 41, and the conductive layer 25 form a metal-insulator-metal (MIM) capacitor. This capacitor can be used as a storage capacitor for the pixel. By providing the storage capacitor, the period during which the potential of the conductive layer 25, which functions as a pixel electrode, can be maintained can be extended, allowing for display at a low frame rate.

[0235] [Configuration Example 3] FIG. 13B shows an example in which an IPS mode liquid crystal element 30 is used.

[0236] The conductive layer 25, which functions as a pixel electrode, and the conductive layer 32, which functions as a common electrode, are both provided on the insulating layer 41c. In this case, the conductive layer 25 and the conductive layer 32 are preferably formed by processing the same conductive film. In Fig. 13B, for ease of explanation, the conductive layer 25 and the conductive layer 32 are given different hatching patterns.

[0237] The conductive layer 25 and the conductive layer 32 each have a comb-like upper surface shape, and are arranged so as to interdigitate with each other without contacting each other.

[0238] [Configuration Example 4] FIG. 14A shows an example in which an FFS mode liquid crystal element 30 is used.

[0239] A conductive layer 32 functioning as a common electrode is provided over the insulating layer 42. One or more openings (also referred to as slits) are provided in the conductive layer 32. The conductive layer 32 includes a conductive film that transmits visible light.

[0240] The conductive layer 32 and the conductive layer 25 have an overlapping region with the insulating layer 22 and the insulating layer 42 interposed therebetween, and this region functions as a storage capacitor. Therefore, there is no need to provide a separate storage capacitor, which makes it easy to increase the pixel occupation area and the aperture ratio.

[0241] Fig. 14B is a modification of Fig. 14A, in which the stacking order of the conductive layer 32 and the conductive layer 25 is reversed.

[0242] Conductive layer 32 is provided on insulating layer 41c, and insulating layer 43 is provided covering conductive layer 32 and insulating layer 41c. Conductive layer 25 is provided on insulating layer 43, and insulating layer 22 and insulating layer 42 are provided covering conductive layer 25. Conductive layer 25 has one or more slits formed therein.

[0243] In FIG. 14B, the region where the conductive layer 32 and the conductive layer 25 overlap with the insulating layer 43 interposed therebetween functions as a storage capacitor.

[0244] [Configuration Example 5] The configuration shown in FIG. 15A is a modification of the configuration shown in FIG. 13A.

[0245] 15A , the portion of the insulating layer 41b that overlaps with the liquid crystal element 30 has been removed by etching. That is, the configuration shown in FIG. 15A has a portion in which the conductive layer 36, the insulating layer 41a, the insulating layer 41b, and the conductive layer 25 are stacked in this order in the region that overlaps with the liquid crystal element 30. This allows for a larger capacitance between the conductive layer 36 and the conductive layer 25 compared to the configuration shown in FIG. 13A . Furthermore, not providing the insulating layer 41b in the portion that functions as the liquid crystal element 30 not only increases light transmittance but also reduces the number of interfaces located on the path of light from the light source, thereby suppressing the effects of interface reflection and interface scattering.

[0246] 15B, not only the insulating layer 41b but also the insulating layer 41c may be etched in a portion that overlaps with the liquid crystal element 30. This not only makes it possible to further increase the capacitance between the conductive layer 36 and the conductive layer 25, but also improves the light transmittance and further suppresses the effects of interface reflection and interface scattering.

[0247] [Configuration Example 6] The configuration shown in FIG. 16A is a modification of the configuration shown in FIG. 15A.

[0248] 16A shows a configuration in which the conductive layer 25 is not provided, and a part of the semiconductor layer 21 also serves as a pixel electrode. The semiconductor layer 21 has a part that does not overlap with the insulating layer 41 and functions as a pixel electrode. A part of the semiconductor layer 21 is provided in a region that overlaps with the conductive layer 36. The semiconductor layer 21, the liquid crystal 31, and the conductive layer 32 form a liquid crystal element 30. Furthermore, the conductive layer 36, the insulating layer 41a, the insulating layer 41c, and the semiconductor layer 21 form a storage capacitor.

[0249] With this structure, the conductive layer 25 can be omitted, thereby reducing the manufacturing process of the display device. In addition, since there is no need to provide a contact portion between the conductive layer 25 and the semiconductor layer 21, the area occupied by the transistor can be further reduced. Therefore, higher definition or a higher aperture ratio can be achieved.

[0250] Fig. 16B is a modification of Fig. 16A, in which the portion of the insulating layer 22 that is not covered by the conductive layer 23 is removed by etching.

[0251] [Configuration Example 7] Fig. 17A is a modification of Fig. 14B, showing an example in which the insulating layer 41b is removed by etching in the region overlapping with the liquid crystal element 30.

[0252] The conductive layer 32 is provided over the insulating layer 11. The conductive layer 32 can be formed by processing the same conductive film as the conductive layer 24b. This is preferable because it can reduce the number of manufacturing steps of the display device.

[0253] Insulating layers 41a and 41c are provided on the conductive layer 32, and a conductive layer 25 is provided on the insulating layer 41c. Note that the conductive layer 25 may be omitted, and the semiconductor layer 21 may also serve as a pixel electrode. Alternatively, one of the insulating layer 41a and the insulating layer 41c may be removed by etching, and either the insulating layer 41a or the insulating layer 41c may be provided between the conductive layer 32 and the conductive layer 25 (or the semiconductor layer 21).

[0254] [Configuration Example 8] Fig. 17B is a modification of Fig. 13B, showing an example in which the insulating layers 41a, 41b, and 41c are removed by etching in the region overlapping with the liquid crystal element 30.

[0255] The insulating layer 41c is provided to cover the side surface of the insulating layer 41b opposite to the semiconductor layer 21 side. The insulating layer 41c also has an area in contact with the insulating layer 41a. By surrounding the insulating layer 41b with the semiconductor layer 21, the insulating layer 41a, and the insulating layer 41c in this manner, it is possible to suppress the diffusion of oxygen contained in the insulating layer 41b, thereby increasing the amount of oxygen supplied to the semiconductor layer 21. This makes it possible to realize a highly reliable display device.

[0256] The conductive layer 25 and the conductive layer 32 are provided on the insulating layer 11. In this way, by arranging as little of the insulating layer as possible in the region overlapping with the liquid crystal element 30, the influence of interface reflection and interface scattering can be suppressed, which is preferable.

[0257] The above is a description of an example of the configuration of the display device.

[0258] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0259] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0260] Embodiment 3 In this embodiment, a display device including a transistor according to one embodiment of the present invention will be described.

[0261] 18A includes a pixel portion 502, a driver circuit portion 504, a protective circuit 506, and a terminal portion 507. Note that the protective circuit 506 may not be provided.

[0262] The transistor of one embodiment of the present invention can be applied to the transistor included in one or both of the pixel portion 502 and the driver circuit portion 504. The transistor of one embodiment of the present invention may also be applied to the protection circuit 506.

[0263] The pixel portion 502 has a plurality of pixel circuits 501 arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). Each pixel circuit 501 has a circuit for driving a display element.

[0264] The driver circuit portion 504 includes driver circuits such as a gate driver 504a that outputs scan signals to the gate lines GL_1 to GL_X and a source driver 504b that supplies data signals to the data lines DL_1 to DL_Y. The gate driver 504a can have at least a shift register. The source driver 504b can be configured using a shift register, a digital-to-analog conversion circuit, a latch circuit, or the like.

[0265] The terminal portion 507 is a portion provided with terminals for inputting power, control signals, image signals, and the like from an external circuit to the display device.

[0266] The protection circuit 506 is a circuit that brings a wiring connected to itself into a conductive state with another wiring when a potential outside a certain range is applied to the wiring. The protection circuit 506 shown in Fig. 18A is connected to various wirings such as a gate line GL and a data line DL. Note that in Fig. 18A, the protection circuit 506 is indicated by a hatched pattern in order to distinguish the protection circuit 506 from the pixel circuit 501.

[0267] The gate driver 504a and the source driver 504b may be provided on the same substrate as the pixel portion 502, or an IC on which a gate driver circuit or a source driver circuit is separately formed may be mounted on the substrate on which the pixel portion 502 is provided by using a COG (chip on glass) method or the like. Alternatively, an FPC (flexible printed circuit) on which an IC is mounted may be attached to the substrate by using an ACF (anisotropic conductive film) or the like.

[0268] In particular, the pixel portion 502 and the gate driver 504a are preferably fabricated over the same substrate and through the same process. In this case, the pixel portion 502 and the gate driver 504a are preferably provided with the transistor of one embodiment of the present invention. Furthermore, when an IC is used for the source driver 504b, it is preferable to provide a demultiplexer circuit on the substrate, because this reduces the number of terminals of the IC. In this case, the transistor of one embodiment of the present invention is preferably used for the demultiplexer circuit.

[0269] FIG. 18B shows an example of the configuration of a pixel circuit that can be applied to the pixel circuit 501.

[0270] 18B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The pixel circuit 501 is connected to a data line DL_n, a gate line GL_m, a potential supply line VL, and the like.

[0271] The vertical transistor of one embodiment of the present invention can be used as the transistor 550 .

[0272] The potential of one of the pair of electrodes of the liquid crystal element 570 is set as appropriate according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by written data. Note that a common potential may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Alternatively, a different potential may be applied to one of the pair of electrodes of the liquid crystal element 570 in the pixel circuit 501 in each row.

[0273] 18C includes a transistor 552, a transistor 554, a capacitor 562, and a light-emitting element 572. The pixel circuit 501 is connected to a data line DL_n, a gate line GL_m, a potential supply line VL_a, a potential supply line VL_b, and the like.

[0274] Note that a high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b, and a low power supply potential VSS is applied to the other. The current flowing through the light-emitting element 572 is controlled in accordance with the potential applied to the gate of the transistor 554, thereby controlling the luminance of light emitted from the light-emitting element 572.

[0275] Next, a pixel circuit including a memory for correcting the gray scale displayed in the pixel and a display device having the same will be described.

[0276] 19A shows a circuit diagram of a pixel circuit 400. The pixel circuit 400 includes a transistor M1, a transistor M2, a capacitor C1, and a circuit 401. The pixel circuit 400 is connected to a wiring S1, a wiring S2, a wiring G1, and a wiring G2.

[0277] The vertical transistor of one embodiment of the present invention can be used as the transistor M1 and the transistor M2.

[0278] The transistor M1 has a gate connected to the wiring G1, one of a source and a drain connected to the wiring S1, and the other connected to one electrode of the capacitor C1. The transistor M2 has a gate connected to the wiring G2, one of a source and a drain connected to the wiring S2, and the other connected to the other electrode of the capacitor C1 and the circuit 401.

[0279] The circuit 401 is a circuit including at least one display element, which is a liquid crystal element.

[0280] The node connecting the transistor M1 and the capacitor C1 is referred to as a node N1, and the node connecting the transistor M2 and the circuit 401 is referred to as a node N2.

[0281] In the pixel circuit 400, the potential of the node N1 can be maintained by turning off the transistor M1. In addition, the potential of the node N2 can be maintained by turning off the transistor M2. In addition, by writing a predetermined potential to the node N1 via the transistor M1 while the transistor M2 is in the off state, the potential of the node N2 can be changed in accordance with the change in the potential of the node N1 due to capacitive coupling via the capacitor C1.

[0282] Here, the transistor including an oxide semiconductor, as exemplified in Embodiment 1, can be used as one or both of the transistors M1 and M2. Therefore, the potential of the node N1 or the node N2 can be held for a long period of time due to an extremely low off-state current. Note that when the period for holding the potential of each node is short (specifically, when the frame frequency is 30 Hz or higher), a transistor including a semiconductor such as silicon may be used.

[0283] [Driving Method Example] Next, an example of an operating method of the pixel circuit 400 will be described with reference to Fig. 19B. Fig. 19B is a timing chart relating to the operation of the pixel circuit 400. Note that, to simplify the explanation, the influence of various resistances such as wiring resistance, parasitic capacitance, and transistor threshold voltages will not be taken into consideration.

[0284] 19B, one frame period is divided into a period T1 and a period T2. The period T1 is a period in which a potential is written to the node N2, and the period T2 is a period in which a potential is written to the node N1.

[0285] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, a fixed potential V ｒｅｆis supplied to the line S2, and the first data potential V ｗ supply.

[0286] The node N1 is connected to the wiring S1 via the transistor M1. ｒｅｆ The node N2 is supplied with a first data potential V ｗ Therefore, the potential difference V ｗ -V ｒｅｆ is maintained.

[0287] [Period T2] Subsequently, in period T2, a potential that turns on the transistor M1 is applied to the wiring G1, and a potential that turns off the transistor M2 is applied to the wiring G2. In addition, a second data potential V ｄａｔａ A predetermined constant potential may be applied to the wiring S2, or the wiring S2 may be in a floating state.

[0288] The node N1 receives a second data potential V ｄａｔａ At this time, the second data potential V ｄａｔａ In other words, the circuit 401 receives the first data potential V ｗ 19B shows the potential dV as a positive value, but it may be a negative value. That is, the second data potential V ｄａｔａ is the potential V ｒｅｆ It may be lower.

[0289] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV is equal to the second data potential V ｄａｔａ The potential is close to

[0290] In this way, the pixel circuit 400 can generate a potential to be supplied to the circuit 401 including a display element by combining two types of data signals, and therefore, it is possible to perform gradation correction within the pixel circuit 400.

[0291] The pixel circuit 400 can also generate a potential that exceeds the maximum potential that can be supplied by a source driver connected to the wirings S1 and S2. For example, when a light-emitting element is used, high dynamic range (HDR) display or the like can be performed. Furthermore, when a liquid crystal element is used, overdrive driving or the like can be realized.

[0292] 19C includes a circuit 401LC, which includes a liquid crystal element LC and a capacitor C2.

[0293] The liquid crystal element LC has one electrode connected to the node N2 and one electrode of the capacitor C2, and the other electrode connected to the potential V ｃｏｍ２ The other electrode of the capacitor C2 is connected to a wiring to which a potential V ｃｏｍ１ Connect with the wiring given.

[0294] The capacitor C2 functions as a storage capacitor. If the capacitor C2 is not required, it can be omitted.

[0295] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, which makes it possible to, for example, achieve high-speed display by overdriving, apply a liquid crystal material with a high driving voltage, etc. Furthermore, by supplying a correction signal to the wiring S1 or the wiring S2, it is possible to correct the gradation in accordance with the operating temperature, the deterioration state of the liquid crystal element LC, etc.

[0296] 19D includes a circuit 401EL. The circuit 401EL includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0297] The transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, and one of its source and drain connected to the potential V Ｈ The other electrode of the capacitor C2 is connected to a wiring to which a potential V ｃｏｍ The other electrode of the light-emitting element EL is connected to a wiring to which a potential V Ｌ Connect with the wiring given.

[0298] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. The capacitor C2 functions as a storage capacitor. The capacitor C2 can be omitted if it is not necessary.

[0299] Although the anode side of the light-emitting element EL is connected to the transistor M3 in this example, the transistor M3 may be connected to the cathode side. Ｈ and potential V Ｌ The value of can be changed as appropriate.

[0300] In the pixel circuit 400EL, by applying a high potential to the gate of the transistor M3, a large current can flow through the light-emitting element EL, thereby realizing, for example, HDR display, etc. Furthermore, by supplying a correction signal to the wiring S1 or the wiring S2, it is possible to correct variations in the electrical characteristics of the transistor M3, the light-emitting element EL, etc.

[0301] Note that the circuits are not limited to those illustrated in FIGS. 19C and 19D, and may be configured to include additional transistors, capacitors, and the like.

[0302] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0303] Embodiment 4 In this embodiment, a configuration example of a touch panel module including a touch panel and an IC will be described.

[0304] 20 shows a block diagram of the touch panel module 6500. The touch panel module 6500 includes a touch panel 6510 and an IC 6520.

[0305] The touch panel 6510 includes a display portion 6511, an input portion 6512, a scanning line driver circuit 6513, a sensor driver circuit 6503, and a detection circuit 6504. The display portion 6511 includes a plurality of pixels, a plurality of signal lines, and a plurality of scan lines, and has a function of displaying an image. The input portion 6512 includes a plurality of sensor elements that detect contact or proximity of a detectable object to the touch panel 6510, and functions as a touch sensor. The scanning line driver circuit 6513 has a function of outputting a scan signal to the scan line included in the display portion 6511.

[0306] The sensor driver circuit 6503 has a function of outputting a signal for driving a sensor element included in the input portion 6512. The sensor driver circuit 6503 can be configured by combining a shift register circuit and a buffer circuit, for example.

[0307] The detection circuit 6504 has a function of amplifying an output signal from the sensor element of the input portion 6512 and outputting it to the AD conversion circuit 6507 .

[0308] Here, for ease of explanation, the configuration of the touch panel 6510 is shown as being separated into a display portion 6511 and an input portion 6512, but it may also be a so-called in-cell type touch panel that has both the function of displaying images and the function of acting as a touch sensor.

[0309] As a touch sensor type that can be used as the input unit 6512, for example, a capacitance type can be applied. The capacitance type includes a surface capacitance type, a projected capacitance type, and the like. The projected capacitance type includes a self-capacitance type, a mutual capacitance type, and the like. The mutual capacitance type is preferable because it enables simultaneous multi-point detection.

[0310] Note that the present invention is not limited to this, and various types of sensors that can detect the approach, contact, or pressure of a detection target such as a finger or a stylus can also be applied to the input portion 6512. For example, as the sensor type, in addition to the capacitance type, various types such as a resistive film type, a surface acoustic wave type, an infrared type, and an optical type can be used.

[0311] Representative in-cell touch panels include hybrid in-cell and full in-cell types. The hybrid in-cell type refers to a configuration in which electrodes constituting a touch sensor are provided on both the substrate supporting the display element and the opposing substrate, or on the opposing substrate. On the other hand, the full in-cell type refers to a configuration in which electrodes constituting a touch sensor are provided on the substrate supporting the display element. A full in-cell touch panel is preferred because it can simplify the configuration of the opposing substrate. In particular, a full in-cell type is preferred because it can simplify the manufacturing process and reduce manufacturing costs if the electrodes constituting the display element also serve as electrodes constituting the touch sensor.

[0312] The display unit 6511 preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the pixels provided in the display unit 6511 is preferably 300 ppi or higher, preferably 500 ppi or higher, more preferably 800 ppi or higher, more preferably 1000 ppi or higher, and more preferably 1200 ppi or higher. The display unit 6511 having such high resolution and high resolution can enhance the sense of realism and depth.

[0313] The IC 6520 includes a circuit unit 6501, a signal line driver circuit 6502, and an AD conversion circuit 6507. The circuit unit 6501 includes a timing controller 6505, an image processing circuit 6506, and the like.

[0314] The signal line driver circuit 6502 has a function of outputting analog video signals to signal lines included in the display portion 6511. For example, the signal line driver circuit 6502 can have a combination of a shift register, a digital-analog converter (DAC), a latch circuit, a buffer circuit, and the like. The touch panel 6510 may also have a demultiplexer circuit connected to the signal lines.

[0315] The AD conversion circuit 6507 has a function of converting an analog signal input from the detection circuit 6504 into a digital signal and outputting the digital signal to the circuit unit 6501. For example, the AD conversion circuit 6507 can have a configuration including an amplifier circuit in addition to an analog-digital converter (ADC).

[0316] The image processing circuit 6506 of the circuit unit 6501 has the function of generating and outputting a signal that drives the display unit 6511 of the touch panel 6510, the function of generating and outputting a signal that drives the input unit 6512, and the function of analyzing the signal output from the input unit 6512 and outputting it to the CPU 6540.

[0317] As a more specific example, the image processing circuit 6506 has a function of generating a video signal in accordance with an instruction from the CPU 6540. The image processing circuit 6506 also has a function of performing signal processing on the video signal in accordance with the specifications of the display unit 6511, converting it into an analog video signal, and supplying it to the signal line driver circuit 6502. The image processing circuit 6506 also has a function of generating a drive signal to be output to the sensor driver circuit 6503 in accordance with an instruction from the CPU 6540. The image processing circuit 6506 also has a function of analyzing a signal input from the detection circuit 6504 via the AD conversion circuit 6507, and outputting it to the CPU 6540 as position information.

[0318] The timing controller 6505 has a function of generating and outputting signals (such as clock signals and start pulse signals) to be output to the scanning line driver circuit 6513 and the sensor driver circuit 6503 based on a synchronization signal included in a video signal processed by the image processing circuit 6506. The timing controller 6505 may also have a function of generating and outputting a signal that determines the timing at which the detection circuit 6504 outputs a signal. Here, the timing controller 6505 preferably outputs signals synchronized with the signals to be output to the scanning line driver circuit 6513 and the sensor driver circuit 6503. In particular, it is preferable to separate a period for rewriting pixel data in the display portion 6511 from a period for sensing in the input portion 6512. For example, one frame period can be divided into a period for rewriting pixel data and a period for sensing, thereby driving the touch panel 6510. Furthermore, for example, by providing two or more sensing periods in one frame period, detection sensitivity and detection accuracy can be improved.

[0319] The image processing circuit 6506 may have a configuration including, for example, a processor. For example, a microprocessor such as a DSP (Digital Signal Processor) or a GPU (Graphics Processing Unit) may be used. These microprocessors may also be configured as programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs) or field programmable analog arrays (FPAAs). The image processing circuit 6506 performs various data processing, program control, and the like by interpreting and executing instructions from various programs using the processor. Programs executable by the processor may be stored in a memory area of ​​the processor or in a separately provided storage device.

[0320] Note that a transistor using an oxide semiconductor for a channel formation region and having extremely low off-state current is preferably used for one or more of the display portion 6511, the input portion 6512, the scanning line driver circuit 6513, the sensor driver circuit 6503, and the detection circuit 6504 included in the touch panel 6510. Since the off-state current of the transistor is extremely low, the transistor can be used as a switch for retaining charge (data) flowing into a capacitor functioning as a memory element, thereby ensuring a long data retention period. Furthermore, the transistor may be applied to the circuit unit 6501, the signal line driver circuit 6502, the AD conversion circuit 6507, the CPU 6540 provided externally, or the like included in the IC 6520. For example, by using this characteristic in the register, cache memory, etc. of the image processing circuit 6506, the image processing circuit 6506 is operated only when necessary, and at other times, the information from the previous processing is saved in the memory element, thereby enabling so-called normally-off computing, in which the power supply to the image processing circuit 6506 is cut off when not in use, thereby enabling low power consumption of the touch panel module 6500 and the electronic device in which it is implemented.

[0321] Note that, here, the circuit unit 6501 has a configuration including a timing controller 6505 and an image processing circuit 6506, but the image processing circuit 6506 itself or a circuit having part of the functions of the image processing circuit 6506 may be provided outside the IC 6520. Alternatively, the functions of the image processing circuit 6506 or part of the functions may be performed by the CPU 6540. For example, the circuit unit 6501 may have a configuration including a signal line driver circuit 6502, a timing controller 6505, and an AD conversion circuit 6507.

[0322] Although an example in which the IC 6520 includes the circuit unit 6501 has been shown here, the circuit unit 6501 may not be included in the IC 6520. In this case, the IC 6520 may include a signal line driver circuit 6502 and an AD conversion circuit 6507. For example, when a plurality of ICs are mounted on the touch panel module 6500, an IC including the circuit unit 6501 may be separately provided, and a plurality of ICs 6520 not including the circuit unit 6501 may be disposed, or the IC 6520 and an IC having only the signal line driver circuit 6502 may be combined and disposed.

[0323] In this way, by incorporating the function of driving the display portion 6511 of the touch panel 6510 and the function of driving the input portion 6512 into a single IC, the number of ICs implemented in the touch panel module 6500 can be reduced, thereby reducing costs.

[0324] 21A, 21B, and 21C are schematic diagrams of a touch panel module 6500 on which an IC 6520 is mounted.

[0325] 21A includes a substrate 6531, an opposing substrate 6532, a plurality of FPCs 6533, an IC 6520, an IC 6530, and the like. A display portion 6511, an input portion 6512, a scanning line driver circuit 6513, a sensor driver circuit 6503, and a detection circuit 6504 are provided between the substrate 6531 and the opposing substrate 6532. The IC 6520 and the IC 6530 are mounted on the substrate 6531 by a mounting method such as a COG (chip on glass) method.

[0326] The IC 6530 is an IC having only the signal line driver circuit 6502 or the signal line driver circuit 6502 and the circuit unit 6501 in the above-described IC 6520. A signal is supplied to the IC 6520 and the IC 6530 from the outside via an FPC 6533. In addition, a signal can be output from the IC 6520 or the IC 6530 to the outside via the FPC 6533.

[0327] 21A shows an example of a configuration in which two scanning line driver circuits 6513 are provided so as to sandwich the display portion 6511. Also, a configuration including an IC 6530 in addition to an IC 6520 is shown. Such a configuration can be suitably used when the display portion 6511 has extremely high resolution.

[0328] 21B shows an example in which one IC 6520 and one FPC 6533 are mounted. This is preferable because the number of components can be reduced by consolidating the functions into one IC 6520. Also, in FIG. 21B, the scanning line driver circuit 6513 is arranged along one of the two short sides of the display portion 6511 that is closer to the FPC 6533.

[0329] 21C shows an example of a configuration having a PCB (Printed Circuit Board) 6534 on which an image processing circuit 6506 and the like are mounted. An IC 6520 and an IC 6530 on a substrate 6531 are electrically connected to the PCB 6534 by an FPC 6533. Here, a configuration not having the image processing circuit 6506 described above can be applied to the IC 6520.

[0330] 21A, 21B, and 21C, the IC 6520 and the IC 6530 may be mounted on the FPC 6533 instead of the substrate 6531. For example, the IC 6520 and the IC 6530 can be mounted on the FPC 6533 by a mounting method such as the COF method or the TAB method.

[0331] 21A and 21B, a configuration in which an FPC 6533, an IC 6520 (and an IC 6530), and the like are arranged on the short side of the display portion 6511 allows for a narrower frame, and is therefore suitable for use in electronic devices such as smartphones, mobile phones, and tablet terminals. Also, a configuration using a PCB 6534 as shown in Fig. 21C is suitable for use in television devices, monitor devices, tablet terminals, and notebook personal computers.

[0332] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0333] Embodiment 5 In this embodiment, an electronic device according to one embodiment of the present invention will be described.

[0334] The electronic devices of this embodiment include the display device of one embodiment of the present invention in their display portions. The display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, the display device of one embodiment of the present invention can be used in the display portions of various electronic devices.

[0335] The semiconductor device of one embodiment of the present invention can be applied to portions other than the display portion of an electronic device. For example, the use of the semiconductor device of one embodiment of the present invention in a control portion of an electronic device is preferable because it enables low power consumption.

[0336] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0337] In particular, the display device of one embodiment of the present invention can be used in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices (e.g., head-mounted displays), AR glasses-type devices, and MR devices.

[0338] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).

[0339] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.

[0340] The electronic device 7000 shown in FIG. 22A is a portable information terminal that can be used as a smartphone.

[0341] The electronic device 7000 includes a housing 7001, a display portion 7002, a power button 7003, a button 7004, a speaker 7005, a microphone 7006, a camera 7007, and a light source 7008. The display portion 7002 has a touch panel function.

[0342] The display device of one embodiment of the present invention can be applied to the display portion 7002 .

[0343] FIG. 22B is a schematic cross-sectional view including the end of the housing 7001 on the microphone 7006 side.

[0344] A light-transmitting protective member 7010 is provided on the display surface side of the housing 7001, and a display panel 7011, optical members 7012, a touch sensor panel 7013, a printed circuit board 7017, a battery 7018, etc. are arranged in the space surrounded by the housing 7001 and the protective member 7010.

[0345] A display panel 7011, an optical member 7012, and a touch sensor panel 7013 are fixed to the protective member 7010 by adhesive layers (not shown).

[0346] A part of the display panel 7011 is folded back in an area outside the display portion 7002, and an FPC 7015 is connected to the folded back part. An IC 7016 is mounted on the FPC 7015. The FPC 7015 is connected to a terminal provided on a printed circuit board 7017.

[0347] The display device of one embodiment of the present invention can be applied to the display panel 7011. Therefore, an extremely lightweight electronic device can be realized. Furthermore, since the display panel 7011 is extremely thin, the thickness of the electronic device can be reduced and a large-capacity battery 7018 can be mounted thereon. Furthermore, by folding back a part of the display panel 7011 and arranging a connection portion with the FPC 7015 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0348] 22C shows an example of a television set. A television set 7100 includes a display portion 7002 built in a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0349] The display device of one embodiment of the present invention can be applied to the display portion 7002 .

[0350] 22C can be operated using operation switches provided on the housing 7101 and a separate remote control 7111. Alternatively, the display portion 7002 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7002 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. Using operation keys or a touch panel provided on the remote control 7111, the channel and volume can be controlled, and an image displayed on the display portion 7002 can be controlled.

[0351] The television device 7100 is configured to include a receiver, a modem, and the like. Ordinary television broadcasts can be received using the receiver. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from a sender to a receiver) or two-way (between a sender and a receiver, or between receivers, etc.) information communication.

[0352] 22D shows an example of a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, and an external connection port 7214. The housing 7211 includes a display portion 7002.

[0353] The display device of one embodiment of the present invention can be applied to the display portion 7002 .

[0354] 22E and 22F show an example of digital signage.

[0355] 22E includes a housing 7301, a display portion 7002, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0356] 22F shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7002 provided along the curved surface of the pillar 7401.

[0357] 22E and 22F, the display device of one embodiment of the present invention can be applied to the display portion 7002.

[0358] The larger the display portion 7002, the more information can be provided at one time. Also, the larger the display portion 7002, the more easily people can see it, which can improve the effectiveness of advertising, for example.

[0359] Applying a touch panel to the display portion 7002 is preferable because it not only displays images or videos on the display portion 7002 but also allows a user to intuitively operate it. Furthermore, when used to provide information such as route information or traffic information, intuitive operation can improve usability.

[0360] 22E and 22F , the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 or an information terminal 7411, such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7002 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Furthermore, by operating the information terminal 7311 or the information terminal 7411, the display on the display unit 7002 can be switched.

[0361] The digital signage 7300 or the digital signage 7400 can also be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller), thereby allowing an unspecified number of users to simultaneously participate in and enjoy the game.

[0362] The electronic device shown in Figures 23A to 23G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including the function of detecting, detecting, or measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), a microphone 9008, etc.

[0363] 23A to 23G, the display device of one embodiment of the present invention can be applied to the display portion 9001.

[0364] The electronic devices shown in Figures 23A to 23G have various functions. For example, they may have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to control processing using various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. Note that the functions of the electronic devices are not limited to these, and they may have various other functions. The electronic devices may have multiple display units. Furthermore, the electronic devices may have a function to include a camera or the like to capture still images or videos and store them on a recording medium (external or built-in to the camera), a function to display the captured images on a display unit, etc.

[0365] The electronic devices shown in FIGS. 23A to 23G will be described in detail below.

[0366] FIG. 23A is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. Note that the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on multiple surfaces. FIG. 23A shows an example in which three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the title of the email or SNS message, the sender's name, the date and time, the remaining battery level, and radio wave intensity. Alternatively, an icon 9050 or the like may be displayed in the position where the information 9051 is displayed.

[0367] 23B is a perspective view showing the mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is placed in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether to answer a call.

[0368] 23C is a perspective view showing a tablet terminal 9103. The tablet terminal 9103 is capable of executing various applications such as mobile phone calls, e-mail, text browsing and creation, music playback, internet communication, and computer games, for example. The tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of a housing 9000, operation keys 9005 as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom.

[0369] FIG. 23D is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark). The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free calling by communicating with, for example, a wirelessly capable headset. The mobile information terminal 9200 can also perform data transmission and charging with another information terminal through a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0370] 23E to 23G are perspective views showing a foldable mobile information terminal 9201. Also, FIG. 23E is a perspective view of the mobile information terminal 9201 in an unfolded state, FIG. 23G is a perspective view of the mobile information terminal 9201 in a folded state, and FIG. 23F is a perspective view of a state in the process of changing from one of FIGS. 23E and 23G to the other. The mobile information terminal 9201 is highly portable when folded, and has a seamless, wide display area when unfolded, providing excellent visibility of the display. The display portion 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display portion 9001 can be bent with a curvature radius of 0.1 mm or more and 150 mm or less.

[0371] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0372] 10: transistor, 10a: transistor, 10b: transistor, 10c: transistor, 10d: transistor, 11: insulating layer, 12: substrate, 21: semiconductor layer, 21a: semiconductor layer, 21AC: region, 21b: semiconductor layer, 21c: semiconductor layer, 21d: semiconductor layer, 22: insulating layer, 23: conductive layer, 23f: conductive film, 24: conductive layer, 24a: conductive layer, 24b: conductive layer, 25: conductive layer, 25f: conductive film, 30: liquid crystal element, 31: liquid crystal, 32: conductive layer, 35a: alignment film, 35b: alignment film, 36: conductive layer, 41: insulating layer, 41a: insulating layer, 41b: insulating layer, 41c : insulating layer, 41p: part, 41q: part, 42: insulating layer, 43: insulating layer, 51: colored layer, 52: light-shielding layer, 53: insulating layer, 54: insulating layer, 55: pixel, 56B: sub-pixel, 56G: sub-pixel, 56R: sub-pixel, 400: pixel circuit, 400EL: pixel circuit, 400LC: pixel circuit, 401: circuit, 401EL: circuit, 401LC: circuit, 501: pixel circuit, 502: pixel section, 504: drive circuit section, 504a: gate driver, 504b: source driver, 506: protection circuit, 507: terminal section, 550: transistor, 552: transistor, 554: transistor, 560: Capacitive element, 562: Capacitive element, 570: Liquid crystal element, 572: Light-emitting element, 6500: Touch panel module, 6501: Circuit unit, 6502: Signal line driving circuit, 6503: Sensor driving circuit, 6504: Detection circuit, 6505: Timing controller, 6506: Image processing circuit, 6507: AD conversion circuit, 6510: Touch panel, 6511: Display unit, 6512: Input unit, 6513: Scanning line driving circuit, 6520: IC, 6530: IC, 6531: Substrate, 6532: Counter substrate, 6533: FPC, 6534: PCB, 6540: CPU, 700 0: electronic device, 7001: housing, 7002: display unit, 7003: power button, 7004: button, 7005: speaker, 7006: microphone, 7007: camera, 7008: light source, 7010: protective member, 7011: display panel, 7012: optical member, 7013: touch sensor panel, 7015: FPC, 7016: IC, 7017: printed circuit board, 7018: battery, 7100: television device, 7101: housing, 7103: stand, 7111: remote control device, 7200: notebook personal computer, 7211: housing, 7212: keyboard,7213: Pointing device, 7214: External connection port, 7300: Digital signage, 7301: Housing, 7303: Speaker, 7311: Information terminal, 7400: Digital signage, 7401: Pillar, 7411: Information terminal, 9000: Housing, 9001: Display unit, 9002: Camera, 9003: Speaker, 9005: Operation keys, 9006: Connection terminal, 9007: Sensor, 9008: Microphone, 9050: Icon, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Hinge, 9101: Portable information terminal, 9102: Portable information terminal, 9103: Tablet terminal, 9200: Portable information terminal, 9201: Portable information terminal,

Claims

A semiconductor device comprising a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer, a first insulating layer, and a second insulating layer; the first insulating layer has an island shape and a first surface located on the first conductive layer; the first surface is a part of a side surface of the first insulating layer and has two or more regions whose normal directions are different from each other; the second conductive layer is located on the first insulating layer; the first semiconductor layer has a first portion in contact with an upper surface of the first conductive layer, a second portion in contact with an upper surface of the second conductive layer, and a third portion in contact with the first surface of the first insulating layer; the second insulating layer covers the third portion of the first semiconductor layer; the third conductive layer covers the third portion of the first semiconductor layer via the second insulating layer; Semiconductor device. 　 In claim 1, the first surface of the first insulating layer has two orthogonal planes on the first conductive layer; Semiconductor device. 　 In claim 1, the first surface of the first insulating layer has a curved shape on the first conductive layer; Semiconductor device. 　 In claim 1, the second insulating layer has an end coincident with an end of the third conductive layer; Semiconductor device. 　 In claim 1, A second semiconductor layer is provided. the first insulating layer has a second surface which is another part of the side surface and is located on the first conductive layer; the second semiconductor layer has a fourth portion in contact with the second surface; the second insulating layer covers the fourth portion of the second semiconductor layer; Semiconductor device. 　 In claim 5, the second semiconductor layer has a fifth portion in contact with an upper surface of the first conductive layer and a sixth portion in contact with an upper surface of the second conductive layer; Semiconductor device. 　 In claim 1, a second semiconductor layer and a fourth conductive layer; the first insulating layer has a third surface which is another part of the side surface and is located on the fourth conductive layer; the second semiconductor layer has a fifth portion in contact with an upper surface of the fourth conductive layer, a sixth portion in contact with an upper surface of the second conductive layer, and a seventh portion in contact with the third surface; the second insulating layer covers the seventh portion of the second semiconductor layer; Semiconductor device. 　 A semiconductor device according to any one of claims 1 to 7, and a liquid crystal element, the liquid crystal element includes a part of the second conductive layer, a liquid crystal, and a fifth conductive layer; the liquid crystal is located on the second conductive layer; The second conductive layer functions as a pixel electrode, The fifth conductive layer functions as a common electrode. Display device. In claim 8, a third insulating layer covering the second conductive layer, the third conductive layer, and the second insulating layer; Display device. 　 In claim 8, the second conductive layer has a region that does not overlap with the first insulating layer; The region functions as the pixel electrode. Display device. 　 a first conductive layer, a third conductive layer, a first semiconductor layer, a first insulating layer, a second insulating layer, and a liquid crystal element; the first insulating layer has an island shape and a first surface that is a part of a side surface and is located on the first conductive layer; the first semiconductor layer has a first portion in contact with an upper surface of the first conductive layer, a third portion in contact with the first surface of the first insulating layer, and an eighth portion located on the first insulating layer; the second insulating layer covers the third portion of the first semiconductor layer; the third conductive layer covers the third portion of the first semiconductor layer via the second insulating layer; the liquid crystal element includes a part of the first semiconductor layer, a liquid crystal, and a fifth conductive layer; the liquid crystal is located on the first semiconductor layer; A portion of the first semiconductor layer functions as a pixel electrode; The fifth conductive layer functions as a common electrode. Display device. 　 In claim 11, the first semiconductor layer has a ninth portion that does not overlap the first insulating layer; The ninth portion functions as the pixel electrode. Semiconductor device.

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