Drive circuit for high-side transistor, switching circuit, and controller circuit for dc / dc converter

Abstract

A drive circuit (300) for an n-type high-side transistor (MH) that is connected between an input line (102) and a switching line (104) comprises: a level-shift circuit (330) that shifts the level of an input signal (HIN); and a high-side driver (310) that drives the high-side transistor in accordance with an output of the level-shift circuit. The level-shift circuit shifts the level of the input signal and passes the input signal to the high-side driver. A first transistor (M1) and a second transistor (M2) constitutes a latch circuit (331). A seventh transistor (M7) is connected between a first node (N1) and the ground, and an eighth transistor (M8) is connected between a second node (N2) and the ground. A logic circuit (332) turns on a pair of a fifth transistor (M5) and the seventh transistor (M7) when the input signal is at a high level, and turns on a pair of a sixth transistor (M6) and the eighth transistor (M8) when the input signal is at a low level.

Description

High-side transistor drive circuits, switching circuits, DC / DC converter controller circuits

[0001] The present disclosure relates to a drive circuit for a high-side transistor.

[0002] 2. Description of the Related Art Switching circuits including power transistors and their drive circuits (gate drive circuits) are used in various applications such as DC / DC converters, power conversion devices, and motor drive circuits.

[0003] 1 is a circuit diagram of a switching circuit 100R. The switching circuit 100R includes a high-side transistor MH, a low-side transistor ML, a high-side driver circuit 200R, and a low-side driver circuit 110.

[0004] The high-side transistor MH is provided between an input terminal (or input line) IN and a switching terminal (or switching line) VS, and the low-side transistor ML is provided between the switching terminal VS and a ground terminal GND. The high-side driver circuit 200R drives the high-side transistor MH in response to a control input HIN, and the low-side driver circuit 110 drives the low-side transistor ML in response to a control input LIN.

[0005] When the high-side transistor MH is on and the low-side transistor ML is off, the input voltage V ＩＮ occurs, and when the high-side transistor MH is off and the low-side transistor ML is on, the switching terminal VS has a ground voltage V ＧＮＤ (0 V) is generated. While both the high-side transistor MH and the low-side transistor ML are off, the switching terminal VS is in a high impedance state. The switching circuit 100R switches between these three states to supply power to a load (not shown).

[0006] An N-type (N-channel) high-side transistor MH may be used. To turn on the high-side transistor MH and maintain the on state, a gate threshold voltage V of a FET (Field-Effect Transistor) is applied between the gate and source of the high-side transistor MH.ＧＳ（ｔｈ） When the high-side transistor MH is on, the voltage V of the switching line VS Ｓ , that is, the source voltage of the high-side transistor MH is the input voltage V ＩＮ Therefore, in order to keep the high-side transistor MH on, V ＩＮ +V ＧＳ（ｔｈ） A higher gate signal needs to be applied.

[0007] Input voltage V ＩＮ A bootstrap circuit is provided to generate a gate signal higher than the ＢＳＴ and a rectifying element D1. A bootstrap capacitor C ＢＳＴ is provided between the bootstrap terminal (or bootstrap line) VB and the switching terminal VS. A DC voltage V ＲＥＧ (>V ＧＳ（ｔｈ） ) is applied.

[0008] Switching voltage V Ｓ When is low (0V), the capacitor C ＢＳＴ is charged through the rectifying element D1, and the voltage across it is ΔV=V ＲＥＧ -Vf, where Vf is the voltage drop across the rectifier element D1. The switching voltage V Ｓ When increases, the voltage V at the bootstrap terminal VB Ｂ is V Ｂ =V Ｓ The voltage rises while maintaining +ΔV. The bootstrap circuit maintains the potential difference between the VB terminal and the VS terminal at ΔV.

[0009] The high-side drive circuit 200R includes a buffer (driver) 210 and a level shift circuit 220. The upper power supply terminal of the buffer 210 is connected to a voltage V Ｂ is supplied to its lower power supply terminal, and the voltage V Ｓ The buffer 210 is supplied with V Ｂ High, V ＳA gate voltage that makes the input terminal Vcc low is supplied to the gate of the high-side transistor MH.

[0010] The level shift circuit 220 shifts the logic level (V ＤＤ 0V) to change the binary control signal HIN to (V Ｂ ・V Ｓ ) into a binary intermediate signal LVSFTOUT. If the voltage drop of the diode D1 is ignored, V Ｂ ≒V Ｓ +V ＲＥＧ Therefore, the amplitude of the output LVSFTOUT of the level shift circuit 220 is V ＲＥＧ This becomes:

[0011] JP 2012-70333 A JP 2020-088842 A

[0012] [Overview] Input voltage V ＩＮ In applications where the voltage is several tens or more, or 100 V or more, a P-channel MOSFET with a DMOS (Double-Diffused MOS) structure having a high breakdown voltage is used for the level shift circuit. In this configuration, the low level of the output LVSFTOUT of the level shift circuit 220 is Ｓ +V ＧＳ（ｔｈ） The amplitude of the output LVSFTOUT of the level shift circuit 220 is V ＲＥＧ -V ＧＳ（ｔｈ） V ＧＳ（ｔｈ） is the gate-source threshold voltage of a P-channel MOSFET. Therefore, the DC voltage V ＲＥＧ When the voltage drops, the circuit operation becomes unstable.

[0013] The present disclosure has been made in view of the above-mentioned problems, and an exemplary purpose of an embodiment thereof is to provide a drive circuit that can accurately drive a high-side transistor.

[0014] An aspect of the present disclosure relates to a drive circuit for an N-type high-side transistor connected between an input line and a switching line. The drive circuit includes a level shift circuit that level-shifts an input signal and a high-side driver that drives the high-side transistor in response to an output of the level shift circuit. The level shift circuit includes a first P-type transistor connected between a bootstrap line and a first node, a second P-type transistor connected between the bootstrap line and a second node and cross-coupled with the first transistor, a third P-type transistor that is a high-voltage element and has its gate connected to the switching line and its source connected to the first node, a fourth P-type transistor that is a high-voltage element and has its gate connected to the switching line and its source connected to the second node, an N-type fifth transistor connected between the drain of the third transistor and a ground line, an N-type sixth transistor connected between the drain of the fourth transistor and the ground line, and a sixth N-type transistor connected between the first node and the ground line. an N-type seventh transistor which is a high-voltage element connected between the first node and the second node; an N-type eighth transistor which is a high-voltage element connected between the second node and the ground line; a logic circuit which turns on the pair of the fifth and seventh transistors when the input signal is at a high level and turns on the pair of the sixth and eighth transistors when the input signal is at a low level; and a first assist circuit which sources a first assist current to the second node in response to a first pulse signal which is based on a positive edge of the input signal which transitions from a low level to a high level, and which sources a second assist current to the first node in response to a second pulse signal which is based on a negative edge of the input signal which transitions from a high level to a low level.

[0015] Any combination of the above elements, or mutual substitution of elements or expressions between methods, devices, systems, etc., are also valid aspects of the present invention or the present disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention.

[0016] Fig. 1 is a circuit diagram of a switching circuit. Fig. 2 is a circuit diagram of a switching circuit according to an embodiment. Fig. 3 is an operational waveform diagram of the drive circuit of Fig. 2. Fig. 4 is a circuit diagram of a level shift circuit according to Modification 1. Fig. 5 is a circuit diagram of a level shift circuit according to Modification 2. Fig. 6 is a circuit diagram of a level shift circuit according to Modification 3. Fig. 7 is a circuit diagram of a controller circuit of a DC / DC converter. Fig. 8 is a circuit diagram of an inverter device including a drive circuit.

[0017] [DETAILED DESCRIPTION] (Summary of Embodiments) A summary of some exemplary embodiments of the present disclosure will be provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0018] A drive circuit according to one embodiment drives an N-type high-side transistor connected between an input line and a switching line. The drive circuit includes a level shift circuit that level-shifts an input signal, and a high-side driver that drives the high-side transistor in response to an output from the level shift circuit. The level shift circuit includes a P-type first transistor connected between a bootstrap line and a first node, a P-type second transistor connected between the bootstrap line and a second node and cross-coupled with the first transistor, a P-type third transistor that is a high-voltage element and has its gate connected to the switching line and its source connected to the first node, a P-type fourth transistor that is a high-voltage element and has its gate connected to the switching line and its source connected to the second node, an N-type fifth transistor connected between the drain of the third transistor and a ground line, an N-type sixth transistor connected between the drain of the fourth transistor and the ground line, and a P-type sixth transistor connected between the first node and the ground line. an N-type seventh transistor which is a high-voltage element connected between the first node and the second node; an N-type eighth transistor which is a high-voltage element connected between the second node and the ground line; a logic circuit which turns on the pair of the fifth and seventh transistors when the input signal is at a high level and turns on the pair of the sixth and eighth transistors when the input signal is at a low level; and a first assist circuit which sources a first assist current to the second node in response to a first pulse signal which is based on a positive edge of the input signal which transitions from a low level to a high level, and which sources a second assist current to the first node in response to a second pulse signal which is based on a negative edge of the input signal which transitions from a high level to a low level.

[0019] According to this configuration, the first assist circuit injects an assist current into the first node or the second node, thereby canceling out the current caused by parasitic capacitance. This accelerates the state transition of the latch circuit, which is composed of the cross-coupled first and second transistors, and the level shift circuit can transmit the input signal to the high-side driver at high speed. Furthermore, when the seventh transistor is on, current is drawn from the first node to ground, thereby lowering the voltage of the first node to near the voltage of the switching line. Similarly, when the eighth transistor is on, current is drawn from the second node to ground, thereby lowering the voltage of the second node to near the voltage of the switching line. This increases the amplitude of the signal generated at the first node and the second node, thereby improving the stability of the circuit when the potential difference between the bootstrap line and the switching line becomes small.

[0020] In one embodiment, the level shift circuit may further include a first resistor connected in series with the seventh transistor between the first node and a ground line, and a second resistor connected in series with the eighth transistor between the second node and a ground line. By providing the first resistor and the second resistor, the amount of steady-state current flowing through the seventh transistor and the eighth transistor can be reduced, thereby suppressing a decrease in efficiency.

[0021] In one embodiment, the first assist circuit may include an N-type ninth transistor which is a high-voltage element having a gate to which a first pulse signal is input, an N-type tenth transistor which is a high-voltage element having a gate to which a second pulse signal is input, a first current mirror circuit which mirrors the current flowing through the ninth transistor to generate a first assist current, and a second current mirror circuit which mirrors the current flowing through the tenth transistor to generate a second assist current.

[0022] In one embodiment, the level shift circuit may further include a second assist circuit that sinks a third assist current from the first node in response to the first pulse signal and a fourth assist current from the second node in response to the second pulse signal, which can further speed up the state transition of the latch circuit formed by the cross-coupled first and second transistors.

[0023] In one embodiment, the second assist circuit may include an N-type 11th transistor that is a high-voltage element, the gate of which receives a first pulse signal and the drain of which is connected to a first node, and an N-type 12th transistor that is a high-voltage element, the gate of which receives a second pulse signal and the drain of which is connected to a second node.

[0024] In one embodiment, the level shift circuit may further include a third assist circuit that sources a fifth assist current to the second node when the input signal is at a high level and a sixth assist current to the first node when the input signal is at a low level. The third assist circuit allows the latch circuit formed by the first transistor and the second transistor to restore its state if the state is erroneously inverted.

[0025] In one embodiment, the third assist circuit may include a 13th N-type transistor which is a high-voltage element that turns on when the input signal is at a high level, a 14th N-type transistor which is a high-voltage element that turns on when the input signal is at a low level, a third current mirror circuit that mirrors the current flowing through the 13th transistor to generate a fifth assist current, and a fourth current mirror circuit that mirrors the current flowing through the 14th transistor to generate a sixth assist current.

[0026] A switching circuit according to one embodiment may include a high-side transistor provided between an input line and a switching line, a low-side transistor provided between the switching line and a ground line, and the above-described drive circuit that drives the high-side transistor.

[0027] A controller circuit of a DC / DC converter according to one embodiment may include a pulse modulator that generates a pulse signal so that the output of the DC / DC converter approaches a target, and the above-described drive circuit that drives the N-type high-side transistor based on the pulse signal.

[0028] (Embodiments) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted where appropriate. Furthermore, the embodiments are illustrative and do not limit the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0029] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their connection.

[0030] Similarly, "a state in which component C is provided between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected to each other, but also a case in which they are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the functions or effects achieved by their combination.

[0031] Furthermore, "signal A (voltage, current) corresponds to signal B (voltage, current)" means that signal A has a correlation with signal B, and specifically means (i) when signal A is signal B, (ii) when signal A is proportional to signal B, (iii) when signal A is obtained by level-shifting signal B, (iv) when signal A is obtained by amplifying signal B, (v) when signal A is obtained by inverting signal B, (vi) or any combination thereof. Those skilled in the art will understand that the scope of "corresponding to" is determined depending on the types and applications of signals A and B.

[0032] 2 is a circuit diagram of a switching circuit 100 according to an embodiment. The switching circuit 100 mainly includes a high-side transistor MH, a low-side transistor ML, and a drive circuit 300. The drive circuit 300 is an integrated circuit (IC) in which components are integrated on a semiconductor chip.

[0033] The high-side transistor MH is an N-channel or NPN type (collectively referred to as N-type) transistor, and is provided between the input line 102 and the switching line 104. The low-side transistor ML is of the same type as the high-side transistor MH, and is connected between the switching line 104 and the ground line. The input line 102 is supplied with an input voltage V ranging from several tens of volts to over 100 volts. ＩＮ is supplied.

[0034] The drive circuit 300 drives the high-side transistor MH and the low-side transistor ML. The drive circuit 300 includes a bootstrap pin VB, a high-side gate pin HG, a switching pin VS, a low-side gate pin LG, and a ground pin GND. A bootstrap capacitor C is connected between the bootstrap pin VB and the switching pin VS. ＢＳＴ The high-side gate pin HG is connected to the gate of the high-side transistor MH, and the low-side gate pin LG is connected to the gate of the low-side transistor ML.

[0035] The drive circuit 300 includes a bootstrap line 302, a switching line 304, a high-side driver 310, a low-side driver 320, a level shift circuit 330, and a rectifying element D1.

[0036] The bootstrap line 302 is connected to the bootstrap pin VB, and the switching line 304 is connected to the switching pin VS. A DC voltage V stabilized to a predetermined voltage level is supplied to the bootstrap line 302 via a rectifier element D1. ＲＥＧ For example, this DC voltage V ＲＥＧ is the power supply voltage V of about 5V ＤＤThe rectifying element D1 may be a diode or a switch that is switched on and off in conjunction with the switching of the switching circuit 100.

[0037] The high-side driver 310 drives the high-side transistor MH in response to an input signal HIN. The input signal HIN is connected to a power supply voltage V ＤＤ is a binary signal with a high level and a ground voltage (0 V) as a low level. In this embodiment, when the input signal HIN is high, the high-side transistor MH is on, and when the input signal HIN is low, the high-side transistor MH is off. Similarly, the low-side driver 320 drives the low-side transistor ML in response to the input signal LIN.

[0038] The level shift circuit 330 level-shifts the input signal HIN and supplies it to the high-side driver 310. The high-side driver 310 drives the high-side transistor MH in accordance with the output of the level shift circuit 330. The high-side driver 310 includes a logic circuit 312 and a buffer 314. The logic circuit 312 shifts the level of the output signal V Ｎ１ , V Ｎ２ The state of the buffer 314 is controlled based on the

[0039] The level shift circuit 330 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a first assist circuit 340, a logic circuit 332, and a pulse generator 334.

[0040] The first transistor M1 and the second transistor M2 are P-channel MOSFETs that are cross-coupled to form a latch circuit 331. The sources of the first transistor M1 and the second transistor M2 are connected to a bootstrap line 302. The drain of the first transistor M1 and the gate of the second transistor M2 are connected to a first node N1. The drain of the second transistor M2 and the gate of the first transistor M1 are connected to a second node N2. The first node N1 and the second node N2 are output nodes of the level shift circuit 330, and each of them outputs a voltage V Ｎ１ , V Ｎ２ is the output signal of the level shift circuit 330.

[0041] The third transistor M3 and the fourth transistor M4 are P-channel MOSFETs that are high-voltage elements. The gates of the third transistor M3 and the fourth transistor M4 are connected to the switching line 304. The source of the third transistor M3 is connected to the first node N1, and the source of the fourth transistor M4 is connected to the second node N2. A diode D3 is connected between the gate and source of the third transistor M3, and a diode D4 is connected between the gate and source of the fourth transistor M4.

[0042] As the high-voltage element, a transistor with a DMOS (Double-Diffused MOS) structure is suitable, but transistors with other structures, such as HVMOS (High Voltage MOSFET), LDMOS (Lateral Diffusion MOSFET), IGBT (Insulated Gate Bipolar Transistor), SiC (Silicon Carbide)-JFET, SIC-MOSFET, etc. may also be used. Other transistors not specifically specified as high-voltage elements are MOSFETs with normal voltage resistance.

[0043] The fifth transistor M5 and the sixth transistor M6 are N-channel MOSFETs. The fifth transistor M5 is connected between the drain of the third transistor M3 and the ground line 306. The sixth transistor M6 is connected between the drain of the fourth transistor M4 and the ground line.

[0044] The seventh transistor M7 and the eighth transistor M8 are N-channel MOSFETs that are high-voltage elements. The seventh transistor M7 is connected between the first node N1 and the ground line. The eighth transistor M8 is connected between the second node N2 and the ground line. The sizes (gate width / gate length ratio W / L) of the seventh transistor M7 and the eighth transistor M8 are smaller than the sizes of the fifth transistor M5 and the sixth transistor M6. In other words, the capabilities of the seventh transistor M7 and the eighth transistor M8 are designed to be lower than the capabilities of the fifth transistor M5 and the sixth transistor M6.

[0045] For example, when the size of the fifth transistor M5 and the sixth transistor M6 is 100, the size of the first transistor M1 and the second transistor M2 may be about 20 to 600. Also, the size of the seventh transistor M7 and the eighth transistor M8 may be about 5 to 200.

[0046] The logic circuit 332 turns on the pair of the fifth transistor M5 and the seventh transistor M7 when the input signal HIN is at a high level, and turns on the pair of the sixth transistor M6 and the eighth transistor M8 when the input signal HIN is at a low level.

[0047] The pulse generator 334 generates a first pulse signal Sp1 and a second pulse signal Sp2 based on the input signal HIN. The first pulse signal Sp1 is a one-shot pulse that starts at a positive edge of the input signal HIN that transitions from low level to high level, and the second pulse signal Sp2 is a one-shot pulse that starts at a negative edge of the input signal HIN that transitions from high level to low level.

[0048] The configuration of the pulse generator 334 is not particularly limited and can be configured using known technology. Instead of inputting the input signal HIN to the pulse generator 334, the gate signal of the fifth transistor M5 and the gate signal of the sixth transistor M6 generated by the logic circuit 332 may be input. In this case, the pulse generator 334 may generate a one-shot pulse whose starting point is the positive edge of the gate signal of the fifth transistor M5 as the first pulse signal Sp1, and may generate a one-shot pulse whose starting point is the positive edge of the gate signal of the sixth transistor M6 as the second pulse signal Sp2.

[0049] The first assist circuit 340 sources a first assist current Ia1 to the second node N2 in response to the first pulse signal Sp1, and sources a second assist current Ia2 to the first node N1 in response to the second pulse signal Sp2.

[0050] The first assist circuit 340 includes a ninth transistor M9 and a tenth transistor M10, which are N-channel MOSFETs serving as high-voltage elements, and a first current mirror circuit CM1 and a second current mirror circuit CM2, which are P-channel MOSFETs. A first pulse signal Sp1 is input to the gate of the ninth transistor M9, and a second pulse signal Sp2 is input to the gate of the tenth transistor M10. The first current mirror circuit CM1 mirrors the current flowing through the ninth transistor M9 to generate a first assist current Ia1. The second current mirror circuit CM2 mirrors the current flowing through the tenth transistor M10 to generate a second assist current Ia2.

[0051] When the size of the fifth transistor M5 and the sixth transistor M6 is 100, the size of the ninth transistor M9 and the tenth transistor M10 may be about 30 to 100.

[0052] The above is the configuration of the drive circuit 300. Next, the operation of the drive circuit 300 will be described.

[0053] 3 is an operation waveform diagram of the drive circuit 300 of FIG. 3. FIG. 3 shows the input signal HIN, the states of the transistors M5 and M7, the states of the transistors M6 and M8, the first pulse signal Sp1, the second pulse signal Sp2, the first assist current Ia1, the second assist current Ia2, and the current I flowing through the fifth transistor M5. Ｍ５ , the current I flowing through the seventh transistor M7 Ｍ７ , the current I flowing through the sixth transistor M6 Ｍ６ , the current I flowing through the eighth transistor M8 Ｍ８ , the voltage V of the first node N1 Ｎ１ , the voltage V of the second node N2 Ｎ２ is shown.

[0054] The voltage V of the first node N1 Ｎ１ and the voltage V of the second node N2 Ｎ２ The waveform of the switching voltage V Ｓ In reality, the switching voltage V Ｓ is 0V and V ＩＮ Note that the switching between

[0055] Time t ０ In this case, the input signal HIN transitions from a low level to a high level. In response to this transition, the logic circuit 332 turns on the fifth transistor M5 and the seventh transistor M7. When the fifth transistor M5 is turned on, a current I flows from the first node N1 through the third transistor M3 and the fifth transistor M5. Ｍ５ This current I Ｍ５ The potential V of the first node N1 is Ｎ１ At this time, the seventh transistor M7 is also on, so the current I Ｍ７ However, since the performance of the seventh transistor M7 is lower than that of the fifth transistor M5, the potential V Ｎ１ It can be said that the ability to reduce

[0056] The potential of the first node N1 is V Ｓ +V ＧＳ（ｔｈ） When the voltage drops to , the third transistor M3 turns off, and the current I Ｍ５is essentially zero.

[0057] The second node N2 has a parasitic capacitance of the fourth transistor M4. To cause the latch circuit 331 to transition between states, the voltages V Ｎ１ and V Ｎ２ Here, the parasitic capacitance of the fourth transistor M4 is the voltage V Ｎ２ The pulse generator 334 prevents the rise of ０ In response to the positive edge of the input signal HIN at the ninth transistor M4, the ninth transistor M9 generates a first pulse signal Sp1. In response to the first pulse signal Sp1, the ninth transistor M9 turns on, and a pulse-like first assist current Ia1 is supplied to the second node N2. The first assist current Ia1 charges the parasitic capacitance of the fourth transistor M4, thereby increasing the potential V Ｎ２ That is, the first assist current Ia1 accelerates the transition of the latch circuit 331 made up of the first transistor M1 and the second transistor M2.

[0058] After the state transition of the latch circuit 331, the seventh transistor M7 remains on even after the third transistor M3 is turned off. Ｍ７ , charges are extracted from the first node N1, and the potential V Ｎ１ is V Ｓ +V ＧＳ（ｔｈ） The potential V of the first node N1 decreases to a voltage level lower than Ｎ１ V Ｓ When the potential V falls to −Vf, the potential V Ｎ１ is clamped by diode D3, and Vf is the forward voltage of diode D3.

[0059] Time t １ In this case, the input signal HIN transitions from a high level to a low level. In response to this transition, the logic circuit 332 turns on the sixth transistor M6 and the eighth transistor M8. When the sixth transistor M6 is turned on, a current I flows from the second node N2 through the fourth transistor M4 and the sixth transistor M6. Ｍ６ This current IＭ６ The potential V of the second node N2 Ｎ２ At this time, the eighth transistor M8 is also on, so the current I Ｍ８ However, since the performance of the eighth transistor M8 is lower than that of the sixth transistor M6, the potential V Ｎ２ It can be said that the ability to reduce

[0060] The potential of the second node N2 is V Ｓ +V ＧＳ（ｔｈ） When the voltage drops to , the fourth transistor M4 turns off, and the current I Ｍ６ is essentially zero.

[0061] The first node N1 also has a parasitic capacitance of the third transistor M3, and this parasitic capacitance is Ｎ１ The pulse generator 334 prevents the rise of １ In response to the negative edge of the input signal HIN at the node N1, the tenth transistor M10 is turned on to generate a second pulse signal Sp2. In response to the second pulse signal Sp2, the tenth transistor M10 is turned on to supply a pulsed second assist current Ia2 to the first node N1. The second assist current Ia2 charges the parasitic capacitance of the third transistor M3, thereby increasing the potential V Ｎ１ That is, the second assist current Ia2 accelerates the transition of the latch circuit 331 formed by the first transistor M1 and the second transistor M2.

[0062] After the state transition of the latch circuit 331, the eighth transistor M8 remains on even after the fourth transistor M4 is turned off. Ｍ８ As a result, charges are extracted from the second node N2, and the potential V Ｎ２ is V Ｓ +V ＧＳ（ｔｈ） The potential V of the second node N2 decreases to a voltage level lower than Ｎ２ V Ｓ When the potential V falls to −Vf, the potential V Ｎ２is clamped by diode D4. Vf is the forward voltage of diode D3.

[0063] The above is the operation of the drive circuit 300. According to this drive circuit 300, the first assist circuit 340 injects the assist currents Ia1 and Ia2 into the first node N1 or the second node N2, thereby accelerating the state transition of the latch circuit 331. This allows the level shift circuit 330 to transmit the input signal HIN to the high-side driver 310 at high speed.

[0064] In this drive circuit 300, when the input signal HIN is at a high level, even after the third transistor M3 is turned off, a current can be extracted from the first node N1 to the ground via the seventh transistor M7. As a result, the voltage V Ｎ１ the voltage V of the switching line Ｓ Specifically, up to the vicinity of V Ｓ Similarly, when the input signal HIN is at a low level, even after the fourth transistor M4 is turned off, a current can be drawn from the second node N2 to the ground via the eighth transistor M8. This reduces the voltage V of the second node N2. Ｎ２ the voltage V of the switching line Ｓ This makes it possible to widen the amplitude of the output signal generated at the first node and the second node, thereby improving the stability of the circuit when the potential difference between the bootstrap line 302 and the switching line 304 becomes small.

[0065] Next, a modification of the level shift circuit 330 will be described.

[0066] 4 is a circuit diagram of a level shift circuit 330A according to Modification 1. The level shift circuit 330A includes a first resistor R1 and a second resistor R2 in addition to the components of the level shift circuit 330 in FIG. 2. The first resistor R1 is connected in series with the seventh transistor M7 between the first node N1 and the ground line 306. The second resistor R2 is connected in series with the eighth transistor M8 between the second node N2 and the ground line 306.

[0067] The first resistor R1 and the second resistor R2 cause a steady current I to flow through the seventh transistor M7 and the eighth transistor M8. Ｍ７ , I Ｍ８ This reduces the amount of current flowing through the inverter, thereby preventing a decrease in efficiency.

[0068] 5 is a circuit diagram of a level shift circuit 330B according to Modification 2. The level shift circuit 330B has a configuration in which a second assist circuit 342 is added to the level shift circuit 330 in FIG.

[0069] The second assist circuit 342 sinks the third assist current Ia3 from the first node N1 in response to the first pulse signal Sp1, and sinks the fourth assist current Ia4 from the second node N2 in response to the second pulse signal Sp2.

[0070] The second assist circuit 342 includes an eleventh transistor M11 and a twelfth transistor M12, which are N-channel MOSFETs that are high-voltage elements. The eleventh transistor M11 receives the first pulse signal Sp1 at its gate and has a drain connected to the first node N1. The twelfth transistor M12 receives the second pulse signal Sp2 at its gate and has a drain connected to the second node N2.

[0071] When the size of the fifth transistor M5 and the sixth transistor M6 is 100, the size of the eleventh transistor M11 and the twelfth transistor M12 may be about 30 to 100.

[0072] The above is the configuration of the level shift circuit 330B. With this level shift circuit 330B, immediately after the input signal HIN transitions from a low level to a high level, the current I Ｍ５ In addition, the third assist current Ia3 flowing through the eleventh transistor M11 increases the potential V Ｎ１ This allows the transition of the latch circuit 331 to be accelerated.

[0073] Similarly, immediately after the input signal HIN transitions from a high level to a low level, the current I flowing through the sixth transistor M6 Ｍ６In addition, the fourth assist current Ia4 flowing through the twelfth transistor M12 increases the potential V Ｎ２ This allows the transition of the latch circuit 331 to be accelerated.

[0074] The potential difference V between the bootstrap line 302 and the switching line 304 Ｂ -V Ｓ When the DC voltage V ＲＥＧ When the voltage V of the bootstrap line 302 decreases (referred to as a reduced voltage state), the drain-source voltage of the transistors of the current mirror circuits CM1 and CM2 of the first assist circuit 340 decreases, which may slow down the operation speed of the first assist circuit 340 and lengthen the delay time of the level shift circuit 330. Ｂ Therefore, by providing the second assist circuit 342, it is possible to prevent the delay time of the level shift circuit 330B from becoming long in a reduced voltage state.

[0075] A second assist circuit 342 may be added to the level shift circuit 330A of the first modified example.

[0076] 6 is a circuit diagram of a level shift circuit 330C according to Modification 3. The level shift circuit 330C has a configuration in which a third assist circuit 344 is added to the level shift circuit 330 in FIG. 2. The third assist circuit 344 sources a fifth assist current Ia5 to the second node N2 when the input signal HIN is at a high level, and sources a sixth assist current Ia6 to the first node N1 when the input signal HIN is at a low level.

[0077] The third assist circuit 344 may include a third transistor M13, a fourteenth transistor M14, a third current mirror circuit CM3, and a fourth current mirror circuit CM4. The third transistor M13 and the fourteenth transistor M14 are P-channel MOSFETs that are high-voltage elements and are controlled by the logic circuit 332. The thirteenth transistor M13 is turned on when the input signal HIN is at a high level. The fourteenth transistor M14 is turned on when the input signal HIN is at a low level. The third current mirror circuit CM3 reflects the current flowing through the thirteenth transistor M13 to generate a fifth assist current Ia5. The fourth current mirror circuit CM4 reflects the current flowing through the fourteenth transistor M14 to generate a sixth assist current Ia6.

[0078] The sizes (current supply capabilities) of the thirteenth transistor M13 and the fourteenth transistor M14 are desirably designed to be smaller than the sizes of the ninth transistor M9 and the tenth transistor M10. When the sizes of the fifth transistor M5 and the sixth transistor M6 are 100, the sizes of the ninth transistor M9 and the tenth transistor M10 can be approximately 30 to 100, and the sizes of the thirteenth transistor M13 and the fourteenth transistor M14 can be approximately 0.1 to 5.

[0079] Similar to the resistors R1 and R2 in FIG. 4, in FIG. 6, current limiting resistors may be inserted in series with the thirteenth transistor M13 and the fourteenth transistor M14, respectively.

[0080] The above is the configuration of the level shift circuit 330C. Next, the operation of the level shift circuit 330C will be described.

[0081] 2, if the state of the latch circuit 331 is inverted due to switching noise or the influence of parasitic elements, the inverted state of the latch circuit 331 is maintained until the next switching cycle, causing the high-side transistor MH to be driven in an incorrect state. To solve this problem, it is necessary to increase the drive capabilities of the seventh transistor M7 and the eighth transistor M8. However, if these transistors are configured as DMOS transistors, increasing the drive capabilities requires increasing the device size. In contrast, the level shift circuit 330C of FIG. 6 adds a third assist circuit 344, which allows the latch circuit 331 to return to the correct state from the erroneously inverted state while minimizing increases in the size of the seventh transistor M7 and the eighth transistor M8.

[0082] (Applications) Next, applications of the drive circuit 300 will be described. The drive circuit 300 can be used in a DC / DC converter. Fig. 7 is a circuit diagram of a controller circuit 400 of a DC / DC converter 500. The DC / DC converter 500 is a synchronous rectification type step-down (buck) converter, and includes capacitors C1 and C2 and an inductor L1 in addition to the controller circuit 400.

[0083] The controller circuit 400 includes a high-side transistor MH, a low-side transistor ML, a pulse modulator 410, a low-side drive circuit 420, and a drive circuit (high-side drive circuit) 300. The pulse modulator 410 generates pulse signals HIN and LIN so that the output (output voltage, output current, or load state) of the DC / DC converter 500 approaches a target. For example, the pulse modulator 410 generates pulse signals HIN and LIN such that the output voltage V ＯＵＴ to the target voltage V ＲＥＦ (constant voltage control), or the output current I ＯＵＴ The target current I ＲＥＦ (constant current control).

[0084] The high-side driver circuit 300 drives an N-channel or NPN-type high-side transistor MH based on a pulse signal HIN, and the low-side driver circuit 420 drives a low-side transistor ML based on a pulse signal LIN.

[0085] The drive circuit 300 can be used in an inverter device. FIG. 8 is a circuit diagram of an inverter device 600 including the drive circuit 300. The inverter device 600 includes a three-phase inverter 610 and U-phase, V-phase, and W-phase drive circuits 620U, 620V, and 620W. The three-phase inverter 610 includes high-side transistors MHU, MHV, and MHW, and low-side transistors MLU, MLV, and MLW. The drive circuit 620# (#=U, V, W) includes a high-side drive circuit 300 and a low-side drive circuit 630.

[0086] The above is a description of an embodiment. This embodiment is merely an example, and it will be understood by those skilled in the art that various modifications are possible in the combination of each component and each treatment process, and that such modifications are also within the scope of the present invention. These modifications will be described below.

[0087] In the embodiment, the high-side transistor MH has been described as an N-channel MOSFET, but it may be an NPN-type bipolar transistor or an IGBT. In this case, the gate, source, and drain should be read as a base, emitter, and drain.

[0088] In the embodiment, the high-side transistor MH is a discrete component externally attached to the IC of the drive circuit 300. However, the high-side transistor MH may be integrated on the same semiconductor substrate (chip) as the drive circuit 300.

[0089] 7, the low-side transistor ML may be replaced with a diode. Furthermore, the topology of the DC / DC converter 500 is not limited to a step-down type, and may be another type including a high-side transistor.

[0090] The application of the switching circuit 100 is not limited to DC / DC converters and inverter devices, but may also be applied to, for example, bidirectional converters, battery charging circuits, and class D amplifiers for audio.

[0091] The embodiments merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted to the embodiments as long as they do not deviate from the spirit of the present invention as defined in the claims.

[0092] [Additional Note] One aspect of the technology disclosed in this specification can be understood as follows.

[0093] (Item 1) A drive circuit for an N-type high-side transistor connected between an input line and a switching line, comprising: a level shift circuit that level-shifts an input signal; and a high-side driver that drives the high-side transistor in accordance with an output of the level shift circuit, wherein the level shift circuit comprises: a P-type first transistor connected between a bootstrap line and a first node; a P-type second transistor connected between the bootstrap line and a second node and cross-coupled with the first transistor; a P-type third transistor that is a P-type high-voltage element and has its gate connected to the switching line and its source connected to the first node; a P-type fourth transistor that is a P-type high-voltage element and has its gate connected to the switching line and its source connected to the second node; an N-type fifth transistor connected between the drain of the third transistor and a ground line; an N-type sixth transistor connected between the drain of the fourth transistor and the ground line; an N-type seventh transistor that is a high-voltage element and is connected between the first node and the ground line; and an N-type eighth transistor that is a high-voltage element and is connected between the second node and the ground line. a logic circuit that turns on the pair of the fifth and seventh transistors when the input signal is at a high level, and turns on the pair of the sixth and eighth transistors when the input signal is at a low level; and a first assist circuit that sources a first assist current to the second node in response to a first pulse signal based on a positive edge of the input signal transitioning from the low level to the high level, and sources a second assist current to the first node in response to a second pulse signal based on a negative edge of the input signal transitioning from the high level to the low level.

[0094] (Item 2) The drive circuit according to item 1, wherein the level shift circuit further includes: a first resistor connected in series with the seventh transistor between the first node and the ground line; and a second resistor connected in series with the eighth transistor between the second node and the ground line.

[0095] (Item 3) The drive circuit according to item 1 or 2, wherein the first assist circuit includes: an N-type ninth transistor that is a high-voltage element and has a gate to which the first pulse signal is input; an N-type tenth transistor that is a high-voltage element and has a gate to which the second pulse signal is input; a first current mirror circuit that mirrors the current flowing through the ninth transistor to generate the first assist current; and a second current mirror circuit that mirrors the current flowing through the tenth transistor to generate the second assist current.

[0096] (Item 4) The drive circuit of any one of items 1 to 3, wherein the level shift circuit further includes a second assist circuit that sinks a third assist current from the first node in response to the first pulse signal and sinks a fourth assist current from the second node in response to the second pulse signal.

[0097] (Item 5) The drive circuit described in Item 4, wherein the second assist circuit includes: an N-type eleventh transistor that is a high-voltage element, the gate of which receives the first pulse signal and the drain of which is connected to the first node; and an N-type twelfth transistor that is a high-voltage element, the gate of which receives the second pulse signal and the drain of which is connected to the second node.

[0098] (Item 6) A drive circuit described in any one of items 1 to 5, wherein the level shift circuit further includes a third assist circuit that sources a fifth assist current to the second node when the input signal is at the high level, and sources a sixth assist current to the first node when the input signal is at the low level.

[0099] (Item 7) The third assist circuit of the drive circuit described in Item 6 includes: an N-type thirteenth transistor that is a high-voltage element that turns on when the input signal is at the high level; an N-type fourteenth transistor that is a high-voltage element that turns on when the input signal is at the low level; a third current mirror circuit that mirrors the current flowing through the thirteenth transistor to generate the fifth assist current; and a fourth current mirror circuit that mirrors the current flowing through the fourteenth transistor to generate the sixth assist current.

[0100] (Item 8) A switching circuit comprising: a high-side transistor provided between an input line and a switching line; a low-side transistor provided between the switching line and a ground line; and a drive circuit according to any one of items 1 to 7 that drives the high-side transistor.

[0101] (Item 9) A controller circuit for a DC / DC converter, comprising: a pulse modulator that generates a pulse signal so that an output of the DC / DC converter approaches a target; and a drive circuit according to any one of items 1 to 7 that drives an N-type high-side transistor based on the pulse signal.

[0102] The present invention relates to a drive circuit for a high-side transistor.

[0103] 100 Switching circuit 102 Input line 104 Switching line 106 Ground line MH High-side transistor ML Low-side transistor 300 Drive circuit 302 Bootstrap line 304 Switching line 310 High-side driver 312 Logic circuit 314 Buffer 320 Low-side driver 330 Level shift circuit N1 First node N2 Second node M1 First transistor M2 Second transistor M3 Third transistor M4 Fourth transistor M5 Fifth transistor M6 Sixth transistor M7 Seventh transistor M8 Eighth transistor M9 Ninth transistor M10 Tenth transistor M11 Eleventh transistor M12 Twelfth transistor M13 Thirteenth transistor M14 Fourteenth transistor CM1 First current mirror circuit CM2 Second current mirror circuit CM3 Third current mirror circuit CM4 Fourth current mirror circuit 332 Logic circuit 334 Pulse generator 340 First assist circuit 342 Second assist circuit 344 Third assist circuit D1 Rectifying element C ＢＳＴ Bootstrap capacitor R1: First resistor R2: Second resistor 400: Controller circuit 410: Pulse modulator 420: Low-side driver circuit 500: DC / DC converter

Claims

1. A drive circuit for an N-type high-side transistor connected between an input line and a switching line, comprising: a level shift circuit that level-shifts an input signal; and a high-side driver that drives the high-side transistor in response to an output of the level shift circuit, wherein the level shift circuit comprises: a P-type first transistor connected between a bootstrap line and a first node; a P-type second transistor connected between the bootstrap line and a second node and cross-coupled with the first transistor; a P-type third transistor that is a P-type high-voltage element having a gate connected to the switching line and a source connected to the first node; a P-type fourth transistor that is a P-type high-voltage element having a gate connected to the switching line and a source connected to the second node; an N-type fifth transistor connected between the drain of the third transistor and a ground line; an N-type sixth transistor connected between the drain of the fourth transistor and the ground line; an N-type seventh transistor that is a high-voltage element connected between the first node and the ground line; a logic circuit that turns on a pair of the fifth transistor and the seventh transistor when the input signal is at a high level, and turns on a pair of the sixth transistor and the eighth transistor when the input signal is at a low level; and a first assist circuit that sources a first assist current to the second node in response to a first pulse signal based on a positive edge of the input signal transitioning from the low level to the high level, and sources a second assist current to the first node in response to a second pulse signal based on a negative edge of the input signal transitioning from the high level to the low level.

2. The drive circuit of claim 1, wherein the level shift circuit further includes: a first resistor connected in series with the seventh transistor between the first node and the ground line; and a second resistor connected in series with the eighth transistor between the second node and the ground line.

3. The drive circuit of claim 1 or 2, wherein the first assist circuit includes: a 9th N-type transistor which is a high-voltage element having a gate to which the first pulse signal is input; a 10th N-type transistor which is a high-voltage element having a gate to which the second pulse signal is input; a first current mirror circuit which mirrors the current flowing through the 9th transistor to generate the first assist current; and a second current mirror circuit which mirrors the current flowing through the 10th transistor to generate the second assist current.

4. The drive circuit of claim 1 or 2, wherein the level shift circuit further includes a second assist circuit that sinks a third assist current from the first node in response to the first pulse signal and sinks a fourth assist current from the second node in response to the second pulse signal.

5. The drive circuit of claim 4, wherein the second assist circuit includes: an N-type eleventh transistor which is a high-voltage element and has its gate receiving the first pulse signal and its drain connected to the first node; and an N-type twelfth transistor which is a high-voltage element and has its gate receiving the second pulse signal and its drain connected to the second node.

6. The drive circuit of claim 1 or 2, wherein the level shift circuit further includes a third assist circuit that sources a fifth assist current to the second node when the input signal is at the high level, and sources a sixth assist current to the first node when the input signal is at the low level.

7. The drive circuit of claim 6, wherein the third assist circuit includes: a thirteenth N-type transistor which is a high-voltage element that is turned on when the input signal is at the high level; a fourteenth N-type transistor which is a high-voltage element that is turned on when the input signal is at the low level; a third current mirror circuit that mirrors the current flowing through the thirteenth transistor to generate the fifth assist current; and a fourth current mirror circuit that mirrors the current flowing through the fourteenth transistor to generate the sixth assist current.

8. A switching circuit comprising: a high-side transistor provided between an input line and a switching line; a low-side transistor provided between the switching line and a ground line; and a drive circuit according to claim 1 or 2 that drives the high-side transistor.

9. A controller circuit for a DC / DC converter, comprising: a pulse modulator that generates a pulse signal so that an output of the DC / DC converter approaches a target; and a drive circuit according to claim 1 or 2 that drives an N-type high-side transistor based on the pulse signal.

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