Sawtooth wave generating device, pulse generating device, and semiconductor manufacturing device

Abstract

The present invention relates to a sawtooth wave generating device, a pulse generating device, and a semiconductor manufacturing device and provides the sawtooth wave generating device including: a high voltage pulse generating device for generating a high voltage pulse; a pulse generating device including a sawtooth wave generating device for adding a sawtooth wave component to a high voltage pulse to generate a pulse signal; and a plurality of power module circuits connected to each other in series and controlled by sawtooth control signals, wherein each of the plurality of power module circuits includes a voltage source path in which an input terminal and an output terminal are connected through a voltage source and a bypass path in which an input terminal and an output terminal are connected by bypassing the voltage source, and depending on the level of a corresponding sawtooth control signal among the sawtooth control signals, one of the voltage source path and the bypass path is activated.

Description

Sawtooth wave generator, pulse generator and semiconductor manufacturing device

[0001] This patent document relates to a device for generating a pulse signal used in a semiconductor manufacturing device using plasma.

[0002]

[0003] Reducing semiconductor production costs requires wafer pattern miniaturization and high etch rates under identical chamber size conditions. However, conventional pulse generators installed in plasma semiconductor equipment provide two-level unipolar output, which limits the ability to achieve wafer pattern miniaturization and high etch rates.

[0004] In addition, the existing pulse output circuit has a problem of generating switching loss by performing hard switching operation.

[0005]

[0006] The main purpose of embodiments of the present invention is to provide a device for generating a high voltage pulse signal that can be used in a semiconductor manufacturing device.

[0007] The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

[0008]

[0009] A pulse generator according to one embodiment of the present invention may include a high voltage pulse generator that generates a high voltage pulse; and a sawtooth wave generator that generates a pulse signal by adding a sawtooth wave component to the high voltage pulse.

[0010] A sawtooth wave generator according to one embodiment of the present invention comprises a plurality of power module circuits connected in series and controlled by sawtooth wave control signals, each of the plurality of power module circuits including a voltage source path through which an input terminal and an output terminal are connected via a voltage source; and a bypass path through which the input terminal and the output terminal are connected by bypassing the voltage source, wherein one of the voltage source path and the bypass path can be activated depending on the level of a corresponding sawtooth wave control signal among the sawtooth wave control signals.

[0011] A semiconductor manufacturing device according to one embodiment of the present invention includes a pulse generating device and a chamber, wherein the pulse generating device includes a high-voltage pulse generating device that generates a high-voltage pulse; and a sawtooth wave generating device that generates a pulse signal by adding a sawtooth wave component to the high-voltage pulse, and the pulse signal generated by the pulse generating device can be used to generate plasma within the chamber.

[0012]

[0013] According to embodiments of the present invention, by providing a bipolar output to the chamber, pattern refinement and high etching rate of the wafer can be obtained under the same chamber size conditions.

[0014] Additionally, by performing soft switching operation on the pulse output circuit, there is an effect of reducing the occurrence of switching loss.

[0015] Additionally, by adding a sawtooth wave component to the pulse signal, the wafer voltage can be kept constant, thereby increasing the etching efficiency.

[0016] The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

[0017]

[0018] FIG. 1 is a drawing showing a high-voltage pulse generator (100) and a capacitive load (200) according to a first embodiment of the present invention.

[0019] FIG. 2 is a drawing showing an output waveform of a high-voltage pulse generator (100) according to the first embodiment.

[0020] FIGS. 3A to 3D are drawings for explaining the operating state in each mode in the output waveform of the high-voltage pulse generator (100) according to the first embodiment.

[0021] Fig. 4 is a block diagram showing a high-voltage pulse generator (400) and a capacitive load (200) according to the second embodiment.

[0022] FIG. 5 is a drawing showing an output waveform of a high-voltage pulse generator (400) according to the second embodiment.

[0023] FIGS. 6A to 6E are drawings for explaining the operating state in each mode in the output waveform of the high-voltage pulse generator (400) according to the second embodiment.

[0024] FIG. 7a is a drawing showing a high-voltage pulse generator (700a) and a capacitive load (200) according to a third embodiment of the present invention.

[0025] FIG. 7b is a drawing showing a classical pulse generator (700b) and a capacitive load (200) according to a fourth embodiment of the present invention.

[0026] FIG. 8a is a drawing showing a high-voltage pulse generator (800a) and a capacitive load (200) according to a fifth embodiment of the present invention.

[0027] FIG. 8b is a drawing showing a high-voltage pulse generator (800b) and a capacitive load (200) according to the sixth embodiment of the present invention.

[0028] Figure 9 is a configuration diagram of a pulse generating device (900) according to one embodiment of the present invention.

[0029] FIG. 10 is a drawing illustrating a semiconductor manufacturing device (100) according to one embodiment of the present invention.

[0030] FIG. 11 is a diagram showing the voltage of the pulse signal (Vout) output from the pulse generator (900) of FIG. 10 and the voltage (VW) of the wafer (W) of the chamber (200).

[0031] FIG. 12 is a diagram showing the waveform of a pulse signal (Vout) that must be applied to the chamber (200) to maintain the wafer voltage (VW) constant.

[0032] Fig. 13 is a configuration diagram of a pulse generating device (1300) according to another embodiment of the present invention.

[0033] Fig. 14 is a configuration diagram of one embodiment of the sawtooth wave generator (1330) of Fig. 13.

[0034] Fig. 15 is a drawing illustrating the operation of the sawtooth wave generator (1330) of Fig. 14.

[0035] Fig. 16 is a drawing illustrating the operation of the pulse generator (1300) of Fig. 13.

[0036] Figures 17a to 17d are diagrams illustrating various forms of pulse signals (Vout) that can be generated by a pulse generator (1300).

[0037]

[0038] Hereinafter, embodiments according to the technical idea of ​​the present invention will be described with reference to the attached drawings.

[0039] In describing components of embodiments of the present invention, symbols such as first, second, i), ii), a), b) may be used. These symbols are only for distinguishing the components from other components, and the nature, order, or sequence of the components are not limited by the symbols. When a part in the specification is said to "include" or "have" a component, this does not mean that other components are excluded, but rather that other components may be included, unless explicitly stated to the contrary.

[0040] The detailed description set forth below, together with the accompanying drawings, is intended to illustrate exemplary embodiments of the present invention and is not intended to represent the only embodiments in which the present invention may be practiced.

[0041]

[0042] FIG. 1 is a drawing showing a high voltage pulse generator (100) and a capacitive load (200) according to a first embodiment of the present invention. The high voltage pulse generator (100) can generate a high voltage pulse (Vout) having a predetermined waveform set by a user, and the generated high voltage pulse (Vout) can be provided to a capacitive load (200). For example, the capacitive load (200) may be a chamber (CB) as a facility for manufacturing semiconductors using plasma.

[0043] In Fig. 1, the components of the high-voltage pulse generator (100) may include a controller (not shown), and the controller (not shown) generates a driving signal so that each switch (SW1, SW2) is switched on or off.

[0044] In the description below, the operation of turning a switch on or off is caused by a controller (not shown) providing a driving signal required to turn the switch on or off to the gate of the switch.

[0045] The frequency of the output pulse of the high voltage pulse generator (100) is tens to hundreds of kHz, and the maximum peak-to-peak voltage Vp-p can be output at a voltage level of several to tens of kV.

[0046] As illustrated in FIG. 1, a high-voltage pulse generator (100) may be implemented including a first voltage source (VS1), a first input capacitor (Ci1), a second voltage source (VS2), a second input capacitor (Ci2), a first switch (SW1), a second switch (SW2), an inductor (L), and a fifth capacitor (C5). In some embodiments, the fifth capacitor (C5) may be omitted and one end of the inductor may be directly connected to a reference terminal (Nref).

[0047] The first voltage source (VS1) has a (+) terminal connected to the first node (N1) and a (-) terminal connected to the reference terminal (Nref), and generates a voltage having a magnitude of V1.

[0048] The first input capacitor (Ci1) is connected in parallel to the first voltage source (VS1).

[0049] The second voltage source (VS2) has its (+) terminal connected to the reference terminal (Nref) and its (-) terminal connected to the second node (N2), and generates a voltage having a magnitude of V2.

[0050] The second input capacitor (Ci2) is connected in parallel to the second voltage source (VS2).

[0051] The first switch (SW1) is connected between the output terminal (Nout) and the first node (N1).

[0052] The second switch (SW2) is connected between the output terminal (Nout) and the second node (N2).

[0053] The first switch (SW1) and the second switch (SW2) may be power semiconductor devices. A power semiconductor device is a semiconductor device used for converting or controlling power, and may be implemented as a device such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor). Each of the first switch (SW1) and the second switch (SW2) may include a transistor and a diode connected in parallel to the transistor.

[0054] An inductor (L) is connected between the reference terminal (Nref) and the output terminal (Nout).

[0055] The fifth capacitor (C5) is connected in series with the inductor (L). For example, one end of the fifth capacitor (C5) is connected to the reference terminal (Nref), the other end of the fifth capacitor (C5) is connected to one end of the inductor (L), and the other end of the inductor (L) is connected to the output terminal (Nout).

[0056] Meanwhile, a first capacitor (C1) and a first resistor element (R1) connected in parallel to each of both ends of the first switch (SW1) may further be included, and a second capacitor (C2) and a second resistor element (R2) connected in parallel to each of both ends of the second switch (SW2) may further be included. In addition, the first switch (SW1) and the second switch (SW2) may each be implemented as a single element, but may also each be implemented in a form in which a plurality of switch elements are connected in series. In addition, a capacitor and a resistor element may be connected in parallel to each of the switch elements connected in series. For example, the first switch (SW1) may be composed of four switches connected in series, and in this case, four capacitors and four resistor elements connected in parallel to the switches may be provided.

[0057]

[0058] FIG. 2 is a drawing showing an output waveform of a high-voltage pulse generator (100) according to the first embodiment.

[0059] FIGS. 3A to 3D are drawings for explaining the operating state in each mode in the output waveform of the high-voltage pulse generator (100) according to the first embodiment.

[0060] Hereinafter, the operation of the high voltage pulse generator (100) according to the first embodiment will be described with reference to FIGS. 2 and 3.

[0061] The high voltage pulse generator (100) operates repeatedly in the order of mode 1 to mode 4.

[0062] When the first switch (SW1) is implemented in a form in which multiple switch elements are connected in series, the capacitors connected in parallel to each of the multiple switch elements are intended to provide dynamic balance so that a high voltage is not applied unevenly to any one of the multiple switch elements during the on / off switching process of the multiple switch elements. In addition, the resistor elements connected in parallel to each of the multiple switch elements are intended to provide static balance so that a high voltage is not applied unevenly to any one of the multiple switch elements during the initial power supply process of the multiple switch elements.

[0063] In addition, when the second switch (SW2) is implemented in a form in which a plurality of switch elements are connected in series, the capacitor connected in parallel to each of the plurality of switch elements is to provide dynamic balance so that a high voltage is not applied unevenly to any one of the plurality of switch elements during the on / off switching process of the plurality of switch elements, and the resistor connected in parallel to each of the plurality of switch elements is to provide static balance so that a high voltage is not applied unevenly to any one of the plurality of switch elements during the initial power supply process of the plurality of switch elements.

[0064] As shown in FIG. 2 and FIG. 3a, when the first gate input signal (Gsw1) of the first switch (SW1) becomes 1 (i.e., the first switch (SW1) is turned ON) and the second gate input signal (Gsw2) of the second switch (SW2) becomes 0 (i.e., the second switch (SW2) is turned OFF), the high-voltage pulse generator (100) enters mode 1.

[0065] In mode 1, the output voltage Vout becomes the same voltage as the voltage V1 of the first voltage source (VS1).

[0066] As shown in FIGS. 2 and 3b, when the first gate input signal (Gsw1) changes to 0 and the first switch (SW1) turns OFF in mode 1, the high-voltage pulse generator (100) becomes mode 2. That is, when the first switch (SW1) is turned OFF while the first switch (SW1) is turned ON and the second switch (SW2) is turned OFF, mode 2 is entered.

[0067] In Fig. 3b, the impedances of R1 and R2 are greater than the impedances of C1 and C2, respectively, and the current of the DC power supply of VS1 and VS2 is substantially blocked from the output terminal Nout by C1 and C2, respectively, so the current paths connecting to R1, R2, VS1, and VS2 are omitted.

[0068] During mode 1, the energy stored in the inductor (L) gradually decreases Vout due to LC resonance by the inductor (L) and the composite capacitance in mode 2. The composite capacitance may be an equivalent capacitance between the ground and the output terminal (Nout) including the capacitance of the first capacitor (C1) and the second capacitor (C2) and parasitic capacitance. The first capacitor (C1) is charged via the parasitic capacitor (Cp) formed between the high voltage pulse generator (100) and the ground terminal, and Vout decreases due to LC resonance in which the second capacitor (C2) is discharged. The decrease in Vout may continue until mode 3.

[0069] As shown in FIGS. 2 and 3c, when the second gate input signal (Gsw2) becomes 1 and the second switch (SW2) turns ON in mode 2, the high-voltage pulse generator (100) becomes mode 3. That is, when the second switch (SW2) is turned ON while the first switch (SW1) and the second switch (SW2) are OFF, mode 3 occurs.

[0070] In mode 3, the output voltage Vout is equal to the voltage of the second voltage source (VS2), which is -V2.

[0071] As shown in FIGS. 2 and 3d, when the second gate input signal (Gsw2) changes to 0 and the second switch (SW2) turns OFF in mode 3, the high-voltage pulse generator (100) becomes mode 4. That is, when the first switch (SW1) is OFF and the second switch (SW2) is ON, and the second switch (SW2) is turned OFF, mode 4 occurs.

[0072] In Fig. 3d, the impedances of R1 and R2 are larger than the impedances of C1 and C2, and the DC power of VS1 and VS2 is substantially blocked from the output terminals by C1 and C2, so the current paths connecting R1, R2, VS1, and VS2 are omitted.

[0073] Meanwhile, Ci1=Ci2=C1=C2 and R1=R2.

[0074] During Mode 3, the (-) energy stored in the inductor (L) gradually increases Vout by the LC resonance by the inductor (L) and the composite capacitance in Mode 4. The composite capacitance may be an equivalent capacitance between the ground and the output terminal (Nout) including the capacitances of the first capacitor (C1) and the second capacitor (C2) and the parasitic capacitance. Vout monotonically increases by the LC resonance that discharges the first capacitor (C1) and charges the second capacitor (C2) via the parasitic capacitor (Cp), and this increase may continue until Mode 1.

[0075] Note that during the periods of mode 2 and mode 4, despite the LC resonance by the composite capacitance and inductor (L), a monotonous decrease in Vout occurs during the period of mode 2, and a monotonous increase in Vout occurs during the period of mode 4.

[0076] The periods of mode 2 and mode 4 are each T as a dead time interval. dead During the dead time period, the capacitances (Co) of C1, C2 and chamber (CB) connected in parallel to each switch are all discharged, enabling turn-on and turn-off by zero voltage switching (ZVS).

[0077] Minimum current (i) to satisfy the discharge time in the dead time interval Lpk ) can be calculated using mathematical formula 1.

[0078]

[0079] Here, △V is the voltage difference between the top and bottom of the output waveform (i.e., peak-to-peak voltage), which can be calculated as V1+V2. Also, C PT represents the (+) terminal equivalent capacitance including the capacitance of the first capacitor (C1) between the output terminal (Nout) and the first node (N1) and parasitic capacitance, and C NT represents the (-) terminal equivalent capacitance including the capacitance of the second capacitor (C2) between the output terminal (Nout) and the second node (N2) and parasitic capacitance, and Co represents a known capacitance value for the corresponding chamber (CB). Here, each equivalent capacitance can be obtained by measurement.

[0080] Therefore, current i Lpk The value Lc of the inductor L for the current to flow can be calculated from mathematical expression 2.

[0081]

[0082] Here, Tsw represents one switching cycle from mode 1 to mode 4, and V L represents the voltage between the two terminals of the inductor.

[0083] The fifth capacitor (C5) is configured to prevent saturation of the inductor (L). If the fifth capacitor (C5) is not present, the average voltage of the inductor (L) may not be 0 when the ON / OFF ratio of each switch (SW1, SW2) is not 5:5. That is, a DC component may exist in the inductor voltage, which may cause saturation of the inductor (L). Here, a case in which the average voltage of the inductor (L) is not 0 may occur when the voltage application time in mode 1 and the voltage application time in mode 3 are different when V1=V2, or when the voltage application time in mode 1 and the voltage application time in mode 3 are the same and V1 and V2 are different. Here, the dead time among one cycle related to switching is excluded from the ON / OFF time. Therefore, the inductor (L) may be saturated due to the non-zero average voltage, and the average voltage, ripple voltage, and resonant current must be considered when selecting the value of C5.

[0084] Average voltage V avg is as shown in mathematical formula 3.

[0085]

[0086] In mathematical expression 3, Intensicty_P means the duty at which V1 is applied when the first switch (SW1) is turned ON, and Intensicty_N means the duty at which V2 is applied when the second switch (SW2) is turned ON.

[0087] Peak-to-peak ripple voltage △v of the inductor c can be calculated as in mathematical formula 4.

[0088]

[0089] Here, i L is the current flowing in the inductor L and iLpk , where Cc5 represents the capacitance value of capacitor C5.

[0090] Here, the maximum value of the ripple voltage v c_max and minimum value v c_min is as shown in mathematical formula 5.

[0091]

[0092] Therefore, the maximum resonant current i is obtained by Equation 6 c_max and minimum value i c_min This can be calculated.

[0093]

[0094] As shown in Fig. 2, in mode 4, when the first switch (SW1) is OFF and the second switch (SW2) is OFF, changing the first switch (SW1) to ON results in mode 1.

[0095] In this way, the high-voltage pulse generator (100) sequentially turns on / off the first switch (SW1) and the second switch (SW2) to control mode 1 to mode 4 to be sequentially generated.

[0096]

[0097] Fig. 4 is a block diagram showing a high-voltage pulse generator (400) and a capacitive load (200) according to the second embodiment.

[0098] As illustrated in FIG. 4, a high voltage pulse generator (400) can be implemented by including a first voltage source (VS1), a first input capacitor (Ci1), a second voltage source (VS2), a second input capacitor (Ci2), a first switch (SW1), a second switch (SW2), a third switch (SW3), a fourth switch (SW4), an inductor (L), a fifth capacitor (C5), a first diode (D1), and a second diode (D2).

[0099] The circuit diagram of the high-voltage pulse generator (400) according to the second embodiment is in the form of the circuit diagram of FIG. 1, which further includes a third switch (SW3), a fourth switch (SW4), a first diode (D1), and a second diode (D2).

[0100] In Fig. 4, the other end of the first switch (SW1) is connected to the output terminal (Nout), and the third switch (SW3) is connected between one end of the first switch (SW1) and the first node (N1).

[0101] One end of the second switch (SW2) is connected to the output terminal Nout, and the fourth switch (SW4) is connected between the other end of the second switch (SW2) and the second node.

[0102] The first to fourth switches (SW1 to SW4) may be power semiconductor devices. Each of the first to fourth switches (SW1) may include a transistor and a diode connected in parallel to the transistor.

[0103] The anode of the first diode (D1) is connected to the reference terminal (Nref) and the cathode is connected to one end of the first switch (SW1).

[0104] The cathode of the second diode (D2) is connected to the reference terminal (Nref) and the anode is connected to the other terminal of the second switch (SW2).

[0105] A first balance capacitor (Cd1) may be connected in parallel across both ends of a first diode (D1), and a second balance capacitor (Cd2) may be connected in parallel across both ends of a second diode (D2). In addition, the first balance capacitor (Cd1) and the second balance capacitor (Cd2) may each be implemented as a single element, but may also each be implemented in a form in which a plurality of diode elements are connected in series. In addition, each capacitor may be connected in parallel to each diode element connected in series.

[0106] The first switch (SW1) may further include a first capacitor (C1) and a first resistor element (R1) connected in parallel at both ends thereof, the second switch (SW2) may further include a second capacitor (C2) and a second resistor element (R2) connected in parallel at both ends thereof, the third switch (SW3) may further include a third capacitor (C3) and a third resistor element (R3) connected in parallel at both ends thereof, and the fourth switch (SW4) may further include a fourth capacitor (C4) and a fourth resistor element (R4) connected in parallel at both ends thereof. In addition, the first switch (SW1) to the fourth switch (SW4) may each be implemented as a single element, but may also each be implemented in a form in which a plurality of switch elements are connected in series. In addition, a capacitor and a resistor element may be connected in parallel to each of the switch elements connected in series. For example, the third switch (SW3) may be composed of seven switches connected in series, in which case seven capacitors and seven resistors connected in parallel to the switches may be provided.

[0107]

[0108] FIG. 5 is a drawing showing an output waveform of a high-voltage pulse generator (400) according to the second embodiment.

[0109] FIGS. 6A to 6E are drawings for explaining the operating state in each mode in the output waveform of the high-voltage pulse generator (400) according to the second embodiment.

[0110] Hereinafter, the operation of the high voltage pulse generator (400) according to the second embodiment will be described with reference to FIGS. 5 and 6.

[0111] The high voltage pulse generator (400) operates repeatedly in the order of mode 1 to mode 5.

[0112] For reference, the first capacitor (C1), the second capacitor (C2), the third capacitor (C3) and the fourth capacitor (C4) connected in parallel to the first switch (SW1), the second switch (SW2), the third switch (SW3) and the fourth switch (SW4) respectively are intended to provide dynamic balance of the first switch (SW1), the second switch (SW2), the third switch (SW3) and the fourth switch (SW4) so ​​that a high voltage is not applied unevenly to at least one of the first switch (SW1), the second switch (SW2), the third switch (SW3) and the fourth switch (SW4) during the on / off switching process of the first switch (SW1), the second switch (SW2), the third switch (SW3) and the fourth switch (SW4).

[0113] In addition, the first resistor element (R1), the second resistor element (R2), the third resistor element (R3), and the fourth resistor element (R4) connected in parallel to the first switch (SW1), the second switch (SW2), the third switch (SW3), and the fourth switch (SW4) respectively are intended to provide static balance among the first switch (SW1), the second switch (SW2), the third switch (SW3), and the fourth switch (SW4) so ​​that high voltage is not applied biasedly to at least one of the first switch (SW1), the second switch (SW2), the third switch (SW3), and the fourth switch (SW4) during the initial power-on process.

[0114] In addition, the first balance capacitor (Cd1) and the second balance capacitor (Cd2), which are connected in parallel to both ends of the first diode (D1) and the second diode (D2), respectively, are intended to provide dynamic balance so that a high voltage is not applied biasedly to either the first diode (D1) or the second diode (D2) during the on / off switching process of the diodes.

[0115] As illustrated in FIGS. 5 and 6a, when the first gate input signal (Gsw1) of the first switch (SW1) and the third gate input signal (Gsw3) of the third switch (SW3) each become 1 (i.e., the first switch (SW1) and the third switch (SW3) are each turned on), and the second gate input signal (Gsw2) of the second switch (SW2) and the fourth gate input signal (Gsw4) of the fourth switch (SW4) each become 0 (i.e., the second switch (SW2) and the fourth switch (SW4) are each turned off), the high-voltage pulse generator (400) enters mode 1.

[0116] In mode 1, the output voltage Vout becomes the same voltage V1 as the voltage V1 of the first voltage source (VS1).

[0117] As illustrated in FIGS. 5 and 6b, when the first gate input signal (Gsw1) and the third gate input signal (Gsw3) are each changed to 0 in mode 1 and the first switch (SW1) and the third switch (SW3) are each turned OFF, the high-voltage pulse generator (400) becomes mode 2. That is, when the first switch (SW1) and the third switch (SW3) are each turned ON and the second switch (SW2) and the fourth switch (SW4) are each turned OFF, and the first switch (SW1) and the third switch (SW3) are each turned OFF, mode 2 is entered.

[0118] In Fig. 6b, the impedances of R1, R2, R3, and R4 are greater than the impedances of C1, C2, C3, and C4, respectively, and the DC power of VS1 and VS2 is substantially blocked from the output terminals by C1, C2, C3, and C4, so the current paths connecting R1, R2, R3, R4, VS1, and VS2 are omitted and shown.

[0119] During Mode 1, the energy stored in the inductor (L) gradually decreases Vout due to LC resonance by the inductor (L) and the composite capacitance in Mode 2. The composite capacitance may be an equivalent capacitance between the ground and the output terminal (Nout) including the capacitances of the first capacitor (C1), the second capacitor (C2), the third capacitor (C3), and the fourth capacitor (C4) and the parasitic capacitance. Vout decreases due to LC resonance in which the first capacitor (C1) and the third capacitor (C3) are charged and the second capacitor (C2) and the fourth capacitor (C4) are discharged via the parasitic capacitor (Cp), and this decrease may continue until Mode 3.

[0120] As shown in FIGS. 5 and 6c, when in mode 2, the second gate input signal (Gsw2) and the fourth gate input signal (Gsw4) are each 1, and the second switch (SW2) and the fourth switch (SW4) are each turned ON, the high-voltage pulse generator (400) becomes mode 3. That is, when the first switch (SW1) to the fourth switch (SW4) are OFF and the second switch (SW2) and the fourth switch (SW4) are each turned ON, mode 3 is entered.

[0121] In mode 3, the output voltage Vout is equal to the voltage of the second voltage source (VS2), which is -V2.

[0122] As illustrated in FIGS. 5 and 6d, when the second gate input signal (Gsw2) and the fourth gate input signal (Gsw4) are each changed to 0 in mode 3, and the second switch (SW2) and the fourth switch (SW4) are each turned OFF, the high-voltage pulse generator (400) becomes mode 4. That is, when the first switch (SW1) and the third switch (SW3) are OFF and the second switch (SW2) and the fourth switch (SW4) are ON, and the second switch (SW2) and the fourth switch (SW4) are each turned OFF, mode 4 is entered.

[0123] During Mode 3, the (-) energy stored in the inductor (L) gradually increases Vout by the LC resonance by the composite capacitance and the inductor (L) in Mode 4. The composite capacitance may be an equivalent capacitance between the ground and the output terminal (Nout) including the capacitances of the first capacitor (C1), the second capacitor (C2), the third capacitor (C3), and the fourth capacitor (C4) and the parasitic capacitance. Vout monotonically increases by the LC resonance that discharges the first capacitor (C1) and the third capacitor (C3) and charges the second capacitor (C2) and the fourth capacitor (C4) via the parasitic capacitor (Cp), and this increase may continue until Mode 1.

[0124] Meanwhile, the parallel-connected capacitors may be Ci1=Ci2=C1=C2=C3=C4, and the parallel-connected resistor elements may be R1=R2=R3=R4. Here, the values ​​of the parallel-connected capacitors and the parallel-connected resistor elements may each have appropriately tuned values ​​to achieve ZVS.

[0125] Here, the L value can be determined by mathematical expression 2 similarly to the first embodiment, and in the second embodiment, i of mathematical expression 2 Lpk The value can be determined as in mathematical formula 7.

[0126]

[0127] Here, △V is the voltage difference between the top and bottom of the output waveform, which can be calculated as V1+V2. Also, C PT represents the (+) terminal equivalent capacitance including the capacitance of the first capacitor (C1), the third capacitor (C3) and the parasitic capacitance between the output terminal (Nout) and the first node (N1), and C NTrepresents the (-) terminal equivalent capacitance including the capacitance of the second capacitor (C2), the fourth capacitor (C4) and parasitic capacitance between the output terminal (Nout) and the second node (N2). Co represents a known capacitance value for the corresponding chamber (CB).

[0128] In this embodiment, each equivalent capacitance can be obtained by measurement.

[0129] Also, the maximum resonant current i c_max and minimum value i c_min The relationship between Lc and Cc5 is as shown in mathematical expression 6.

[0130] As shown in Fig. 5, when the first switch (SW1) to the fourth switch (SW4) are OFF in mode 4, mode 1 is achieved by turning the first switch (SW1) and the third switch (SW3) ON.

[0131] In this way, the high voltage pulse generator (400) can control the first switch (SW1) to the fourth switch (SW4) to sequentially turn on / off so that modes 1 to 4 are sequentially generated.

[0132] The high voltage pulse generator (400) can also be controlled to switch to mode 5 after mode 3.

[0133] As shown in Fig. 5, in mode 3, when the first switch (SW1) and the third switch (SW3) are OFF and the second switch (SW2) and the fourth switch (SW4) are ON, mode 5 is achieved by changing the first switch (SW1) to ON and the fourth switch (SW4) to OFF.

[0134] As illustrated in FIGS. 5 and 6e, in mode 5, the output terminal Nout is connected to the reference terminal via the first diode (D1) and the first switch (SW1), and to the reference terminal via the second diode (D2) and the second switch (SW2), so that Vout becomes 0 V. At this time, there is a process of consuming energy by LC resonance in the process of Vout switching from -V2 to 0 V, but for the sake of simplicity, the output voltage when switching from mode 3 to mode 5 is illustrated as in FIG. 5.

[0135] As illustrated in Fig. 5, when the first switch (SW1) and the second switch (SW2) are ON and the third switch (SW3) and the fourth switch (SW4) are OFF in mode 5, when the second switch (SW2) is turned OFF and the third switch (SW3) is turned ON, mode 1 is obtained. Here, too, there is a process of accumulating energy by LC resonance in the process of Vout switching from 0 V to V1, but for simplicity, the output voltage when switching from mode 5 to mode 1 is illustrated as in Fig. 5.

[0136]

[0137] Fig. 7a is a drawing showing a high-voltage pulse generator (700a) and a capacitive load (200) according to a third embodiment of the present invention. The high-voltage pulse generator (700a) according to the third embodiment may be a high-voltage pulse generator (100) according to the first embodiment with the addition of a function capable of controlling the amplitude of a high-voltage pulse.

[0138] Referring to FIG. 7a, the high voltage pulse generator (700a) may further include a third voltage source (VS3), first power switches (PSW1_0, PSW1_1), second power switches (PSW2_0, PSW2_1), a third power switch (PSW3), and a fourth power switch (PSW4) compared to the high voltage pulse generator (100).

[0139] The third voltage source (VS3) has a (-) terminal connected to the reference terminal (Nref) and can generate a voltage having a level of V3. The magnitude (V3) of the voltage generated by the third voltage source (VS3) can be smaller than the magnitude (V1) of the voltage generated by the first voltage source (VS1).

[0140] The first power switches (PSW1_0, PSW1_1) are connected in series with each other and can control the connection between the (+) terminal of the first voltage source (VS1) and the first node (N1). The first power switches (PSW1_0, PSW1_1) can be turned on when the high voltage mode signal (HV) becomes 1, and can be turned off when the high voltage mode signal (HV) becomes 0. Each of the first power switches (PSW1_0, PSW1_1) can include a transistor and a diode. It can be confirmed that the directions of the diodes of the first power switch (PSW1_0) and the first power switch (PSW1_1) are opposite to each other, which may be to block current from flowing through the first power switches (PSW1_0, PSW1_1) when the first power switches (PSW1_0, PSW1_1) are turned off.

[0141] The second power switches (PSW2_0, PSW2_1) are connected in series with each other and can control the connection between the (+) terminal of the third voltage source (VS3) and the first node (N1). The second power switches (PSW2_0, PSW_1) can be turned on when the low voltage mode signal (LV) becomes 1, and can be turned off when the low voltage mode signal (LV) becomes 0. Each of the second power switches (PSW2_0, PSW2_1) can include a transistor and a diode. It can be confirmed that the directions of the diodes of the second power switch (PSW2_0) and the second power switch (PSW2_1) are opposite to each other, which may be to block current from flowing through the second power switches (PSW2_0, PSW2_1) when the second power switches (PSW2_0, PSW2_1) are turned off.

[0142] The third power switch (PSW3) can control the connection between the (-) terminal of the second voltage source (VS2) and the second node (N2). The third power switch (PSW3) can be turned on when the high voltage mode signal (HV) is 1, and can be turned off when the high voltage mode signal (HV) is 0. The third power switch (PSW3) can include a transistor and a diode.

[0143] The fourth power switch (PSW4) can control the connection between the reference terminal (Nref) and the second node (N2). The fourth power switch (PSW4) can be turned on when the low voltage mode signal (LV) is 1, and can be turned off when the low voltage mode signal (LV) is 0. The fourth power switch (PSW4) can include a transistor and a diode.

[0144] The operating modes of the high voltage pulse generator (700a) may include a high voltage mode and a low voltage mode. In the high voltage mode, the high voltage mode signal (HV) may be activated to 1, and in the low voltage mode, the low voltage mode signal (LV) may be activated to 1.

[0145] In the high voltage mode, a first voltage source (VS1) may be connected to a first node (N1) and a second voltage source (VS2) may be connected to a second node (N2). In the high voltage mode, when the operation mode of the high voltage pulse generator (700a) is controlled from mode 1 (MODE1) to mode 4 (MODE4) as shown in FIG. 2, the high voltage pulse generator (700a) may generate a high voltage pulse signal (Vout) that swings from -V2 to V1. That is, the high voltage pulse generated by the high voltage pulse generator (700) in the high voltage mode may have an amplitude of V1 + V2.

[0146] In the low voltage mode, a third voltage source (VS3) may be connected to the first node (N1), and a reference terminal (Nref), i.e., a ground terminal, may be connected to the second node (N2). In the low voltage mode, when the operation mode of the high voltage pulse generator (700a) is controlled from mode 1 (MODE1) to mode 4 (MODE4) as shown in Fig. 2, the high voltage pulse generator (700a) may generate a high voltage pulse (Vout) that swings from 0 to V3. That is, the high voltage pulse (Vout) generated by the high voltage pulse generator (700a) in the low voltage mode may have an amplitude of V3.

[0147] That is, by using the additional components in the high voltage pulse generator (700a) compared to the high voltage pulse generator (100), the amplitude of the high voltage pulse (Vout) generated in the high voltage pulse generator (700a) can be adjusted to be larger or smaller.

[0148]

[0149] Fig. 7b is a drawing showing a high-voltage pulse generator (700b) and a capacitive load (200) according to a fourth embodiment of the present invention. The high-voltage pulse generator (700b) according to the fourth embodiment may also be a high-voltage pulse generator (100) according to the first embodiment with the addition of a function for controlling the amplitude of a high-voltage pulse, similar to the third embodiment.

[0150] Referring to FIG. 7b, the high voltage pulse generator (700b) may further include a third voltage source (VS3), a fourth voltage source (VS4), first power switches (PSW1_0, PSW1_1), second power switches (PSW2_0, PSW2_1), third power switches (PSW3_0, PSE3_1), and fourth power switches (PSW4_0, PSW4_1) compared to the high voltage pulse generator (100).

[0151] The third voltage source (VS3) has a (-) terminal connected to the reference terminal (Nref) and can generate a voltage having a level of V3. The magnitude (V3) of the voltage generated by the third voltage source (VS3) can be smaller than the magnitude (V1) of the voltage generated by the first voltage source (VS1).

[0152] The fourth voltage source (VS4) has its (+) terminal connected to the reference terminal (Nref) and can generate a voltage having a level of V4. The magnitude (V4) of the voltage generated by the fourth voltage source (VS4) can be smaller than the magnitude (V2) of the voltage generated by the second voltage source (VS2).

[0153] The first power switches (PSW1_0, PSW1_1) are connected in series with each other and can control the connection between the (+) terminal of the first voltage source (VS1) and the first node (N1). The first power switches (PSW1_0, PSW1_1) can be turned on when the high voltage mode signal (HV) becomes 1, and can be turned off when the high voltage mode signal (HV) becomes 0. Each of the first power switches (PSW1_0, PSW1_1) can include a transistor and a diode. It can be confirmed that the directions of the diodes of the first power switch (PSW1_0) and the first power switch (PSW1_1) are opposite to each other, which may be to block current from flowing through the first power switches (PSW1_0, PSW1_1) when the first power switches (PSW1_0, PSW1_1) are turned off.

[0154] The second power switches (PSW2_0, PSW2_1) are connected in series with each other and can control the connection between the (+) terminal of the third voltage source (VS3) and the first node (N1). The second power switches (PSW2_0, PSW_1) can be turned on when the low voltage mode signal (LV) becomes 1, and can be turned off when the low voltage mode signal (LV) becomes 0. Each of the second power switches (PSW2_0, PSW2_1) can include a transistor and a diode. It can be confirmed that the directions of the diodes of the second power switch (PSW2_0) and the second power switch (PSW2_1) are opposite to each other, which may be to block current from flowing through the second power switches (PSW2_0, PSW2_1) when the second power switches (PSW2_0, PSW2_1) are turned off.

[0155] The third power switches (PSW3_0, PSW3_1) can control the connection between the (-) terminal of the second voltage source (VS2) and the second node (N2). The third power switches (PSW3_0, PSW3_1) can be turned on when the high voltage mode signal (HV) is 1, and can be turned off when the high voltage mode signal (HV) is 0. Each of the third power switches (PSW3_0, PSW3_1) can include a transistor and a diode. The directions of the diodes of the third power switches (PSW3_0, PSW3_1) can be opposite to each other.

[0156] The fourth power switches (PSW4_0, PSW4_1) can control the connection between the reference terminal (Nref) and the second node (N2). The fourth power switches (PSW4_0, PSW4_1) can be turned on when the low voltage mode signal (LV) is 1, and can be turned off when the low voltage mode signal (LV) is 0. Each of the fourth power switches (PSW4_0, PSW4_1) can include a transistor and a diode. The directions of the diodes of the fourth power switches (PSW4_0, PSW4_1) can be opposite to each other.

[0157] The operating modes of the high voltage pulse generator (700b) may include a high voltage mode and a low voltage mode. In the high voltage mode, the high voltage mode signal (HV) may be activated to 1, and in the low voltage mode, the low voltage mode signal (LV) may be activated to 1.

[0158] In the high voltage mode, a first voltage source (VS1) may be connected to a first node (N1) and a second voltage source (VS2) may be connected to a second node (N2). In the high voltage mode, when the operation mode of the high voltage pulse generator (700b) is controlled from mode 1 (MODE1) to mode 4 (MODE4) as shown in FIG. 2, the high voltage pulse generator (700b) may generate a high voltage pulse signal (Vout) that swings from -V2 to V1. That is, the high voltage pulse generated by the high voltage pulse generator (700b) in the high voltage mode may have an amplitude of V1 + V2.

[0159] In the low voltage mode, a third voltage source (VS3) may be connected to the first node (N1) and a fourth voltage source (VS4) may be connected to the second node (N2). In the low voltage mode, when the operation mode of the high voltage pulse generator (700b) is controlled from mode 1 (MODE1) to mode 4 (MODE4) as shown in FIG. 2, the high voltage pulse generator (700b) may generate a high voltage pulse (Vout) that swings from -V4 to V3. That is, the high voltage pulse (Vout) generated by the high voltage pulse generator (700b) in the low voltage mode may have an amplitude of V3 + V4.

[0160] That is, by using the additional components in the high voltage pulse generator (700b) compared to the high voltage pulse generator (100), the amplitude of the high voltage pulse (Vout) generated in the high voltage pulse generator (700b) can be adjusted to be larger or smaller.

[0161]

[0162] Fig. 8a is a drawing showing a high-voltage pulse generator (800a) and a capacitive load (200) according to a fifth embodiment of the present invention. The high-voltage pulse generator (800a) according to the fifth embodiment may be a high-voltage pulse generator (400) according to the second embodiment with the addition of a function capable of controlling the amplitude of a high-voltage pulse.

[0163] Referring to FIG. 8A, the high voltage pulse generator (800a) may include the same additional components as the high voltage pulse generator (700a). That is, the high voltage pulse generator (800a) may further include a third voltage source (V3), first power switches (PSW1_0, PSW1_1), second power switches (PSW2_0, PSW2_1), a third power switch (PSW3), and a fourth power switch (PSW4) compared to the high voltage pulse generator (400).

[0164] The operating modes of the high voltage pulse generator (800a) may include a high voltage mode and a low voltage mode. In the high voltage mode, the high voltage mode signal (HV) may be activated to 1, and in the low voltage mode, the low voltage mode signal (LV) may be activated to 1.

[0165] In the high voltage mode, a first voltage source (VS1) may be connected to a first node (N1) and a second voltage source (VS2) may be connected to a second node (N2). In the high voltage mode, when the operation mode of the high voltage pulse generator (800a) is controlled from mode 1 (MODE1) to mode 4 (MODE4) as shown in FIG. 5, the high voltage pulse generator (800a) may generate a high voltage pulse signal (Vout) that swings from -V2 to V1. That is, the high voltage pulse generated by the high voltage pulse generator (800a) in the high voltage mode may have an amplitude of V1 + V2.

[0166] In the low voltage mode, a third voltage source (VS3) may be connected to the first node (N1), and a reference terminal (Nref), i.e., a ground terminal, may be connected to the second node (N2). In the low voltage mode, when the operation mode of the high voltage pulse generator (800a) is controlled from mode 1 (MODE1) to mode 4 (MODE4) as shown in FIG. 5, the high voltage pulse generator (800a) may generate a high voltage pulse (Vout) that swings from 0 to V3. That is, the high voltage pulse (Vout) generated by the high voltage pulse generator (800a) in the low voltage mode may have an amplitude of V3.

[0167] That is, by using the additional components in the high voltage pulse generator (800a) compared to the high voltage pulse generator (400), the amplitude of the high voltage pulse (Vout) generated in the high voltage pulse generator (800a) can be adjusted to be larger or smaller.

[0168]

[0169] Fig. 8b is a drawing showing a high-voltage pulse generator (800b) and a capacitive load (200) according to a sixth embodiment of the present invention. The high-voltage pulse generator (800a) according to the sixth embodiment may be, like the fifth embodiment, a high-voltage pulse generator (400) according to the second embodiment with the addition of a function capable of controlling the amplitude of a high-voltage pulse.

[0170] Referring to FIG. 8b, the high voltage pulse generator (800b) may include the same additional configurations as the high voltage pulse generator (700b). That is, the high voltage pulse generator (800b) may further include a third voltage source (VS3), a fourth voltage source (VS4), first power switches (PSW1_0, PSW1_1), second power switches (PSW2_0, PSW2_1), third power switches (PSW3_0, PSE3_1), and fourth power switches (PSW4_0, PSW4_1) compared to the high voltage pulse generator (400).

[0171] The operating modes of the high voltage pulse generator (800b) may include a high voltage mode and a low voltage mode. In the high voltage mode, the high voltage mode signal (HV) may be activated to 1, and in the low voltage mode, the low voltage mode signal (LV) may be activated to 1.

[0172] In the high voltage mode, a first voltage source (VS1) may be connected to a first node (N1) and a second voltage source (VS2) may be connected to a second node (N2). In the high voltage mode, when the operation mode of the high voltage pulse generator (800b) is controlled from mode 1 (MODE1) to mode 4 (MODE4) as shown in FIG. 5, the high voltage pulse generator (800b) may generate a high voltage pulse signal (Vout) that swings from -V2 to V1. That is, the high voltage pulse generated by the high voltage pulse generator (800b) in the high voltage mode may have an amplitude of V1 + V2.

[0173] In the low voltage mode, a third voltage source (VS3) may be connected to the first node (N1) and a fourth voltage source (VS4) may be connected to the second node (N2). In the low voltage mode, when the operation mode of the high voltage pulse generator (800b) is controlled from mode 1 (MODE1) to mode 4 (MODE4) as shown in FIG. 5, the high voltage pulse generator (800b) may generate a high voltage pulse (Vout) that swings from -V4 to V3. That is, the high voltage pulse (Vout) generated by the high voltage pulse generator (800b) in the low voltage mode may have an amplitude of V3 + V4.

[0174] That is, by using the additional components in the high voltage pulse generator (800b) compared to the high voltage pulse generator (100), the amplitude of the high voltage pulse (Vout) generated in the high voltage pulse generator (800b) can be adjusted to be larger or smaller.

[0175] In FIGS. 7a, 7b, 8a, and 8b, the first power switches (PSW1) and the third power switches (PSW3) are turned on and off simultaneously, and the second power switches (PSW2) and the fourth power switches (PSW4) are turned on and off simultaneously. However, these may be designed to be controlled independently, in which case the amplitude of the high voltage pulse can be adjusted more diversely. For example, in the high voltage pulse generator (700a) of FIG. 7a, when the first power switches (PSW1_0, PSW1_1) and the fourth power switch (PSW4) are turned on and the second power switches (PSW2_0, PSW2_1) and the third power switch are turned off, the high voltage pulse generator (700a) can generate a high voltage pulse (Vout) that swings from 0 to V1. In addition, when the second power switches and the third power switches are turned on and the first power switches and the fourth power switches are turned off in the high voltage pulse generator (800b) of FIG. 8b, the high voltage pulse generator (800b) can generate a high voltage pulse (Vout) that swings from -V2 to V3.

[0176] Also, in FIGS. 7a, 7b, 8a, and 8b, some power switches are configured with two and some power switches are configured with one, but it is natural that the number of these may be different from the examples in the drawings.

[0177]

[0178] Figure 9 is a configuration diagram of a pulse generating device (900) according to one embodiment of the present invention.

[0179] Referring to FIG. 9, the pulse generator (900) may include a high-voltage pulse generator (920) and a controller (910) for controlling the same. The high-voltage pulse generator (920) may be one of the high-voltage pulse generators (100, 400, 700a, 700b, 800a, 800b) of the first to sixth embodiments described above. In addition, multiple high-voltage pulse generators may be provided and used selectively.

[0180] The controller (910) can generate control signals for controlling the voltage mode and operating modes of the high voltage pulse generator (920).

[0181] A pulse signal generated from a pulse generator (900) can be provided to a chamber (200).

[0182]

[0183] FIG. 10 is a drawing illustrating a semiconductor manufacturing device (100) according to one embodiment of the present invention.

[0184] Referring to FIG. 10, a semiconductor manufacturing device (1000) may include a chamber (200) and a pulse generating device (900).

[0185] A ceramic cover (210) is placed in the upper area of ​​the chamber (200), and a plurality of induction coils (220) are placed on the outside of the ceramic cover (210).

[0186] A bottom electrode (230) is placed in the lower region of the chamber (200), and a wafer (W) can be placed on top of the bottom electrode (230).

[0187] The lower electrode (230) may be an electrostatic chuck (ESC) that supports a wafer (W) by absorbing it using electrostatic force. In addition, the chamber (200) may include a gas supply unit (not shown) and a gas exhaust unit (not shown), and the gas supply unit (not shown) may supply a reaction gas into the chamber (200) and exhaust the gas through the gas exhaust unit (not shown) to maintain the chamber (200) in a vacuum state.

[0188] The RF power generator (1010) can generate RF power in the form of a sinusoidal wave (i.e., first power) and provide the generated first power to the induction coil (220). The first power is power for generating plasma and may be referred to as source power. The first power generator (1010) may be a device that generates high-frequency power in the form of a sinusoidal wave of several tens of MHz.

[0189] The semiconductor manufacturing device (1000) is a semiconductor facility to which the ICP (Inductively Coupled Plasma) method is applied.

[0190] When RF power is supplied to the induction coil (220), an electric field is generated within the chamber (200) by the induction coil (220), and free electrons generated within the chamber (200) are accelerated in concentric circles by the magnetic field. The free electrons within the chamber (200) do not collide with the inner wall of the chamber (200) but continue to collide with neutral particles to form plasma, thereby forming a high-density plasma.

[0191] A high density plasma (HDP) can be formed within the chamber (200) by a magnetic field generated by an induction coil (220), and the ion density of the plasma can be controlled by controlling the intensity of the first power.

[0192] The pulse generator (900) can generate a pulse (i.e., second power) in a non-sinusoidal form. The second power is power for controlling the ion energy of the plasma.

[0193] The pulse generator (900) can operate in such a manner that the high voltage pulse generator (920) generates pulses under the control of the controller (910). The controller (910) can control the switches of the high voltage pulse generator (920) so that a pulse having an appropriate amplitude and shape is generated from the high voltage pulse generator (920). The pulse generated from the pulse generator (900) is provided to the lower electrode (230) as a second power.

[0194] When a second power is supplied to the lower electrode (230), a voltage can be induced in the wafer (W) placed on the lower electrode (230). Accordingly, the voltage of the wafer (W) can be controlled according to the second power, and accordingly, the ion energy of the plasma generated within the chamber (200) can be controlled.

[0195] The reaction gas can be diffused within the chamber (200) and converted into plasma by the first power applied to the induction coil (220) and the second power applied to the lower electrode (230). The plasma comes into contact with the surface of the wafer (W) and reacts physically or chemically, and through this reaction, wafer processing processes such as plasma annealing, etching, plasma-enhanced chemical vapor deposition, physical vapor deposition, and plasma cleaning can be performed.

[0196] When the semiconductor manufacturing device (1000) is used in an etching process, the reaction gas is converted into plasma by high-frequency discharge on the upper portion of the lower electrode (230), and the film to be processed on the wafer (W) can be etched into a desired pattern by radicals, electrons, and ions activated by the plasma. According to the present embodiment, by precisely controlling the radicals, electrons, and ions of the plasma, the etching performance such as the etching rate, aspect ratio, critical dimension of the etching pattern, profile of the etching pattern, and selectivity can be improved.

[0197]

[0198] FIG. 11 is a diagram showing the voltage of the pulse signal (Vout) output from the pulse generator (900) of FIG. 10 and the voltage (Vw) of the wafer (W) of the chamber (200).

[0199] Referring to Fig. 11, it can be confirmed that the pulse signal (Vout) and the wafer voltage (VW) formed by the pulse signal (Vout) are different. In particular, in the section where the pulse signal (Vout) is at a low level, it can be confirmed that the wafer voltage (VW) does not maintain a voltage level similar to the pulse signal (Vout) and the voltage level increases over time. This may be due to the influence of components such as the sheath capacitance of the chamber (200). In this case, when the wafer voltage (Vw) does not maintain a constant level contrary to the intention, the ion energy may be distributed over a wide area, which may lower the flux and reduce the etching efficiency of the chamber (200).

[0200]

[0201] FIG. 12 is a diagram showing the waveform of a pulse signal (Vout) that must be applied to the chamber (200) to maintain the wafer voltage (Vw) constant.

[0202] Referring to Fig. 12, when the pulse signal (Vout) has a waveform in which the voltage level decreases in the form of a sawtooth wave in a section where the pulse signal (Vout) is at a low level, it can be confirmed that the wafer voltage (Vw) maintains a constant level. That is, in order to prevent the phenomenon (phenomenon of Fig. 11) in which the wafer voltage (Vw) increases over time in a section where the pulse signal (Vout) is at a low level due to components such as the covering capacitance, the voltage level of the pulse signal (Vout) can be applied so that it decreases over time in this section.

[0203]

[0204] Fig. 13 is a configuration diagram of a pulse generating device (1300) according to another embodiment of the present invention.

[0205] Referring to FIG. 13, the pulse generator (1300) may include a high-voltage pulse generator (920), a sawtooth wave generator (1330), and a controller (1310) for controlling the high-voltage pulse generator (920) and the sawtooth wave generator (1330). The high-voltage pulse generator (920) may be one of the high-voltage pulse generators (100, 400, 700a, 700b, 800a, 800b) of the first to sixth embodiments described above. In addition, multiple high-voltage pulse generators may be provided and used selectively.

[0206] The sawtooth wave generator (1330) can generate a pulse signal (Vout) by adding a sawtooth wave component to a high voltage pulse (Nout) generated by the high voltage pulse generator (920). The sawtooth wave generator (1330) can be connected between the output terminal (Nout) of the high voltage pulse generator (920) and the input terminal (Vout) of the chamber (200).

[0207] The controller (1310) can generate control signals for controlling the switches of the high voltage pulse generator (920) and the sawtooth generator (1330).

[0208]

[0209] Fig. 14 is a configuration diagram of one embodiment of the sawtooth wave generator (1330) of Fig. 13.

[0210] Referring to FIG. 14, the sawtooth wave generator (1330) may include a plurality of power module circuits (1410_1 to 1410_10).

[0211] A plurality of power module circuits (1410_1 to 1410_10) may have input terminals (IN) and output terminals (OUT) connected in series with each other. For example, the output terminal (OUT1) of the power module circuit (1410_1) may be connected to the input terminal (IN2) of the power module circuit (1410_2), and the output terminal (OUT2) of the power module circuit (1410_2) may be connected to the input terminal (IN3) of the power module circuit (1410_3). The input terminal (IN1) of the power module circuit (1410_1) of the first stage may be connected to the output terminal (Nout) of the high voltage pulse generator (920), and the output terminal (OUT10) of the power module circuit (1410_10) of the last stage may be connected to the input terminal (Vout) of the chamber (200). Here, the number of power module circuits (1410_1 to 1410_10) is exemplified as 10, but it is natural that the number of power module circuits may vary depending on the design.

[0212] The power module circuits (1410_1 to 1410_10) can be controlled by sawtooth control signals (S1 to S10). The power module circuits (1410_1 to 1410_10) can lower the voltage level of the input terminal (IN) and output it to the output terminal (OUT) according to the level of the sawtooth control signals (S1 to S10), or output the voltage of the input terminal (IN) as it is to the output terminal (OUT). For example, the power module circuit (1410_2) can lower the voltage of the input terminal (IN2) and output it to the output terminal (OUT2) when the sawtooth control signal (S2) is 1, and can output the voltage of the input terminal (IN2) as it is to the output terminal (OUT2) when the sawtooth control signal (S2) is 0.

[0213] The power module circuit (1410_1) may include a voltage source path including a voltage source (1411_1), a stabilizing capacitor (1413_1), and a first path switch (1415_1), and a bypass path including a second path switch (1417_1). The voltage source (1411_1) may be used to lower the voltage level of the output terminal compared to the input terminal. The voltage source (1411_1) is for generating a sawtooth wave and may generate a voltage at a lower level than the voltage sources used in the high voltage pulse device (920). For example, the voltage sources used in the high voltage pulse device (920) generate a voltage of at least several kV, but the voltage source (1411_1) may generate a relatively small voltage level of several tens to several hundred V. A stabilizing capacitor (1413_1) connected in parallel to the voltage source (1411_1) can be used to stabilize the voltage level of the voltage source (1411_1). The first path switch (1415_1) can be turned on when the sawtooth control signal (S1) is 1 to activate the voltage source path. The second path switch (1415_1) can be turned on when the sawtooth control signal (S1) is 0, that is, turned on when the inverted sawtooth control signal (S1B) is 1 to activate the bypass path.

[0214] When the sawtooth control signal (S1) is activated to 1, the voltage source path of the power module circuit (1410_1) is activated so that the input terminal (IN1) and the output terminal (OUT1) can be connected through the voltage source (1411_1). That is, the output terminal (OUT1) can have a voltage level that is lower than the input terminal (IN1) by the voltage of the voltage source (1411_1). When the sawtooth control signal (S1) is deactivated to 0, the bypass path of the power module circuit (1410_1) is activated so that the input terminal (IN1) and the output terminal (OUT1) can be directly connected through the second path switch (1415_1). That is, the output terminal (OUT1) can have the same voltage level as the input terminal (IN1).

[0215] The power module circuits (1410_2 to 1410_10) may also include a voltage source path and a bypass path, similar to the power module circuit (1410_1), and may operate in the same manner as the power module circuit (1410_1). That is, the power module circuits (1410_2 to 1410_10) may lower the voltage level of the output terminal (OUT) compared to the input terminal (IN) or make the voltage levels of the input terminal (IN) and the output terminal (OUT) the same, depending on the level of the sawtooth control signals (S2 to S10).

[0216]

[0217] Fig. 15 is a diagram illustrating the operation of the sawtooth wave generator (1330) of Fig. 14. Fig. 15 illustrates the levels of sawtooth wave control signals (S1 to S10) and the voltage difference (Nout-Vout) between the input terminal (Nout) and the output terminal (Vout) of the sawtooth wave generator (1330) according to the levels.

[0218] The sawtooth control signals (S1 to S10) can be sequentially activated in such a manner that the sawtooth control signal (S2) is activated within the activation period of the sawtooth control signal (S1), the sawtooth control signal (S3) is activated within the activation period of the sawtooth control signal (S2), and the sawtooth control signal (S4) is activated within the activation period of the sawtooth control signal (S3).

[0219] When all sawtooth control signals (S1 to S10) are 0, the voltage difference (Nout-Vout) can be 0 V. And as the number of activated sawtooth control signals (S1 to S10) increases, the voltage difference (Nout-Vout) can increase in a sawtooth shape.

[0220]

[0221] Fig. 16 is a diagram illustrating the operation of the pulse generator (1300) of Fig. 13. Here, it is assumed that the high-voltage pulse generator (920) of the pulse generator (1300) has the same configuration as the second embodiment (400).

[0222] Referring to FIG. 16, it can be confirmed that the sawtooth control signals (S1 to S10) are sequentially activated within the section where the pulse signal (Vout) is at a low level, that is, within the MODE 3 section where the first switch (SW1) and the third switch (SW3) are turned off and the second switch (SW2) and the fourth switch (SW4) are turned on. Since the sawtooth control signals (S1 to S10) are sequentially activated within the section where the pulse signal (Vout) is at a low level, the voltage level of the pulse signal (Vout) in this section can decrease in a sawtooth shape over time.

[0223] In the first section where the pulse signal (Vout) is at a low level, that is, the first MODE 3 section, the sawtooth control signals (S1 to S10) are activated in the order of S1 to S10, and in the second section where the pulse signal (Vout) is at a low level, that is, the second MODE 3 section, the sawtooth control signals (S1 to S10) are activated in the order of S10 to S1. This may be to ensure that the voltage source (1411_0) that is turned on the longest in the sawtooth wave generator (1330) is turned on the shortest next time, so that the voltage sources (1411_0 to 1411_10) of the sawtooth wave generator (1330) can be used uniformly.

[0224]

[0225] Figures 17a to 17d are diagrams illustrating various forms of pulse signals (Vout) that can be generated by a pulse generator (1300).

[0226] Fig. 17a shows the waveform of the same pulse signal (Vout) as Fig. 16, and a pulse signal (Vout) having the same form as Fig. 17 can be generated by sequentially activating the sawtooth control signals (S1 to S10) in a section where the pulse signal (Vout) is at a low level.

[0227] Fig. 17b may be a form of a pulse signal (Vout) that can be generated by sequentially activating and then deactivating all sawtooth control signals (S1 to S10) in a section where the pulse signal (Vout) is at a low level.

[0228] Fig. 17c may be a form of a pulse signal (Vout) that can be generated when a part (e.g., S1 to S5) of the sawtooth control signals (S1 to S10) is activated in a section where the pulse signal (Vout) is at a low level, and then the remaining sawtooth control signals (e.g., S6 to S10) are simultaneously activated after a certain period of time.

[0229] Fig. 17d may be a form of a pulse signal (Vout) that can be generated when all sawtooth control signals (S1 to S10) are activated in a section where the pulse signal (Vout) is at a low level, and then some of the sawtooth control signals (e.g., S1 to S5) are deactivated simultaneously after a certain period of time.

[0230]

[0231] Although the embodiments according to the technical idea of ​​the present invention have been described with reference to the attached drawings, this is only for the purpose of explaining the embodiments according to the concept of the present invention, and the present invention is not limited to the embodiments described above. Various forms of substitution, modification, and change of the embodiments may be made by those skilled in the art to which the present invention pertains within the scope that does not depart from the technical idea of ​​the present invention as described in the claims, and such may also be considered to fall within the scope of the present invention.

Claims

1. A high voltage pulse generator that generates a high voltage pulse; and A sawtooth wave generator that generates a pulse signal by adding a sawtooth wave component to the above high voltage pulse. A pulse generating device comprising:

2. In paragraph 1, The above sawtooth wave generating device The sawtooth component is generated so that the level of the pulse signal can become lower as time passes in the section where the high voltage pulse is at a low level. Pulse generator.

3. In paragraph 1, The above sawtooth wave generator comprises a plurality of power module circuits connected in series, Each of the above multiple power module circuits In response to the level of the sawtooth control signal corresponding to itself among the sawtooth control signals, the voltage of its input terminal is lowered and output to its output terminal, or the voltage of its input terminal is output as is to its output terminal. Pulse generator.

4. In paragraph 1, The above sawtooth wave generator comprises power module circuits connected in series and controlled by sawtooth wave control signals, Each of the above power module circuits A voltage source path in which an input terminal and an output terminal are connected through a voltage source and a bypass path in which the input terminal and the output terminal are connected by bypassing the voltage source, and one of the voltage source path and the bypass path is activated according to the level of a corresponding sawtooth control signal among the sawtooth control signals. Pulse generator.

5. In paragraph 4, The above sawtooth control signals are The above high voltage pulses are activated with different pulse widths within the low level section. Pulse generator.

6. In paragraph 5, The above sawtooth control signals are The sawtooth control signal with a shorter activation pulse width is activated within the activation interval of the sawtooth control signal with a longer activation pulse width. Pulse generator.

7. In paragraph 4, The above voltage source path is the above voltage source; and A first path switch is connected in series with the voltage source and is turned on when the corresponding sawtooth control signal is activated. The above bypass path is A second path switch connected between the input terminal and the output terminal and turned on when the corresponding sawtooth control signal is deactivated. Pulse generator.

8. In paragraph 7, The above voltage source path is Further comprising a stabilizing capacitor connected in parallel to the above voltage source. Pulse generator.

9. In paragraph 1, The above high voltage pulse generating device A first voltage source having the (+) terminal connected to the first node and the (-) terminal connected to the reference terminal; A second voltage source having a (+) terminal connected to the above reference terminal and a (-) terminal connected to the second node; A first switch connected between an output terminal from which the high voltage pulse is output and a third node; A third switch connected between the third node and the first node; A second switch connected between the above output terminal and the fourth node; A fourth switch connected between the fourth node and the second node; A first capacitor connected in parallel to the first switch; A second capacitor connected in parallel to the second switch; A third capacitor connected in parallel to the third switch; A fourth capacitor connected in parallel to the fourth switch; A first diode having an anode connected to the above reference terminal and a cathode connected to the third node; A second diode having a cathode connected to the above reference terminal and an anode connected to the fourth node; and Including an inductor connected between the reference terminal and the output terminal. Pulse generator.

10. In paragraph 1, The above high voltage pulse generating device A first voltage source having its (-) terminal connected to the reference terminal; A second voltage source having a (+) terminal connected to the above reference terminal; A third voltage source having a (-) terminal connected to the above reference terminal; At least one first power switch for connecting the first node and the (+) terminal of the first voltage source in high voltage mode; At least one second power switch for connecting the (+) terminal of the first node and the third voltage source in low voltage mode; A third power switch for connecting the second node and the (-) terminal of the second voltage source in the above high voltage mode; A fourth power switch for connecting the second node and the reference terminal in the low voltage mode; A first switch connected between an output terminal from which the high voltage pulse is output and a third node; A third switch connected between the third node and the first node; A second switch connected between the above output terminal and the fourth node; A fourth switch connected between the fourth node and the second node; A first capacitor connected in parallel to the first switch; A second capacitor connected in parallel to the second switch; A third capacitor connected in parallel to the third switch; A fourth capacitor connected in parallel to the fourth switch; A first diode having an anode connected to the above reference terminal and a cathode connected to the third node; A second diode having a cathode connected to the above reference terminal and an anode connected to the fourth node; and Including an inductor connected between the reference terminal and the output terminal. Pulse generator.

11. In paragraph 10, The one or more first power switches include two first power switches connected in series, Each of the two first power switches includes a transistor and a diode connected in parallel with the transistor, The directions of the diodes of the two first power switches are opposite to each other. Pulse generator.

12. In paragraph 11, The one or more second switches include two second power switches connected in series, Each of the two second power switches includes a transistor and a diode connected in parallel with the transistor, The directions of the diodes of the above two second power switches are opposite to each other. Pulse generator.

13. In paragraph 1, The above high voltage pulse generating device A first voltage source having its (-) terminal connected to the reference terminal; A second voltage source having a (+) terminal connected to the above reference terminal; A third voltage source having a (-) terminal connected to the above reference terminal; A fourth voltage source having a (+) terminal connected to the above reference terminal; At least one first power switch for connecting the first node and the (+) terminal of the first voltage source in high voltage mode; At least one second power switch for connecting the (+) terminal of the first node and the third voltage source in low voltage mode; A third power switch for connecting the second node and the (-) terminal of the second voltage source in the above high voltage mode; A fourth power switch for connecting the (-) terminal of the second node and the fourth voltage source in the above low voltage mode; A first switch connected between an output terminal from which the high voltage pulse is output and a third node; A third switch connected between the third node and the first node; A second switch connected between the above output terminal and the fourth node; A fourth switch connected between the fourth node and the second node; A first capacitor connected in parallel to the first switch; A second capacitor connected in parallel to the second switch; A third capacitor connected in parallel to the third switch; A fourth capacitor connected in parallel to the fourth switch; A first diode having an anode connected to the above reference terminal and a cathode connected to the third node; A second diode having a cathode connected to the above reference terminal and an anode connected to the fourth node; and Including an inductor connected between the reference terminal and the output terminal. Pulse generator.

14. Contains a plurality of power module circuits connected in series and controlled by sawtooth control signals; Each of the above multiple power module circuits A voltage source path connecting the input terminal and the output terminal through a voltage source; and It includes a bypass path that bypasses the voltage source and connects the input terminal and the output terminal. One of the voltage source path and the bypass path is activated depending on the level of the corresponding sawtooth control signal among the above sawtooth control signals. Sawtooth wave generator.

15. In paragraph 14, The above sawtooth control signals are activated with different pulse widths. Sawtooth wave generator.

16. In paragraph 15, The above sawtooth control signals are The sawtooth control signal with a shorter activation pulse width is activated within the activation interval of the sawtooth control signal with a longer activation pulse width. Sawtooth wave generator.

17. In paragraph 15, The above voltage source path is the above voltage source; and A first path switch is connected in series with the voltage source and is turned on when the corresponding sawtooth control signal is activated. The above bypass path is A second path switch connected between the input terminal and the output terminal and turned on when the corresponding sawtooth control signal is deactivated. Sawtooth wave generator.

18. In paragraph 17, The above voltage source path is Further comprising a stabilizing capacitor connected in parallel to the above voltage source. Sawtooth wave generator.

19. Including a pulse generating device and chamber, The above pulse generating device A high voltage pulse generator for generating a high voltage pulse; and A sawtooth wave generator is included that generates a pulse signal by adding a sawtooth wave component to the high voltage pulse. The pulse signal generated by the pulse generator is used to generate plasma within the chamber. Semiconductor manufacturing equipment.

20. In paragraph 19, The above sawtooth wave generating device The sawtooth component is generated so that the level of the pulse signal can become lower as time passes in the section where the high voltage pulse is at a low level. Semiconductor manufacturing equipment.

21. In paragraph 19, The above sawtooth wave generator comprises a plurality of power module circuits connected in series, Each of the above multiple power module circuits In response to the level of the sawtooth control signal corresponding to itself among the sawtooth control signals, the voltage of its input terminal is lowered and output to its output terminal, or the voltage of its input terminal is output as is to its output terminal. Semiconductor manufacturing equipment.

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