Method for manufacturing high-integration semiconductor device by using selective transfer, and semiconductor device manufactured thereby

Abstract

Provided is a high-integration semiconductor device resulting from the following steps: a first step of forming a sacrificial layer on an epitaxial substrate and forming an electronic device layer on the sacrificial layer; a second step of etching the electronic device layer and the sacrificial layer corresponding to an active device region, so as to form an epitaxial template in which an epitaxial pattern is implemented; a third step of forming, on the epitaxial template, a first insulation layer that encompasses the epitaxial pattern; a fourth step of etching a part of the first insulation layer that encompasses a target epitaxial pattern to be transferred, so as to expose the sacrificial layer, and forming a first bonding layer on the electronic device layer; a fifth step of forming a second insulation layer on a target substrate, and etching a part of the second insulation layer corresponding to the first bonding layer, so as to form a stepped second bonding layer; a sixth step of mounting the epitaxial template on the target substrate so that the first bonding layer and the second bonding layer are bonded to each other; and a seventh step of removing the sacrificial layer exposed by means of the selective etching process, so as to selectively transfer the electronic device layer onto the active device region on the target substrate, wherein the fourth to seventh steps are repeatedly performed by etching a part of the first insulation layer that encompasses another target epitaxial pattern to be transferred, and thus the electronic device layer is selectively transferred onto each active device region on the target substrate.

Description

Method for manufacturing a highly integrated semiconductor device using selective transfer and a semiconductor device manufactured thereby

[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device manufactured thereby, and more particularly, to a method for manufacturing a highly integrated semiconductor device utilizing selective transfer capable of selectively and repeatedly transferring one or more electronic device layers from an epitemplate onto a target substrate, and to a highly integrated semiconductor device manufactured thereby.

[0002] The national research and development projects that supported this invention are as follows.

[0003] Assignment ID 1711185308

[0004] Assignment number 2022M3I8A1078437

[0005] Ministry of Science and ICT

[0006] Project Management (Professional) Institution Name: National Research Foundation of Korea

[0007] Research Project Name: Core Technology Development Project / Next-Generation Compound Semiconductor Core Technology Development Project

[0008] Research Project Name: Development of InGaAs HEMT, mHEMT, and HBT epitaxial materials and mHEMT device manufacturing technology.

[0009] Contribution rate 1 / 1

[0010] Name of the project performing organization: Korea Institute of Nanotechnology

[0011] Research period: January 1, 2023 - December 31, 2023

[0012] The conventional method of manufacturing InP or GaAs-based MMIC (monolithic microwave integrated circuits) chips is to first manufacture active components on an InP or GaAs substrate, and then manufacture passive components, transmission lines, etc. in the area excluding the active components.

[0013] In general, the proportion of epitaxial films for active components in MMIC chips is very small, while passive components and transmission lines must all be manufactured on expensive InP or GaAs epitaxial wafers. Therefore, the number of MMIC chips that can be manufactured is limited and the manufacturing cost is very high.

[0014] The technology for integrating expensive InP-based ultra-high frequency active devices into conventional GaAs high-frequency MMIC chips is based on the traditional GaAs high-frequency MMIC chip manufacturing method, in which InP-based ultra-high frequency active devices are additionally manufactured and bonded in a die form or by wire bonding. Since individual active devices must be die bonded, mass production is low.

[0015] In addition, the conventional method of transferring a compound semiconductor onto a heterogeneous substrate through epitaxial lift-off is a method of transferring the entire patterned compound semiconductor epi thin film, and thus has limitations in selectively transferring or repeatedly transferring to multiple substrates.

[0016] Prior art 1 (Korean registration number 10-024815) is a method of fabricating an active element for ultra-high frequencies on an InP, GaAs substrate, and fabricating passive elements and transmission lines for radio wave transmission in an area excluding the active element through a continuous process to implement an MMIC chip, which is a method of fabricating an InP, GaAs ultra-high frequency MMIC chip using a traditional method.

[0017] And, prior art 2 (Korean registration number 10-2437646) is a method for manufacturing an MMIC chip having two or more functions by mounting an expensive InP-based ultra-high frequency active element die on a GaAs high-frequency MMIC chip manufactured in a traditional manner in the form of die bonding or wire bonding.

[0018] And, prior art 3 (application number 10-2015-0069836) is a method of transferring a compound semiconductor epi thin film to a Si or heterogeneous substrate using epitaxial lift-off.

[0019] In this way, the conventional InP or GaAs-based MMIC chip manufacturing technology is implemented by manufacturing active components for electronic components on each substrate using ultra-high frequency electronic component epitaxial thin films manufactured on InP or GaAs substrates, and manufacturing passive components (resistors, capacitors, inductors, etc.) and transmission lines for radio wave transmission in areas excluding the active components.

[0020] Typically, in the design process for manufacturing an MMIC chip for RF, about three active elements measuring 1 mm x 3 mm and 100 μm x 100 μm are required, so the epitaxial film in all areas except for this area is removed through an etching process and cannot be used.

[0021] Calculating this, the actual utilization rate of the epitaxial film relative to the fabrication area of ​​the MMIC chip on the InP or GaAs electronic device epitaxial substrate is about 1 / 100 for a 3-stage LNA MMIC chip and about 1 / 150 for a 2-stage LMA MMIC chip. Therefore, it can be said that the waste of expensive compound semiconductor-based epitaxial films compared to the manufacturing cost during the MMIC chip manufacturing process is very large.

[0022] In addition, in the case of a technology for transferring a conventional InP or GaAs-based epitaxial film or active element to a Si or Si CMOS-based substrate, there is a limitation that the entire epitaxial film or active element must be transferred at once, and it is impossible to selectively and repeatedly transfer only the epitaxial film or active element at a required location.

[0023] The present invention was derived to solve the above problem, and its purpose is to provide a method for manufacturing a highly integrated semiconductor device utilizing selective transfer, which enables the implementation of a highly integrated semiconductor device by selectively and repeatedly transferring one or more electronic device layers onto a target substrate from an epitaxial template using an epitaxial growth substrate, and a highly integrated semiconductor device manufactured thereby.

[0024] The present invention for achieving the above object comprises the steps of: a first step of forming a sacrificial layer on a substrate for epitaxial growth and forming an electronic component layer on the sacrificial layer; a second step of forming an epitaxial template in which an epitaxial pattern is implemented by etching the electronic component layer and the sacrificial layer corresponding to an active component area; a third step of forming a first insulating layer surrounding the epitaxial pattern on the epitaxial template; a fourth step of etching a portion of the first insulating layer surrounding a target epitaxial pattern to be transferred to expose the sacrificial layer and forming a first bonding layer on the electronic component layer; a fifth step of forming a second insulating layer on a target substrate and etching a portion of the second insulating layer corresponding to the first bonding layer to form a second bonding layer having a step; a sixth step of settling the epitaxial template on the target substrate such that the first bonding layer and the second bonding layer are bonded; and a sixth step of removing the sacrificial layer exposed by a selective etching process, thereby forming an epitaxial template on the target substrate. The technical gist of the present invention is a method for manufacturing a highly integrated semiconductor device using selective transfer, characterized in that it includes a seventh step of selectively transferring an electronic device layer onto the active device area on the target substrate, and repeating the fourth to seventh steps by etching a portion of the first insulating layer surrounding another target epitaxial pattern to be transferred, thereby selectively transferring an electronic device layer onto each active device area on the target substrate.

[0025] In addition, the present invention includes a target substrate having a second bonding layer formed thereon with a step, and an active element including an electronic element layer formed on the target substrate and having a first bonding layer bonded to the second bonding layer formed thereon, wherein the active element is formed on an epitaxial growth substrate with a sacrificial layer interposed therebetween and is selectively transferred onto the target substrate, and a highly integrated semiconductor element chip is implemented on the target substrate at a high density using selective transfer, which is another technical point of the present invention.

[0026] In addition, it is preferable that the substrate for epitaxial growth is formed of a III-V group compound semiconductor.

[0027] In addition, it is preferable that the sacrificial layer uses a material that can be selectively etched with the first insulating layer and the second insulating layer.

[0028] In addition, the first insulating layer and the second insulating layer are formed of an oxide or a nitride, and the first insulating layer and the second insulating layer may use the same type of material or different types of material.

[0029] In addition, it is preferable that the first bonding layer of the fourth step is formed on the upper side of the electronic element layer of the epi pattern corresponding to the area of ​​the active element. Here, the area of ​​the first bonding layer may be 10㎛ x 10㎛ to 300㎛ x 300㎛.

[0030] In addition, it is preferable that the second bonding layer of the fifth step is formed to have an area equal to or larger than the area of ​​the first bonding layer.

[0031] In addition, it is preferable that the second bonding layer of the fifth step has a step difference of 10 nm to 10 μm.

[0032] In addition, it is preferable that the period of the pattern of the second bonding layer be formed to be equal to or larger than the size of the unit semiconductor element chip. In addition, it is preferable that at least one second bonding layer is included within the size of the unit semiconductor element chip.

[0033] In addition, it is preferable that the bonding of the first bonding layer and the second bonding layer of the sixth step be implemented by a direct bonding method.

[0034] In addition, it is preferable that the bonding of the first bonding layer and the second bonding layer is positioned within a 30% offset range from the edge of the first bonding layer to the edge of the second bonding layer.

[0035] In addition, it is preferable that the epi template and the target substrate, or the substrate for epi growth and the target substrate, include an align key for alignment when bonding the first bonding layer and the second bonding layer.

[0036] In addition, it is preferable that the target substrate is any one of an inorganic substrate, an organic substrate, a CMOS circuit substrate, and a PCB.

[0037] In addition, the target substrate may be an inorganic substrate of any one of Si, SiC, ZnO, MgO, sapphire, quartz, and glass, an organic substrate of any one of polycarbonate, polyethylene terephthalate, polyacrylate ether cellulose, polyimide, and polyvinyl alcohol, or a Si-based CMOS circuit substrate.

[0038] In addition, it is preferable that the target substrate has a size equal to or larger than the size of the substrate for epitaxial growth.

[0039] In addition, it is preferable that the high-density semiconductor device is a monolithic microwave integrated circuit (MMIC).

[0040] The present invention provides a method for manufacturing a highly integrated semiconductor device utilizing selective transfer, which enables the implementation of a highly integrated semiconductor device by selectively and repeatedly transferring one or more electronic device layers from an epitaxial template having an epitaxial pattern implemented on a target substrate using an epitaxial growth substrate, and a highly integrated semiconductor device manufactured thereby.

[0041] In addition, the present invention implements an epi template in which an epi pattern including an electronic device layer is formed using an epi growth substrate, and repeatedly transfers the epi template onto a target substrate to implement a highly integrated semiconductor device. This allows the relatively expensive epi growth substrate to be recycled or reused, thereby reducing the production cost. In addition, the epi pattern manufactured on a small-diameter epi growth substrate can be easily expanded to a large-diameter target substrate, so the applicability is excellent.

[0042] In addition, depending on the type of electronic device layer formed on the substrate for epitaxial growth, it is easy to integrate electronic device layers with different functions into the required locations of a single unit semiconductor device chip through repeated transfer using one or more epitemplates, and it is also easy to integrate electronic device layers with different functions into each required unit semiconductor device chip. Accordingly, mass production is possible, which can lower the manufacturing cost and enhance price competitiveness.

[0043] Thus, the present invention provides a highly integrated semiconductor device by transferring an epitaxial pattern from an epitemplate to a target substrate. Since repetitive, selective transfer is possible regardless of the target substrate type, low-cost mass production is possible using existing process infrastructure. In particular, when using silicon as the target substrate, the process compatibility with existing silicon processes is highly high, offering the advantage of further reducing production costs.

[0044] Figure 1 - Flowchart of a method for manufacturing a highly integrated semiconductor device utilizing selective transfer according to an embodiment of the present invention.

[0045] FIGS. 2 to 5 - Schematic diagrams showing the main parts of a method for manufacturing a highly integrated semiconductor device using selective transfer according to an embodiment of the present invention (left: cross-sectional schematic diagram, right: frontal schematic diagram).

[0046] FIG. 6 and FIG. 7 - Schematic diagrams showing the MMIC manufacturing sequence according to the embodiments of FIGS. 2 to 6.

[0047] FIG. 8 - A schematic diagram showing an MMIC chip in which the final plating electrode has been formed in the embodiments of FIGS. 6 and 7 (top: cross-sectional schematic diagram, bottom: frontal schematic diagram).

[0048] FIGS. 9 to 12 - Schematic diagrams showing the main parts of a method for manufacturing a highly integrated semiconductor device using selective transfer according to another embodiment of the present invention (left: cross-sectional schematic diagram, right: frontal schematic diagram).

[0049] FIG. 13 - A schematic diagram showing a semiconductor device manufactured according to the embodiments of FIGS. 9 to 12.

[0050] FIG. 14 - A schematic diagram showing an MMIC chip in which the final plating electrode has been formed in the embodiment of FIG. 13 (top: cross-sectional schematic diagram, bottom: frontal schematic diagram).

[0051] The present invention provides a highly integrated semiconductor device by selectively and repeatedly transferring one or more electronic device layers onto a target substrate from an epitaxial template having an epitaxial pattern using a substrate for epitaxial growth.

[0052] This allows for the recycling or reuse of relatively expensive substrates for epitaxial growth, thereby reducing production costs. In addition, the epitaxial pattern produced on a small-diameter substrate for epitaxial growth can be easily expanded to a large-diameter target substrate, thereby enhancing applicability.

[0053] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0054] FIG. 1 is a flowchart for a method for manufacturing a highly integrated semiconductor device using selective transfer according to an embodiment of the present invention, and FIGS. 2 to 5 are schematic diagrams (left: cross-sectional schematic diagram, right: frontal schematic diagram) showing the main part of a method for manufacturing a highly integrated semiconductor device using selective transfer according to an embodiment of the present invention, and FIGS. 6 and 7 are schematic diagrams showing the MMIC manufacturing sequence according to the embodiment of FIGS. 2 to 6, and FIG. 8 is a schematic diagram showing an MMIC chip in which the formation of the final plating electrode is completed in the embodiment of FIGS. 6 and 7, and FIGS. 9 to 12 are schematic diagrams (left: cross-sectional schematic diagram, right: frontal schematic diagram) showing the main part of a method for manufacturing a highly integrated semiconductor device using selective transfer according to another embodiment of the present invention, and FIG. 13 is a schematic diagram showing a semiconductor device manufactured according to the embodiment of FIGS. 9 to 12, and FIG. 14 is a schematic diagram showing an MMIC chip in which the formation of the final plating electrode is completed in the embodiment of FIG. 13. This is a schematic diagram.

[0055] As illustrated, a method for manufacturing a highly integrated semiconductor device using selective transfer according to an embodiment of the present invention comprises: a first step of forming a sacrificial layer (120) on a substrate (110) for epitaxial growth, and forming an electronic device layer (130) on the sacrificial layer (120); a second step of forming an epitaxial template (100) in which an epitaxial pattern (140) is implemented by etching the electronic device layer (130) and the sacrificial layer (120) corresponding to an active device area; a third step of forming a first insulating layer (200) surrounding the epitaxial pattern (140) on the epitaxial template (100); and a third step of etching a part of the first insulating layer (200) surrounding the target epitaxial pattern (140) to be transferred to expose the sacrificial layer (120), and forming an electronic device layer (130) on the electronic device layer (130). A fourth step of forming a first bonding layer (220), a fifth step of forming a second insulating layer (300) on a target substrate (400) and etching a part of the second insulating layer (300) corresponding to the first bonding layer (220) to form a second bonding layer (320) having a step (322), a sixth step of settling the epitome (100) on the target substrate (400) so that the first bonding layer (220) and the second bonding layer (320) are bonded, and a seventh step of selectively transferring the electronic component layer (130) onto the active component area on the target substrate (400) by removing the sacrificial layer (120) exposed by a selective etching process, and etching a part of the first insulating layer (200) surrounding another target epitome (140) to be transferred. It is characterized in that the electronic component layer (130) is selectively transferred onto each active component area on the target substrate (400) by repeatedly performing steps 4 to 7.

[0056] A highly integrated semiconductor device utilizing selective transfer according to an embodiment of the present invention manufactured thereby includes a target substrate (400) having a second bonding layer (320) formed thereon with a step (322) thereon, and an active device including an electronic device layer (130) formed on the target substrate (400) and having a first bonding layer (220) bonded to the second bonding layer (320) formed thereon, the electronic device being formed thereon, and the active device being formed on an epitaxial growth substrate (110) with a sacrificial layer (120) therebetween and selectively transferred onto the target substrate (400), and is characterized in that a unit semiconductor device chip is highly integrated and implemented on the target substrate (400).

[0057] First, a method for manufacturing a high-density semiconductor device using selective transfer according to an embodiment of the present invention forms a sacrificial layer (120) on a substrate (110) for epitaxial growth, and forms an electronic device layer (130) on the sacrificial layer (120) (first step, FIG. 2(a), FIG. 9(a)).

[0058] The epitaxial growth substrate (110) according to an embodiment of the present invention is formed of a III-V group compound semiconductor, and an appropriate epitaxial growth substrate (110) is selected and used depending on the electronic device layer (130) to be epitaxially grown. That is, an epitaxial growth substrate (110) made of GaAs, GaP, GaAsP, GaN, InP, InAs, or the like can be used depending on the function or type of the electronic device layer (130), and in one embodiment of the present invention, an InP or GaAs substrate is used.

[0059] Then, a sacrificial layer (120) is formed on the substrate (110) for epitaxial growth. The sacrificial layer (120) is formed using a material having a high etching selectivity compared to other surrounding materials, and is used as a material that is easy to etch or remove by absorbing a specific solvent or specific energy. In addition, it may be formed using a material different from the substrate (110) for epitaxial growth, or may have a different lattice constant. In this case, a buffer layer or the like may be additionally formed.

[0060] According to an embodiment of the present invention, the sacrificial layer (120) may be formed of a compound semiconductor material such as In, Ga, As, Al, or P, depending on the type of the substrate (110) for epitaxial growth and the electronic device layer (130).

[0061] According to one embodiment of the present invention, when the substrate (110) for epitaxial growth is made of InP or GaAs, it is preferable to use AlAs or AlGaAs as the sacrificial layer (120) formed on the upper layer for epitaxial growth.

[0062] The above sacrificial layer (120) can be formed by a conventional physical or chemical thin film deposition process, and in one embodiment of the present invention, can be formed by a sputtering or CVD (Chemical Vapor Deposition) process.

[0063] And, an electronic component layer (130) is formed on the sacrificial layer (120). The electronic component layer (130) can be formed selectively according to the use or purpose of the final semiconductor component, and is implemented as a single-layer or multi-layer compound semiconductor layer. In one embodiment of the present invention, a HEMT (High Electron Mobility Transistor) for forming an MMIC chip can be formed. This can also be utilized for manufacturing an MMIC chip having various functions such as an electronic component, an optical component, and a sensor component.

[0064] In addition, the electronic component layer (130) may form different types of electronic component layers (130) for each specific region. For example, it may be formed as an InP-based LNA (Low-Noise Amplifier) ​​electronic component layer (130) or a GaAs-based PA (Power Amplifier) ​​electronic component layer (130). In addition, in the case of an optical component, electronic component layers (130) that emit red, blue, green, etc. may be implemented, and these may be transferred individually or simultaneously by the transfer process described below.

[0065] Then, the electronic element layer (130) and the sacrificial layer (120) are etched in response to the active element area to form an epitome (100) in which an epitome (140) is implemented (second step, FIG. 1(b), FIG. 9(b)).

[0066] In general, in an MMIC chip, the electronic component layer (130) is formed in the active component area, and passive components and transmission lines are also included. Therefore, the epitaxial pattern (140) formed by the patterning process of the electronic component layer (130) and the sacrificial layer (120) is formed to correspond to the active component area. That is, the remaining electronic component layer (130) and sacrificial layer (120) patterns that are etched are formed to be the same size as or slightly smaller than the active component area, and are transferred to the active component area by a process to be described later.

[0067] The formation of an epitaxial pattern (140) by etching the electronic component layer (130) and the sacrificial layer (120) is formed by patterning using a photolithography process, and the spacing and size of the epitaxial pattern (140) are designed according to the final MMIC chip layout to be manufactured.

[0068] In this way, the epitome (100) according to the present invention includes a sacrificial layer (120) and an electronic component layer (130) on a substrate (110) for epitaxial growth, and each electronic component layer (130) is implemented as an individually separated epitaxial pattern (140). In the transfer process described below, the electronic component layers (130) are transferred to a target substrate (400) at a desired location in a desired number of sequential or simultaneous repetitions.

[0069] Then, a first insulating layer (200) is formed on the epi template (100) to surround the epi pattern (140) (step 3, Fig. 1(c), Fig. 9(c)).

[0070] The first insulating layer (200) is formed over the entire area of ​​the epi template (100) to surround the epi pattern (140), thereby protecting the substrate for epi growth (110) and the epi pattern (140) from the etching process, and the first insulating layer (200) formed on the upper portion of the electronic device layer (130) serves as the first bonding layer (220) in the transfer process to be described later. Therefore, the first insulating layer (200) protects the substrate for epi growth (110) and the epi pattern (140), and can be formed of a sacrificial layer (120) that is not etched even by the etching process of the sacrificial layer (120) and a material that allows for selective etching.

[0071] The first insulating layer (200) may be formed of an oxide or a nitride, and may be formed of the same type of material as the second insulating layer (300) described below, or may be formed of a different type of material.

[0072] The first insulating layer (200) according to one embodiment of the present invention is made of SiO2, SiO x , oxides such as Al2O3, HfO2, ZrO2, Y2O3, Ta2O5, SiN x , nitrides such as Si3N4, AlN, BN, TaN, TiN, and ZrN can be used, and two or more materials can be mixed and used or formed into multilayers as needed.

[0073] In this way, a first insulating layer (200) is formed over the entire area of ​​the epitome (100) on which the epitome (140) formed by being separated and arranged is implemented, and each epitome (140) is surrounded and protected by the first insulating layer (200). Here, when one or more of the separated and arranged epitome (140) is to be transferred to the target substrate (400), the epitome (140) is referred to as a “target epitome (140)” for convenience, and the other epitome (140) is referred to as “another target epitome (140).”

[0074] Then, a part of the first insulating layer (200) surrounding the target epitaxial pattern (140) to be transferred is etched to expose the sacrificial layer (120), and a first bonding layer (220) is formed on the electronic component layer (130) (Step 4, FIG. 2(d), FIG. 9(d)). The first insulating layer (200) is removed to expose the sacrificial layer (120), and the first bonding layer (220) is left on the upper side of the electronic component layer (130) for the bonding process to be described later. This is done by removing a part of the first insulating layer (200) by a dry or wet etching process. That is, the first insulating layer (200) should be removed so that the sacrificial layer (120) is exposed to an extent that wet etching of the sacrificial layer (120) is possible.

[0075] In addition, the first bonding layer (220) is formed on the upper side of the electronic element layer (130) of the epi pattern (140) corresponding to the area of ​​the active element for stable bonding. That is, the first bonding layer (220) may be formed in a shape that is identical to the area of ​​the electronic element layer (130) separated and arranged by the epi pattern (140) or surrounds a portion of the electronic element layer (130).

[0076] In one embodiment of the present invention, when providing an MMIC chip, the area of ​​the first bonding layer (220) is preferably 10 µm x 10 µm to 300 µm x 300 µm. In addition, the spacing between the first bonding layers (220) is formed to be 10 µm to 100 µm, so that the patterns of the first bonding layers (220) are arranged in the maximum number that can be manufactured on the substrate (110) for epitaxial growth in one embodiment of the present invention.

[0077] That is, the area of ​​the active element region in the MMIC chip and the area of ​​the electronic element layer (130) are the same or similar, and the first bonding layer (220) is also formed similarly, and the gap between them is also formed similarly.

[0078] Then, a second insulating layer (300) is formed on the target substrate (400), and a part of the second insulating layer (300) corresponding to the first bonding layer (220) is etched to form a second bonding layer (320) having a step (322) (step 5, FIGS. 3(a), (b), and 10(a), (b), (c)).

[0079] The target substrate (400) according to an embodiment of the present invention is easier to obtain and cheaper than the substrate for epitaxial growth (110), and has no limitations in size and material. It is sufficient as a substrate that supports the epitaxial pattern (140) to be transferred and can support various passive components and transmission lines in the subsequent process.

[0080] According to an embodiment of the present invention, the target substrate (400) may use any one of an inorganic substrate, an organic substrate, a CMOS circuit board, and a PCB depending on the purpose or function of the MMIC chip.

[0081] For example, the target substrate (400) may be an inorganic substrate of any one of Si, SiC, ZnO, MgO, sapphire, quartz, and glass, a flexible organic substrate of any one of polycarbonate, polyethylene terephthalate, polyacrylate ether cellphone, polyimide, and polyvinyl alcohol, or a Si-based CMOS circuit substrate.

[0082] In one embodiment of the present invention, since it has the advantage of being able to utilize an existing silicon-based semiconductor process, a Si or Si-based CMOS circuit board can be used as the target substrate (400). Here, the CMOS circuit board may be for driving an active element (electronic element layer (130)).

[0083] In addition, the target substrate (400) is preferably at least the same size as the substrate for epi growth (110) or larger than the size of the substrate for epi growth (110) for expansion to a large area.

[0084] That is, the existing compound semiconductor base (InP or GaAs) is difficult to achieve high integration due to the high cost of small diameter, and the actual substrate usage area of ​​the MMIC chip manufactured using the existing epi growth substrate (110) is about 1 / 100 for a 3-stage LNA MMIC chip and about 1 / 150 for a 2-stage LMA MMIC chip, so the waste compared to the manufacturing cost of the expensive compound semiconductor-based epitaxial film in the MMIC chip manufacturing process is very large.

[0085] Accordingly, the present invention implements an epi template (100) in which an epi pattern (140) including an electronic device layer (130) is formed using an epi growth substrate (110), and repeatedly transfers this onto a target substrate (400) to implement a highly integrated semiconductor device. This allows the relatively expensive epi growth substrate (110) to be recycled or reused, thereby reducing the production cost. In addition, the epi pattern (140) manufactured on a small-diameter epi growth substrate (110) can be easily expanded to a large-diameter target substrate (400), so that the applicability thereof is excellent.

[0086] A second insulating layer (300) is formed on the target substrate (400), and a part of the second insulating layer (300) is etched corresponding to the first bonding layer (220) to form a second bonding layer (320) having a step (322).

[0087] The second insulating layer (300) is made of the same or similar material as the first insulating layer (200) described above, and a second bonding layer (320) having a step (322) is formed by etching a portion of the second insulating layer (300) through an etching process. The second bonding layer (320) is formed into an array pattern through a selective etching process of the second insulating layer (300).

[0088] Since the first bonding layer (220) and the second bonding layer (320) are bonded to each other by a transfer process to be described later, it is preferable that the second bonding layer (320) be formed to have an area equal to or larger than the area of ​​the first bonding layer (220).

[0089] That is, in order to achieve more stable bonding by taking alignment tolerance into account in the transfer process, the second bonding layer (320) is formed relatively larger than the first bonding layer (220). In one embodiment of the present invention, the second bonding layer (320) may be formed 50% larger than the area of ​​the first bonding layer (220), and is preferably formed 10 to 30% larger. This is to implement optimal bonding and take into account the integration density of the device.

[0090] In addition, the second bonding layer (320) is characterized by having a step (322) formed by etching a portion of the second insulating layer (300). That is, the arrangement pattern of the second bonding layer (320) having the step (322) is formed on the second insulating layer (300). This allows for smooth bonding of the first bonding layer (220) and the second bonding layer (320), which are selective areas, without interference from other structures in the transfer process described later.

[0091] The height of the step (322) of the second bonding layer (320) is formed to have a step (322) of 10 nm to 10 μm from the upper surface of the etched second insulating layer (300), so that stable bonding is achieved in a selective area of ​​the first bonding layer (220) and the second bonding layer (320).

[0092] In addition, the period of the pattern of the second bonding layer (320) is formed to be equal to or larger than the size (A) of the unit semiconductor element chip (MMIC chip) to ensure stable bonding. Typically, the period of the pattern of the second bonding layer (320) is approximately 1 mm to 5 mm.

[0093] In addition, the second bonding layer (320) may be formed one or more times within the size (A) of a unit semiconductor element chip, and may be formed two or more times, three or more times, depending on the type of element.

[0094] And, the epitome (100) is placed on the target substrate (400) so that the first bonding layer (220) and the second bonding layer (320) are bonded (Step 6, FIGS. 4(a), (b), 11(a), (b)). In the bonding process according to one embodiment of the present invention, the first bonding layer (220) and the second bonding layer (320) are physically and chemically bonded by applying heat and pressure.

[0095] In this case, alignment bonding is performed, or the epi template (100) and the target substrate (400), or the epi growth substrate (110) and the target substrate (400), may include an alignment key for alignment when bonding the first bonding layer (220) and the second bonding layer (320).

[0096] In the bonding process according to the present invention, in order to alleviate alignment tolerance, the area of ​​the second bonding layer (320) is made wider than the area of ​​the first bonding layer (220) to ensure stable bonding, and a step (322) is provided in the second bonding layer (320) to selectively bond only the bonding layer area.

[0097] In addition, it is preferable that the bonding of the first bonding layer (220) and the second bonding layer (320) is performed within a range of a 30% offset (D) from the edge of the second bonding layer (320). That is, if the vertical central axes of the first bonding layer (220) and the second bonding layer (320) are aligned, the alignment is optimized, and if the alignment is not perfect and the vertical central axes thereof are offset, the edge of the first bonding layer (220) is bonded within a range of a 30% offset (D) from the edge of the second bonding layer (320).

[0098] To this end, the area of ​​the second bonding layer (320) is formed to be larger than that of the first bonding layer (220), and the bonding strength is maintained even if the first bonding layer (220) is offset within a range of 30%. If the offset range becomes larger than this, the bonding strength may decrease or tolerance may accumulate, which may affect the quality of the device depending on the device configuration or whether or not a flexible substrate is used.

[0099] Then, the sacrificial layer (120) exposed by the selective etching process is removed, and the electronic device layer (130) is selectively transferred onto the active device area on the target substrate (400) (Step 7, Figs. 4(c), (d), Figs. 11(c), (d)).

[0100] In a state where the first bonding layer (220) and the second bonding layer (320) are bonded, the sacrificial layer (120) exposed in the fourth step is removed through a selective etching process, specifically, a selective wet etching process, thereby separating the electronic component layer (130) from the substrate for epitaxial growth (110) and transferring it to the target substrate (400).

[0101] Here, in order to smoothly wet etch the sacrificial layer (120), the wet etching selectivity between the sacrificial layer (120) and other thin films is set to 10:1 or more, so that only the sacrificial layer (120) is removed and other thin films and structures are protected by the first insulating layer (200) and the second insulating layer (300). In particular, the sacrificial layer (120) is made of a material having a different etching selectivity from the first insulating layer (200) and the second insulating layer (300) so that selective etching can be performed.

[0102] According to one embodiment of the present invention, when the sacrificial layer (120) is made of AlAs or AlGaAs, hydrofluoric acid or BOE (buffered oxide etchant) is used as the etchant.

[0103] By the above process, the target epitaxial pattern (140) is transferred onto the active element area (on the second bonding layer (320) array pattern) on the target substrate (400). Thereafter, a portion of the first insulating layer (200) surrounding another target epitaxial pattern (140) to be transferred is etched, and steps 4 to 7 are repeated to selectively transfer the electronic element layer (130) onto each active element area on the target substrate (400) (Fig. 5, Fig. 12).

[0104] This selective repetitive transfer process is carried out in the same manner as described above, and in one embodiment of the present invention, although there may be differences depending on the layout of the MMIC chip and the selectivity of the sacrificial layer (120), it can be repeated approximately 2 to 100 times. That is, 2 to 100 epitaxial patterns (140) formed on an epitaxial growth substrate (InP or GaAs substrate) (110) are selectively arranged and transferred onto a target substrate (Si or Si CMOS substrate) (400), enabling the production of a large number of MMIC chips.

[0105] That is, by highly integrating a high-performance electronic device layer (130) on a Si or Si CMOS substrate through selective array transfer repetition, it includes not only a HEMT thin film but also various active device-use epitaxial thin films grown and transferred on an epitaxial growth substrate (InP or GaAs substrate) (110).

[0106] FIG. 6 and FIG. 7 are schematic diagrams showing the MMIC manufacturing sequence according to the embodiments of FIG. 2 to FIG. 6.

[0107] In Fig. 6(a) and (b), gate, source, and drain electrodes for electronic devices are formed from an electronic device layer (130) transferred onto a Si or Si CMOS substrate, and in Fig. 6(c), a resistor (R), which is a passive device, is formed.

[0108] In Fig. 7(a), an insulating layer (600) is formed and then planarized, in Fig. 7(b), a via hole (V) for an electrode is formed to connect a passive resistor (R) and an active HEMT electronic device (electronic device layer (130)), in Fig. 7(c), an electrode is formed to form a transmission line for radio wave transmission, and in Fig. 7(d), a passive capacitor (C) is formed.

[0109] FIG. 8 is a schematic diagram showing an MMIC chip in which the final plating electrode has been formed in the embodiments of FIGS. 6 and 7. By forming a plating electrode to electrically connect the active component, the HEMT electronic component layer (130), and the passive components, the resistor (R) and the z-capacitor (C), the manufacturing of an MMIC chip in which the active component, the passive component, the transmission line, and the electrode have been formed is completed.

[0110] Meanwhile, the above-described FIGS. 9 to 12 and FIGS. 13 and 14 illustrate a process for manufacturing an MMIC chip by selectively transferring a high-performance compound semiconductor electronic element layer (130) manufactured on a small-diameter epitaxial growth substrate (InP or GaAs substrate) (110) onto a large-diameter target substrate (Si or Si CMOS substrate) (400) using a selective array transfer method, specifically demonstrating the expandability of large diameters, and the manufacturing method is similar to the overall process described above. Accordingly, the epitaxial pattern (140) manufactured on the small-diameter epitaxial growth substrate (110) can be easily expanded to a large-diameter target substrate (400), thereby providing excellent applicability.

[0111] In this way, the present invention implements an epi template in which an epi pattern including an electronic device layer is formed using an epi growth substrate, and repeatedly transfers the epi template onto a target substrate to implement a highly integrated semiconductor device. This allows the relatively expensive epi growth substrate to be recycled or reused, thereby reducing the production cost. In addition, the epi pattern manufactured on a small-diameter epi growth substrate can be easily expanded to a large-diameter target substrate, so that the applicability is excellent.

[0112] Furthermore, it is easy to integrate electronic device layers with different functions onto each required unit semiconductor chip. This enables mass production, lowering manufacturing costs and enhancing price competitiveness. Furthermore, low-cost mass production is possible using existing process infrastructure. In particular, when using silicon as the target substrate, the process compatibility with existing silicon processes is highly advantageous, further reducing production costs.

Claims

1. A first step of forming a sacrificial layer on a substrate for epi growth and forming an electronic device layer on the sacrificial layer; A second step of forming an epitome in which an epi pattern is implemented by etching the electronic device layer and the sacrificial layer corresponding to the active device area; A third step of forming a first insulating layer surrounding the epi pattern on the epi template; A fourth step of etching a portion of the first insulating layer surrounding the target epi pattern to be transferred to expose the sacrificial layer, and forming a first bonding layer on the electronic device layer; A fifth step of forming a second insulating layer on a target substrate and etching a part of the second insulating layer corresponding to the first bonding layer to form a second bonding layer having a step; A sixth step of placing the epitemplate on the target substrate so that the first bonding layer and the second bonding layer are bonded; A seventh step of selectively transferring an electronic device layer onto the active device area on the target substrate by removing the sacrificial layer exposed by a selective etching process; A method for manufacturing a highly integrated semiconductor device utilizing selective transfer, characterized in that the steps 4 to 7 are repeated by etching a portion of the first insulating layer surrounding another target epi pattern to be transferred, thereby selectively transferring an electronic device layer onto each active device area on the target substrate.

2. In the first paragraph, the substrate for epi growth is A method for manufacturing a highly integrated semiconductor device using selective transfer, characterized in that the device is formed of a III-V group compound semiconductor.

3. In paragraph 1, the sacrificial layer is A method for manufacturing a highly integrated semiconductor device using selective transfer, characterized in that the first insulating layer and the second insulating layer use a material capable of selective etching.

4. In paragraph 1, the first insulating layer and the second insulating layer, It is formed as an oxide or nitride, A method for manufacturing a highly integrated semiconductor device using selective transfer, characterized in that the first insulating layer and the second insulating layer use materials of the same type or different types.

5. In the first paragraph, the first bonding layer of the fourth step is A method for manufacturing a highly integrated semiconductor device using selective transfer, characterized in that the electronic device layer of the epi pattern is formed on the upper side corresponding to the area of ​​the active device.

6. In paragraph 5, the area of ​​the first bonding layer is A method for manufacturing a highly integrated semiconductor device using selective transfer, characterized in that the device has a size of 10㎛ x 10㎛ to 300㎛ x 300㎛.

7. In the first paragraph, the second bonding layer of the fifth step is The area is equal to or greater than the area of ​​the first bonding layer, A method for manufacturing a highly integrated semiconductor device using selective transfer, characterized in that the area of ​​the first bonding layer is formed to a large extent compared to the area of ​​the first bonding layer.

8. In the first paragraph, the second bonding layer of the fifth step is A method for manufacturing a highly integrated semiconductor device using selective transfer, characterized by having a step size of 10 nm to 10 μm.

9. In the first paragraph, the period of the pattern of the second bonding layer is, Same as the size of a unit semiconductor device chip, or A method for manufacturing a highly integrated semiconductor device using selective transfer, characterized in that the device is formed to a size larger than that of a unit semiconductor device chip.

10. In the first paragraph, the second bonding layer, A method for manufacturing a highly integrated semiconductor device using selective transfer, characterized in that at least one semiconductor device is included within a unit semiconductor device chip size.

11. In the first paragraph, the bonding of the first bonding layer and the second bonding layer in the sixth step is A method for manufacturing a highly integrated semiconductor device using selective transfer, characterized in that it is implemented by a direct bonding method.

12. In the first paragraph, the bonding of the first bonding layer and the second bonding layer in the sixth step is A method for manufacturing a highly integrated semiconductor device using selective transfer, characterized in that the edge of the first bonding layer is positioned within a 30% offset range from the edge of the second bonding layer.

13. In the first paragraph, the epi template and the target substrate, or the substrate for epi growth and the target substrate, A method for manufacturing a highly integrated semiconductor device using selective transfer, characterized in that the method comprises an align key for alignment during bonding of the first bonding layer and the second bonding layer.

14. In paragraph 1, the target substrate is, A method for manufacturing a highly integrated semiconductor device using selective transfer, characterized in that the substrate is any one of an inorganic substrate, an organic substrate, a CMOS circuit board, and a PCB.

15. In paragraph 14, the target substrate is, An inorganic substrate of any one of Si, SiC, ZnO, MgO, sapphire, quartz and glass, or An organic substrate of any one of polycarbonate, polyethylene terephthalate, polyacrylate ether cellulose, polyimide and polyvinyl alcohol, or A method for manufacturing a highly integrated semiconductor device using selective transfer, characterized in that the semiconductor device is a Si-based CMOS circuit board.

16. In paragraph 1, the target substrate is, Same as the size of the substrate for epi growth above, or A method for manufacturing a highly integrated semiconductor device using selective transfer, characterized in that the size of the substrate for epitaxial growth is larger than that of the substrate for epitaxial growth.

17. In the first paragraph, the high-density semiconductor device, A method for manufacturing a highly integrated semiconductor device utilizing selective transfer, characterized in that it is a monolithic microwave integrated circuit (MMIC).

18. A target substrate having a second bonding layer formed thereon with a step; An active element formed on the target substrate, having a first bonding layer formed underneath and bonded to the second bonding layer, and including an electronic element layer; A highly integrated semiconductor device utilizing selective transfer, characterized in that the above active element is formed on a substrate for epitaxial growth with a sacrificial layer interposed therebetween and is selectively transferred onto the target substrate.

19. In paragraph 18, the first bonding layer is, An integrated semiconductor device utilizing selective transfer, characterized in that it is formed corresponding to the area of ​​the above active element.

20. In paragraph 18, the second bonding layer, The area is equal to or greater than the area of ​​the first bonding layer, A highly integrated semiconductor device utilizing selective transfer, characterized in that the device is formed to a larger area than the area of ​​the first bonding layer.

21. In paragraph 18, the second bonding layer is A highly integrated semiconductor device utilizing selective transfer characterized by a step size of 10 nm to 10 μm.

22. In paragraph 18, the period of the pattern of the second bonding layer is, Same as the size of a unit semiconductor device chip, or A highly integrated semiconductor device utilizing selective transfer, characterized in that it is formed larger than the size of a unit semiconductor device chip.

23. In paragraph 18, the second bonding layer, A highly integrated semiconductor device utilizing selective transfer, characterized in that at least one semiconductor device is included within a unit semiconductor device chip size.

24. In paragraph 18, the bonding of the first bonding layer and the second bonding layer is A highly integrated semiconductor device utilizing selective transfer, characterized in that the edge of the first bonding layer is positioned within a 30% offset range from the edge of the second bonding layer.

25. In paragraph 18, the target substrate is, A highly integrated semiconductor device utilizing selective transfer characterized by any one of an inorganic substrate, an organic substrate, a CMOS circuit board, and a PCB.

26. In paragraph 25, the target substrate is, An inorganic substrate of any one of Si, SiC, ZnO, MgO, sapphire, quartz and glass, or An organic substrate of any one of polycarbonate, polyethylene terephthalate, polyacrylate ether cellulose, polyimide and polyvinyl alcohol, or A highly integrated semiconductor device utilizing selective transfer, characterized by a Si-based CMOS circuit board.

27. In the 18th paragraph, the high-density semiconductor device, Highly integrated semiconductor devices utilizing selective transfer, characterized by being monolithic microwave integrated circuits (MMICs).

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