Display device

Abstract

An embodiment of the present invention discloses a display device including a display area and a non-display area outside the display area. The display device includes: island parts arranged in the display area and spaced apart from each other; bridge parts connecting adjacent island parts from among the island parts; and wirings arranged in the bridge parts, respectively, wherein each of the wirings includes a first layer, and the first layer includes a first sub-layer including an alloy of aluminum and a rare earth element, and a second sub-layer including aluminum.

Description

display device

[0001] Embodiments of the present invention relate to a display device, for example, a flexible display device.

[0002] As display devices that visually display electrical signals evolve, a variety of display devices with superior characteristics, such as thinness, lightness, and low power consumption, are being introduced. For example, flexible display devices that can be folded or rolled are being introduced. Recently, active research and development is underway on display devices with diverse structures, such as stretchable display devices capable of transforming into various forms.

[0003] Embodiments of the present invention provide a display device, such as a flexible display device. However, these tasks are exemplary and do not limit the scope of the present invention.

[0004] In one aspect of the present invention, a display device including a display area and a non-display area outside the display area, the display device including: island portions arranged in the display area and spaced apart from each other; bridge portions respectively connecting adjacent island portions among the island portions; and wirings arranged in each of the bridge portions; wherein each of the wirings includes a first layer, the first layer including a first sub-layer including an alloy of aluminum (Al) and a rare earth element, and a second sub-layer including aluminum.

[0005] In another aspect of the present invention, a display device including a display area and a non-display area outside the display area, the display device including islands arranged in the display area, each island including a transistor and a light-emitting element electrically connected to the transistor; and bridges connecting adjacent islands among the islands, each of the bridges including a wiring electrically connected to the transistor of one of the adjacent islands, the wiring including a first layer, the first layer including a first sub-layer including an alloy of aluminum and a rare earth element, and a second sub-layer including aluminum.

[0006] According to one embodiment of the present invention, a display device can be provided that prevents damage due to stress concentration and can be stretched in various directions. Of course, the scope of the present invention is not limited by these effects.

[0007] FIG. 1 is a perspective view schematically showing a display device according to one embodiment of the present invention.

[0008] Figures 2a and 2b are perspective views showing the display device of Figure 1 extended in the first direction.

[0009] Figure 2c is a perspective view showing the display device of Figure 1 extended in the second direction.

[0010] Figure 2d is a perspective view showing the display device of Figure 1 extended in the first direction and the second direction.

[0011] Figure 2e is a perspective view showing the display device of Figure 1 extended in the third direction.

[0012] Figure 3 is a schematic plan view of a display device according to one embodiment of the present invention.

[0013] FIG. 4a is an enlarged plan view of part IV of FIG. 3 as part of a display device according to one embodiment of the present invention.

[0014] FIG. 4b is an enlarged plan view of part IV of FIG. 3 as part of a display device according to another embodiment of the present invention.

[0015] FIG. 4c is an enlarged plan view of part IV of FIG. 3 as part of a display device according to another embodiment of the present invention.

[0016] FIG. 5 is a cross-sectional view schematically showing a first island portion and a first bridge portion arranged in a display area of ​​a display device according to one embodiment of the present invention.

[0017] FIGS. 6A to 6C are equivalent circuit diagrams of subpixels of a display device according to one embodiment of the present invention, respectively.

[0018] FIG. 7a is a cross-sectional view schematically showing a light-emitting element of a display device according to one embodiment of the present invention.

[0019] FIG. 7b is a cross-sectional view schematically showing a light-emitting element of a display device according to one embodiment of the present invention.

[0020] FIG. 8A is an enlarged plan view of a first island portion of a display device according to one embodiment of the present invention.

[0021] FIG. 8b is a plan view showing the arrangement of wiring on the first bridge portion of the display device according to one embodiment of the present invention.

[0022] Figure 9 shows a cross-section along line I-I' of Figure 8a and a cross-section along line II-II' of Figure 8b.

[0023] FIG. 10 is a cross-sectional view of a conductive layer constituting a wiring or connection electrode of a display device according to one embodiment of the present invention.

[0024] FIG. 11 is a cross-sectional view of a conductive layer of a display device according to another embodiment of the present invention.

[0025] Fig. 12 is a cross-sectional view of a conductive layer of a display device according to a comparative example of the present invention.

[0026] Figure 13 is a flowchart showing a method for manufacturing an alloy layer included in a conductive layer according to one embodiment of the present invention.

[0027] Fig. 14 shows the microstructure of an alloy layer according to one embodiment of the present invention.

[0028] Fig. 15 shows the microstructure of a conductive layer according to one embodiment of the present invention.

[0029] Figure 16 is a graph showing the resistivity of a conductive layer according to embodiments of the present invention.

[0030] Figure 17 is a graph showing the resistivity of a conductive layer according to embodiments and comparative examples of the present invention.

[0031] Figure 18 is a graph showing the results of a tensile test of a conductive layer according to comparative examples of the present invention.

[0032] Figure 19 is a graph showing the results of a tensile test of a conductive layer according to embodiments of the present invention.

[0033] Figure 20 is a graph showing the results of a tensile test of a conductive layer according to other embodiments of the present invention.

[0034] FIGS. 21A to 21G are perspective views schematically illustrating embodiments of an electronic device including a display device according to one embodiment of the present invention.

[0035] In one embodiment, each of the first sub-layer and the second sub-layer is provided in multiple numbers, and the first layer may have a structure in which the first sub-layers and the second sub-layers are alternately stacked.

[0036] In one embodiment, two of the first sublayers may be disposed on the top and bottom of the first layer, respectively.

[0037] In one embodiment, the first sublayer may be an amorphous alloy layer.

[0038] In one embodiment, the rare earth element may include at least one of yttrium (Y), samarium (Sm), cerium (Ce), or lanthanum (La).

[0039] In one embodiment, the content of the rare earth element may be 4 at% or more and 10 at% or less based on the total atomic weight of the first sublayer.

[0040] In one embodiment, the ratio of the thickness of each of the first sublayers to the thickness of each of the second sublayers may be 1 or less.

[0041] In one embodiment, the resistivity of the first layer may be greater than 5.6 μΩ·cm and less than 11 μΩ·cm.

[0042] In one embodiment, the elastic strain of the first layer may be greater than or equal to 2.0%.

[0043] In one embodiment, the yield strength of the first layer may be greater than or equal to 0.8 GPa and less than or equal to 1.2 GPa.

[0044] In one embodiment, each of the wires further comprises a second layer below the first layer and a third layer above the first layer, wherein the second layer and the third layer may comprise a different material than the first layer.

[0045] In one embodiment, each of the islands comprises: a transistor including a semiconductor and a gate electrode; a light-emitting element electrically connected to the transistor; and an electrode disposed between the gate electrode and the light-emitting element; wherein the electrode may include a third sub-layer including an alloy of aluminum and a rare earth element, and a fourth sub-layer including aluminum.

[0046] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0047] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals and redundant descriptions thereof will be omitted.

[0048] In the examples below, the terms first, second, etc. are not used in a limiting sense, but are used for the purpose of distinguishing one component from another.

[0049] In the examples below, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0050] In the following examples, terms such as “include” or “have” mean that a feature or component described in the specification is present, and do not preclude the possibility that one or more other features or components may be added.

[0051] In the following examples, when a part such as a film, region, component, etc. is said to be on or above another part, it includes not only a case where it is directly on top of the other part, but also a case where another film, region, component, etc. is interposed in between.

[0052] For convenience of explanation, the sizes of components in the drawings may be exaggerated or reduced. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily indicated for convenience of explanation, and thus the present invention is not necessarily limited to what is shown.

[0053] In some embodiments, where implementations are otherwise feasible, specific process sequences may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously, or in a reverse order from the described order.

[0054] In this specification, 'A and / or B' indicates the case where it is A, or B, or both A and B. In addition, 'at least one of A or B' indicates the case where it is A, or B, or both A and B.

[0055] In the following examples, when it is said that a film, region, component, etc. are connected, it includes cases where the films, regions, components, etc. are directly connected, and / or cases where other films, regions, components, etc. are interposed between the films, regions, components, etc. and are indirectly connected. For example, when it is said in this specification that a film, region, component, etc. are electrically connected, it refers to cases where the films, regions, components, etc. are directly electrically connected, and / or cases where other films, regions, components, etc. are interposed between them and are indirectly electrically connected.

[0056] The x-axis, y-axis, and z-axis are not limited to the three axes in the Cartesian coordinate system, but can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they can also refer to different directions that are not orthogonal to each other.

[0057] As used herein, the terms "approximately" or "about" include the stated value and mean an acceptable range of deviation from the stated value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with measuring the particular quantity (i.e., limitations of the measurement system). For example, "approximately" can mean within one or more standard deviations, or within ± 10%, 5%, or 2% of the stated value.

[0058] Fig. 1 is a perspective view schematically illustrating a display device (1) according to one embodiment of the present invention. Figs. 2a and 2b are perspective views illustrating the display device (1) of Fig. 1 in a state extended in a first direction. Fig. 2c is a perspective view illustrating the display device (1) of Fig. 1 in a state extended in a second direction. Fig. 2d is a perspective view illustrating the display device (1) of Fig. 1 in a state extended in the first and second directions. Fig. 2e is a perspective view illustrating the display device (1) of Fig. 1 in a state extended in a third direction.

[0059] Referring to FIG. 1, a display device (1) may include a display area (DA) and a non-display area (NDA). The display area (DA) may include pixels. The display device (1) may provide a predetermined image using light emitted from the pixels. The non-display area (NDA) may be positioned outside the display area (DA). The non-display area (NDA) may entirely surround the display area (DA).

[0060] The display device (1) can be extended or contracted in various directions. The display device (1) can be extended in a first direction (e.g., in the x-direction and / or in the -x-direction) by an external force applied by an external object or a user. In one embodiment, as illustrated in FIGS. 2A and 2B, the display area (DA) and / or the non-display area (NDA) of the display device (1) can be extended in the first direction (e.g., in the x-direction and / or in the -x-direction). For example, as illustrated in FIG. 2A, the display device (1) can be extended along the x-direction and the -x-direction, or as illustrated in FIG. 2B, one side of the display device (1) can be fixed and the display device (1) can be extended along the x-direction.

[0061] The display device (1) can be stretched in a second direction (e.g., the y direction and / or the -y direction) by an external force applied by an external object or a user. In one embodiment, as illustrated in FIG. 2c, the display area (DA) and / or the non-display area (NDA) of the display device (1) can be stretched in the y direction and the -y direction. In another embodiment, one side of the display device (1) can be fixed while being stretched in the y direction or the -y direction.

[0062] The display device (1) can be extended in a direction, for example, in a first direction (e.g., in the x direction and / or in the -x direction) and a second direction (e.g., in the y direction and / or in the -y direction) by an external force applied by an external object or a part of a human body. As illustrated in Fig. 2d, the display area (DA) and / or the non-display area (NDA) of the display device (1) can be extended in the ±x direction and the ±y direction.

[0063] The display device (1) can be elongated in a third direction (e.g., the z direction or the -z direction) by an external force applied by an external object or a part of a human body. In one embodiment, FIG. 2e illustrates that a part of the display device (1), for example, a part of the display area (DA), protrudes in the z direction. In another embodiment, a part of the display device (1), for example, a part of the display area (DA), can protrude along the -z direction (or be sunken along the z direction).

[0064] Although FIGS. 2A to 2E illustrate the display device (1) extending in the first, second, and / or third directions, the present invention is not limited thereto. In other embodiments, the display device (1) may be variously deformed into an irregular shape, such as being bent or twisted along two or more axes.

[0065] Figure 3 is a schematic plan view of a display device (1) according to one embodiment of the present invention.

[0066] Pixels may be arranged in a display area (DA) of a display device (1). Each pixel may include subpixels that emit light of different colors. Light-emitting elements corresponding to each subpixel may be arranged in the display area (DA). A circuit for providing electrical signals to the light-emitting elements arranged in the display area (DA) and to transistors electrically connected to the light-emitting elements may be located in a non-display area (NDA) surrounding the display area (DA). A gate driving circuit (GDC) may be arranged in a first non-display area (NDA1) and a second non-display area (NDA2) arranged on both sides of the display area (DA). The gate driving circuit (GDC) may include drivers for providing electrical signals to gate electrodes of each of the transistors electrically connected to the light-emitting elements. FIG. 3 illustrates that the gate driving circuit (GDC) is arranged in each of the first non-display area (NDA1) and the second non-display area (NDA2), but the present invention is not limited thereto. In another embodiment, the gate drive circuit (GDC) may be placed in either the first non-display area (NDA1) or the second non-display area (NDA2).

[0067] The data drive circuit (DDC) may be disposed in a third non-display area (NDA3) and / or a fourth non-display area (NDA4) connecting the first non-display area (NDA1) and the second non-display area (NDA2). In one embodiment, FIG. 3 illustrates that the data drive circuit (DDC) is disposed in the fourth non-display area (NDA4). In another embodiment, the data drive circuit (DDC) may be disposed in each of the third non-display area (NDA3) and the fourth non-display area (NDA4).

[0068] Although Fig. 3 illustrates that the data drive circuit (DDC) is arranged in the fourth non-display area (NDA4) of the display device (1), the present invention is not limited thereto. In another embodiment, the display device (1) may further include a flexible circuit board (not shown) electrically connected to the display device (1) through a terminal portion (not shown) arranged in the fourth non-display area (NDA4), and the data drive circuit (DDC) may be arranged on the aforementioned flexible circuit board.

[0069] In some embodiments, the elongation rate of the non-display area (NDA) may be equal to or less than the elongation rate of the display area (DA). In one embodiment, the elongation rates of the non-display areas (NDAs) may be different for each area. For example, the first non-display area (NDA1), the second non-display area (NDA2), and the third non-display area (NDA3) may have substantially the same elongation rates, but the elongation rate of the fourth non-display area (NDA4) may be less than the elongation rates of each of the first non-display area (NDA1), the second non-display area (NDA2), and the third non-display area (NDA3).

[0070] FIG. 4a is an enlarged plan view of part IV of FIG. 3 as part of a display device (1) according to one embodiment of the present invention.

[0071] Referring to FIG. 4a, the display device (1) may include first island portions (11) spaced apart from each other along a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in a display area (DA), and first bridge portions (12) connecting adjacent first island portions (11).

[0072] Each first island portion (11) may be connected to first bridge portions (12). For example, each first island portion (11) may be connected to four first bridge portions (12). Two first bridge portions (12) may be arranged on both sides of the first island portion (11) along a first direction (e.g., x direction or -x direction), and the remaining two first bridge portions (12) may be arranged on both sides of the first island portion (11) along a second direction (e.g., y direction or -y direction). In one embodiment, four first bridge portions (12) may be connected to four sides of the first island portion (11), respectively. Each of the four first bridge portions (12) may be adjacent to each corner of the first island portion (11).

[0073] The first bridge portions (12) may be spaced apart from each other by first openings (CS1) positioned between the first bridge portions (12). In one embodiment, the first openings (CS1) having an approximately H shape and the first openings (CS1) having an approximately I shape obtained by rotating the aforementioned H shape by 90 degrees may be alternately and repeatedly arranged along the first direction (e.g., the x direction or the -x direction) and the second direction (e.g., the y direction or the -y direction). Both ends of each first bridge portion (12) are connected to each of the adjacent first island portions (11), but one side of each first bridge portion (12) may be spaced apart from one side of the adjacent first island portion (11) and / or one side of another first bridge portion (12) by the first openings (CS1).

[0074] The display device (1) may include second island portions (21) spaced apart from each other and second bridge portions (22) connecting adjacent second island portions (21) in a non-display area (NDA), for example, the first non-display area (NDA1) illustrated in FIG. 4a.

[0075] Each second island portion (21) may extend along a first direction (e.g., x-direction or -x-direction). The second island portions (21) may be spaced apart from each other along a second direction (e.g., y-direction or -y-direction) intersecting the first direction (e.g., x-direction or -x-direction). Each second island portion (21) may include drivers of a gate drive circuit (GDC, FIG. 3) described with reference to FIG. 3.

[0076] The second bridge portion (22) may have a serpentine shape. The length of the second bridge portion (22) may be greater than the shortest distance between adjacent second island portions (21) along the second direction (e.g., the y direction or the -y direction). In one embodiment, the second bridge portion (22) may have a shape of approximately omega (Ω) that is convex toward the first direction (e.g., the x direction or the -x direction). The second bridge portions (22) may be arranged between adjacent second island portions (21), but may be spaced apart from each other.

[0077] The second bridge portions (22) between adjacent second island portions (21) can be spaced apart from each other by the second opening portions (CS2). Between the adjacent second island portions (21), the second opening portions (CS2) and the second bridge portions (22) can be alternately arranged along the first direction (e.g., the x-direction or the -x-direction). The second opening portions (CS2) can have the same shape. Both ends of each second bridge portion (22) are connected to the adjacent second island portions (21), but one side of each second bridge portion (22) can be spaced apart from one side of the second island portion (21) adjacent to the second bridge portion (22) and / or one side of another second bridge portion (22) by the second opening portions (CS2).

[0078] Any one of the second island portions (21) arranged in the first non-display area (NDA1) can correspond to the first island portions (11) of the rows arranged in the display area (DA). For example, any one of the second island portions (21) arranged in the first non-display area (NDA1) can correspond to the first island portions (11) arranged in the (i)-th row and the first island portions (11) arranged in the (i+1)-th row in the display area (DA) (here, i is a positive integer greater than 0). Although Fig. 4a illustrates that one second island portion (21) corresponds to two rows of the first island portions (11), the present invention is not limited thereto. In another embodiment, any one of the second island portions (21) arranged in the first non-display area (NDA1) can correspond to n rows of the first island portions (11) arranged in the display area (DA) (here, n is a positive integer greater than or equal to 3).

[0079] A non-display area (NDA), for example, a first non-display area (NDA1), may include a first sub-non-display area (SNDA1) in which the second island portions (21) and the second bridge portions (22) described above are arranged, and a second sub-non-display area (SNDA2) between the first sub-non-display area (SNDA1) and the display area (DA). Third bridge portions (23) may be arranged in the second sub-non-display area (SNDA2) to connect the display area (DA) and the first sub-non-display area (SNDA1). One end of the third bridge portion (23) may be connected to the second island portion (21) and / or the second bridge portion (22), and the other end of the third bridge portion (23) may be connected to the first island portion (11) and / or the first bridge portion (12).

[0080] The third bridge portion (23) may have a serpentine shape. In one embodiment, the shape of the third bridge portion (23) may be different from the shapes of the first bridge portion (12) and the second bridge portion (22). In one embodiment, as illustrated in FIG. 4A, the third bridge portion (23) may have a shape of approximately omega (Ω) that is convex in the second direction (e.g., the y direction or the -y direction). Among adjacent third bridge portions (23) arranged along the second direction (e.g., the y direction or the -y direction), one may have a structure that is symmetrical to each other, such as being convex in the y direction and the other being convex in the -y direction. Between the third bridge portions (23), the third opening portions (CS3) and the fourth opening portions (CS4) of different shapes may have a structure in which they are repeated. The width of the third bridge portion (23) may be different from the width of the first bridge portion (12) and the width of the second bridge portion (22). In one embodiment, the width of the third bridge portion (23) may be larger than the width of the first bridge portion (12) and smaller than the width of the second bridge portion (22).

[0081] FIG. 4a shows that the second island portion (21) and the second bridge portion (22) of the non-display area (NDA), for example, the first non-display area (NDA1), have different shapes from the first island portion (11) and the first bridge portion (12) of the display area (DA), respectively. In another embodiment of the present invention, the second island portion (21) and the second bridge portion (22) of the non-display area (NDA) may have the same shapes as the first island portion (11) and the first bridge portion (12) of the display area (DA), respectively.

[0082] FIG. 4b is an enlarged plan view of part IV of FIG. 3 as part of a display device (1) according to another embodiment of the present invention.

[0083] Referring to Fig. 4b, the display device (1) includes first island portions (11) spaced apart from each other in the display area (DA) and first bridge portions (12) connecting adjacent first island portions (11) spaced apart from each other by a first opening (CS1). The structure of the display area (DA) of Fig. 4b may be the same as the structure of the display area (DA) described above with reference to Fig. 4a.

[0084] The display device (1) may include second island portions (21) and second bridge portions (22) arranged in a non-display area (NDA), for example, a first non-display area (NDA1). In one embodiment, the second island portions (21) and the second bridge portions (22) may have substantially the same shape as the first island portions (11) and the first bridge portion (12), respectively.

[0085] The second island portions (21) can be spaced apart from each other in a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in a non-display area (NDA), for example, a first non-display area (NDA1). Each of the second bridge portions (22) can connect adjacent second island portions (21). The second bridge portions (22) can be spaced apart from each other by a second opening (CS2) located between the second bridge portions (22).

[0086] The second opening (CS2) may have substantially the same shape as the first opening (CS1). For example, the second opening (CS2) having an approximately H shape and the second opening (CS2) having an approximately I shape may be alternately and repeatedly arranged in a non-display area (NDA), for example, the first non-display area (NDA1). The two ends of each second bridge portion (22) are connected to each of the adjacent second island portions (21), and one side of each second bridge portion (22) may be spaced apart from one side of the second island portion (21) adjacent to the second bridge portion (22) and / or one side of another second bridge portion (22) by the second opening (CS2).

[0087] Each second island section (21) can be connected to four second bridge sections (22). Each second island section (21) can include drivers of the gate drive circuit (GDC, FIG. 3) described with reference to FIG. 3.

[0088] The second island portions (21) of any one row arranged in the first non-display area (NDA1) may correspond to the first island portions (11) of any one row arranged in the display area (DA). For example, the second island portions (21) arranged in the (i)th row along the first direction (e.g., the x-direction or the -x-direction) in the first non-display area (NDA1) may correspond to the first island portions (11) arranged in the same row, e.g., the (i)th row, in the display area (DA) (wherein, i is a positive number greater than 0).

[0089] The display device (1) may include third bridge units (23) arranged in a second sub-non-display area (SNDA2) for connecting a display area (DA) and a first sub-non-display area (SNDA1). The non-display area (NDA), for example, the first non-display area (NDA1), may include a first sub-non-display area (SNDA1) in which second island units (21) and second bridge units (22) are arranged, and a second sub-non-display area (SNDA2) including third bridge units (23) and positioned between the first sub-non-display area (SNDA1) and the display area (DA). The third bridge unit (23) may be substantially the same as the first bridge unit (12) and the second bridge unit (22). For example, the width of the third bridge unit (23) may be the same as the width of the first bridge unit (12) and the width of the second bridge unit (22).

[0090] FIG. 4c is an enlarged plan view of part IV of FIG. 3 as part of a display device (1) according to another embodiment of the present invention.

[0091] Referring to FIG. 4c, the display device (1) may include first island portions (11) spaced apart from each other in a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in the display area (DA), and first bridge portions (12) connecting adjacent first island portions (11).

[0092] The first bridge portions (12) may be arranged to be spaced apart from each other by a first opening (CS1) located between the first bridge portions (12). The first bridge portion (12) may have a winding shape. For example, as illustrated in Fig. 4c, the first bridge portion (12) may have a shape roughly like the letter 'S'.

[0093] Each first island portion (11) can be connected to first bridge portions (12). For example, each first island portion (11) can be connected to four first bridge portions (12). Two first bridge portions (12) can be arranged on both sides of the first island portion (11) along a first direction (e.g., x direction or -x direction), and the remaining two first bridge portions (12) can be arranged on both sides of the first island portion (11) along a second direction (e.g., y direction or -y direction). The four first bridge portions (12) can be connected to the four sides of the first island portion (11), respectively. Each of the four first bridge portions (12) can be adjacent to each corner of the first island portion (11).

[0094] The display device (1) may include second island portions (21) spaced apart from each other in a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in a non-display area (NDA), for example, a first non-display area (NDA1) illustrated in FIG. 4c, and second bridge portions (22) connecting adjacent second island portions (21).

[0095] The second bridge portions (22) may be spaced apart from each other by a second opening (CS2) located between the second bridge portions (22). The second bridge portion (22) may have a winding shape. For example, as illustrated in FIG. 4C, the second bridge portion (22) may have a shape roughly like the letter 'S'. The size and / or width of the second bridge portion (22) may be different from the size and / or width of the first bridge portion (12). For example, the size and / or width of the second bridge portion (22) may be larger than the size and / or width of the first bridge portion (12). The radius of curvature of the rounded portion of the second bridge portion (22) may be different from the radius of curvature of the rounded portion of the first bridge portion (12). For example, the radius of curvature of the rounded portion of the second bridge portion (22) may be greater than the radius of curvature of the rounded portion of the first bridge portion (12).

[0096] Each second island portion (21) can be connected to second bridge portions (22). Each second island portion (21) can be connected to four second bridge portions (22). Two second bridge portions (22) can be arranged on both sides of the second island portion (21) along a first direction (e.g., x direction or -x direction), and the remaining two second bridge portions (22) can be arranged on both sides of the second island portion (21) along a second direction (e.g., y direction or -y direction). In one embodiment, four second bridge portions (22) can be respectively connected to four sides of the second island portion (21). Each second bridge portion (22) can be connected to a central portion of each side of the second island portion (21).

[0097] The second island portions (21) of any one row arranged in the first non-display area (NDA1) may correspond to the first island portions (11) of the rows arranged in the display area (DA). For example, the second island portions (21) of any one row arranged in the first non-display area (NDA1) may correspond to the first island portions (11) arranged in the (i)-th row of the display area (DA) and the first island portions (11) arranged in the (i+1)-th row (here, i is a positive integer greater than 0). In another embodiment, the second island portions (21) of any one row may correspond to n rows of the first island portions (11) (here, n is a positive integer greater than 3).

[0098] A non-display area (NDA), for example, a first non-display area (NDA1), may include a first sub-non-display area (SNDA1) in which the aforementioned second island portions (21) and second bridge portions (22) are arranged, and a second sub-non-display area (SNDA2) between the first sub-non-display area (SNDA1) and the display area (DA). Third bridge portions (23) may be arranged in the second sub-non-display area (SNDA2) to connect the display area (DA) and the first sub-non-display area (SNDA1). One end of the third bridge portion (23) may be connected to the second island portion (21), and the other end of the third bridge portion (23) may be connected to the first island portion (11). For example, one end of the third bridge portion (23) may be connected to the central portion of one side of the second island portion (21), and the other end of the third bridge portion (23) may be connected to the central portion of one side of the first island portion (11).

[0099] The third bridge portion (23) may have a serpentine shape. In one embodiment, the shape of the third bridge portion (23) may be different from the shapes of the first bridge portion (12) and the second bridge portion (22). The width of the third bridge portion (23) may be different from the width of the first bridge portion (12) and the width of the second bridge portion (22). The width of the third bridge portion (23) may be larger than the width of the first bridge portion (12) and smaller than the width of the second bridge portion (22). Third openings (CS3) and fourth openings (CS4) of different shapes may be alternately arranged between the third bridge portions (23) in the second direction (e.g., the y direction or the -y direction).

[0100] FIG. 5 is a cross-sectional view schematically showing a first island portion (11) and a first bridge portion (12) arranged in a display area (DA) of a display device (1) according to one embodiment of the present invention.

[0101] Referring to Fig. 5, the first island portion (11) and the first bridge portion (12) arranged in the display area (DA) may be spaced apart from each other with the first opening (CS1) therebetween. The first island portion (11) includes light-emitting elements (LEDs) and a circuit for driving the light-emitting elements electrically connected thereto, for example, a pixel driving circuit portion (PC), and the first bridge portion (12) may include wiring (WL) electrically connected to pixel driving circuit portions (PC) arranged in each of the adjacent first island portions (11).

[0102] Looking at the first island portion (11), a buffer layer (111) including an inorganic insulator is disposed on a substrate (100), and a pixel driver circuit (PC) may be disposed on the buffer layer (111). An insulating layer (IL) including an inorganic insulator and / or an organic insulator may be disposed between the pixel driver circuit (PC) and the light emitting element (LED). The light emitting element (LED) is disposed on the insulating layer (IL) and may be electrically connected to a corresponding pixel driver circuit (PC). The light emitting elements (LED) may emit light of different colors or the same color. In one embodiment, the light emitting elements (LED) may emit red, green, and blue light, respectively. In some embodiments, the light emitting elements (LED) may emit white light. In another embodiment, the light emitting elements (LED) may emit red, green, blue, and white light, respectively.

[0103] The substrate (100) may include a polymer resin such as polyethersulfone, polyarylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate. In one embodiment, the substrate (100) may be a single layer including the aforementioned polymer resin. In another embodiment, the substrate (100) may be a multilayer structure including a base layer including the aforementioned polymer resin and a barrier layer including an inorganic insulating material. The substrate (100) including the polymer resin may have flexible, rollable, and bendable properties.

[0104] In one embodiment, FIG. 5 illustrates three pixel driver circuits (PCs) arranged in each first island portion (11) and three light-emitting elements (LEDs) connected to each pixel driver circuit portion (PC), but the present invention is not limited thereto. In another embodiment, the number of pixel driver circuits (PCs) and light-emitting elements (LEDs) arranged in the first island portion (11) may be one, two, four or more.

[0105] The encapsulation layer (300) may be disposed on a light-emitting element (LED) and may protect the light-emitting element (LED) from external force and / or moisture permeation. The encapsulation layer (300) may include an inorganic encapsulation layer and / or an organic encapsulation layer. In some embodiments, the encapsulation layer (300) may include a structure in which an inorganic encapsulation layer including an inorganic insulating material, an organic encapsulation layer including an organic insulating material, and an inorganic encapsulation layer including an inorganic insulating material are laminated. In other embodiments, the encapsulation layer (300) may include an organic material such as a resin. In some embodiments, the encapsulation layer (300) may include urethane epoxy acrylate. The encapsulation layer (300) may include a photosensitive material, for example, a material such as a photoresist.

[0106] Looking at the first bridge portion (12), an insulating layer (IL) including an organic insulating material may be placed on the substrate (100). When the display device (1) is stretched, the first bridge portion (12), which is relatively subject to a large amount of deformation, may not have a layer including an inorganic insulating material that is prone to cracking, unlike the first island portion (11).

[0107] In one embodiment, the substrate (100) corresponding to the first bridge portion (12) may have the same laminated structure as the substrate (100) corresponding to the first island portion (11). In one embodiment, the substrate (100) corresponding to the first bridge portion (12) and the substrate (100) corresponding to the first island portion (11) may be polymer resin layers formed together in the same process. In another embodiment, the substrate (100) corresponding to the first bridge portion (12) may have a different laminated structure from the substrate (100) corresponding to the first island portion (11). In some embodiments, the substrate (100) corresponding to the first island portion (11) may have a multilayer structure including a base layer including a polymer resin and a barrier layer including an inorganic insulating material, and the substrate (100) corresponding to the first bridge portion (12) may have a structure of a polymer resin layer without a layer including an inorganic insulating material.

[0108] The wirings (WL) of the first bridge unit (12) may be signal lines (e.g., gate lines, data lines, etc.) for providing electrical signals to transistors included in the pixel driving circuit unit (PC) of the first island unit (11), as described above, or voltage lines (e.g., driving voltage lines, initialization voltage lines, etc.) for providing voltage. In one embodiment, a sealing layer (300) may also be disposed on the first bridge unit (12). In another embodiment, the sealing layer (300) may not be disposed on the first bridge unit (12).

[0109] Referring to FIGS. 4A to 4C and FIG. 5, the substrate (100) corresponding to the first island portion (11) and the substrate (100) corresponding to the first bridge portion (12) may be connected to each other. In other words, the plan views illustrated in FIGS. 4A to 4C may be substantially the same as the plan view of the substrate (100) of FIG. 5. In other words, the substrate (100) may include an area corresponding to the first island portion (11), an area corresponding to the first bridge portion (12), and an opening (100OP1) having the same shape as the first opening (CS1).

[0110] Similarly, the sealing layer (300) corresponding to the first island portion (11) and the sealing layer (300) corresponding to the first bridge portion (12) may be connected to each other. For example, the plan views illustrated in FIGS. 4A to 4C above may be substantially identical to the plan views of the sealing layer (300). In other words, the sealing layer (300) may include an area corresponding to the first island portion (11), an area corresponding to the first bridge portion (12), and an opening (300OP1) having the same shape as the first opening portion (CS1).

[0111] The circuit-light-emitting element layer (200) between the substrate (100) and the encapsulation layer (300) may include a buffer layer (111), a pixel driving circuit (PC), a wiring (WL), an insulating layer (IL), and a light-emitting element (LED). Similar to the substrate (100), the plan views illustrated in FIGS. 4A to 4C may be substantially the same as the plan views of the circuit-light-emitting element layer (200). In other words, the circuit-light-emitting element layer (200) may include an opening (200OP1) having the same shape as the first opening (CS1).

[0112] Figures 6a to 6c are equivalent circuit diagrams of subpixels of a display device (1) according to one embodiment of the present invention, respectively.

[0113] Referring to FIG. 6a, a light emitting element (LED) corresponding to a subpixel is electrically connected to a pixel driver circuit (PC), and the pixel driver circuit (PC) may include a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst). The pixel driver circuit (PC) may be electrically connected to a signal line and a voltage line. The signal line may include a gate line such as a first scan line (SL1) and a data line (DL), and the voltage line may include a first voltage line (VDDL).

[0114] The second transistor (T2) can be electrically connected to the first scan line (SL1) and the data line (DL). The first scan line (SL1) can provide a first scan signal (GW) to a gate electrode of the second transistor (T2). The second transistor (T2) can transmit a data signal (Dm) input from the data line (DL) to the first transistor (T1) according to the first scan signal (GW) input from the first scan line (SL1).

[0115] The storage capacitor (Cst) is electrically connected to the second transistor (T2) and the first voltage line (VDDL), and can store a voltage corresponding to the difference between the voltage received from the second transistor (T2) and the first power voltage (VDD) supplied by the first voltage line (VDDL).

[0116] The first transistor (T1) is a driving transistor and can control a driving current flowing through a light-emitting element (LED). The first transistor (T1) can be connected to a first voltage line (VDDL) and a storage capacitor (Cst). The first transistor (T1) can control a driving current flowing through the light-emitting element (LED) from the first voltage line (VDDL) in response to a voltage value stored in the storage capacitor (Cst). The light-emitting element (LED) can emit light having a predetermined brightness by the driving current. A first electrode of the light-emitting element (LED) can be electrically connected to the first transistor (T1), and a second electrode can be electrically connected to a second voltage line (VSSL) that supplies a second power voltage (VSS).

[0117] Although FIG. 6a illustrates that the pixel driver circuit (PC) includes two transistors and one storage capacitor, in other embodiments, the pixel driver circuit (PC) may include three or more transistors.

[0118] Referring to FIG. 6b, the pixel driving circuit unit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), and a storage capacitor (Cst).

[0119] The pixel driver circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines such as a first scan line (SL1), a second scan line (SL2), a third scan line (SL3), and an emission control line (EML), and a data line (DL). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2) and a first voltage line (VDDL).

[0120] The first voltage line (VDDL) can transmit the first power voltage (VDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit the first initialization voltage (Vint) that initializes the first transistor (T1) to the pixel driver circuit (PC). The second initialization voltage line (VIL2) can transmit the second initialization voltage (Vaint) that initializes the first electrode of the light-emitting element (LED) to the pixel driver circuit (PC).

[0121] The first transistor (T1) may be electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and may be electrically connected to the light-emitting element (LED) via the sixth transistor (T6). The first transistor (T1) functions as a driving transistor, and receives a data signal (Dm) according to the switching operation of the second transistor (T2) to supply a driving current to the light-emitting element (LED).

[0122] The second transistor (T2) is a data writing transistor and is electrically connected to the first scan line (SL1) and the data line (DL). The second transistor (T2) is electrically connected to the first voltage line (VDDL) via the fifth transistor (T5). The second transistor (T2) is turned on in response to the first scan signal (GW) received through the first scan line (SL1) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0123] The third transistor (T3) is electrically connected to the first scan line (SL1) and is electrically connected to the light-emitting element (LED) via the sixth transistor (T6). The third transistor (T3) can be turned on in response to the first scan signal (GW) received through the first scan line (SL1) to diode-connect the first transistor (T1).

[0124] The fourth transistor (T4) is a first initialization transistor and is electrically connected to the third scan line (SL3) and the first initialization voltage line (VIL1). The fourth transistor (T4) is turned on according to the third scan signal (GI) received through the third scan line (SL3) and transmits the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1) to initialize the voltage of the gate electrode of the first transistor (T1). The third scan signal (GI) may correspond to the first scan signal of another pixel driver circuit unit arranged in the previous row of the corresponding pixel driver circuit unit (PC).

[0125] The fifth transistor (T5) may be a motion control transistor, and the sixth transistor (T6) may be a light emission control transistor. The fifth transistor (T5) and the sixth transistor (T6) are electrically connected to the light emission control line (EML), and are turned on simultaneously according to the light emission control signal (EM) transmitted through the light emission control line (EML), thereby forming a current path so that a driving current can flow from the first voltage line (VDDL) in the direction of the light emitting element (LED).

[0126] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to the second scan line (SL2), the second initialization voltage line (VIL2), and the sixth transistor (T6). The seventh transistor (T7) is turned on according to the second scan signal (GB) transmitted through the second scan line (SL2), and can transmit the second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the first electrode of the light-emitting element (LED) to initialize the first electrode of the light-emitting element (LED).

[0127] A storage capacitor (Cst) includes a first electrode (CE1) and a second electrode (CE2). The first electrode (CE1) is electrically connected to the gate electrode of the first transistor (T1), and the second electrode (CE2) is electrically connected to the first voltage line (VDDL). The storage capacitor (Cst) can maintain a voltage applied to the gate electrode of the first transistor (T1) by storing and maintaining a voltage corresponding to a difference between the voltages at both ends of the first voltage line (VDDL) and the gate electrode of the first transistor (T1).

[0128] Referring to FIG. 6c, the pixel driving circuit unit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), an eighth transistor (T8), a ninth transistor (T9), a storage capacitor (Cst), and an auxiliary capacitor (Ca).

[0129] The pixel driver circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines such as a first scan line (SL1), a second scan line (SL2), a third scan line (SL3), and an emission control line (EML), and a data line (DL). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2), a sustain voltage line (VSL), and a first voltage line (VDDL).

[0130] The first voltage line (VDDL) can transmit a first power voltage (VDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit a first initialization voltage (Vint) for initializing the first transistor (T1) to the pixel driver circuit (PC). The second initialization voltage line (VIL2) can transmit a second initialization voltage (Vaint) for initializing the first electrode of the light-emitting element (LED) to the pixel driver circuit (PC). The sustain voltage line (VSL) can provide a sustain voltage (VSUS) to the second node (N2), for example, the second electrode (CE2) of the storage capacitor (Cst), during the initialization period and the data writing period.

[0131] The first transistor (T1) may be electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and the eighth transistor (T8), and may be electrically connected to the light-emitting element (LED) via the sixth transistor (T6). The first transistor (T1) functions as a driving transistor, and may receive a data signal (Dm) according to the switching operation of the second transistor (T2) to supply a driving current to the light-emitting element (LED).

[0132] The second transistor (T2) is electrically connected to the first scan line (SL1) and the data line (DL), and is electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and the eighth transistor (T8). The second transistor (T2) is turned on in response to the first scan signal (GW) received through the first scan line (SL1) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0133] The third transistor (T3) is electrically connected to the first scan line (SL1) and is electrically connected to the light-emitting element (LED) via the sixth transistor (T6). The third transistor (T3) is turned on in response to the first scan signal (GW) received through the first scan line (SL1), thereby diode-connecting the first transistor (T1), thereby compensating for the threshold voltage of the first transistor (T1).

[0134] The fourth transistor (T4) is electrically connected to the third scan line (SL3) and the first initialization voltage line (VIL1), and is turned on in response to the third scan signal (GI) transmitted through the third scan line (SL3) to transmit the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1) to initialize the voltage of the gate electrode of the first transistor (T1). The third scan signal (GI) may correspond to the first scan signal of another pixel driving circuit unit arranged in the previous row of the corresponding pixel driving circuit unit (PC).

[0135] The fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are electrically connected to the light emission control line (EML), and are simultaneously turned on in response to the light emission control signal (EM) transmitted through the light emission control line (EML), thereby forming a current path so that a driving current can flow from the first voltage line (VDDL) in the direction of the light emitting element (LED).

[0136] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to the second scan line (SL2), the second initialization voltage line (VIL2), and the sixth transistor (T6). The seventh transistor (T7) is turned on in response to the second scan signal (GB) received through the second scan line (SL2) and transmits the second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the first electrode of the light-emitting element (LED) to initialize the first electrode of the light-emitting element (LED).

[0137] The ninth transistor (T9) can be electrically connected to the second scan line (SL2), the second electrode (CE2) of the storage capacitor (Cst), and the sustain voltage line (VSL). The ninth transistor (T9) is turned on according to the second scan signal (GB) transmitted through the second scan line (SL2), and can transmit the sustain voltage (VSUS) to the second node (N2), for example, the second electrode (CE2) of the storage capacitor (Cst), during the initialization section and the data writing section.

[0138] The eighth transistor (T8) and the ninth transistor (T9) may be electrically connected to a second node (N2), for example, a second electrode (CE2) of a storage capacitor (Cst), respectively. In some embodiments, the eighth transistor (T8) may be turned off and the ninth transistor (T9) may be turned on in an initialization period and a data writing period, and the eighth transistor (T8) may be turned on and the ninth transistor (T9) may be turned off in an emission period. Since the sustain voltage (VSUS) is transmitted to the second node (N2) in the initialization period and the data writing period, the uniformity of the luminance (e.g., LRU, Long Range Uniformity) of the display device (1) according to the voltage drop of the first voltage line (VDDL) may be improved.

[0139] The storage capacitor (Cst) includes a first electrode (CE1) and a second electrode (CE2). The first electrode (CE1) is electrically connected to the gate electrode of the first transistor (T1), and the second electrode (CE2) is electrically connected to the eighth transistor (T8) and the ninth transistor (T9).

[0140] The auxiliary capacitor (Ca) can be electrically connected to the sixth transistor (T6), the sustain voltage line (VSL), and the first electrode of the light-emitting element (LED). The auxiliary capacitor (Ca) stores and maintains a voltage corresponding to the voltage difference between the first electrode of the light-emitting element (LED) and the sustain voltage line (VSL) while the seventh transistor (T7) and the ninth transistor (T9) are turned on, thereby preventing the problem of the black luminance increasing when the sixth transistor (T6) is turned off.

[0141] FIG. 7a is a cross-sectional view schematically showing a light emitting element (LED) of a display device (1) according to one embodiment of the present invention.

[0142] Referring to FIG. 7A, a light-emitting element (LED) according to one embodiment of the present invention may include an organic light-emitting diode (220) including an organic material. The organic light-emitting diode (220) may include a first electrode (221) disposed on an insulating layer, a second electrode (225) facing the first electrode (221), and a light-emitting layer (223) interposed between the first electrode (221) and the second electrode (225). A first functional layer (222) may be disposed between the first electrode (221) and the light-emitting layer (223), and a second functional layer (224) may be disposed between the light-emitting layer (223) and the second electrode (225).

[0143] The edge of the first electrode (221) may be covered with a bank layer (BKL) including an insulating material. On a plane, the bank layer (BKL) may define an opening (B-OP) that overlaps the central portion of the first electrode (221).

[0144] The first electrode (221) may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, the first electrode (221) may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In another embodiment, the first electrode (221) may further include a layer formed of ITO, IZO, ZnO, AZO, or In2O3 on / under the aforementioned reflective layer.

[0145] The light-emitting layer (223) may include a polymer or low-molecular organic material that emits light of a predetermined color. The first functional layer (222) may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer (224) may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0146] The second electrode (225) may be formed of a conductive material having a low work function. In one embodiment, for example, the second electrode (225) may include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the second electrode (225) may further include a layer such as ITO, IZO, ZnO, AZO, or In2O3 on the (semi-)transparent layer including the aforementioned material.

[0147] FIG. 7b is a cross-sectional view schematically showing a light emitting element (LED) of a display device (1) according to one embodiment of the present invention.

[0148] Referring to FIG. 7b, in one embodiment of the present invention, a light emitting element (LED) may include an inorganic light emitting diode (230) including an inorganic material. The inorganic light emitting diode (230) may include a first semiconductor layer (231), a second semiconductor layer (232), an intermediate layer (233) between the first semiconductor layer (231) and the second semiconductor layer (232), a first electrode (235) electrically connected to the first semiconductor layer (231), and a second electrode (238) electrically connected to the second semiconductor layer (232). The first electrode (235) and the second electrode (238) of the inorganic light emitting diode (230) may be electrically connected to a first electrode pad (241) and a second electrode pad (242) disposed on the same layer, respectively.

[0149] In some embodiments, the first semiconductor layer (231) may include a p-type semiconductor layer. The p-type semiconductor layer may be In x Al y Ga 1-x-y N A semiconductor material having a composition formula of (0≤x≤1, 0≤y≤1, 0≤x+y≤1) can be selected from among, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and a p-type dopant such as Mg, Zn, Ca, Sr, Ba, etc. can be doped.

[0150] The second semiconductor layer (232) may include, for example, an n-type semiconductor layer. The n-type semiconductor layer may be In x Al y Ga 1-x-y A semiconductor material having a composition formula of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) can be selected from among, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and an n-type dopant such as Si, Ge, or Sn can be doped.

[0151] The intermediate layer (233) is a region where electrons and holes recombine, and as electrons and holes recombine, they transition to a lower energy level and can generate light with a corresponding wavelength. The intermediate layer (233) is, for example, In x Al y Ga 1-x-y It can be formed by including a semiconductor material having a composition formula of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1), and can be formed as a single quantum well structure or a multi quantum well structure (MQW: Multi Quantum Well). In addition, the intermediate layer (233) may include a quantum wire structure or a quantum dot structure.

[0152] Although Fig. 7b illustrates that the first semiconductor layer (231) includes a p-type semiconductor layer and the second semiconductor layer (232) includes an n-type semiconductor layer, the present invention is not limited thereto. In another embodiment, the first semiconductor layer (231) may include an n-type semiconductor layer and the second semiconductor layer (232) may include a p-type semiconductor layer.

[0153] Fig. 8a is an enlarged plan view of a first island portion (11) of a display device (1) according to one embodiment of the present invention, and Fig. 8b is a plan view showing the arrangement of wiring on a first bridge portion (12) of a display device (1) according to one embodiment of the present invention. In addition, Fig. 9 shows a cross-section taken along line I-I' of Fig. 8a and a cross-section taken along line II-II' of Fig. 8b.

[0154] Referring to Fig. 8a, the first island portion (11) arranged in the display area (DA) may include light-emitting elements and a pixel driver circuit portion (PC) electrically connected thereto. The pixel driver circuit portion (PC) may include transistors and at least one capacitor, as described above. Although Fig. 8a illustrates three pixel driver circuit portions (PC) arranged in the first island portion (11), the present invention is not limited thereto. In another embodiment, the number of pixel driver circuit portions (PC) and light-emitting elements arranged in the first island portion (11) may be one, two, four or more.

[0155] Referring to FIG. 9, the substrate (100) corresponding to the first island portion (11) may include a first base layer (101), a first barrier layer (102), a second base layer (103), and a second barrier layer (104). The first base layer (101) and the second base layer (103) may each include a polymer resin such as polyethersulfone, polyarylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc. The first barrier layer (102) and the second barrier layer (104) may each include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0156] A buffer layer (111) is disposed on the substrate (100), and a pixel driving circuit (PC) may be disposed on the buffer layer (111). The buffer layer (111) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0157] A thin film transistor (TFT) may include a semiconductor layer (Act), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE). FIG. 9 illustrates a top gate type in which the gate electrode (GE) is disposed on the semiconductor layer (Act) with a gate insulating layer (113) therebetween, but according to another embodiment, the thin film transistor (TFT) may be a bottom gate type.

[0158] The semiconductor layer (Act) may include polysilicon. Alternatively, the semiconductor layer (Act) may include amorphous silicon, an oxide semiconductor, an organic semiconductor, or the like. The gate electrode (GE) may include a low-resistance metal material. The gate electrode (GE) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multilayer or single layer including the above materials.

[0159] The gate insulating layer (113) between the semiconductor layer (Act) and the gate electrode (GE) may include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide. The gate insulating layer (113) may be a single layer or a multilayer including the aforementioned material.

[0160] The source electrode (SE) and the drain electrode (DE) may be positioned on the same layer, for example, the second interlayer insulating layer (117), and may include the same material. The source electrode (SE) and the drain electrode (DE) may include a conductive material and may be formed as a multilayer or a single layer. The second interlayer insulating layer (117) may include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide, and may be a single layer or a multilayer including the aforementioned materials.

[0161] On a plane, the storage capacitor (Cst) may include a first electrode (CE1) and a second electrode (CE2) that overlap with a first interlayer insulating layer (115) therebetween. On a plane, the storage capacitor (Cst) may overlap with a thin film transistor (TFT). In this regard, FIG. 9 illustrates that the gate electrode (GE) of the thin film transistor (TFT) is the first electrode (CE1) of the storage capacitor (Cst). In another embodiment, on a plane, the storage capacitor (Cst) may not overlap with the thin film transistor (TFT). The storage capacitor (Cst) may be covered with a second interlayer insulating layer (117). The second electrode (CE2) of the storage capacitor (Cst) may include a conductive material and may be formed in a multilayer or single layer. The first interlayer insulating layer (115) may be disposed between the gate insulating layer (113) and the second interlayer insulating layer (117). The first interlayer insulating layer (115) may include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide, and may be a single layer or multilayer including the aforementioned materials.

[0162] The inorganic insulating layer (IOL) on the substrate (100) may include, for example, a buffer layer (111), a gate insulating layer (113), a first interlayer insulating layer (115), and a second interlayer insulating layer (117).

[0163] The first organic insulating layer (119) may be disposed on the second interlayer insulating layer (117), and the second organic insulating layer (121) may be disposed on the first organic insulating layer (119). The first organic insulating layer (119) and the second organic insulating layer (121) may each include an organic insulating material such as polyimide.

[0164] The second voltage line (VSSL) is disposed on the second organic insulating layer (121), and the third organic insulating layer (123) may be disposed on the second organic insulating layer (121) and the second voltage line (VSSL). The third organic insulating layer (123) may include an organic insulating material such as polyimide. The second voltage line (VSSL) may include a conductive material and may be formed in a multilayer or single layer.

[0165] The first electrode pad (241) and the second electrode pad (242) may be arranged on the third organic insulating layer (123). The first electrode pad (241) may be electrically connected to a thin film transistor (TFT) through a first connection electrode (CM1) between the first organic insulating layer (119) and the second organic insulating layer (121) and a second connection electrode (CM2) between the second organic insulating layer (121) and the third organic insulating layer (123). The inorganic light-emitting diode (230) on the first electrode pad (241) and the second electrode pad (242) is as described above with reference to FIG. 7b. A light emitting diode, for example, an inorganic light emitting diode (230), may be protected by an encapsulating layer (300), and the encapsulating layer (300) may include an inorganic encapsulating layer and / or an organic encapsulating layer, or may include an organic material such as a resin. FIG. 9 illustrates that the light emitting diode is an inorganic light emitting diode (230) described with reference to FIG. 7b, but as another embodiment, the light emitting diode may be an organic light emitting diode (220) described with reference to FIG. 7a.

[0166] Referring to FIG. 8b, the first bridge unit (12) may include wirings (WL) electrically connected to pixel driver circuit units (PC) disposed in each of the adjacent first island units (11). As described above, the wirings (WL) may be signal lines (e.g., gate lines, data lines, etc.) for providing electrical signals to transistors included in the pixel driver circuit units (PC) of the first island unit (11) or voltage lines (e.g., driving voltage lines, initialization voltage lines, etc.) for providing voltage. FIG. 8b illustrates wirings (WL), for example, first to third wirings (WL1, WL2, WL3), disposed on the first bridge unit (12), but the present invention is not limited thereto. In another embodiment, one wiring (WL) may be disposed on the first bridge unit (12).

[0167] Referring to FIG. 9, in one embodiment, the substrate (100) corresponding to the first bridge portion (12) may have the same laminated structure as the substrate (100) corresponding to the first island portion (11). In one embodiment, the substrate (100) corresponding to the first bridge portion (12) may include a first base layer (101), a first barrier layer (102), a second base layer (103), and a second barrier layer (104). In another embodiment, the substrate (100) corresponding to the first bridge portion (12) may have a different laminated structure from the substrate (100) corresponding to the first island portion (11). The substrate (100) corresponding to the first bridge portion (12) may have a structure of a first base layer (101) and a second base layer (103).

[0168] On the substrate (100), an inorganic insulating layer (IOL) may not be disposed, and an insulating layer (OL), a first organic insulating layer (119), and a second organic insulating layer (121) may be disposed. The insulating layer (OL) may include an organic insulating material such as polyimide. In one embodiment, the insulating layer (OL) may have a thickness corresponding to the inorganic insulating layer (IOL). In some embodiments, the insulating layer (OL) may be omitted.

[0169] The wirings (WL), for example, the first to third wirings (WL1, WL2, WL3), may be arranged on different layers but may be electrically connected to the same pixel driver circuit (PC). For example, the first wiring (WL1) may be arranged between the second organic insulating layer (121) and the third organic insulating layer (123), the second wiring (WL2) may be arranged between the first organic insulating layer (119) and the second organic insulating layer (121), and the third wiring (WL3) may be arranged between the insulating layer (OL) and the first organic insulating layer (119). However, the present invention is not limited thereto, and in another embodiment, at least some of the first to third wirings (WL1, WL2, WL3) may be arranged on the same layer.

[0170] Figures 10 and 11 are cross-sectional views of a conductive layer (SCL) constituting a wiring or connection electrode of a display device according to one embodiment of the present invention. Figure 12 is a cross-sectional view of a conductive layer (SCL') according to a comparative example of the present invention.

[0171] Referring to FIGS. 10 and 11, the conductive layer (SCL) may include a first layer (L1). In one embodiment, the first layer (L1) may have a laminated structure including sublayers. The sublayers may include a first sublayer (AL) and a second sublayer (CL).

[0172] The first sublayer (AL) may be an alloy layer. The first sublayer (AL) may include an alloy of aluminum (Al) and a rare-earth element. The first sublayer (AL) may be an amorphous alloy layer. An amorphous alloy may not include grain boundaries. An amorphous alloy may have a high elastic strain limit. Among amorphous alloys, a fully amorphous alloy can undergo elastic deformation without plastic deformation. In the present specification, an amorphous alloy may include a case in which the alloy is composed of a fully amorphous phase, and a case in which a nanocrystalline phase, in which the crystal size is only several nanometers, exists in a dispersed form within the amorphous phase.

[0173] The atomic radius of the rare earth element may be larger than the atomic radius of aluminum (Al). The difference ratio between the atomic radius of aluminum and the atomic radius of the rare earth element relative to the atomic radius of aluminum may be greater than or equal to about 25%. When the difference ratio relative to the atomic radius of aluminum is greater than or equal to about 25%, the atoms may be regularly arranged, which may hinder crystallization. The electronegativity of the rare earth element may be less than the electronegativity of aluminum. The electronegativity of the rare earth element may be greater than or equal to about 1.0 and less than or equal to about 1.2. In one embodiment, the rare earth element may include at least one of yttrium (Y), samarium (Sm), cerium (Ce), or lanthanum (La). Such rare earth elements may have excellent amorphous forming ability.

[0174] In one embodiment, the first sublayer (AL) is Al a M bIt may include a binary alloy having a composition formula of . M may be at least one rare earth element selected from yttrium (Y), samarium (Sm), cerium (Ce), and lanthanum (La). a and b represent the content (at%) of each element based on the total atomic weight of the first sub-layer (AL), and the sum of a and b may be 100. In one embodiment, a may be about 90 or more and about 96 or less, and b may be about 4 or more and about 10 or less. In other words, based on the total atomic weight of the first sub-layer (AL), the content of aluminum (Al) may be about 90 at% or more and about 96 at% or less, and the content of the rare earth element (M) may be about 4 at% or more and about 10 at% or less. When the aluminum and rare earth element (M) included in the first sub-layer (AL) satisfy the above range, the first sub-layer (AL) may be an amorphous alloy layer having excellent resistivity. When the aluminum content is less than about 90 at%, the resistivity of the first sub-layer (AL) may increase. When the aluminum content exceeds about 96 at%, the first sub-layer (AL) may not be formed as an amorphous alloy layer. When the content of the first sub-layer (AL) is less than about 4 at%, the first sub-layer (AL) may not be formed as an amorphous alloy layer. When the content of the rare earth element (M) exceeds about 10 at%, the resistivity of the first sub-layer (AL) may increase. In one embodiment, the first sub-layer (AL) may be Al a Y b It may include an alloy having a composition formula of (90≤a≤96, 4≤b≤10).

[0175] In some embodiments, the first sublayer (AL) may further include nickel (Ni) and / or cobalt (Co). Nickel and cobalt may be elements that stabilize the amorphous phase. In some embodiments, the first sublayer (AL) may include a ternary alloy or a quaternary alloy. In some embodiments, the first sublayer (AL) may include Al. a M b Ni c Cod A quaternary alloy having a composition formula may be included. M may be at least one rare earth element selected from yttrium (Y), samarium (Sm), cerium (Ce), and lanthanum (La). a, b, c, and d represent the content (at%) of each element based on the total atomic weight of the first sublayer (AL), and the sum of a, b, c, and d may be 100. In some embodiments, a may be about 80 or more and about 90 or less, b may be about 5 or more and about 10 or less, c may be about 3 or more and about 8 or less, and d may be about 1 or more and about 3 or less. In other words, based on the total atomic weight of the first sub-layer (AL), the content of aluminum (Al) may be about 80 at% or more and about 90 at% or less, the content of rare earth elements (M) may be about 5 at% or more and about 10 at% or less, the content of nickel may be about 3 at% or more and about 8 at% or less, and the content of cobalt may be about 1 at% or more and about 3 at% or less. In one embodiment, the first sub-layer (AL) may be Al 85 It may include an alloy having a composition formula of Y8Ni5Co2.

[0176] The second sublayer (CL) may include aluminum (Al). The second sublayer (CL) may be a pure aluminum layer. The second sublayer (CL) may be a crystalline aluminum layer. Pure aluminum undergoes plastic deformation after elastic deformation and may have a relatively low elastic strain compared to an amorphous alloy. For example, pure aluminum may have a low elastic strain of about 0.2% to about 0.5%. Meanwhile, pure aluminum may have a low resistivity of less than 10 microohm-centimeters (μΩ·cm).

[0177] The first layer (L1) of the conductive layer (SCL) may have a structure in which first sub-layers (AL) and second sub-layers (CL) are alternately stacked. In one embodiment, FIG. 10 illustrates that the first layer (L1) has an 11-layer structure, and that the first layer (L1) includes six first sub-layers (AL1, AL2, AL3, AL4, AL5, AL6) and five second sub-layers (CL1, CL2, CL3, CL4, CL5). For convenience of explanation, the first sub-layers (AL1, AL2, AL3, AL4, AL5, AL6) of the 6th floor are referred to as the 1-1st sub-layer (AL1), the 1-2nd sub-layer (AL2), the 1-3rd sub-layer (AL3), the 1-4th sub-layer (AL4), the 1-5th sub-layer (AL5), and the 1-6th sub-layer (AL6), respectively, and the second sub-layers (CL1, CL2, CL3, CL4, CL5) of the 5th floor are referred to as the 2-1st sub-layer (CL1), the 2-2nd sub-layer (CL2), the 2-3rd sub-layer (CL3), the 2-4th sub-layer (CL4), and the 2-5th sub-layer (CL5), respectively. The uppermost and lowermost layers of the 1st floor (L1) may be the 1st sub-layer (AL). For example, in FIG. 10, the uppermost layer of the first layer (L1) is the 1-6th sublayer (AL6), and the lowermost layer is the 1-1st sublayer (AL1). In other words, each of the second sublayers (CL) in the first layer (L1) can be located between the first sublayers (AL).

[0178] The first-first sublayer (AL1) to the first-sixth sublayer (AL6) may include the same material. Each of the first-first sublayer (AL1) to the first-sixth sublayer (AL6) may include an alloy of aluminum and rare earth elements having the same composition. In addition, each of the second-first sublayer (CL1) to the second-fifth sublayer (CL5) may include the same material. Each of the second-first sublayer (CL1) to the second-fifth sublayer (CL5) may be a pure aluminum layer.

[0179] In order to lower the resistivity of the first layer (L1), the first-1 sub-layer (AL1) to the first-6 sub-layer (AL6) may be provided with substantially the same thickness. The second-1 sub-layer (CL1) to the second-5 sub-layer (CL5) may be provided with substantially the same thickness.

[0180] Although FIG. 10 illustrates that the first layer (L1) has an 11-layer structure, the present invention is not limited thereto. In another embodiment, the first layer (L1) may include at least one second sub-layer (CL) and at least two first sub-layers (AL) disposed below and above the second sub-layer (CL). Considering the thickness of the first layer (L1) functioning as a wiring or electrode, the first layer (L1) may have a 3-layer to 25-layer structure.

[0181] In one embodiment, the thickness of the first layer (L1) can be from about 300 nanometers (nm) to about 1000 nm.

[0182] In one embodiment, the thickness of the first sublayer (AL) may be from about 30 nm to about 100 nm. Preferably, the thickness of the first sublayer (AL) may be from about 40 nm to about 80 nm.

[0183] In one embodiment, the ratio of the thickness of the first sub-layer (AL) to the thickness of the second sub-layer (CL) may be less than about 2. Preferably, the ratio of the thickness of the first sub-layer (AL) to the thickness of the second sub-layer (CL) may be greater than 0 and less than or equal to about 1. When the thickness ratio of the first sub-layer (AL) and the second sub-layer (CL) satisfies the above-described preferred range (i.e., 11 μΩ·cm or less), the first layer (L1) may have excellent resistivity characteristics.

[0184] Referring to FIG. 10, in one embodiment, the conductive layer (SCL) may include a lower barrier layer (L2) below the first layer (L1), and an upper barrier layer (L3) above the first layer (L1). The conductive layer (SCL) may have a structure in which the lower barrier layer (L2), the first layer (L1), and the upper barrier layer (L3) are sequentially laminated. In one embodiment, the lower barrier layer (L2) may be a second layer, and the upper barrier layer (L3) may be a third layer. The lower barrier layer (L2) and the upper barrier layer (L3) may include a different material from the first layer (L1). Each of the lower barrier layer (L2) and the upper barrier layer (L3) may include a metal material, a transparent conductive oxide, or a nitride. In one embodiment, the metal material may include, for example, molybdenum (Mo), copper (Cu), titanium (Ti), nickel (Ni), chromium (Cr), tungsten (W), and alloys thereof, such as NiTi, CuTi, CuMn, CuMg, etc. The transparent conductive oxide may include, for example, indium tin oxide (ITO), etc. The nitride may include, for example, titanium nitride (TiN), etc. In one embodiment, the lower barrier layer (L2) and the upper barrier layer (L3) may include titanium (Ti) or molybdenum (Mo). In one embodiment, the lower barrier layer (L2) and the upper barrier layer (L3) may have a crystalline or amorphous microstructure. Referring to FIG. 11, in another embodiment, the conductive layer (SCL) may not include the lower barrier layer (L2) and the upper barrier layer (L3). The conductive layer (SCL) may be formed of only the first layer (L1).

[0185] The structure of the aforementioned conductive layer (SCL) can be applied to the wiring (WL) arranged on the first bridge portion (12). The wiring (WL) arranged on the first bridge portion (12) can include a first layer (L1) having an alternating stacked structure of a first sub-layer (AL) including an alloy of aluminum and a rare earth element and a second sub-layer (CL) including aluminum. For example, the first wiring (WL1), the second wiring (WL2), and the third wiring (WL3) illustrated in FIG. 9 can include a first layer (L1) having an alternating stacked structure of a first sub-layer (AL) including an alloy of aluminum and a rare earth element and a second sub-layer (CL) including aluminum.

[0186] Referring to Fig. 12, as a comparative example, the wiring arranged on the first bridge portion may have a structure of a conductive layer (SCL'). The first layer (L1') of the conductive layer (SCL') may not include a laminated structure of sub-layers. The first layer (L1') includes an alloy of aluminum and rare earth elements and may be an amorphous alloy layer. In this case, the first layer (L1') may have a high elastic strain. The first layer (L1') may reduce the resistivity by adjusting the content of aluminum and rare earth elements. However, the first layer (L1') may have a higher resistivity than a pure aluminum layer.

[0187] However, according to one embodiment of the present invention, the wiring (WL) arranged in the first bridge portion (12) may have the structure of the conductive layer (SCL) described with reference to FIGS. 10 and 11. The first layer (L1) of the conductive layer (SCL) may include a first sub-layer (AL) including an alloy of aluminum and a rare earth element and a second sub-layer (CL) including aluminum, and may have a structure in which the first sub-layer (AL) and the second sub-layer (CL) are cross-laminated. In this case, by cross-laminating the first sub-layer (AL) and the second sub-layer (CL) having different physical properties, the first layer (L1) may have improved resistivity (i.e., low resistivity) compared to the first layer (L1') of FIG. 12. The first layer (L1) of one embodiment may maintain a high elastic strain while securing a resistivity comparable to that of a pure aluminum layer.

[0188] In one embodiment, the resistivity of the first layer (L1) may be less than about 11 μΩ·cm. More preferably, the resistivity of the first layer (L1) may be greater than about 5 μΩ·cm and less than about 11 μΩ·cm. More preferably, the resistivity of the first layer (l1) may be greater than about 5.6 μΩ·cm and less than about 11 μΩ·cm.

[0189] In one embodiment, the elastic strain limit of the first layer (L1) may be about 2.0% or more. Preferably, the elastic strain limit of the first layer (L1) may be about 3.0% or more. More preferably, the elastic strain limit of the first layer (L1) may be about 3.0% or more and about 4.0% or less. Since the first layer (L1) has a high elastic strain limit of about 2.0% or more, the design area limitation of the wiring (WL) within the first bridge portion (12) having a winding shape may be reduced. In addition, when a tensile force is applied to the first bridge portion (12) and the first bridge portion (12) is stretched in various directions, the risk of destruction of the wiring (WL) may be reduced and the lifespan may be effectively increased.

[0190] In one embodiment, the yield strength of the first layer (L1) may be greater than or equal to about 0.7 gigapascals (GPa) and less than or equal to about 1.5 GPa. Preferably, the yield strength of the first layer (L1) may be greater than or equal to about 0.8 GPa and less than or equal to about 1.5 GPa. More preferably, the yield strength of the first layer (L1) may be greater than or equal to about 0.8 GPa and less than or equal to about 1.2 GPa.

[0191] In one embodiment, the structure of the conductive layer (SCL) can also be applied to a connecting electrode disposed on the first island portion (11). The connecting electrode can be disposed between the inorganic insulating layer (IOL) and the light-emitting element. The connecting electrode is disposed between the gate electrode (GE) of the thin film transistor (TFT) and the light-emitting element, and can be electrically connected to the thin film transistor (TFT) and / or the light-emitting element. For example, the connecting electrode can be disposed between the inorganic insulating layer (IOL) and the first organic insulating layer (119). Alternatively, the connecting electrode can be disposed between the first organic insulating layer (119) and the second organic insulating layer (121). Alternatively, the connecting electrode can be disposed between the second organic insulating layer (121) and the third organic insulating layer (123). For example, the connecting electrodes may be the source electrode (SE), the drain electrode (DE), the first connecting electrode (CM1), the second connecting electrode (CM2), and the second voltage line (VSSL) illustrated in FIG. 9. The connecting electrode disposed in the first island portion (11) may include a first layer (L1) having an alternating stacked structure of a first sub-layer (AL) including an alloy of aluminum and a rare earth element and a second sub-layer (CL) including only aluminum. For example, the source electrode (SE), the drain electrode (DE), the first connecting electrode (CM1), the second connecting electrode (CM2), and the second voltage line (VSSL) may include a first layer (L1) having an alternating stacked structure of a first sub-layer (AL) including an alloy of aluminum and a rare earth element and a second sub-layer (CL) including aluminum. In another embodiment, the structure of the conductive layer (SCL) may be applied only to the wiring (WL) arranged in the first bridge portion (12), and may not be applied to the connection electrode arranged in the first island portion (11).

[0192] Fig. 13 is a flowchart showing a method for manufacturing an alloy layer included in a conductive layer according to one embodiment of the present invention, and Fig. 14 shows the results of observing the microstructure of the alloy layer according to one embodiment of the present invention using a transmission electron microscope (TEM). Figure (a) of Fig. 14 shows an image mode image, and figure (b) shows a diffraction mode image.

[0193] A method for manufacturing a display device according to one embodiment may include a step of forming first bridge portions (12) that connect first island portions (11) and adjacent island portions, respectively, and a step of forming wires (WL, FIG. 9) arranged in the first bridge portions (12).

[0194] As described above, the wirings (WL) arranged in the first bridge portions (12) may have a structure of a conductive layer (SCL, FIG. 10). The wirings (WL) arranged in the first bridge portions (12) may include a first sub-layer (AL, FIG. 10) including an alloy of aluminum and a rare earth element and a second sub-layer (CL, FIG. 10) including aluminum. The wirings (WL) arranged in the first bridge portions (12) may include an alternating stacked structure of the first sub-layer (AL) and the second sub-layer (CL). The step of forming the wiring (WL) may include a step of forming the first sub-layer (AL) which is an alloy layer and a step of forming the second sub-layer (CL). In one embodiment, the step of forming the first sub-layer (AL) and the second sub-layer (CL) may be performed by a sputtering method.

[0195] In one embodiment, the step of forming the first sub-layer (AL) may include a step of designing an alloy of aluminum and a rare earth element (S110), a step of forming a mother alloy including aluminum and a rare earth element (S120), a step of forming powder of the mother alloy (S130), a step of forming an alloy body by sintering the powder (S140), and a step of depositing the first sub-layer (AL) on a substrate by sputtering the alloy body as a target (S150).

[0196] First, in step S110, the alloy's constituent elements and contents can be designed. The target composition can be designed based on the composition of the first sublayer (AL) to be ultimately formed. As an example, the first sublayer (AL) to be ultimately formed is a binary alloy, Al a M b The first sub-layer (AL) may have a composition formula. M may be at least one rare earth element selected from yttrium (Y), samarium (Sm), cerium (Ce), and lanthanum (La). a and b represent the content (at%) of each element based on the total atomic weight of the alloy layer (L1), and the sum of a and b may be 100. In one embodiment, a may be about 90 or more and about 96 or less, and b may be about 4 or more and about 10 or less. In other words, based on the total atomic weight of the first sub-layer (AL), the content of aluminum (Al) may be about 90 at% or more and about 96 at% or less, and the content of the rare earth element (M) may be about 4 at% or more and about 10 at% or less. In one embodiment, the first sub-layer (AL) may be Al a Y b It may include an alloy having a composition formula of (90≤a≤96, 4≤b≤10).

[0197] Next, in step S120, a master alloy can be formed using high-purity raw materials. For example, vacuum induction melting (VIM) methods can be used to form the master alloy.

[0198] At step S130, a powder of the master alloy can be formed. The master alloy can be powdered in a highly purified state. The powder can be formed using atomization, such as electrode-induced gas atomization (EIGA) methods. The formed powder can have a size of about 30 micrometers (μm) to about 50 μm.

[0199] At step S140, the powder can be sintered to form an alloy. The sintering process can form an alloy with a uniform composition. For example, spark plasma sintering (SPS) and hot isostatic pressing (HIP) processes can be used to form the alloy. The alloy can be processed into a size suitable for the sputtering process target.

[0200] At step S150, a sputtering process can be performed targeting the alloy. The first sublayer (AL) can be deposited on the substrate through the sputtering process. For example, a DC-magnetron sputtering method can be used for the sputtering process.

[0201] The microstructure of the first sublayer (AL) may vary depending on the sputtering process conditions. For example, the microstructure of the first sublayer (AL) may vary depending on the temperature, power density, and deposition pressure of the sputtering substrate.

[0202] Referring to Figures (a) and (b) of FIG. 14, it can be seen that in one embodiment, the first sub-layer (AL) is an amorphous alloy layer and has a high-density microstructure without a columnar structure. When the first sub-layer (AL) has a high-density microstructure without a columnar structure, it can have superior physical properties (e.g., mechanical properties) compared to when the first sub-layer (AL) has a microstructure including a columnar structure.

[0203] Fig. 15 is a drawing showing the microstructure of a conductive layer according to one embodiment of the present invention. Fig. 16 is a graph showing the resistivity of a conductive layer according to embodiments of the present invention. Fig. 17 is a graph showing the resistivity of a conductive layer according to embodiments and comparative examples of the present invention.

[0204] In FIGS. 15 to 17, Examples 1 to 7 formed a first layer (L1) in which a first sub-layer (AL) including aluminum and a rare earth element and a second sub-layer (CL) including aluminum were alternately laminated. Specifically, an amorphous alloy layer including aluminum and a rare earth element was formed as the first sub-layer (AL), and a crystalline pure aluminum layer was formed as the second sub-layer (CL). Six first sub-layers (AL) and five second sub-layers (CL) were alternately laminated to form a first layer (L1) having an 11-layer structure.

[0205] Examples 1 to 7 formed the first layer (L1) by varying the type and content of the rare earth elements constituting the first sublayer (AL), the thickness of the first sublayer (AL), the thickness of the second sublayer (CL), and the thickness ratio of the first sublayer (AL) and the second sublayer (CL) according to the conditions of Table 1 below.

[0206] Composition of the first sublayer Thickness of the first sublayer (nm) Thickness of the second sublayer (nm) Ratio of the thickness of the first sublayer to the thickness of the second sublayer Thickness of the first layer (nm) Example 1 Al 94 Y630301330Example 2Al 94Y650501550Example 3Al 94 Y660601660Example 4Al 90 Y 10 80402680 Example 5Al 90 Y 10 60601660 Example 6Al 90 Y 10 40801 / 2640 Example 7Al 85 Y8Ni5Co260601660

[0207] Comparative Examples 1 to 3 formed an alloy layer containing aluminum and rare earth elements. Specifically, an amorphous alloy layer containing aluminum and rare earth elements was formed. Comparative Example 1 formed an Al layer having a thickness of 600 nm. 94 An alloy layer of aluminum and yttrium having a composition formula of Y6 was formed. Comparative Example 2 is a 600 nm thick Al 90 Y 10 An alloy layer of aluminum and yttrium having a composition formula of was formed. Comparative Example 3 is a 600 nm thick Al 85 An alloy layer of aluminum, yttrium, nickel, and cobalt having a composition formula of Y8Ni5Co2 was formed.

[0208] Comparative Example 4 formed a pure crystalline aluminum layer (Al). Specifically, a 600 nm thick aluminum layer was formed.

[0209] Comparative Example 5 formed a crystalline aluminum alloy layer (Al7075).

[0210] Figure 15 shows the results of observing the microstructure of the first layer (L1) of Examples 3 and 7 using a transmission electron microscope (TEM). Figure (a) of Figure 15 shows the microstructure of Example 7, and Figure (b) shows the microstructure of Example 3.

[0211] Referring to FIG. 15, it can be confirmed that the first layer (L1) of Examples 3 and 7 has a structure in which the first sub-layer (AL), which is an amorphous alloy layer, and the second sub-layer (CL), which is crystalline, are cross-stacked. Specifically, it can be confirmed that the first sub-layer (AL) of Example 7 has a fully amorphous phase. On the other hand, it can be confirmed that the first sub-layer (AL) of Example 3 exists in the form of a nanocrystalline phase with a crystal size of only several nanometers dispersed within the amorphous phase.

[0212] The resistivity was measured for the first layer (L1) of Examples 1 to 7, the alloy layer of Comparative Examples 1 to 3, and the aluminum layer of Comparative Example 4. The resistivity was measured using the 4-point probe (4PB) method. The results are shown in Figs. 16 and 17. Fig. 16 shows the resistivity of Examples 1 and 2, and Fig. 17 shows the resistivity of Examples 3 to 7 and Comparative Examples 1 to 4.

[0213] Referring to FIGS. 16 and 17, it can be confirmed that Examples 1 and 2 (13.1 and 8.5 μΩ·cm) each exhibit lower resistivities than Comparative Example 1 (17.7 μΩ·cm). In addition, it can be seen that Example 1 has a resistivity of 11 μΩ·cm or more, whereas Example 2 has a resistivity of less than 11 μΩ·cm. When the thickness of the first sub-layer (AL) decreases to a certain level or more, the electron scattering phenomenon may increase, thereby increasing the resistivity of the first layer (L1). In order to secure a resistivity of less than 11 μΩ·cm, the thickness of the first sub-layer (AL) may be 40 nm or more. Preferably, the thickness of the first sub-layer (AL) may be 40 nm to 100 nm. More preferably, the thickness of the first sub-layer (AL) may be 40 nm to 80 nm.

[0214] Referring to FIG. 17, Example 3 (8.7 μΩ·cm) had a lower resistivity than Comparative Example 1 (17.7 μΩ·cm), Examples 4 to 6 (12.6, 9.9, and 7.2 μΩ·cm, respectively) had lower resistivities than Comparative Example 2 (22.9 μΩ·cm), and Example 7 (10.9 μΩ·cm) had a lower resistivity than Comparative Example 3 (68.5 μΩ·cm). Comparative Examples 1 to 3 and Example 4 (17.7, 22.9, 68.5, and 12.6 μΩ·cm, respectively) had resistivities of 11 μΩ·cm or more, whereas Examples 3, 5 to 7 (8.7, 9.9, and 10.9 μΩ·cm, respectively) had resistivities of less than 11 μΩ·cm, which is comparable to Comparative Example 4 (5.6 μΩ·cm). Therefore, it can be confirmed that when the thickness of the first sub-layer with respect to the thickness of the second sub-layer is 1 or less, the first layer has a resistivity of less than 11 μΩ·cm. From the above Examples and Comparative Examples, it can be seen that the resistivity varies depending on the thickness of the first sub-layer, the ratio of the thickness of the first sub-layer to the thickness of the second sub-layer, and the content of aluminum with respect to the total atomic weight of the first sub-layer.

[0215] FIG. 18 is a graph showing the results of a tensile test of a conductive layer according to comparative examples of the present invention, FIG. 19 is a graph showing the results of a tensile test of a conductive layer according to embodiments of the present invention, and FIG. 20 is a graph showing the results of a tensile test of a conductive layer according to other embodiments of the present invention.

[0216] Tensile tests were performed on the first layer of Examples 3 to 7 and the alloy layers of Comparative Examples 1 to 5. The tensile tests were performed by patterning the first layer or the alloy layer into a dog-bone shape using an ion beam (FIB) method to manufacture specimens, and then measuring and recording the experimental results in real time (in-situ) using an SEM facility equipped with a picoindenter. The results are shown in Table 2 and FIGS. 18 to 20. FIG. 18 is a graph comparing the results of Comparative Examples 1 to 3, FIG. 19 is a graph comparing the results of Examples 3, 5, and 7, and FIG. 20 is a graph comparing the results of Examples 4, 5, and 6, respectively.

[0217] Elastic strain (%) Yield strength [MPa] Comparative example 13.721255.7 Comparative example 23.451249.2 Comparative example 33.831625.3 Example 33.27920.5 Example 43.301005.1 Example 53.15906.2 Example 63.091015.9 Example 73.261168.5 Comparative example 40.2124 Comparative example 50.6503

[0218] Referring to FIGS. 18 to 20, Comparative Example 3 did not undergo plastic deformation in a completely amorphous phase, but underwent elastic deformation and then fractured, whereas Comparative Examples 1 and 2 had nanocrystals dispersed within the amorphous phase, and it can be confirmed that plastic deformation occurred after elastic deformation. Since Examples 3 to 7 have a laminated structure of the first sub-layer, which is an amorphous alloy layer, and the second sub-layer, which is a crystalline metal layer, it can be confirmed that plastic deformation occurred after elastic deformation.

[0219] Referring to Table 2 and FIGS. 18 to 20, it can be seen that the elastic strain of Comparative Example 4 is low at 0.2% and that of Comparative Example 5 is low at 0.6%, whereas Comparative Examples 1 to 3 have high elastic strains of 3.0% or more. Although Examples 3 to 7 have lower elastic strains than Comparative Examples 1 to 3, it can be seen that they maintain a high elastic strain of 2.0% or more, preferably a high elastic strain of 3.0% or more. It can be seen that Examples 3 to 7 have an elastic strain that is about 10 times higher than that of Comparative Examples 4 and 5.

[0220] The yield strength of Comparative Example 4 was 124 megapascals (MPa), and that of Comparative Example 5 was 503 MPa, which are relatively lower than the other Comparative Examples or Examples, whereas Comparative Examples 1 to 3 were confirmed to have yield strengths of 1.2 GPa or more. Although Examples 3 to 7 had lower yield strengths than Comparative Examples 1 to 3, they were confirmed to have high yield strengths of 0.8 GPa or more. It was found that Examples 3 to 7 had yield strengths that were eight times or more that of Comparative Example 4.

[0221] FIGS. 21A to 21G are perspective views schematically illustrating embodiments of an electronic device including a display device according to one embodiment of the present invention.

[0222] The display device (1) according to the above-described embodiments can be used in various electronic devices capable of providing images. Here, the term "electronic device" refers to a device that uses electricity and can provide a predetermined image.

[0223] Referring to FIG. 21A, a display device according to an embodiment of the present invention may be utilized in a wearable electronic device (3100) that can be worn on a part of a user's body. The wearable electronic device (3100) may include a body portion (3110) and a display portion (3120) provided on the body portion (3110). The display device according to embodiments of the present invention may be utilized as the display portion (3120) of the wearable electronic device (3100). As illustrated in FIG. 21A, the wearable electronic device (3100) may be transformable. In one embodiment, it may be utilized as a smart watch or a smartphone, depending on the user's selection.

[0224] FIG. 21B illustrates a medical electronic device (3200). In one embodiment, the medical electronic device (3200) may include a body portion (3210) and a light-emitting portion (3220). A display device according to embodiments of the present invention may be used as the light-emitting portion (3220) of the medical electronic device (3200). The light-emitting portion (3220) may emit light of a certain wavelength band (e.g., infrared, visible light, etc.) to the patient's body. In one embodiment, the body portion (3210) may have a stretchable fiber material, and the light-emitting portion (3220) may have a structure that can be worn on the user's body.

[0225] FIG. 21C illustrates an educational electronic device (3300). In one embodiment, the educational electronic device may include a display unit (3320) provided within a frame (3310). The display unit (3320) may utilize a display device according to embodiments of the present invention. The display unit (3320) may provide an image such as a sea with waves, a snow-covered mountain, or a volcano with flowing lava, wherein the display unit (3320) may expand in the height direction (e.g., the z direction) to reflect the height of the wave, mountain, or volcano. In some embodiments, a portion of the display unit (3320) may sequentially vary in height along the direction of flowing lava to display the movement of lava in three dimensions. The educational electronic device (3300) may include pins (or stroke units, 3330) arranged on the back of the display unit (3320) so that the display unit (3320) expands in the height direction. The pins (3330) can be implemented to move along a third direction (e.g., the z direction or the -z direction) so that the image displayed on the display unit (3320) has a three-dimensional height. Fig. 21c describes an educational electronic device (3300), but its use is not limited to providing certain image information.

[0226] While the electronic devices illustrated in FIGS. 21A to 21C are described as electronic devices whose shapes can be variable, the present invention is not limited thereto. As described in the embodiments below, display devices according to embodiments of the present invention can be used in electronic devices in which a portion capable of displaying an image (e.g., a screen) is fixed.

[0227] FIG. 21D illustrates a robot (3400) as another electronic device according to one embodiment of the present invention. The robot (3400) can recognize movement or objects using a camera unit (3440) and display a predetermined image to a user through a display unit (3420, 3430). In some embodiments, since the display devices according to one embodiment of the present invention can extend in various directions as described above, they can be assembled into a body frame having a hemispherical shape, and thus the robot (3400) can include a hemispherical display unit (3420, 3430).

[0228] FIG. 21E illustrates a vehicle display device (3500) as another electronic device according to one embodiment of the present invention. The vehicle display device (3500) may include a cluster (3510), a center information display (CID) (3520), and / or a co-driver display (3530). Since the display device according to the embodiment of the present invention can be extended in various directions, it may be used in the cluster (3510), the center information display (CID) (3520), and / or the co-driver display (3530) regardless of the shape of the internal frame of the vehicle.

[0229] Although FIG. 21e illustrates that the cluster (3510), the Center Information Display (CID) (3520), and / or the co-driver display are each separate, the present invention is not limited thereto. In another embodiment, two or more selected from the cluster (3510), the Center Information Display (CID) (3520), and the co-driver display may be connected as one unit.

[0230] In some embodiments, a vehicle display device (3500) may include a button (3540) capable of displaying a predetermined image. Referring to the enlarged view of FIG. 21E, the hemispherical button (3540) may include an object (3542) that provides a button usability by moving in the z-direction or -z-direction, and a display device positioned on the object (3542). In some embodiments, when the object (3542) has a three-dimensionally rounded surface, the display device may also have a three-dimensionally rounded surface.

[0231] FIG. 21F illustrates an electronic device according to one embodiment of the present invention, which is an electronic device (3600) for advertising or display purposes. In some embodiments, the electronic device (3600) for advertising or display purposes may be installed on a fixed structure (3610), such as a wall or a pillar. If the structure (3610) includes a recessed surface as illustrated in FIG. 21F, the electronic device (3600) for advertising or display purposes may also be positioned along the recessed surface of the structure (3610). In some embodiments, the electronic device (3600) for advertising or display purposes may be installed on the structure (3610) using a thermostatic film or the like.

[0232] FIG. 21G illustrates an electronic device according to one embodiment of the present invention as a controller (3700). The controller (3700) may include an image-type button. For example, the controller (3700) may include first to third button areas (3720, 3730, 3740) in which a portion of the display unit (3710) protrudes in the z direction or protrudes in the -z direction (or is sunken in the z direction). In some embodiments, the first and third button areas (3720, 3740) may protrude in the z direction, and the second button area (3730) may protrude in the -z direction (or is sunken in the z direction).

[0233] While the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will appreciate that various modifications and variations of the embodiments are possible. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. A display device including a display area and a non-display area outside the display area, A plurality of island sections arranged in the above display area and spaced apart from each other; A plurality of bridge sections each connecting adjacent island sections among the above-mentioned plurality of island sections; and A plurality of wires arranged in each of the plurality of bridge sections; Each of the above plurality of wires includes a first layer, A display device, wherein the first layer includes a first sub-layer including an alloy of aluminum (Al) and a rare earth element, and a second sub-layer including aluminum.

2. In paragraph 1, Each of the above first sub-layer and the above second sub-layer is provided in multiple units, A display device, wherein the first layer has a structure in which the plurality of first sub-layers and the plurality of second sub-layers are alternately laminated.

3. In paragraph 2, A display device, wherein two of the plurality of first sub-layers are respectively positioned at the uppermost and lowermost portions of the first layer.

4. In paragraph 1, A display device, wherein the first sub-layer is an amorphous alloy layer.

5. In paragraph 1, A display device, wherein the rare earth element comprises at least one of yttrium (Y), samarium (Sm), cerium (Ce), or lanthanum (La).

6. In paragraph 1, A display device, wherein the content of the rare earth element is 4 at% or more and 10 at% or less based on the total atomic weight of the first sublayer.

7. In paragraph 2, A display device, wherein a ratio of the thickness of each of the plurality of first sub-layers to the thickness of each of the plurality of second sub-layers is 1 or less.

8. In paragraph 1, A display device, wherein the resistivity of the first layer is greater than 5.6 μΩ·cm and less than 11 μΩ·cm.

9. In paragraph 1, A display device, wherein the elastic strain of the first layer is 2.0% or more.

10. In paragraph 1, A display device, wherein the yield strength of the first layer is 0.8 GPa or more and 1.2 GPa or less.

11. In paragraph 1, Each of the above plurality of wires further includes a second layer below the first layer, and a third layer above the first layer, A display device, wherein the second layer and the third layer include materials different from those of the first layer.

12. In paragraph 1, Each of the above multiple islands, A transistor comprising a semiconductor and a gate electrode; a light emitting element electrically connected to said transistor; and An electrode disposed between the gate electrode and the light-emitting element; A display device, wherein the electrode includes a third sub-layer including an alloy of aluminum and a rare earth element, and a fourth sub-layer including aluminum.

13. A display device including a display area and a non-display area outside the display area, A plurality of islands arranged in the above display area, each island including a transistor and a light-emitting element electrically connected to the transistor; and It includes a plurality of bridge sections each connecting adjacent island sections among the above-mentioned multiple island sections; Each of the above multiple bridge sections is: comprising wiring electrically connected to a transistor of one of the adjacent islands; The above wiring includes the first layer, A display device, wherein the first layer includes a first sub-layer including an alloy of aluminum and a rare earth element, and a second sub-layer including aluminum.

14. In paragraph 13, The above first sub-layer and the above second sub-layer are each provided in multiples, A display device, wherein the first layer has a structure in which the plurality of first sub-layers and the plurality of second sub-layers are alternately laminated.

15. In paragraph 14, A display device, wherein two of the plurality of first sub-layers are respectively positioned at the uppermost and lowermost portions of the first layer.

16. In paragraph 13, A display device, wherein the rare earth element comprises at least one of yttrium (Y), samarium (Sm), cerium (Ce), or lanthanum (La).

17. In paragraph 13, A display device, wherein the content of the rare earth element is 4 at% or more and 10 at% or less based on the total atomic weight of the first sublayer.

18. In paragraph 14, A display device, wherein a ratio of the thickness of each of the plurality of first sub-layers to the thickness of each of the plurality of second sub-layers is greater than 0 and less than or equal to 1.

19. In paragraph 13, A display device, wherein the resistivity of the first layer is greater than 5.6 μΩ·cm and less than 11 μΩ·cm.

20. In paragraph 13, A display device, wherein the elastic strain of the first layer is 2.0% or more.

21. In paragraph 13, A display device, wherein the yield strength of the first layer is 0.8 GPa or more and 1.2 GPa or less.

Images