Array substrate, display panel, and display apparatus

Abstract

An array substrate (001), a display panel, and a display apparatus. The array substrate (001) comprises: a base substrate (100); a plurality of pixel electrodes (101) arranged in an array on the base substrate (100), wherein first gaps (GP1) extending in a first direction (X) and second gaps (GP2) extending in a second direction (Y) are provided between the pixel electrodes (101), and every two pixel electrodes (101) arranged in the first direction (X) serve as one pixel electrode group (PX); a plurality of gate lines (102) extending in the first direction (X) on the base substrate (100) and arranged in the second direction (Y), wherein orthographic projections of the gate lines (102) on the base substrate (100) at least partially overlap with orthographic projections of the first gaps (GP1) on the base substrate (100), and two gate lines (102) are included in a same first gap (GP1); and a first common electrode line (103), wherein an orthographic projection of the first common electrode line (103) on the base substrate (100) is located within the orthographic projections of the first gaps (GP1) and orthographic projections of the second gaps (GP2) between the pixel electrode groups (PX) on the base substrate (100); and where the first gap (GP1) does not overlap the second gap (GP2), the orthographic projection of the first common electrode line (103) on the base substrate (100) passes through, in the second direction (Y), an orthographic projection of a gap between the two gate lines (102) on the base substrate (100).

Description

Array substrate, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) feature compact size, low power consumption, high image quality, zero radiation, and portability. They have experienced rapid development in recent years, gradually replacing traditional cathode ray tube (CRT) displays and dominating the current flat-panel display market. Currently, TFT-LCDs are widely used in a variety of large, medium, and small-sized products, encompassing nearly every major electronic product in today's information society, including LCD TVs, high-definition digital TVs, computers (desktop and laptop), mobile phones, tablets, navigation systems, in-car displays, projection displays, camcorders, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays.

[0003] Summary of the Invention

[0004] The array substrate, display panel, and display device provided by the embodiments of the present disclosure are specifically described as follows:

[0005] In one aspect, an embodiment of the present disclosure provides an array substrate, comprising:

[0006] substrate;

[0007] a plurality of pixel electrodes arranged in an array on the base substrate, with a first gap extending along a first direction and a second gap extending along a second direction between the pixel electrodes, every two pixel electrodes arranged in the first direction constitute a pixel electrode group, and the second direction intersects the first direction;

[0008] a plurality of gate lines extending along the first direction and arranged along the second direction on the base substrate, wherein the orthographic projections of the gate lines on the base substrate at least partially overlap with the orthographic projections of the first gaps on the base substrate, and two gate lines are located in the same first gap;

[0009] A first common electrode line, the orthographic projection of the first common electrode line on the base substrate is located within the first gap and the orthographic projection of the second gap between the pixel electrode groups on the base substrate; and at the first gap that does not overlap with the second gap, the orthographic projection of the first common electrode line on the base substrate passes through the orthographic projection of the gap between the two gate lines on the base substrate along the second direction.

[0010] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the first common electrode line includes a plurality of first sub-common electrode lines located at the first gap, and at least part of the orthographic projections of the first sub-common electrode lines on the base substrate pass through the orthographic projections of the gaps between the two gate lines on the base substrate along the second direction.

[0011] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a color resist layer located between the layer where the gate lines are located and the layer where the pixel electrodes are located, wherein the color resist layer includes an opening located at the first gap;

[0012] The first common electrode line further includes a first extension portion adjacent to the pixel electrode in the first gap and connected to the first sub-common electrode line, the first extension portion including a first boundary adjacent to the pixel electrode and extending along the first direction, an orthographic projection of a portion of the first boundary on the base substrate being located within an orthographic projection of the opening on the base substrate;

[0013] The pixel electrode includes a second boundary adjacent to the first extension portion and extending along the first direction, and an orthographic projection of the second boundary on the base substrate is located outside an orthographic projection of the opening on the base substrate.

[0014] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the opening includes a fourth boundary located between the first boundary and the second boundary, the distance between the first boundary and the fourth boundary in the second direction is greater than or equal to 4 μm, and the distance between the second boundary and the fourth boundary in the second direction is greater than or equal to 4 μm.

[0015] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a second common electrode line, and a first insulating layer located between a layer where the second common electrode line is located and a layer where the pixel electrode is located, wherein the first insulating layer includes the color resist layer;

[0016] The second common electrode line includes a plurality of common electrode repeating units, each of which includes a protruding portion, which is electrically connected to the first extension portion through a first via hole penetrating the first insulating layer, and the orthographic projection of the first via hole on the base substrate is located within the orthographic projection of the opening on the base substrate.

[0017] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the gate line includes a winding portion, the winding portion is spaced apart from the protruding portion, and the protruding portion includes a third boundary facing one side of the winding portion, and the routing method of the winding portion is the same as the direction of the third boundary.

[0018] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, part of the orthographic projection of the first via on the base substrate is located within the orthographic projection of the protrusion on the base substrate, and the remaining part of the orthographic projection is located on the side of the orthographic projection of the protrusion on the base substrate facing the orthographic projection of the gate line on the base substrate.

[0019] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a plurality of transistors, and a second insulating layer located between a layer where the transistors are located and a layer where the pixel electrodes are located, wherein the second insulating layer includes the color resist layer, and the first insulating layer includes the second insulating layer;

[0020] The first electrode of the transistor is electrically connected to the pixel electrode through a second via hole penetrating the second insulating layer, and the orthographic projection of the second via hole on the base substrate is located within the orthographic projection of the opening on the base substrate;

[0021] The orthographic projections of at least part of the second via holes and at least part of the first via holes on the base substrate are located within the orthographic projection of the same opening on the base substrate.

[0022] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the first electrode of the transistor includes a widened portion extending along the first direction, the widened portion is electrically connected to the pixel electrode through the second via hole, and the orthographic projection of the widened portion on the base substrate is located on the side where the orthographic projections of the two gate lines on the base substrate are close to the orthographic projection of the pixel electrode on the base substrate.

[0023] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure further includes a plurality of connecting electrodes, wherein the connecting electrodes are integrally arranged with the pixel electrode at the first gap, the connecting electrodes are electrically connected to the widened portion through the second via hole, and the orthographic projection of the connecting electrodes on the base substrate at least partially overlaps with the orthographic projection of the widened portion on the base substrate.

[0024] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the two connecting electrodes connected to the same pixel electrode group are separated at the first gap arranged along the second direction on both sides of the pixel electrode group, and the two connecting electrodes at the same first gap are staggered in the second direction.

[0025] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, within the first gap between two adjacent pixel electrode groups arranged in the second direction, two adjacent transistors are symmetrically arranged about the center of the first gap, and at least part of the transistors overlap with the first gap between two pixel electrodes included in one pixel electrode group along the second direction.

[0026] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the second pole of the transistor includes a connecting portion extending along the first direction, at least part of the orthographic projection of the connecting portion on the base substrate overlaps with the orthographic projection of the gap between the two gate lines on the base substrate, and the routing method of the connecting portion is the same as the direction of the third boundary of the protrusion toward the side of the gate line.

[0027] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the base substrate includes a plurality of red sub-pixel regions, a plurality of green sub-pixel regions, and a plurality of blue sub-pixel regions, and the plurality of pixel electrodes are located in the plurality of red sub-pixel regions, the plurality of green sub-pixel regions, and the plurality of blue sub-pixel regions;

[0028] The orthographic projection of the second via hole corresponding to the pixel electrode of the blue sub-pixel area on the base substrate and the orthographic projection of the first via hole on the base substrate are located within the orthographic projection of the same opening on the base substrate.

[0029] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, the first sub-common electrode line includes a first portion, a second portion, and a third portion that are sequentially connected; wherein,

[0030] The first portion extends along the second direction, and an orthographic projection of the first portion on the base substrate at least partially overlaps with an orthographic projection of one of the gate lines on the base substrate;

[0031] The second portion extends along the first direction, and an orthographic projection of at least a portion of the second portion on the base substrate overlaps with an orthographic projection of a gap between two gate lines on the base substrate;

[0032] The third portion extends along the second direction, and an orthographic projection of the third portion on the base substrate at least partially overlaps with an orthographic projection of another gate line on the base substrate;

[0033] The orthographic projection of the first portion on the substrate and the orthographic projection of the third portion on the substrate are located on both sides of the orthographic projection of the gates of the two transistors on the substrate.

[0034] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the first extension portion is connected to the third portion, and the orthographic projection of the first extension portion on the base substrate covers the orthographic projection of the edge of the gate line close to the pixel electrode on the base substrate.

[0035] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the first common electrode line also includes a second extension portion connected to the first portion, and the orthographic projection of the second extension portion on the base substrate covers the orthographic projection of the edge of the gate line close to the pixel electrode on the base substrate.

[0036] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a plurality of transistors, wherein a first electrode of the transistor includes a widened portion extending along the first direction, the widened portion is electrically connected to the pixel electrode, and an orthographic projection of the widened portion on the base substrate is located within an orthographic projection of a gap between two gate lines on the base substrate;

[0037] Part of the orthographic projection of a portion of the first sub-common electrode line on the base substrate is located between the orthographic projections of the widened portions of the two transistors on the base substrate.

[0038] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a plurality of connecting electrodes, wherein the connecting electrodes are integrally provided with the pixel electrodes, the connecting electrodes are electrically connected to the widened portion, and the orthographic projections of the connecting electrodes on the base substrate span the orthographic projection of one gate line on the base substrate and extend to a gap between two gate lines within the orthographic projection on the base substrate;

[0039] The orthographic projections of the remaining first sub-common electrode lines on the base substrate are disconnected at the connecting electrodes.

[0040] In some embodiments, the above-mentioned array substrate provided by the embodiments of the present disclosure further includes a third common electrode line extending along the first direction at the first gap, the third common electrode line is arranged in the same layer as the gate line, the third common electrode line is located between the two gate lines, and the orthographic projection of the third common electrode line on the base substrate overlaps with the orthographic projection of the connection position of the connecting electrode and the widened portion on the base substrate.

[0041] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, part of the first sub-common electrode lines includes a first portion, a second portion, and a third portion that are sequentially connected; wherein,

[0042] The orthographic projection of the first portion on the base substrate at least partially overlaps with the orthographic projection of one of the gate lines on the base substrate, and the orthographic projection of the first portion on the base substrate is parallel to a partial orthographic projection of one of the connecting electrodes on the base substrate;

[0043] The second portion extends along the second direction, and an orthographic projection of the second portion on the substrate is located between orthographic projections of the widened portions of the two transistors on the substrate;

[0044] The orthographic projection of the third portion on the base substrate at least partially overlaps with the orthographic projection of another gate line on the base substrate, and the orthographic projection of the third portion on the base substrate is parallel to a partial orthographic projection of another connecting electrode on the base substrate;

[0045] The orthographic projection of the first portion on the base substrate and the orthographic projection of the third portion on the base substrate are located between the orthographic projections of the two connecting electrodes on the base substrate.

[0046] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the first sub-common electrode line includes a fourth part and a fifth part, the orthographic projection of the fourth part on the base substrate covers a partial orthographic projection of the edge of one of the gate lines close to the pixel electrode on the base substrate, and the orthographic projection of the fifth part on the base substrate covers a partial orthographic projection of the edge of another gate line close to the pixel electrode on the base substrate.

[0047] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure further includes a second common electrode line on the same layer as the multiple gate lines, the second common electrode line includes a plurality of common electrode repeating units, the common electrode repeating unit includes a second sub-common electrode line extending along the second direction, the orthographic projection of the second sub-common electrode line on the base substrate covers the orthographic projection of adjacent edges of two pixel electrodes in the pixel electrode group on the base substrate, and the line width of the second sub-common electrode line in the first direction is greater than or equal to 7 μm and less than or equal to 15 μm.

[0048] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the common electrode repetition unit also includes a third sub-common electrode line extending along the second direction, the orthographic projection of the third sub-common electrode line on the base substrate covers the orthographic projection of the opposite edges of the two pixel electrodes in the pixel electrode group on the base substrate, and the size of the third sub-common electrode line in the second direction is less than or equal to the size of the second sub-common electrode line in the second direction.

[0049] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, at a position adjacent to the second sub-common electrode line: the gate line includes a fold line portion protruding in a direction away from the second sub-common electrode line, or the gate line includes a straight line portion extending along the first direction.

[0050] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the second common electrode line further includes a plurality of common electrode connecting lines, and the plurality of common electrode connecting lines are connected to adjacent common electrode repeating units arranged along the first direction.

[0051] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, the common electrode connection line is connected to at least one of the two end portions and the middle portion of the common electrode repeating unit in the second direction.

[0052] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a plurality of data lines extending along the second direction and arranged along the first direction, wherein the orthographic projections of the data lines on the base substrate are located within the orthographic projections of the second gaps between adjacent pixel electrode groups on the base substrate;

[0053] The first common electrode line further includes a fourth sub-common electrode line extending along the second direction, and an orthographic projection of the fourth sub-common electrode line on the base substrate at least partially covers an orthographic projection of the data line on the base substrate.

[0054] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the pixel electrode is a plate electrode or a slit electrode.

[0055] On the other hand, an embodiment of the present disclosure provides a display panel, including an array substrate and an opposite substrate arranged opposite to each other, wherein the array substrate is the above-mentioned array substrate provided in the embodiment of the present disclosure.

[0056] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, the counter substrate includes a common electrode layer.

[0057] In some embodiments, in the display panel provided by the embodiments of the present disclosure, the counter substrate further comprises a black matrix located on a side of the common electrode layer away from the array substrate;

[0058] The orthographic projection of the black matrix on the base substrate overlaps with the orthographic projection of the first gap on the base substrate, and the orthographic projection of the black matrix on the base substrate and the orthographic projection of the second gap on the base substrate that does not overlap with the first gap do not overlap with each other.

[0059] On the other hand, an embodiment of the present disclosure provides a display device, including the above-mentioned display panel provided by an embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] FIG1 is a schematic diagram of a dual-gate pixel architecture;

[0061] FIG2 is a schematic structural diagram of four pixel electrodes and their adjacent wirings in an array substrate provided by an embodiment of the present disclosure;

[0062] FIG3 is a schematic diagram of the enlarged structure of the Z1 area in FIG2 ;

[0063] FIG4 is a schematic structural diagram of the layer where the gate lines are located in FIG2 ;

[0064] FIG5 is a schematic structural diagram of the layer where the active layer is located in FIG2;

[0065] FIG6 is a schematic structural diagram of the layer where the first and second electrodes are located in FIG2 ;

[0066] FIG7 is a schematic structural diagram of the first via hole and the second via hole in FIG2 ;

[0067] FIG8 is a schematic structural diagram of the layer where the pixel electrode is located in FIG2 ;

[0068] FIG9 is a schematic diagram of the cross-sectional structure along line I-II in FIG2 ;

[0069] FIG10 is a schematic diagram of the enlarged structure of the Z2 area in FIG3;

[0070] FIG11 is a schematic diagram of the pixel electrode and the first extension portion climbing simultaneously;

[0071] FIG12 is a schematic diagram of photoresist accumulation at a climbing location;

[0072] FIG13 is a schematic diagram of another structure of four pixel electrodes and their adjacent wirings in an array substrate provided by an embodiment of the present disclosure;

[0073] FIG14 is a schematic structural diagram of the layer where the gate lines are located in FIG13;

[0074] FIG15 is a schematic structural diagram of the layer where the active layer is located in FIG13;

[0075] FIG16 is a schematic structural diagram of the layer where the first and second electrodes are located in FIG13;

[0076] FIG17 is a schematic structural diagram of the first via hole and the second via hole in FIG13;

[0077] FIG18 is a schematic structural diagram of the layer where the pixel electrode is located in FIG13;

[0078] FIG19 is a schematic structural diagram of a pixel electrode provided in an embodiment of the present disclosure;

[0079] FIG20 is a schematic diagram of another structure of a pixel electrode provided in an embodiment of the present disclosure;

[0080] FIG21 is a schematic diagram of a structure of four pixel electrodes and their adjacent wirings in a display panel provided by an embodiment of the present disclosure;

[0081] FIG22 is another structural schematic diagram of four pixel electrodes and their adjacent wirings in a display panel provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0082] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the following description will be made in conjunction with the accompanying drawings of the embodiments of the present disclosure. For clarity, the thickness of layers, films, panels, regions, etc. is exaggerated in the drawings. In this disclosure, exemplary embodiments are described with reference to cross-sectional views that are schematic diagrams of idealized embodiments. As such, deviations from the shapes of the drawings as a result of, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shapes of the regions shown in this disclosure, but rather include deviations in shape resulting from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the drawings are schematic in nature, and their sizes and shapes are not intended to illustrate the precise shapes of the regions or reflect true scale, but are intended only to illustrate the contents of the present disclosure. Throughout, the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions.

[0083] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in the present disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0084] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be an intermediate element or intermediate layer. When an element or layer is referred to as being "disposed on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more related listed items. The various embodiments of the present disclosure may be combined with each other without conflict.

[0085] Thin-film transistor liquid crystal displays (TFT-LCDs) include twisted nematic (TN), vertically aligned (VA), fringe field switching (FFS), advanced dimension switch (ADS), and in-plane switching (IPS). VA displays offer better dark-state performance and contrast compared to other types of displays.

[0086] VA-type liquid crystal displays are mostly single-gate structures, where one gate line connects to one row of sub-pixels, and one data line connects to one column of sub-pixels. To reduce production costs, dual-gate VA-type liquid crystal displays have been developed. As shown in FIG1 , the dual-gate structure is specifically as follows: a row of sub-pixel regions (e.g., a red sub-pixel region R, a green sub-pixel region G, and a blue sub-pixel region B) is electrically connected to two gate lines (GL) through transistors (TFTs), and two sub-pixel regions in adjacent rows and columns (e.g., a red sub-pixel region R and a green sub-pixel region G, a blue sub-pixel region B and a green sub-pixel region G, and a blue sub-pixel region B and a red sub-pixel region R) are electrically connected to the same data line (DL) through transistors (TFTs). This connection method allows two gate lines (GL) to be provided between two adjacent rows of sub-pixel regions (e.g., a red sub-pixel region R, a green sub-pixel region G, and a blue sub-pixel region B), and one data line (DL) to be provided between each two adjacent columns of sub-pixels (e.g., a column where the red sub-pixel region R is located and a column where the green sub-pixel region G is located, a column where the blue sub-pixel region B is located and a column where the red sub-pixel region R is located, and a column where the green sub-pixel region G is located and a column where the blue sub-pixel region B is located). This reduces the number of data lines (DL) and correspondingly reduces the number of source driver chips (Source) connected to the data lines (DL). The total number of ICs is greatly reduced, which greatly reduces the material cost and is especially suitable for medium and large-sized products such as car displays and TVs.

[0087] Some VA-type liquid crystal display products (such as VA curved display screens) can use a process in which a color film (also called a color resist layer) is made on an array substrate (CF On Array, COA). Taking into account the large alignment offset between the array substrate and the opposing substrate in the case of a curved surface, a black matrix (BM) cannot be set in the direction of the data line. It is necessary to use a transparent material (such as indium tin oxide ITO) to replace the black matrix (DATA BM Succedaneum, DBS) in the direction of the data line to cover the data line, and load the DBS ITO with a common electrode signal to prevent the data signal from affecting the deflection of the liquid crystal and causing light leakage. However, the DBS ITO material is very thin and has a high resistance. In actual product applications, a mesh structure must be formed, otherwise it will not meet the light shielding requirements.

[0088] In a dual-gate pixel design based on the COA process, DBS ITO mesh wiring can be placed in the gap between the sub-pixel columns between two data lines. Given that the DBS ITO and the pixel electrode (pixel) are on the same layer and made of the same material, in actual production, the minimum line width of DBS ITO is 3.5μm, and the spacing between different signals on the same layer must be greater than or equal to 5μm. Therefore, the minimum spacing between adjacent pixel electrodes is 13.5μm, resulting in a significant loss in pixel aperture ratio.

[0089] To improve the above-mentioned technical problems existing in the related art, an embodiment of the present disclosure provides an array substrate. FIG2 mainly shows four pixel electrodes 101 arranged along a first direction X and a second direction Y in the array substrate, and a wiring scheme near the four pixel electrodes 101. FIG3 is an enlarged structural schematic diagram of the Z1 region in FIG2. FIG4 to FIG8 are structural schematic diagrams of each single film layer in FIG2. As can be seen from FIG2 to FIG8, the array substrate provided in the embodiment of the present disclosure may include:

[0090] Base substrate 100. In some embodiments, base substrate 100 is a substrate that allows visible light to pass through, such as glass, quartz, plastic, etc.

[0091] A plurality of pixel electrodes 101 are arranged in an array on a base substrate 100. A first gap GP1 extending along a first direction X and a second gap GP2 extending along a second direction Y are defined between the pixel electrodes 101. Every two pixel electrodes 102 arranged in the first direction X constitute a pixel electrode group PX. The two pixel electrodes 102 in the same pixel electrode group PX are electrically connected to the same data line 111. The second direction Y intersects the first direction X. Optionally, the material of the pixel electrodes 101 may include at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), or gallium zinc oxide (GZO).

[0092] A plurality of gate lines 102 extend along a first direction X and are arranged along a second direction Y on a base substrate 100. The orthographic projection of the gate lines 102 on the base substrate 100 at least partially overlaps with the orthographic projection of the first gap GP1 on the base substrate 100. For example, the orthographic projection of the gate lines 102 on the base substrate 100 is located within the orthographic projection of the first gap GP1 on the base substrate 100. In some embodiments, two gate lines 102 are included in the same first gap GP1. Optionally, the material of the gate lines 102 may include a metal such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), or nickel (Ni). The gate lines 102 may have a single-layer structure or a stacked-layer structure. For example, the gate lines 102 may have a single-layer structure composed of a copper metal layer.

[0093] The first common electrode line 103 can be provided in the same layer and with the same material as the pixel electrode 101. Optionally, the orthographic projection of the first common electrode line 103 on the base substrate 100 is located within the first gap GP1 and the orthographic projection of the second gap GP2 between the pixel electrode groups PX on the base substrate 100, that is, the first common electrode line 103 does not exist in the second gap GP2 between the two pixel electrodes 101 contained in the pixel electrode group PX; and at the first gap GP1 that does not overlap with the second gap GP2, the orthographic projection of the first common electrode line 103 on the base substrate 100 passes through the orthographic projection of the gap between the two gate lines 102 on the base substrate 100 along the second direction Y.

[0094] In the array substrate provided in the embodiment of the present disclosure, the first common electrode line 103 is positioned within the first gap GP1 and the second gap GP2 between the pixel electrode groups PX. Furthermore, in the first gap GP1 that does not overlap with the second gap GP2, the first common electrode line 103 passes through the gap between the two gate lines 102. This allows the first common electrode line 103 to form a mesh structure within the first gap GP1 and the second gap GP2 between the pixel electrode groups PX that meets light shielding requirements. Because the first common electrode line 103 (equivalent to DBS ITO) is not present in the second gap GP2 between the two pixel electrodes 101 included in the pixel electrode group PX, the width of the DBS ITO in the second gap GP2 between the two pixel electrodes 101 included in the pixel electrode group PX can be at least reduced. This significantly increases the pixel aperture ratio and product transmittance while still meeting the light shielding effect.

[0095] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, in combination with Figures 2 to 4 and Figure 8, it can be seen that the first common electrode line 103 includes a plurality of first sub-common electrode lines 1031 located at the first gap GP1. Optionally, the first sub-common electrode lines 1031 can be arranged within the black matrix (BM) range of the opposite substrate; in addition, the orthographic projection of the first sub-common electrode line 1031 on the base substrate 100 at least partially overlaps with the edges of the two gate lines 102 close to the pixel electrode 101, so that the first sub-common voltage line 1031 can be used to effectively shield the scanning signal of the gate line 102, so that the pixel electrode 101 will no longer be interfered by the gate line 102. 2 to 4 and 8 , it can be seen that in order to continuously arrange the first sub-common electrode lines 1031 and thereby ensure that the first common electrode lines 103 can form a mesh structure, the present disclosure can arrange that the orthographic projections of at least part of the first sub-common electrode lines 1031 on the base substrate 100 pass through the gaps between the two gate lines 102 along the second direction Y on the base substrate 100.

[0096] In some embodiments, in the above-mentioned array substrate provided by the embodiment of the present disclosure, as shown in Figures 2 to 4 and Figures 8 to 10, it may further include a color resist layer 104 located between the layer where the gate line 102 is located and the layer where the pixel electrode 101 is located, the color resist layer 104 includes an opening h0 located at the first gap GP1, and color resists of different colors such as red color resist, green color resist, and blue color resist; optionally, the first common electrode line 103 also includes a first extension portion 1032 adjacent to the pixel electrode 101 in the first gap GP1 and connected to the first sub-common electrode line 1031, the first The extension portion 1032 includes a first boundary BL1 adjacent to the pixel electrode 101 and extending along the first direction X. The partial orthographic projection of the first boundary BL1 on the base substrate 100 is located within the orthographic projection of the opening h0 on the base substrate 100. In other words, the first boundary BL1 extends from the area where the opening h0 is located to outside the area of ​​the opening h0. The pixel electrode 101 includes a second boundary BL2 adjacent to the first extension portion 1032 and extending along the first direction X. The orthographic projection of the second boundary BL2 on the base substrate 100 is located outside the orthographic projection of the opening h0 on the base substrate 100.

[0097] Because the first common electrode line 103 and the pixel electrode 101 are formed from the same layer and material, and the boundary step difference of the opening h0 of the color resist layer 104 is relatively large, for example, reaching 2.5 μm, if the first extension 1032 of the first common electrode line 103 and the pixel electrode 101 are both in a sloped position, photoresist (PR) accumulation will form at the sloped position, preventing full exposure during exposure, resulting in a short circuit (leak) between the first extension 1032 and the pixel electrode 101, as shown in Figures 11 and 12. The present disclosure extends the first boundary BL1 between the first extension 1032 and the pixel electrode 101 from within the opening h0 of the color resist layer 104 to outside the opening h0, while the second boundary BL2 between the pixel electrode 101 and the first extension 1032 is located outside the opening h0. This allows only the first extension 1032 to slope, thus preventing the first extension 1032 and the pixel electrode 101 from sloped simultaneously and effectively preventing a short circuit between the first extension 1032 and the pixel electrode 101.

[0098] In some embodiments, as shown in FIG10 , the opening h0 includes a fourth boundary BL4 located between the first boundary BL1 and the second boundary BL2. A distance D1 between the first boundary BL1 and the fourth boundary BL4 in the second direction Y is greater than or equal to 4 μm, and a distance D2 between the second boundary BL2 and the fourth boundary BL4 in the second direction Y is greater than or equal to 4 μm. This prevents short circuits between the first extension 1032 and the pixel electrode 101 due to process fluctuations. It should be noted that 4 μm is the limit of current processes. With advancements in manufacturing processes and equipment, the distances D1 and D2 may be less than 4 μm, for example, 3 μm.

[0099] In some embodiments, in the above-mentioned array substrate provided by the embodiment of the present disclosure, as shown in Figures 2 to 4 and Figures 7 to 10, it can also include a second common electrode line 105 and a first insulating layer IL1 located between the layer where the second common electrode line 105 is located and the layer where the pixel electrode 101 is located. Optionally, the second common electrode line 105 and the gate line 102 are in the same layer and are provided with the same material. The first insulating layer IL1 includes a color resist layer 104, a gate insulating layer 106, a passivation layer 107 and a flat layer 108. The materials of the gate insulating layer 106 and the passivation layer 107 can be silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), At least one inorganic insulating material such as hafnium oxide (HfOx) and tantalum oxide (TaOx); the material of the flat layer 108 may be at least one organic insulating material such as polyacrylic resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, phenolic epoxy acrylic resin, etc.; the second common electrode line 105 includes a plurality of common electrode repeating units 1051, and the common electrode repeating unit 1051 includes a protrusion 511, which is electrically connected to the first extension portion 1032 through a first via hole h1 penetrating the first insulating layer IL1, and the orthographic projection of the first via hole h1 on the base substrate 100 is located within the orthographic projection of the opening h0 on the base substrate 100.

[0100] By connecting the first common electrode line 103 and the second common electrode line 105 via the first via h1, the overall resistance of the first common electrode line 103 and the second common electrode line 105 is reduced, thereby reducing the voltage drop (IR drop) of the common voltage signal and improving the uniformity and anti-interference capability of the common voltage signal. For example, during actual display, changes in the data signal can increase the potential of the common voltage signal, which in turn indirectly increases the potential of the common electrode layer on the opposing substrate, leading to crosstalk. The present disclosure effectively ensures a relatively stable common voltage signal, thus preventing crosstalk.

[0101] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 2 to 4 and Figure 7, part of the orthographic projection of the first via h1 on the base substrate 100 is located within the orthographic projection of the protrusion 511 on the base substrate 100, and the orthographic projection of the remaining part is located on the side of the orthographic projection of the protrusion 511 on the base substrate 100 facing the orthographic projection of the gate line 102 on the base substrate 100, which is equivalent to that in the direction perpendicular to the base substrate 100, part of the area of ​​the first via h1 overlaps with the protrusion 511, and the remaining area does not overlap with the protrusion 511. In this way, due to the presence of the protrusion 511, a step can be formed at the first via h1, which is beneficial to the flow of the alignment liquid (such as PI liquid), improves the uniformity of PI film formation, and enhances the alignment effect. Optionally, the length of the first via h1 exceeding the protrusion 511 can be greater than or equal to 2.5μm.

[0102] In some embodiments, the array substrate provided in the embodiments of the present disclosure, as shown in Figures 2 to 9, may further include a plurality of transistors 109, and a second insulating layer IL2 located between the layer where the transistors 109 are located and the layer where the pixel electrodes 101 are located. Optionally, the first insulating layer IL1 includes a second insulating layer IL2, and the second insulating layer IL2 includes a color resist layer 104, a passivation layer 107, and a planarization layer 108; the first electrode d of the transistor 109 is electrically connected to the pixel electrode 101 through a second via h2 penetrating the second insulating layer IL2, and the orthographic projection of the second via h2 on the base substrate 100 is located within the orthographic projection of the opening h0 on the base substrate 100; in some embodiments, at least part of the second via h2 and at least part of the orthographic projection of the first via h1 on the base substrate 100 are located within the same orthographic projection of the opening h0 on the base substrate 100.

[0103] Since both the first via h1 and the second via h2 penetrate the planar layer 108, each via that penetrates the planar layer 108 requires at least an opening h0 of the color resist layer 104 of at least 20 μm by 20 μm in size. Therefore, this has a significant impact on the aperture ratio. The present disclosure arranges the orthographic projections of at least a portion of the second via h2 and at least a portion of the first via h1 on the base substrate 100 within the orthographic projection of the same opening h0 on the base substrate 100. This is equivalent to sharing a portion of the opening h0 required for the two vias that penetrate the planar layer 108. For example, two 20 μm by 20 μm openings h0 can be merged into a single 20 μm by 30 μm opening h0. This helps reduce the overall size of all openings h0 in the entire color resist layer 104, reduces pixel aperture ratio loss, and improves transmittance.

[0104] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 2 to 8, the base substrate 100 includes multiple red sub-pixel areas R, multiple green sub-pixel areas G and multiple blue sub-pixel areas B, and multiple pixel electrodes 101 are located in the multiple red sub-pixel areas R, the multiple green sub-pixel areas G and the multiple blue sub-pixel areas B; the orthographic projection of the first via hole h1 on the base substrate 100 and the orthographic projection of the second via hole h2 corresponding to the pixel electrode 101 of the blue sub-pixel area B on the base substrate 100 are located within the orthographic projection of the same opening h0 on the base substrate 100.

[0105] It should be understood that the more first vias h1 used to connect the first common electrode line 103 and the second common electrode line 105, the lower the overall resistance of the first common electrode line 103 and the second common electrode line 105, which is more conducive to ensuring the stability of the common electrode signal. In order to reduce the loss of pixel aperture ratio and improve transmittance, the first via h1 and the second via h2 can be set within the same opening h0. However, this will inevitably make the opening h0 that accommodates both the first via h1 and the second via h2 larger than the opening h0 that accommodates only the first via h1 or the second via h2. It is more likely to cause the alignment film subsequently formed on the color resist layer 104 to accumulate at the opening h0 that accommodates both the first via h1 and the second via h2, which is not conducive to improving the film formation uniformity and alignment effect of the alignment film. Based on this, to balance the alignment effect and the stability of the common electrode signal, the present disclosure only provides the first via h1 with the second via h2 corresponding to the pixel electrode 101 of the blue sub-pixel area B located in the same opening h0. Although this has a certain impact on the alignment effect of the blue sub-pixel area B, given that the pixel brightness of the blue sub-pixel area B is the lowest among the red sub-pixel area R, the green sub-pixel area G and the blue sub-pixel area B, even if part of the alignment effect of the blue sub-pixel area B is sacrificed, it will not have a significant impact on the overall display effect of the product.

[0106] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 2 to 8, the first electrode d of the transistor 109 includes a widened portion d1 extending along the first direction X, the widened portion d1 is electrically connected to the pixel electrode 101 through the second via h2, and the orthographic projection of the widened portion d1 on the base substrate 1000 is located on a side where the orthographic projections of the two gate lines 102 on the base substrate 100 are close to the orthographic projection of the pixel electrode 101 on the base substrate 100.

[0107] Since the thickness of the layer where the first electrode d of the transistor 109 is located can be 4 to 5 times the thickness of the layer where the pixel electrode 101 is located, the risk of disconnection of the wiring of the layer where the first electrode d of the transistor 109 is located is smaller than that of the wiring of the layer where the pixel electrode 101 is located. Based on this, the present disclosure effectively avoids the disconnection problem and enhances the electrical connection effect between the first electrode d of the transistor 109 and the pixel electrode 101 by setting the first electrode d of the transistor 109 to include a widened portion d1 located on the side of the gate line 102 close to the pixel electrode 101, and adopts a solution of electrically connecting the widened portion d1 to the pixel electrode 101.

[0108] In some embodiments, the array substrate provided in the embodiments of the present disclosure, as shown in Figures 2, 3, and 6 to 8, may further include a plurality of connecting electrodes 110. The connecting electrodes 110 are integrally arranged with the pixel electrodes 101 at the first gap GP1. The connecting electrodes 110 are electrically connected to the widened portion d1 through the second via h2. The orthographic projections of the connecting electrodes 110 on the base substrate 100 at least partially overlap with the orthographic projections of the widened portion d1 on the base substrate 100. Optionally, the orthographic projections of the connecting electrodes 110 on the base substrate 100 are located within the orthographic projections of the widened portion d1 on the base substrate 100. Because the connecting electrodes 110 located within the widened portion d1 are relatively large, even if the connecting electrodes 110 are relatively thin, they are less likely to break and can still maintain a good electrical connection with the widened portion d1.

[0109] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG8 , two connection electrodes 110 connected to the same pixel electrode group PX are separated at first gaps GP1 arranged along the second direction Y on both sides of the pixel electrode group PX, and the two connection electrodes 110 at the same first gap GP1 are staggered in the second direction Y. Compared to arranging the two connection electrodes 110 at the same first gap GP1 side by side along the second direction Y, the present disclosure staggers the two connection electrodes 110 at the same first gap GP1 in the second direction Y, which can effectively reduce the size of the first gap GP1 in the second direction Y, thereby increasing the pixel aperture ratio and improving the transmittance.

[0110] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, as shown in Figure 3, at least part of the transistors 109 overlap with the first gap GP1 between two pixel electrodes 101 included in a pixel electrode group PX along the second direction Y. Optionally, in the first gap GP1 between two adjacent pixel electrode groups PX arranged in the second direction Y, two adjacent transistors 109 located between two data lines 111 are symmetrically arranged about the center O of the first gap GP1 to ensure that the parasitic capacitance formed by other film layers other than the gate g in each transistor 109 (for example, the layer where the first electrode d and the second electrode s are located, and the active layer a) and the gate line 102 is approximately the same (for example, within an error range of ±5%), ensuring that the signal change amount (△Vp) caused by the parasitic capacitance of each pixel electrode 101 is similar, thereby effectively improving the bad shaking head wrinkles.

[0111] Specifically, as shown in Figures 2 to 4 and Figure 6, the first electrode d of the transistor 109 also includes a first electrode portion d2 integrally arranged with the widened portion d1 in the first gap GP1, the first electrode portion d2 extends along the second direction Y, and the orthographic projection of the first electrode portion d2 on the base substrate 100 at least partially overlaps with the orthographic projection of the gate line 102 on the base substrate 100. For example, the orthographic projection of the first electrode portion d2 on the base substrate 100 and the orthographic projection of the gate line 102 on the base substrate 100 intersect with each other. Optionally, the first electrodes d of the two transistors 109 between the two data lines 111 are symmetrically arranged about the center O. Specifically, the first electrode portions d2 of the two transistors 109 between the two data lines 111 are collinearly arranged in the second direction Y and symmetrically arranged about the center O, and the widened portions d1 of the two transistors 109 between the two data lines 111 are symmetrically arranged about the center O. In this way, the parasitic capacitances between the gate line 102 and the first electrodes d of the two transistors 109 can be ensured to be approximately the same (for example, within an error range of ±5%), thereby improving the bad shaking head wrinkles.

[0112] 2 to 4 and 6, it can be seen that the second electrode s of the transistor 109 includes a connecting portion s1 extending along the first direction X and connected to the data line 111, and a second electrode portion s2 integrally provided with the connecting portion s1 and extending along the second direction Y; wherein, the orthographic projection of at least part of the connecting portion s1 on the substrate 100 overlaps with the orthographic projection of the gap between the two gate lines 102 on the substrate 100, for example, the orthographic projection of the connecting portion s1 on the substrate 101 is located within the orthographic projection of the gap between the two gate lines 102 on the substrate 101; the second electrode portion s2 is provided parallel to the first electrode portion d2 on the side close to the data line 111 connected thereto, and the orthographic projection of the second electrode portion s2 on the substrate 100 overlaps with the orthographic projection of the gap between the two gate lines 102 on the substrate 101. The orthographic projection of 102 on the base substrate 100 at least partially overlaps, for example, the orthographic projection of the second electrode portion s2 on the base substrate 100 intersects with the orthographic projection of the gate line 102 on the base substrate 100. Optionally, the second electrodes s of the two transistors 109 between the two data lines 111 are symmetrically arranged about the center O. Specifically, the second electrode portions s2 of the two transistors 109 between the two data lines 111 are symmetrically arranged about the center O, and the connecting portions s1 of the two transistors 109 between the two data lines 111 are symmetrically arranged about the center O. In this way, the parasitic capacitance between the gate line 102 and the second electrodes s of the two transistors 109 can be ensured to be approximately the same (for example, within an error range of ±5%), thereby improving the bad shaking head lines.

[0113] In some embodiments, as shown in Figures 2 to 5, the orthographic projection of the active layer a of the transistor 109 on the base substrate 100 is located within the orthographic projection of the gate line 102 on the base substrate 100, and the active layers a of the two transistors 109 between the two data lines 111 are symmetrically arranged about the center O. This ensures that the parasitic capacitance between the gate line 102 and the active layers a of the two transistors 109 is approximately the same (for example, within an error range of ±5%), thereby improving the bad shaking head ripple.

[0114] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in FIG4 , the gate line 102 includes a winding portion 1021, the winding portion 1021 is spaced apart from the protrusion 511, and the protrusion 511 includes a third boundary BL3 facing one side of the winding portion 1021, and the routing of the winding portion 1021 is the same as the third boundary BL3. Optionally, in combination with FIG4 and FIG5 , it can be seen that the routing of the connection portion s1 whose orthographic projection is located at the gap between the two gate lines 102 is also the same as the third boundary BL3 of the protrusion 511. By making way of this winding, the second via h2 overlapping with the protrusion 511 is made free. Compared with the scheme in which the gate line 102 is arranged in a straight line between the two protrusions 511, the space of the first gap GP1 can be effectively utilized, which is conducive to improving the pixel aperture ratio.

[0115] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, as shown in Figures 2 to 4 and 8, in order to ensure that the first sub-common electrode line 1031 is continuously arranged in the first gap GP1, the first sub-common electrode line 1031 may include a first portion 311, a second portion 312 and a third portion 313 that are sequentially connected; wherein the first portion 311 extends along the second direction Y, and the orthographic projection of the first portion 311 on the substrate substrate 100 at least partially overlaps with the orthographic projection of a gate line 102 on the substrate substrate 100; the second portion 312 extends along the first direction X, and the orthographic projection of at least part of the second portion 312 on the substrate substrate 100 overlaps with the gap between the two gate lines 102 on the substrate substrate 100. the orthographic projection of the third portion 313 on the substrate 100 overlaps with the orthographic projection of another gate line 102 on the substrate 100; the orthographic projection of the first portion 311 on the substrate 101 and the orthographic projection of the third portion 313 on the substrate 100 are separated on both sides of the orthographic projection of the gate g of the two transistors 109 on the substrate 100; in some embodiments, in the second direction Y, the structure consisting of the first portion 311, the second portion 312 and the third portion 313 of the two first sub-common electrode lines 1031 located on both sides of the same pixel electrode group PX can be symmetrically arranged about the center of the pixel electrode group PX.

[0116] In some embodiments, as shown in Figures 2 to 4, 6 and 8, the orthographic projection of the second portion 312 on the base substrate 100 overlaps with the orthographic projections of the two first electrodes d2, the two second electrodes s2, and the two connecting portions s1 on the base substrate 100, so that the line width of the second portion 312 in the second direction Y is larger, thereby effectively preventing the second portion 312 from being thin and broken.

[0117] In some embodiments, as shown in Figures 2 to 4 and 8, the first extension portion 1032 of the first common electrode line 103 is connected to the third portion 313, the first common electrode line 103 further includes a second extension portion 1033 connected to the first portion 311, and the first sub-common electrode line 1031 further includes a fourth portion 314 connected to the first portion 311 and a fifth portion 315 connected to the third portion, wherein the fourth portion 314 and the second extension portion 1033 are separated on both sides of the first portion 311 in the first direction X, and the fifth portion 315 is separated from the first extension portion 1033. 1032 are located on both sides of the third portion 313 in the first direction X. The orthographic projection of the first extension portion 1032 on the substrate 100 and the orthographic projection of the fifth portion 315 on the substrate 100 jointly cover the orthographic projection of the edge of a gate line 102 close to the pixel electrode 101 on the substrate 100. The orthographic projection of the second extension portion 1033 on the substrate 101 and the orthographic projection of the fourth portion 314 on the substrate 100 jointly cover the orthographic projection of the edge of another gate line 102 close to the pixel electrode 101 on the substrate 100. In this way, the first extension portion 1031, the second extension portion 1032, the fourth portion 314, and the fifth portion 315 can jointly shield the scanning signal of the gate line 102 from interfering with the data signal of the pixel electrode 101.

[0118] In some embodiments, as shown in Figures 3, 6 and 8, at the first gap GP1 between the two data lines 111, the first extension portion 1032 is located on the side of one of the connecting electrodes 110 close to the first portion 311, that is, the first extension portion 1032 does not cover the edge of the gate line 102 on the side of the connecting electrode 110 facing the gate line 102; the second extension portion 1033 is located on the side of the other connecting electrode 110 close to the third portion 313, that is, the second extension portion 1033 does not cover the edge of the gate line 102 on the side of the connecting electrode 110 facing the gate line 102. Although the first extension portion 1032 and the second extension portion 1033 are used to cover the edge of the gate line 102 on the side of the connecting electrode 110 facing the gate line 102, which can better shield the scanning signal of the gate line 102 from interfering with the data signal of the pixel electrode 101; however, because the first extension portion 1032 and the second extension portion 1033 are arranged on the same layer as the switching electrode 110, in order to avoid short circuit between the first extension portion 1032 and the second extension portion 1033 and the switching electrode 110, it is necessary to ensure that the spacing between the first extension portion 1032 and the second extension portion 1033 and the switching electrode 110 is greater than or equal to 5μm, which is not conducive to reducing the width of the first gap GP1 in the second direction Y, resulting in a loss in the pixel aperture ratio. Since most of the edge of the gate line 102 facing the pixel electrode 101 is covered by the fourth portion 314, the fifth portion 315, the first extension portion 1032 between the first portion 311 and the transfer electrode 110, and the second extension portion 1033 between the third portion 313 and the transfer electrode 110, the interference of the scanning signal of the gate line 102 on the data signal of the pixel electrode 101 can be effectively shielded. Therefore, in order to ensure transmittance, the first extension portion 1032 and the second extension portion 1033 are not extended to the side of the transfer electrode 110 facing the gate line 102 in the present disclosure.

[0119] In some embodiments, FIG13 mainly shows four pixel electrode groups 101 arranged in an array along a first direction X and a second direction Y in an array substrate, and a wiring scheme near these four pixels 101. FIG14 to FIG18 are schematic structural diagrams of each single film layer in FIG13. As can be seen from FIG13 to FIG18, in the array substrate provided by the embodiment of the present disclosure, in the first gap GP1 between two adjacent pixel electrode groups PX arranged in the second direction Y (equivalent to the first gap GP1 between two second gaps GP2 arranged in the first direction X), the two transistors 109 between the two data lines 111 are symmetrically arranged about the center O of the first gap GP1, and the widened portion d1 included in the first electrode d of the transistor 109 is on the substrate. The orthographic projection on the substrate 100 is located in the orthographic projection of the gap between the two gate lines 102 on the base substrate 100, the orthographic projection of the connecting portion s1 contained in the second electrode s of the transistor 109 on the base substrate 100 is located in the gap between the gate line 102 and the third common electrode line 112 on the base substrate 100, the connecting electrode 110 is led out from the corner position of the pixel electrode 101 close to the center O, and the orthographic projection of the connecting electrode 110 on the base substrate 100 spans the orthographic projection of one gate line 102 on the base substrate 100 and extends to the gap between the two gate lines 102 on the base substrate 100, so that the connecting electrode 110 can be electrically connected to the widened portion s1 at the gap between the two gate lines 102 through the second via h2.

[0120] In some embodiments, referring to Figures 13 to 18 , it can be seen that within the same first gap GP1 between two adjacent data lines 111, in order to ensure that the first sub-common electrode line 1031 is continuously arranged, a portion of the orthographic projection of the first sub-common electrode line 1031 on the base substrate 100 can be located between the orthographic projections of the widened portions d1 of the two transistors 109 on the base substrate 100. At the same time, in order to avoid short-circuiting the first sub-common electrode line 1031 and the connecting electrode 110, the orthographic projection of the remaining portion of the first sub-common electrode line 1031 on the base substrate 100 can be disconnected at the orthographic projection of the connecting electrode 110 on the base substrate 100.

[0121] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, as shown in Figures 13, 14 and 18, within the same first gap GP1 between two adjacent data lines 111, restricted by the two connecting electrodes 110, the continuously arranged first sub-common electrode line 1031 can include a first portion 311, a second portion 312 and a third portion 313 that are sequentially connected; wherein the orthographic projection of the first portion 311 on the base substrate 100 at least partially overlaps with the orthographic projection of a gate line 102 on the base substrate 100, and the orthographic projection of the first portion 311 on the base substrate 100 is parallel to a partial orthographic projection of a connecting electrode 110 on the base substrate 100; the second portion 312 extends along the second direction Y, and the orthographic projection of the second portion 312 on the base substrate 100 is located at the widened portion of the two transistors 109. d1 is between the orthographic projections on the base substrate 100; the orthographic projection of the third portion 313 on the base substrate 100 at least partially overlaps with the orthographic projection of another gate line 102 on the base substrate 100, and the orthographic projection of the third portion 313 on the base substrate 100 is parallel to a partial orthographic projection of another connecting electrode 110 on the base substrate 100; the orthographic projection of the first portion 311 on the base substrate 100 and the orthographic projection of the third portion 313 on the base substrate 100 are located between the orthographic projections of the two connecting electrodes 110 on the base substrate 100; in some embodiments, in the second direction Y, the structure consisting of the first portion 311, the second portion 312 and the third portion 313 of the two first sub-common electrode lines 1031 located on both sides of the same pixel electrode group PX can be symmetrically arranged about the center of the pixel electrode group PX.

[0122] In some embodiments, in order to effectively shield the interference of the scanning signal of the gate line 102 on the data signal of the pixel electrode 101, as shown in Figures 13, 14 and 18, each first sub-common electrode line 1031 can be set to include a fourth portion 314 and a fifth portion 315, wherein the orthographic projection of the fourth portion 314 on the base substrate 100 covers the orthographic projection of the edge of one gate line 102 close to the pixel electrode 101 on the base substrate 100, and the orthographic projection of the fifth portion 315 on the base substrate 100 covers the orthographic projection of the edge of another gate line 102 close to the pixel electrode 101 on the base substrate 100. The edge of 101 is partially orthographically projected on the base substrate 100, and the fourth portion 314 and the fifth portion 315 correspond to sub-pixels of adjacent pixel columns; optionally, when the first sub-common electrode line 1031 includes the first portion 311, the second portion 312, the third portion 313, the fourth portion 314 and the fifth portion 315 at the same time, the fourth portion 314 is located on the side of the first portion 311 away from the second portion 312 in the first direction X, and the fifth portion 315 is located on the side of the third portion 313 away from the second portion 312 in the first direction X.

[0123] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, as shown in Figures 2, 4, 8, 13, 14 and 18, in the multiple common electrode repeating units 1051 contained in the second common electrode line 105 on the same layer as the multiple gate lines 102, each common electrode repeating unit 1051 can be arranged corresponding to a pixel electrode group PX. Optionally, the common electrode repeating unit 1051 includes a second sub-common electrode line 512 extending along the second direction Y, and the orthographic projection of the second sub-common electrode line 512 on the base substrate 101 covers the orthographic projection of the adjacent edges of the two pixel electrodes 101 in the pixel electrode group PX on the base substrate 100. Since the present disclosure does not set a DBS between the two pixel electrodes 101 in the pixel electrode group PX ITO, so the second gap GP2 between the two pixel electrodes 101 can be reduced. In order to ensure that the second sub-common electrode line 512 and the two pixel electrodes 101 form a storage capacitor while improving the pixel aperture ratio, the line width w1 of the second sub-common electrode line 512 in the first direction X can be set to be greater than or equal to 7μm and less than or equal to 15μm, for example, 10μm.

[0124] In some embodiments, referring again to Figures 2, 4, 8, 13, 14, and 18, the common electrode repeating unit 1051 may further include a third sub-common electrode line 513 extending along the second direction Y. The orthographic projection of the third sub-common electrode line 513 on the base substrate 100 overlaps the orthographic projections of the opposite edges of two pixel electrodes 101 in the pixel electrode group PX on the base substrate 100. The dimension l2 of the third sub-common electrode line 513 in the second direction Y is less than or equal to the dimension l1 of the second sub-common electrode line 512 in the second direction Y. For example, in Figure 4, the dimension l2 of the third sub-common electrode line 513 in the second direction Y is equal to the dimension l1 of the second sub-common electrode line 512 in the second direction Y; and in Figure 14, the dimension l2 of the third sub-common electrode line 513 in the second direction Y is less than the dimension l1 of the second sub-common electrode line 512 in the second direction Y.

[0125] As can be seen from FIG. 4 , at a position adjacent to the second sub-common electrode line 512 , the gate line 102 includes a straight portion 1022 extending along the first direction X, and the wiring method is relatively simple. In addition, it can be seen from Figure 14 that at the position adjacent to the second sub-common electrode line 512: in order to avoid the second sub-common electrode line 512, the gate line 102 includes a fold line portion 1023 that protrudes in the direction away from the second sub-common electrode line 512; since in the solution where DBS ITO is provided between the two pixel electrodes 101 of the pixel electrode group PX, in order to achieve a better light shielding effect, the dimension l2 of the third sub-common electrode line 513 in the second direction Y is set to be smaller than the dimension l1 of the second sub-common electrode line 512 in the second direction Y. Although the present disclosure removes the DBS ITO between the two pixel electrodes 101 of the pixel electrode group PX, it can still keep the dimension l2 of the third sub-common electrode line 513 in the second direction Y smaller than the dimension l1 of the second sub-common electrode line 512 in the second direction Y, so as to continue to use the mask plate of the layer where the second common electrode line 105 is located (that is, the layer where the gate line 102 is located), thereby reducing costs.

[0126] In addition, it should be understood that since the second sub-common electrode line 512 overlaps with the edges of the two pixel electrodes 101 and the second gap GP2 between the two pixel electrodes 101 in a direction perpendicular to the base substrate 100, and the third sub-common electrode line 513 overlaps with the edge of one pixel electrode 101 in a direction perpendicular to the base substrate 100, the dimension w1 of the second sub-common electrode line 512 in the first direction X is greater than the dimension w2 of the third sub-common electrode line 513 in the second direction X.

[0127] In some embodiments, as shown in Figures 2, 4, 8, 13, 14 and 18, in order to increase the storage capacitance between the second common electrode line 105 and the pixel electrode 101, the common electrode repeating unit 1051 of the second common electrode line 105 can be set to further include a sub-common electrode connecting line 514 extending along the first direction X, the sub-common electrode connecting line 514 is connected between the ends on the same side of the second sub-common electrode line 512 and the third sub-common electrode line 513, and the sub-common electrode connecting line 514 and an edge of the pixel electrode 101 extending along the first direction X overlap with each other in a direction perpendicular to the base substrate 100. Optionally, in Figure 4, for the area where the same pixel electrode 101 is located, the sub-common electrode connecting line 514 and the protrusion 511 are opposite to each other in the first direction X, that is, the protrusion 511 is connected between the other end portions on the same side of the second sub-common electrode line 512 and the third sub-common electrode line 513; in Figure 14, the sub-common electrode connecting line 514 is connected between the two end portions on the same side of the second sub-common electrode line 512 and the third sub-common electrode line 513.

[0128] In some embodiments, as shown in Figures 8 and 18, the second common electrode line 105 may further include a plurality of common electrode connection lines 1052, which are connected to adjacent common electrode repeating units 1051 arranged along the first direction X to improve the uniformity of the common voltage signal. Optionally, the common electrode connection lines 1052 may be connected to at least one of the two ends and the middle portion of the common electrode repeating unit 1051 in the second direction Y. For example, in Figure 8, the common electrode connection line 1052 is connected to the end of the common electrode repeating unit 1051 having the protrusion 511 in the second direction Y; in Figure 18, the common electrode connection line 1052 is connected to the middle portion of the common electrode repeating unit 1051. In the case where the common electrode connection line 1052 is connected to the end of the common electrode repeating unit 1051 as shown in FIG8 , the common voltage signal can be directly transmitted between adjacent common electrode repeating units 1051 through the common electrode connection line 105; however, in the case where the common electrode connection line 1052 is connected to the middle portion of the common electrode repeating unit 1051 as shown in FIG18 , the common voltage signal must pass through the common electrode connection line 105, as well as a portion of the third sub-common electrode line 513 on the left side of the common electrode repeating unit 1051, the fourth sub-common electrode line 514, and a portion of the third sub-common electrode line 513 on the right side of the common electrode repeating unit 1051, before being transmitted to the adjacent common electrode repeating unit 1051. This longer signal transmission path causes a certain voltage drop in the common voltage signal. Based on this, in some embodiments, it is preferable to dispose the common electrode connection line 1052 at the end of the common electrode repeating unit 1051.

[0129] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, as shown in Figures 14, 15 and 17, a third common electrode line 112 extending along the first direction X can also be provided at the first gap GP1. The third common electrode line 112 is provided in the same layer as the gate line 102. The third common electrode line 112 is located between the two gate lines 102, and the orthographic projection of the third common electrode line 112 on the base substrate 100 overlaps with the orthographic projection of the connection position of the connecting electrode 110 and the widened portion d1 (for example, the first via hole h1) on the base substrate 100. When the pixel electrode 101 is abnormally bright, the widened portion d1 can be connected to the third common electrode line 112 at the connection position of the connecting electrode 110 and the widened portion d1 (for example, the first via hole h1) to achieve pixel darkening. The conductive via hole can be located within the positive projection of the gap between the two gate lines 20 on the base substrate 100. Since a black matrix is ​​usually set at the first gap GP1 where the two gate lines 20 and the gap between the two gate lines 20 are located, the present disclosure can achieve hiding the darkened via hole in the area where the light shielding layer is located without affecting the transmittance.

[0130] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 2, 6, 8, 13, 16 and 18, the orthographic projection of the data line 111 on the base substrate 100 is located within the orthographic projection of the second gap GP2 between adjacent pixel electrode groups PX on the base substrate 101; the first common electrode line 103 also includes a fourth sub-common electrode line 1034 extending along the second direction Y, and the orthographic projection of the fourth sub-common electrode line 1034 on the base substrate 100 at least partially covers the orthographic projection of the data line 111 on the base substrate 100, so as to utilize the fourth sub-common electrode line 1034 to shield the data signal of the data line 111 from interfering with the data signal of the pixel electrode 102 adjacent to it and not connected to it.

[0131] It should be understood that the presence of the fourth sub-common electrode line 1034 will cause the width of the second gap GP2 between the pixel electrode groups PX to be greater than or equal to the width of the second gap GP2 between the two pixel electrodes 101 within the pixel electrode group PX; optionally, in order to improve the transmittance, the present disclosure sets the width of the second gap GP2 between the pixel electrode groups PX to be greater than the width of the second gap GP2 between the two pixel electrodes 101 within the pixel electrode group PX.

[0132] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the pixel electrode 101 may be a plate-shaped electrode or a slit electrode. Alternatively, the slit electrode may be a horizontal domain pixel electrode as shown in FIG19 , or a cross-shaped pixel electrode as shown in FIG20 , or a slit electrode of other shapes known to those skilled in the art, which is not specifically limited in the present disclosure.

[0133] Based on the same inventive concept, an embodiment of the present disclosure provides a display panel, as shown in Figures 21 and 22, including an array substrate 001 and an opposing substrate 002 arranged opposite to each other, wherein the array substrate 001 is the above-mentioned array substrate 001 provided in the embodiment of the present disclosure, and the opposing substrate 002 includes a black matrix 202 and a common electrode layer 201 located on the side of the black matrix 202 facing the array substrate 001. Optionally, the common electrode layer 201 provided on the opposing substrate is provided on the entire surface within the display area AA, and the orthographic projection of the black matrix 202 on the base substrate 100 overlaps with the orthographic projection of the first gap GP1 on the base substrate 100, so as to connect the gate line 1 at the first gap GP1. 02, the first sub-common electrode line 1031, the first extension 1032, and the second extension 1033 are hidden within the black matrix 202 area, so that the black matrix 202 is used to block light at the first gap GP1. Optionally, the orthographic projection of the black matrix 202 on the base substrate 100 and the orthographic projection of the second gap GP2 on the base substrate 100 that does not overlap with the first gap GP1 do not overlap. The fourth sub-common electrode line 1034 can be used to block light at the second gap GP2 that does not overlap with the first gap GP1. The black matrix 202 and the fourth sub-common electrode line 1034 are used simultaneously to block light at the intersection of the first gap GP1 and the second gap GP2. In some embodiments, the common electrode layer 201 can also be provided on the array substrate 001, which is not limited here. This disclosure uses the example of the common electrode layer 201 being located on the counter substrate 002.

[0134] In some embodiments, the display panel provided by the embodiments of the present disclosure may be a curved display panel. The display panel may further include a liquid crystal layer between an array substrate and an opposing substrate, a first polarizer on a side of the array substrate facing away from the opposing substrate, and a second polarizer on a side of the opposing substrate facing away from the array substrate, wherein the polarization direction of the first polarizer is perpendicular to the polarization direction of the second polarizer. Other essential components of the display panel are readily understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure.

[0135] Based on the same inventive concept, an embodiment of the present disclosure provides a display device, comprising the above-mentioned display panel provided by the embodiment of the present disclosure, and a backlight module located on the light incident side of the display panel. The backlight module can be a direct-type backlight module or an edge-entry backlight module. Optionally, the edge-entry backlight module may include a light bar, a stacked reflective sheet, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightening film stacked on the light emitting side of the matrix light source, and the reflective sheet includes an opening arranged opposite to the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source may be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.).

[0136] Submillimeter or even micron-scale micro-LEDs are self-luminous devices, just like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because inorganic light-emitting diodes emit light based on metal semiconductors with more stable properties and lower resistance, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life compared to organic light-emitting diodes that emit light based on organic matter. And when micro-LEDs are used as backlight sources, more precise dynamic backlight effects can be achieved. While effectively improving screen brightness and contrast, they can also solve the glare phenomenon caused by traditional dynamic backlighting between bright and dark areas of the screen, thereby optimizing the visual experience.

[0137] In some embodiments, the above-mentioned display device provided in the embodiments of the present disclosure may be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function. Optionally, the display device provided in the present disclosure includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip. Optionally, the control chip is a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may further include a memory, a power module, etc., and realize power supply and signal input and output functions through additionally provided wires, signal lines, etc. For example, the control chip may further include hardware circuits and computer executable code, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc. In addition, those skilled in the art will understand that the above structure does not constitute a limitation on the above display device provided in the embodiment of the present disclosure. In other words, the above display device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.

[0138] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0139] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: substrate; a plurality of pixel electrodes arranged in an array on the base substrate, with a first gap extending along a first direction and a second gap extending along a second direction between the pixel electrodes, every two pixel electrodes arranged in the first direction constitute a pixel electrode group, and the second direction intersects the first direction; a plurality of gate lines extending along the first direction and arranged along the second direction on the base substrate, wherein the orthographic projections of the gate lines on the base substrate at least partially overlap with the orthographic projections of the first gaps on the base substrate, and two gate lines are located in the same first gap; A first common electrode line, the orthographic projection of the first common electrode line on the base substrate is located within the first gap and the orthographic projection of the second gap between the pixel electrode groups on the base substrate; and at the first gap that does not overlap with the second gap, the orthographic projection of the first common electrode line on the base substrate passes through the orthographic projection of the gap between the two gate lines on the base substrate along the second direction.

2. The array substrate according to claim 1, wherein: The first common electrode line includes a plurality of first sub-common electrode lines located at the first gap, and at least some of the orthographic projections of the first sub-common electrode lines on the base substrate pass through the orthographic projections of the gaps between two gate lines on the base substrate along the second direction.

3. The array substrate according to claim 2, wherein: It also includes a color resist layer located between the layer where the gate line is located and the layer where the pixel electrode is located, and the color resist layer includes an opening located at the first gap; The first common electrode line further includes a first extension portion adjacent to the pixel electrode in the first gap and connected to the first sub-common electrode line, the first extension portion including a first boundary adjacent to the pixel electrode and extending along the first direction, an orthographic projection of a portion of the first boundary on the base substrate being located within an orthographic projection of the opening on the base substrate; The pixel electrode includes a second boundary adjacent to the first extension portion and extending along the first direction, and an orthographic projection of the second boundary on the base substrate is located outside an orthographic projection of the opening on the base substrate.

4. The array substrate according to claim 3, wherein: The opening includes a fourth boundary located between the first boundary and the second boundary, a distance between the first boundary and the fourth boundary in the second direction is greater than or equal to 4 μm, and a distance between the second boundary and the fourth boundary in the second direction is greater than or equal to 4 μm.

5. The array substrate according to claim 3, wherein: It also includes a second common electrode line, and a first insulating layer located between a layer where the second common electrode line is located and a layer where the pixel electrode is located, wherein the first insulating layer includes the color resist layer; The second common electrode line includes a plurality of common electrode repeating units, each of which includes a protruding portion, which is electrically connected to the first extension portion through a first via hole penetrating the first insulating layer, and the orthographic projection of the first via hole on the base substrate is located within the orthographic projection of the opening on the base substrate.

6. The array substrate according to claim 5, wherein: The gate line includes a winding portion, the winding portion is spaced apart from the protruding portion, and the protruding portion includes a third boundary facing one side of the winding portion. The routing of the winding portion is the same as the direction of the third boundary.

7. The array substrate according to claim 5 or 6, wherein: Part of the orthographic projection of the first via on the base substrate is located within the orthographic projection of the protrusion on the base substrate, and the remaining orthographic projection is located on the side of the orthographic projection of the protrusion on the base substrate facing the orthographic projection of the gate line on the base substrate.

8. The array substrate according to any one of claims 5 to 7, wherein: It also includes a plurality of transistors, and a second insulating layer located between a layer where the transistors are located and a layer where the pixel electrodes are located, wherein the second insulating layer includes the color resist layer, and the first insulating layer includes the second insulating layer; The first electrode of the transistor is electrically connected to the pixel electrode through a second via hole penetrating the second insulating layer, and the orthographic projection of the second via hole on the base substrate is located within the orthographic projection of the opening on the base substrate; The orthographic projections of at least part of the second via holes and at least part of the first via holes on the base substrate are located within the orthographic projection of the same opening on the base substrate.

9. The array substrate according to claim 8, wherein: The first electrode of the transistor includes a widened portion extending along the first direction, the widened portion is electrically connected to the pixel electrode through the second via hole, and the orthographic projection of the widened portion on the base substrate is located on a side where the orthographic projections of the two gate lines on the base substrate are close to the orthographic projection of the pixel electrode on the base substrate.

10. The array substrate according to claim 9, wherein: It also includes a plurality of connecting electrodes, which are integrally arranged with the pixel electrode at the first gap, and are electrically connected to the widened portion through the second via hole, and the orthographic projection of the connecting electrode on the base substrate at least partially overlaps with the orthographic projection of the widened portion on the base substrate.

11. The array substrate according to claim 10, wherein: The two connecting electrodes connected to the same pixel electrode group are separated at the first gaps arranged along the second direction on both sides of the pixel electrode group, and the two connecting electrodes at the same first gap are staggered in the second direction.

12. The array substrate according to claim 11, wherein: In the first gap between two adjacent pixel electrode groups arranged in the second direction, two adjacent transistors are symmetrically arranged about the center of the first gap, and at least part of the transistors overlap with the first gap between two pixel electrodes included in one pixel electrode group along the second direction.

13. The array substrate according to any one of claims 8 to 12, wherein: The second electrode of the transistor includes a connecting portion extending along the first direction, and at least a portion of the connecting portion has an orthographic projection on the substrate overlapping with the orthographic projection of the gap between the two gate lines on the substrate, and the routing of the connecting portion is the same as the direction of the third boundary of the protrusion toward the side of the gate line.

14. The array substrate according to any one of claims 8 to 13, wherein: The base substrate includes a plurality of red sub-pixel regions, a plurality of green sub-pixel regions, and a plurality of blue sub-pixel regions, and the plurality of pixel electrodes are located in the plurality of red sub-pixel regions, the plurality of green sub-pixel regions, and the plurality of blue sub-pixel regions; The second via hole corresponding to the pixel electrode of the blue sub-pixel area is located on the substrate The orthographic projection of the opening on the substrate and the orthographic projection of the first via hole on the substrate are located within the orthographic projection of the same opening on the substrate.

15. The array substrate according to any one of claims 8 to 14, wherein: The first sub-common electrode line includes a first portion, a second portion and a third portion that are sequentially connected; wherein, The first portion extends along the second direction, and an orthographic projection of the first portion on the base substrate at least partially overlaps with an orthographic projection of one of the gate lines on the base substrate; The second portion extends along the first direction, and an orthographic projection of at least a portion of the second portion on the base substrate overlaps with an orthographic projection of a gap between two gate lines on the base substrate; The third portion extends along the second direction, and an orthographic projection of the third portion on the base substrate at least partially overlaps with an orthographic projection of another gate line on the base substrate; The orthographic projection of the first portion on the substrate and the orthographic projection of the third portion on the substrate are located on both sides of the orthographic projection of the gates of the two transistors on the substrate.

16. The array substrate according to claim 15, wherein: The first extension portion is connected to the third portion, and an orthographic projection of the first extension portion on the base substrate covers an orthographic projection of a portion of an edge of the gate line close to the pixel electrode on the base substrate.

17. The array substrate according to claim 16, wherein: The first common electrode line further includes a second extending portion connected to the first portion, and an orthographic projection of the second extending portion on the base substrate covers an orthographic projection of a portion of an edge of the gate line close to the pixel electrode on the base substrate.

18. The array substrate according to claim 2, wherein: The device further comprises a plurality of transistors, wherein a first electrode of the transistor comprises a widened portion extending along the first direction, the widened portion is electrically connected to the pixel electrode, and an orthographic projection of the widened portion on the base substrate is located within an orthographic projection of a gap between two gate lines on the base substrate; Part of the orthographic projection of a portion of the first sub-common electrode line on the base substrate is located between the orthographic projections of the widened portions of the two transistors on the base substrate.

19. The array substrate according to claim 18, wherein: The device further comprises a plurality of connecting electrodes, wherein the connecting electrodes are integrally provided with the pixel electrodes, the connecting electrodes are electrically connected to the widened portion, and the orthographic projections of the connecting electrodes on the base substrate span the orthographic projection of one gate line on the base substrate and extend to the orthographic projection of a gap between two gate lines on the base substrate; The orthographic projection of the remaining first sub-common electrode lines on the base substrate is disconnected at the connecting electrode.

20. The array substrate according to claim 19, wherein: It also includes a third common electrode line extending along the first direction at the first gap, the third common electrode line is arranged in the same layer as the gate line, the third common electrode line is located between two of the gate lines, and the orthographic projection of the third common electrode line on the base substrate overlaps with the orthographic projection of the connection position of the connecting electrode and the widened portion on the base substrate.

21. The array substrate according to claim 19 or 20, wherein: Part of the first sub-common electrode line includes a first portion, a second portion and a third portion that are sequentially connected; wherein, The orthographic projection of the first portion on the base substrate at least partially overlaps with the orthographic projection of one of the gate lines on the base substrate, and the orthographic projection of the first portion on the base substrate is parallel to a partial orthographic projection of one of the connecting electrodes on the base substrate; The second portion extends along the second direction, and an orthographic projection of the second portion on the substrate is located between orthographic projections of the widened portions of the two transistors on the substrate; The orthographic projection of the third portion on the base substrate at least partially overlaps with the orthographic projection of another gate line on the base substrate, and the orthographic projection of the third portion on the base substrate is parallel to a partial orthographic projection of another connecting electrode on the base substrate; The orthographic projection of the first portion on the base substrate and the orthographic projection of the third portion on the base substrate are located between the orthographic projections of the two connecting electrodes on the base substrate.

22. The array substrate according to any one of claims 2 to 21, wherein: The first sub-common electrode line includes a fourth portion and a fifth portion, the orthographic projection of the fourth portion on the base substrate covers a partial orthographic projection of an edge of the gate line close to the pixel electrode on the base substrate, and the orthographic projection of the fifth portion on the base substrate covers a partial orthographic projection of an edge of another gate line close to the pixel electrode on the base substrate.

23. The array substrate according to any one of claims 1 to 22, wherein: It also includes a second common electrode line on the same layer as the multiple gate lines, the second common electrode line includes a plurality of common electrode repeating units, the common electrode repeating unit includes a second sub-common electrode line extending along the second direction, the orthographic projection of the second sub-common electrode line on the base substrate covers the orthographic projection of adjacent edges of two pixel electrodes in the pixel electrode group on the base substrate, and the line width of the second sub-common electrode line in the first direction is greater than or equal to 7μm and less than or equal to 15μm.

24. The array substrate according to claim 23, wherein: The common electrode repetition unit also includes a third sub-common electrode line extending along the second direction, the orthographic projection of the third sub-common electrode line on the base substrate covers the orthographic projection of the opposite edges of two pixel electrodes in the pixel electrode group on the base substrate, and the size of the third sub-common electrode line in the second direction is less than or equal to the size of the second sub-common electrode line in the second direction.

25. The array substrate according to claim 23, wherein: At a position adjacent to the second sub-common electrode line: the gate line includes a folded line portion protruding in a direction away from the second sub-common electrode line, or the gate line includes a straight line portion extending along the first direction.

26. The array substrate according to any one of claims 23 to 25, wherein: The second common electrode lines further include a plurality of common electrode connecting lines, and the plurality of common electrode connecting lines are connected to adjacent common electrode repeating units arranged along the first direction.

27. The array substrate according to claim 26, wherein: The common electrode connection line is connected to at least one of the two end portions and the middle portion of the common electrode repeating unit in the second direction.

28. The array substrate according to any one of claims 1 to 27, wherein: Also comprising a plurality of data lines extending along the second direction and arranged along the first direction, wherein the orthographic projections of the data lines on the base substrate are located within the orthographic projections of the second gaps between adjacent pixel electrode groups on the base substrate; The first common electrode line further includes a fourth sub-common electrode line extending along the second direction, and an orthographic projection of the fourth sub-common electrode line on the base substrate at least partially covers an orthographic projection of the data line on the base substrate.

29. The array substrate according to any one of claims 1 to 28, wherein: The pixel electrode is a plate electrode or a slit electrode.

30. A display panel, wherein: The invention comprises an array substrate and an opposite substrate which are opposite to each other, wherein the array substrate is the array substrate according to any one of claims 1 to 29.

31. The display panel according to claim 30, wherein: The opposite substrate includes a common electrode layer.

32. The display panel according to claim 30 or 31, wherein: The opposite substrate further includes a black matrix, and the common electrode layer is located on a side of the black matrix facing the array substrate; The orthographic projection of the black matrix on the base substrate overlaps with the orthographic projection of the first gap on the base substrate, and the orthographic projection of the black matrix on the base substrate and the orthographic projection of the second gap on the base substrate that does not overlap with the first gap do not overlap with each other.

33. A display device, wherein: Comprising the display panel according to any one of claims 30 to 32.

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