Method for preparing back contact cell by means of one-shot annealing

Abstract

The present disclosure belongs to the technical field of the preparation of back contact cells, and particularly relates to a method for preparing a back contact cell by means of one-shot annealing. The method comprises the following steps: S1, providing a silicon wafer with both surfaces thereof polished; S2, sequentially depositing a first semiconductor layer and a first mask layer on the back surface of the silicon wafer by using a tubular polycrystalline silicon deposition furnace, wherein annealing is not performed in this step; S3, subjecting the back surface to first etching for opening formation, so as to form a second semiconductor opening region; S4, sequentially depositing a second semiconductor layer and a second mask layer on the back surface by using the tubular polycrystalline silicon deposition furnace, wherein annealing is not performed in this step; S5, then performing high-temperature annealing; S6, removing a wrap-around coating on the front surface of the silicon wafer obtained in step S5 by using a laser; and S7, texturing and cleaning the front surface of the silicon wafer, and removing the second mask layer on the back surface. The present disclosure greatly simplifies the process flow, and reduces the amount of plate-type PECVD equipment; therefore, the cost of investment in equipment is greatly reduced, the product yield can also be increased, and the conversion efficiency of a battery can be improved.

Description

One-time annealing preparation method for back contact battery

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to application number CN202311765641.1, filed with the Patent Office of China on December 21, 2023, entitled “A single annealing preparation method for a back-contact battery,” the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0003] The present disclosure belongs to the technical field of back contact battery preparation, and particularly relates to a single annealing preparation method for a back contact battery. Background Art

[0004] At present, the process flow of back contact cells is generally as follows: S101, providing a silicon wafer with a single-sided texturing and single-sided polishing structure. During texturing on one side, a protective mask layer needs to be formed in advance on the other side, and the protective mask layer is removed after texturing; S102, sequentially coating a first semiconductor layer and a first mask layer on the back of the silicon wafer. The first semiconductor layer is formed by PECVD or Hot-wire method. The first semiconductor layer includes an intrinsic amorphous or microcrystalline silicon layer and an N-type doped amorphous or microcrystalline silicon layer; S103, opening an opening on the back of the silicon wafer by laser or mask etching, removing the first mask layer and part of the first semiconductor layer to form a second semiconductor opening area. The mask etching method requires an additional protective mask layer to be set and removed after the opening; S104, cleaning the silicon wafer, removing the first half of the first semiconductor layer in the second semiconductor opening area Conductor layer; S105, forming a second semiconductor layer on the back of the silicon wafer, the second semiconductor layer is formed by PECVD or Hot-wire method, the second semiconductor layer includes an intrinsic amorphous or microcrystalline silicon layer and a P-type doped amorphous or microcrystalline silicon layer; S106, forming a third semiconductor layer on the front, the third semiconductor layer includes a front passivation layer and an anti-reflection layer; S107, opening the back of the silicon wafer to form a first semiconductor opening area arranged alternately with the second semiconductor opening area; S108, cleaning the silicon wafer to remove the first mask layer in the first semiconductor opening area; S109, depositing a conductive film on the back of the silicon wafer; S110, forming an insulating groove between the first semiconductor opening area and the second semiconductor opening area by laser or etching; S111, forming metal electrodes on the first semiconductor opening area and the second semiconductor opening area of ​​the silicon wafer.

[0005] As can be seen from the above, back-contact batteries generally require the preparation of silicon wafers with polished back sides and textured front sides. The preparation process is relatively long, and the first semiconductor layer and the second semiconductor layer on the back side are respectively an intrinsic amorphous silicon layer and an N-type doped amorphous / microcrystalline silicon stack, and an intrinsic amorphous silicon layer and a P-type doped amorphous / microcrystalline silicon stack. The intrinsic amorphous silicon layer and the doped amorphous / microcrystalline silicon layer are generally formed separately by plate-type PECVD coating. Plate-type PECVD equipment is very expensive. If tube-type PECVD coating is used, it is necessary to anneal after in-situ doping deposition. At the same time, the mask layer needs to be deposited and removed multiple times during the production process, resulting in a cumbersome process and a low yield. Therefore, the current back-contact batteries have problems such as long process flow and high equipment investment.

[0006] It should be noted that this part of the present disclosure only provides background technology related to the present disclosure and does not necessarily constitute prior art or public known technology.

[0007] Summary of the Invention

[0008] The purpose of the present disclosure is to overcome the defects of the prior art in the back-contact battery, such as the long process flow, low yield and high equipment investment, and to provide a one-time annealing preparation method for the back-contact battery. The one-time annealing preparation method greatly simplifies the process flow, reduces the equipment usage of plate-type PECVD, thereby significantly reducing the equipment investment cost, while being able to improve product yield and enhance battery conversion efficiency.

[0009] To achieve the above objectives, the present disclosure provides a single-annealing method for preparing a back-contact cell, comprising the following steps:

[0010] S1, provide double-sided polished silicon wafers;

[0011] S2. Using a tubular polysilicon deposition furnace, sequentially deposit a first semiconductor layer and a first mask layer on the back side of the silicon wafer. The first semiconductor layer includes a first tunneling silicon oxide layer and a first doped polysilicon layer. Annealing is not performed in this step.

[0012] S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region;

[0013] S4. Using a tubular polysilicon deposition furnace, sequentially deposit a second semiconductor layer and a second mask layer on the back surface of the film obtained in S3, wherein the second semiconductor layer comprises a second tunneling silicon oxide layer and a second doped polysilicon layer. No annealing is performed in this step. The ratio of the surface doping index of the first doped polysilicon layer to the second doped polysilicon layer is 3-115:1, where the surface doping index is the ratio of the effective doping concentration of the corresponding doped polysilicon layer to the thickness of the doped polysilicon layer.

[0014] S5, then high temperature annealing is performed;

[0015] S6, using laser to remove the wrap-around coating on the front side of the silicon wafer obtained in S5;

[0016] S7. Perform texturing and cleaning on the front side of the silicon wafer obtained in S6, and remove the second mask layer on the back side.

[0017] In some preferred embodiments of the present disclosure, the ratio of the effective doping concentration of the first doped polysilicon layer to the second doped polysilicon layer is 1-100:1, preferably 10-70:1, and the ratio of the thickness of the first doped polysilicon layer to the second doped polysilicon layer is 0.5-3:1, preferably 0.8-3:1, and further preferably 1-3:1.

[0018] In some preferred embodiments of the present disclosure, the effective doping concentration of the first doped polysilicon layer is 1×10 20 cm -3 -1×10 22 cm -3 The effective doping concentration of the second doped polysilicon layer is 1×10 19 cm -3 -1×10 20 cm -3 .

[0019] In some preferred embodiments of the present disclosure, the thickness of the first doped polysilicon layer is 40-120 nm, preferably 70-120 nm, and the thickness of the second doped polysilicon layer is 40-80 nm.

[0020] In some preferred embodiments of the present disclosure, the thickness of the first tunneling silicon oxide layer is 1-2 nm, and the thickness of the second tunneling silicon oxide layer is 1-3 nm.

[0021] In some preferred embodiments of the present disclosure, the thickness of the first mask layer and the second mask layer are independently 40-90 nm.

[0022] In some preferred embodiments of the present disclosure, the deposition temperatures in S2 and S4 are both 400-500°C, and the conditions for high-temperature annealing in S5 include: being carried out in the presence of a protective gas, an annealing temperature of 850-950°C, and a pressure of 1000-25000Pa, preferably 1000-10000Pa.

[0023] In some preferred embodiments of the present disclosure, the high temperature annealing conditions in S5 further include: a mass flow rate of the protective gas of 5000-15000 sccm, and an annealing time of 40-60 min.

[0024] In some more preferred embodiments of the present disclosure, the high temperature annealing in S5 is a multi-stage annealing and the process includes: constant temperature annealing at a first temperature, then heating to a second temperature for constant temperature annealing, and then continuing to heat to a third temperature for constant temperature annealing, wherein the adjacent temperature difference between the first temperature and the second temperature and the adjacent temperature difference between the second temperature and the third temperature are each independently 20-30°C and each temperature is within 850-950°C, and the annealing time for each stage is 10-20min.

[0025] In some more preferred embodiments of the present disclosure, in S2 and S4, the conditions for depositing the first tunneling silicon oxide layer and the second tunneling silicon oxide layer independently include: controlling the mass flow rate of the introduced nitrous oxide to 8000-12000sccm, the pressure to 100-200Pa, the power supply to 3-20kW, and the time to 20-100s; the conditions for depositing the first doped polysilicon layer and the second doped polysilicon layer independently include: controlling the mass flow rate of the introduced silane to 1000-3000sccm, the mass flow rate of hydrogen to 7000-9000sccm, and introducing a mixed gas of hydrogen carrying the doping element gas source, and controlling the power supply to 5-20kW, and the deposition time to 800-1300s.

[0026] Preferably, when the doping element gas source is a phosphorus source, the mass flow rate of the mixed gas is 1000-2500 sccm, and the pressure is controlled to be 400-500 Pa; when the doping element gas source is a boron source, the mass flow rate of the mixed gas is 2000-4000 sccm, and the pressure is controlled to be 200-800 Pa.

[0027] In some preferred embodiments of the present disclosure, the conditions for depositing the first mask layer and the second mask layer independently include: controlling the mass flow rate of the introduced silane to be 1000-2000 sccm, the mass flow rate of the nitrogen to be 2000-5000 sccm, the pressure to be 200-300 Pa, the power supply to be 3-20 kW, and the time to be 300-800 s.

[0028] In some more preferred embodiments of the present disclosure, in S6, the wrap-around coating on the front side of the silicon wafer obtained in S5 is removed by laser edge scanning along the edge of the silicon wafer.

[0029] Further preferably, the conditions for the laser edge sweeping include: the width of the laser edge sweeping is 0.5-3 cm, preferably 0.5-1.5 cm, and the laser etching depth is 50-500 nm, preferably 50-200 nm.

[0030] Further preferably, the conditions for the laser edge scanning include: the laser is an ultraviolet or green laser, the pulse width is less than 10ns, and the laser power is 15-45W, preferably 15-40W.

[0031] In some preferred embodiments of the present disclosure, the one-time annealing method for preparing a back contact cell further comprises:

[0032] S8, forming a third semiconductor layer on the front surface of the silicon wafer obtained in S7, wherein the third semiconductor layer comprises an intrinsic hydrogenated amorphous silicon layer and a third doped silicon layer;

[0033] S9, then forming an anti-reflection layer on the surface of the third semiconductor layer on the front side of the silicon wafer;

[0034] S10, performing a second etching to open a predetermined area of ​​the back second semiconductor layer obtained in S9, to form a first semiconductor opening region spaced apart from the second semiconductor opening region;

[0035] S11, depositing a conductive film layer on the back surface obtained in S10;

[0036] S12, performing a third etching opening on the conductive film layer on the back surface obtained in S11 to form an insulating trench between the second semiconductor layer and the first semiconductor layer;

[0037] S13, forming metal electrodes respectively at the first semiconductor opening region and the second semiconductor opening region on the back surface obtained in S12. Beneficial effects:

[0038] The present disclosure adopts the above-mentioned technical scheme, especially the first semiconductor layer and the second semiconductor layer, both of which are passivated with tunneling silicon oxide on the back side, after being deposited in a tubular polysilicon deposition furnace, and then the surface doping index ratio of the two semiconductor layers is appropriately adjusted, so that the two semiconductor layers have a common annealing window, so that they can be annealed together in one time through the high-temperature annealing process of S5. At the common annealing temperature, the two polar semiconductor layers are crystallized and doped and activated together, so as to achieve the effect of both passivation and conductive properties, and avoid the problem of passivation failure caused by the doping elements of a certain semiconductor layer penetrating into the corresponding oxide layer during a single annealing process. At the same time, the process flow is greatly simplified, the equipment usage of plate-type PECVD is reduced, and the equipment investment cost is greatly reduced. At the same time, in conjunction with S6, a laser is used to remove multiple winding layers from the back side to the front side at one time, thereby reducing the process steps. At the same time, since different winding layers do not need to pass through different etching solutions that may bring the risk of damage to the functional film layer, the product yield and product reliability can be improved, and the battery conversion efficiency can be improved. Furthermore, since the present disclosure adopts a tubular polysilicon deposition furnace for deposition, the second mask layer can be deposited in the same furnace tube while the second semiconductor layer is deposited, thereby reducing the step of separately preparing the mask layer in the conventional process and virtually simplifying the process flow.

[0039] The inventors of the present disclosure have found that the multi-step annealing method in the prior art can use a solution to remove the front-side wrap-around coating caused by the corresponding film layer on the back layer layer by layer according to the properties of the film layer; while the single annealing method of the present disclosure will cause the multiple wrap-around coatings on the front side to be mixed together, and conventional acid solution removal requires increased concentration or prolonged time, which may damage the film layer on the back side. In this regard, in the preferred embodiment of the present disclosure, the present disclosure adopts a laser edge scanning method, which can effectively remove the multiple wrap-around coatings from the back side to the front side. Compared with the conventional method of removing wrap-around coating with an acid solution (such as a mixed solution of nitric acid and hydrofluoric acid), the process is simplified, the process time of removing wrap-around coating is greatly shortened, the amount of chemical solution used is greatly reduced, and the possibility of damage to the back-side film layer caused by corrosion by the acid solution is avoided, thereby improving the product yield, making the process more environmentally friendly and the battery performance (including product yield, reliability and battery conversion efficiency) more superior. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0041] FIG1 is a process flow chart of a specific embodiment of a single annealing method for preparing a back contact cell disclosed herein;

[0042] FIG2 is a schematic structural diagram of the back contact battery obtained in FIG1 .

[0043] Description of Reference Numerals

[0044] 1. Silicon wafer, 2.1. First tunneling silicon oxide layer, 2.2. First doped polysilicon layer, 3. First mask layer, 4.1. Second tunneling silicon oxide layer, 4.2. Second doped polysilicon layer, 5. Metal electrode, 6. Intrinsic hydrogenated amorphous silicon layer, 7. Third doped silicon layer, 8. Anti-reflection layer, 9. Conductive film layer. DETAILED DESCRIPTION

[0045] In this disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this disclosure, "plurality" means two or more, unless otherwise specifically specified.

[0046] In the present disclosure, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0047] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. Among them, the terms "optional" and "optional" all mean that they may be included or not (or may be present or not).

[0048] The present disclosure provides a single-annealing method for preparing a back-contact battery, comprising the following steps:

[0049] S1, provide double-sided polished silicon wafers;

[0050] S2. Using a tubular polysilicon deposition furnace, sequentially deposit a first semiconductor layer and a first mask layer on the back side of the silicon wafer. The first semiconductor layer includes a first tunneling silicon oxide layer and a first doped polysilicon layer. Annealing is not performed in this step.

[0051] S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region;

[0052] S4. Using a tubular polysilicon deposition furnace, sequentially deposit a second semiconductor layer and a second mask layer on the back surface obtained in S3, wherein the second semiconductor layer comprises a second tunneling silicon oxide layer and a second doped polysilicon layer. Annealing is not performed in this step. The ratio of the surface doping index of the first doped polysilicon layer to the second doped polysilicon layer is 3-115:1, preferably 5-100:1, and more preferably 10-70:1, wherein the surface doping index is the ratio of the effective doping concentration of the corresponding doped polysilicon layer to the thickness of the doped polysilicon layer.

[0053] S5, then high temperature annealing is performed;

[0054] S6, using laser to remove the wrap-around coating on the front side of the silicon wafer obtained in S5;

[0055] S7. Perform texturing and cleaning on the front side of the silicon wafer obtained in S6, and remove the second mask layer on the back side.

[0056] Those skilled in the art can select the type and type of silicon wafer as needed. The silicon wafer in S1 can be an N-type single crystal silicon wafer, a Czochralski single crystal silicon wafer, or a cast single crystal silicon wafer. After double-sided polishing, those skilled in the art can perform conventional steps such as cleaning as needed.

[0057] In the present disclosure, the first tunneling silicon oxide layer is located between the silicon wafer and the first doped polysilicon layer, and the second tunneling silicon oxide layer is located between the first mask layer and the second doped polysilicon layer.

[0058] In some preferred embodiments of the present disclosure, the effective doping concentration ratio of the first doped polysilicon layer to the second doped polysilicon layer is 1-100:1, preferably 10-70:1, and more preferably 10-50:1, and the thickness ratio of the first doped polysilicon layer to the second doped polysilicon layer is 0.5-3:1, preferably 0.8-3:1, further preferably 1-3:1, and more preferably 1-2.5:1. In this preferred embodiment, the first doped polysilicon layer and the second doped polysilicon layer with appropriate thickness ratios and doping concentration ratios can better balance the conductivity and annealing conditions of both layers, which is more conducive to finding a common annealing window and further improving battery performance.

[0059] On the basis of satisfying the above-mentioned ratio of the effective doping concentration of the first doped polysilicon layer to the second doped polysilicon layer, the effective doping concentration of the first doped polysilicon layer and the second doped polysilicon layer of the present disclosure can be selected in a wide range. In some preferred embodiments of the present disclosure, the effective doping concentration of the first doped polysilicon layer is 1×10 20 cm -3 -5×10 21 cm -3 The effective doping concentration of the second doped polysilicon layer is 1×10 19 cm -3 -5×10 20 cm -3 In this preferred embodiment, the effective doping concentration range of the first doped polysilicon layer and the second doped polysilicon layer is suitable, which is conducive to using a single annealing method in a more suitable process window, while reducing the process flow and further improving battery performance, especially product yield.

[0060] Based on the aforementioned thickness ratio between the first doped polysilicon layer and the second doped polysilicon layer, the thickness of the first doped polysilicon layer and the second doped polysilicon layer disclosed herein can be selected over a wide range. In some preferred embodiments of the present disclosure, the thickness of the first doped polysilicon layer is 40-120 nm, preferably 70-120 nm, and the thickness of the second doped polysilicon layer is 40-80 nm. In this preferred embodiment, a single annealing process can achieve equivalent or better performance than a conventional double annealing process, further facilitating matching of the annealing windows of the two processes.

[0061] Those skilled in the art can select the thickness of each tunneling silicon oxide layer from the prior art, as long as it is conducive to enhancing the passivation performance. In some preferred embodiments of the present disclosure, the thickness of the first tunneling silicon oxide layer is 1-2nm, and the thickness of the second tunneling silicon oxide layer is 1-3nm.

[0062] Those skilled in the art can select the thickness of each mask layer from the prior art. In some preferred embodiments of the present disclosure, the thickness of the first mask layer and the second mask layer are each independently 40-90 nm. The thickness of the first mask layer and the second mask layer can be the same or different.

[0063] The first etching opening described in S3 can be carried out by laser or mask etching, as long as the second semiconductor opening area can be formed. It can be understood that after the etching opening, the first semiconductor layer and the first mask layer deposited thereon are arranged as a whole at intervals on the back side.

[0064] In some specific preferred embodiments, the laser used for the first etching of the opening may be ultraviolet or green laser with a pulse width less than 10 ns. The width of the formed second semiconductor opening region may be determined according to actual needs, for example, 400-800 μm.

[0065] It can be understood that in S5, the entire structure obtained in S4 is subjected to high-temperature annealing. During this process, the first doped polysilicon layer and the second doped polysilicon layer are annealed simultaneously, and the present disclosure only performs annealing once, which greatly shortens the process flow while ensuring production yield.

[0066] In some preferred embodiments of the present disclosure, the deposition temperatures in S2 and S4 are both 400-500°C.

[0067] Preferably, the high-temperature annealing conditions in S5 include: annealing in the presence of a protective gas, using a gradient temperature increase and relatively low-pressure annealing method, with an annealing temperature of 850-950°C and a pressure of 1000-25000 Pa, more preferably 1000-10000 Pa. The present disclosure employs suitable high-temperature annealing conditions, particularly a suitable pressure range, to avoid the risk of film explosion caused by annealing two semiconductor layers simultaneously, thereby facilitating crystallization of the two semiconductor layers while maintaining a good balance between film quality and electrical properties.

[0068] The high temperature annealing described in the present disclosure can be directly performed as a single-stage annealing at the same temperature, such as annealing at any temperature between 850-950°C for the required time; or multiple-stage annealing can be performed separately at different temperatures, that is, multi-stage annealing with step-by-step heating. In some embodiments of the present disclosure, the high temperature annealing described in S5 is a multi-stage annealing and the process includes: constant temperature annealing at a first temperature, then heating to a second temperature for constant temperature annealing, and then continuing to heat to a third temperature for constant temperature annealing, wherein the adjacent temperature difference between the first temperature and the second temperature, and the adjacent temperature difference between the second temperature and the third temperature are each independently 20-30°C and each temperature is within 850-950°C, and the annealing time for each stage is 10-20 minutes. In a specific embodiment, the high temperature annealing process includes: annealing at 850°C for 15 minutes, and then keeping the temperature constant for 15 minutes every time the temperature is increased by 25°C until 925°C.

[0069] In some preferred embodiments of the present disclosure, the high temperature annealing conditions in S5 further include: a mass flow rate of a protective gas of 5000-15000 sccm, and an annealing time of 40-60 min. The protective gas may be an inert gas such as nitrogen.

[0070] In the present disclosure, the deposition process of the first semiconductor layer and the second semiconductor layer can be selected from the existing technology, as long as a film layer of the required thickness and the corresponding required doping concentration can be obtained. In some more preferred embodiments of the present disclosure, in S2 and S4, the conditions for depositing the first tunneling silicon oxide layer and the second tunneling silicon oxide layer independently include: controlling the mass flow rate of the nitrous oxide to be 8000-12000 sccm, the pressure to be 100-200 Pa, the power supply to be 3-20 kW, and the time to be 20-100 s; the conditions for depositing the first doped polysilicon layer and the second doped polysilicon layer independently include: controlling the mass flow rate of the silane to be 1000-3000 sccm, the mass flow rate of the hydrogen to be 7000-9000 sccm, and the introduction of a mixed gas of hydrogen carrying a doping element gas source, and controlling the power supply to be 5-20 kW, and the deposition time to be 800-1300 s.

[0071] Preferably, when the doping element gas source is a phosphorus source, the mass flow rate of the mixed gas is 1000-2500 sccm, and the pressure is controlled at 400-500 Pa; when the doping element gas source is a boron source, the mass flow rate of the mixed gas is 2000-4000 sccm, and the pressure is controlled at 200-800 Pa. The present disclosure employs an appropriate flow rate range and pressure range when the doping element gas source is different, and can adjust appropriate parameters according to the difficulty of doping different doping elements, which is more conducive to achieving the desired doping concentration of the two semiconductor layers.

[0072] The flow ratio of hydrogen and the doping element source gas in the mixed gas of hydrogen and the doping element source gas can be selected according to actual needs. For example, the flow ratio of the doping element source gas in the mixed gas is 1%-10%.

[0073] In the present disclosure, one of the first doped polysilicon layer and the second doped polysilicon layer is N-type, and the other is P-type.

[0074] It should be noted that when the first doped polysilicon layer is N-type, the doping element gas source is a phosphorus source, and the second doped polysilicon layer is correspondingly doped with boron; when the first doped polysilicon layer is P-type, the doping element gas source is a boron source, and the second doped polysilicon layer is correspondingly doped with phosphorus. The types of phosphorus and boron sources described in this disclosure can be selected by those skilled in the art from existing sources. For example, the phosphorus source can be a gas source such as phosphine, and the boron source can be diborane or trimethylborane.

[0075] In the present disclosure, the deposition processes for the first and second mask layers can be selected from existing techniques, as long as a film of the desired thickness can be obtained. In some preferred embodiments of the present disclosure, the conditions for depositing the first and second mask layers independently include: controlling the mass flow rate of silane to 1000-2000 sccm, the mass flow rate of nitrogen to 2000-5000 sccm, the pressure to 200-300 Pa, the power to 3-20 kW, and the time to 300-800 s.

[0076] Those skilled in the art can select the types of the first mask layer and the second mask layer from the prior art. The first mask layer and the second mask layer can be the same or different. For example, they can each independently be at least one of silicon nitride, silicon oxide, silicon oxynitride, or nitrogen-containing polysilicon. Preferably, the first mask layer is silicon nitride, and the second mask layer is silicon oxide.

[0077] During the deposition process in S2 and S4 of the present disclosure, multiple wrap-around coatings will be generated on the front side of the silicon wafer.

[0078] The method disclosed in the present invention for removing the wrap-around coating on the front side of the silicon wafer obtained by S5 adopts laser. Compared with the conventional method of removing the wrap-around coating by acid solution, the laser removal method simplifies the process, greatly shortens the process time of removing the wrap-around coating, greatly reduces the amount of chemical solution used, and avoids the possibility of damage to the back film layer by corrosion by acid solution, thereby improving product yield and product reliability, making the process flow more environmentally friendly and improving battery performance.

[0079] In some more preferred embodiments of the present disclosure, in S6, the coating layer on the front side of the silicon wafer obtained in S5 is removed by laser scanning along the edge of the silicon wafer. This is more beneficial for protecting the functional film layer on the back side from the risk of damage caused by immersion in different corrosive solutions, and at the same time avoids the possibility of excessive corrosion of the silicon wafer and inability to be repaired through subsequent steps.

[0080] It is understood that the laser edge sweeping described in this disclosure has the conventional meaning of lasers used in the field of solar cells, namely, sweeping and scribing the edges of a silicon wafer around the coating. Laser edge sweeping specifically refers to the use of a laser to rapidly sweep and scribble around the edges of the silicon wafer, removing the coating around the edges. This is done by controlling the desired width and depth to avoid the risk of excessive silicon loss and difficult repair.

[0081] Further preferably, the laser edge sweeping conditions include: a laser edge sweeping width of 0.5-3 cm, preferably 0.5-1.5 cm, and a laser etching depth of 50-500 nm, preferably 50-200 nm. Adopting the preferred embodiment of the present disclosure, using a laser edge sweeping of an appropriate width and etching an appropriate width can prevent laser etching of non-plating areas, which could damage the silicon wafer (i.e., bulk silicon) surface, and is more conducive to repairing and passivating the bulk silicon surface in subsequent steps.

[0082] It can be understood that since laser edge sweeping is the process of sweeping and scratching the coating around the edges of the silicon wafer, the width of the laser edge sweeping here refers to the width of the laser radiation, when the laser radiates to the edge of the silicon wafer.

[0083] Further preferably, the laser edge scanning conditions include: the laser is an ultraviolet or green laser, with a pulse width of less than 10ns and a laser power of 15-45W, preferably 15-40W. In this preferred embodiment, using a smaller laser and an appropriately low power can avoid excessive laser energy that may lead to excessive etching depth, which is more conducive to surface passivation of the silicon wafer in subsequent steps.

[0084] The texturing cleaning described in S7 includes first texturing with a texturing liquid, then cleaning with a cleaning agent, and removing the second mask layer on the back side during cleaning; wherein the cleaning agent can not only play a cleaning role, but also remove the second mask layer on the back side. Those skilled in the art can select texturing liquid and cleaning agent from the existing technology. For example, the texturing liquid used can be a mixture of alkali (such as potassium hydroxide or sodium hydroxide), texturing additive and water, wherein the mass percentage of alkali in the texturing liquid is 1%-5%, and the mass percentage of texturing additive is 0.5%-1%. The texturing additive can be a commercial product or prepared. For another example, the cleaning agent used can be an acid solution such as HF acid, and the mass concentration of HF acid is 0.5%-5%. For the specific conditions of texturing and cleaning, those skilled in the art can select from the existing technology. For example, the texturing conditions include: texturing time of 8-30 minutes, texturing temperature of 75℃-85℃; for another example, the cleaning conditions include: processing temperature of 20℃-30℃, and removal time of 60-300s.

[0085] The single annealing preparation method of the back contact battery disclosed in the present invention may also include conventional steps for preparing the desired battery structure, such as a preparation process for an interdigitated battery structure.

[0086] In some preferred embodiments of the present disclosure, the single annealing preparation method of the back contact battery further includes: S8, forming a third semiconductor layer on the front side of the silicon wafer obtained in S7, wherein the third semiconductor layer comprises an intrinsic hydrogenated amorphous silicon layer and a third doped silicon layer. The third doped silicon layer can be a doped amorphous or microcrystalline silicon layer, and its conductivity type is the same as that of the silicon wafer. Those skilled in the art can refer to the prior art for the deposition method, thickness, doping concentration, etc. of the third semiconductor layer. For example, the third semiconductor layer can be formed by plate CVD. For example, the thickness of the intrinsic hydrogenated amorphous silicon layer can be 4-8nm, the thickness of the third doped silicon layer can be 6-12nm, and the effective doping concentration can be 1×10 19 cm -3 -1×10 20 cm -3 .

[0087] In some preferred embodiments of the present disclosure, the single-annealing method for preparing a back-contact cell further includes: S9, subsequently forming an anti-reflection layer on the surface of the third semiconductor layer on the front side of the silicon wafer. The formation method, type, and thickness of the anti-reflection layer can all refer to existing technologies. For example, the anti-reflection layer can be at least one of silicon nitride, silicon oxide, and silicon oxynitride, and can have a thickness of 70-120 nm. The anti-reflection layer can be formed by deposition using a conventional PECVD coating method, followed by cleaning to remove the back-surface coating.

[0088] In some preferred embodiments of the present disclosure, the single-annealing method for preparing a back-contact cell further includes: S10, performing a second etching opening in a predetermined region of the second semiconductor layer on the back side obtained in S9, thereby forming a first semiconductor opening region spaced apart from the second semiconductor opening region. It will be understood that the second etching opening removes the second semiconductor layer within the predetermined region and the first mask layer within the corresponding region to expose the first semiconductor layer, thereby forming the first semiconductor opening region.

[0089] The second etching opening can be formed by laser or mask etching, as long as the second semiconductor layer above the first semiconductor layer and the first mask layer in the corresponding region are etched away to form the first semiconductor opening region. For example, the conditions for the second etching opening include: using a laser, which can be an ultraviolet or green laser, with a pulse width of less than 10 ns, and forming a second semiconductor opening region with a width of 100-250 μm.

[0090] In some preferred embodiments of the present disclosure, the single-annealing method for preparing a back-contact battery further includes: S11, depositing a conductive film layer on the back surface obtained in S10. The method for depositing the conductive film layer can, for example, employ physical vapor deposition (PVD) or activated plasma deposition (RPD). The thickness of the conductive film layer can, for example, be 40-80 nm, and the material of the conductive film layer can, for example, be an indium oxide-based film doped with at least one of tin, tungsten, titanium, and zinc, or a zinc oxide-based film doped with aluminum and / or boron.

[0091] In some preferred embodiments of the present disclosure, the single-annealing method for preparing a back-contact cell further includes: S12, performing a third etching on the conductive film layer on the back surface obtained in S11 to form an insulating trench between the second semiconductor layer and the first semiconductor layer. The third etching can be performed, for example, by mask etching or laser etching. The insulating trench can be 20-100 μm wide, and after etching, the resistance between the first semiconductor opening region and the second semiconductor opening region is greater than 1 kΩ.

[0092] In some preferred embodiments of the present disclosure, the single annealing method for preparing a back-contact cell further includes: S13, forming metal electrodes at the first semiconductor opening region and the second semiconductor opening region on the back side obtained in S12. The metal electrodes can be formed using screen printing technology.

[0093] The embodiments of the present disclosure are described in detail below, which are exemplary and only used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0094] Example 1

[0095] A single annealing method for preparing a back contact cell, as shown in FIG1 , comprises the following steps:

[0096] S1, double-sided polishing of silicon wafer 1:

[0097] The double-sided polishing and cleaning of an N-type single crystal silicon wafer 1 is performed, wherein the silicon wafer 1 is a Czochralski single crystal silicon wafer.

[0098] S2. Forming a first semiconductor layer and a first mask layer 3 on the back side of the silicon wafer 1:

[0099] The first semiconductor layer includes a first tunneling silicon oxide layer 2.1 and an N-type first doped polysilicon layer 2.2. The first mask layer 3 is silicon nitride. The first tunneling silicon oxide layer 2.1 has a thickness of 2 nm, the first doped polysilicon layer 2.2 has a thickness of 100 nm, and an effective doping concentration of 2×10 21 cm -3 , the thickness of the first mask layer 3 is 50nm. The first tunneling silicon oxide layer 2.1, the first doped polysilicon layer 2.2, and the first mask layer 3 are sequentially deposited using a tubular polysilicon deposition furnace at a deposition temperature of 450°C. When depositing the first tunneling silicon oxide layer 2.1, the mass flow rate of nitrous oxide is 9000sccm, the pressure is 150Pa, the power is 10kW, and the time is 50s. When depositing the first doped polysilicon layer 2.2, the mass flow rate of silane is 2000sccm, the mass flow rate of the mixed gas of hydrogen carrying phosphine (flow ratio is 2% PH3 / 98% H2) is 2000sccm, the mass flow rate of hydrogen is 8000sccm, the pressure is 450Pa, the power is 10kW, and the coating time is 1000s. When depositing silicon nitride, the mass flow rate of silane is 1500 sccm, the mass flow rate of nitrogen is 3000 sccm, the pressure is 250 Pa, the power is 10 kW, and the time is 500 s.

[0100] S3, performing a first etching opening on the back side of the silicon wafer 1 to form a second semiconductor opening region W1;

[0101] The first etching opening can be formed by laser, wherein the laser is ultraviolet laser with a pulse width of 5 ps. The width of the formed second semiconductor opening region is 500 μm.

[0102] S4, forming a second semiconductor layer and a second mask layer on the back side of the silicon wafer 1;

[0103] The second semiconductor layer includes a second tunneling silicon oxide layer 4.1 and a P-type second doped polysilicon layer 4.2. The second mask layer is silicon oxide. The second tunneling silicon oxide layer 4.1 has a thickness of 2 nm, and the second doped polysilicon layer 4.2 has a thickness of 80 nm and an effective doping concentration of 8.5×10 19 cm -3The second mask layer has a thickness of 50 nm. The second tunneling silicon oxide layer 4.1, the second doped polysilicon layer 4.2, and the second mask layer are sequentially deposited using a tubular polysilicon deposition furnace at a deposition temperature of 450°C. During the deposition of the second tunneling silicon oxide layer 4.1, the mass flow rate of nitrous oxide (NO) was 9000 sccm, the pressure was 100 Pa, the power was 10 kW, and the deposition time was 50 s. During the deposition of the second doped polysilicon layer 4.2, the mass flow rate of silane was 2000 sccm, the mass flow rate of a mixture of hydrogen and diborane (with a flow ratio of 2% B2H6 / 98% H2) was 2000 sccm, the mass flow rate of hydrogen was 8000 sccm, the pressure was 400 Pa, the power was 10 kW, and the deposition time was 1000 s. During the deposition of silicon oxide, the mass flow rate of silane was 2000 sccm, the mass flow rate of nitrous oxide (NO) was 3000 sccm, the pressure was 200 Pa, the power was 10 kW, and the deposition time was 500 s.

[0104] S5, performing high-temperature annealing on the entire structure of the first semiconductor layer, the first mask layer 3, the second semiconductor layer, and the second mask layer formed on the back side of the silicon wafer 1;

[0105] During the high-temperature annealing, nitrogen gas was introduced at a mass flow rate of 10,000 sccm, the annealing temperature was 900° C., the pressure was 5,000 Pa, and the time was 50 minutes.

[0106] S6. Laser removal of the coating on the front side of silicon wafer 1:

[0107] The coating on the front side of the silicon wafer 1 is removed by laser edge sweeping. The laser used for the laser edge sweeping is an ultraviolet laser with a pulse width of 5 ps, a laser power of 20 W, a laser edge sweeping width of 1.0 cm, and a laser etching depth of 100 nm.

[0108] S7: Clean the front surface of the silicon wafer 1 and remove the second mask layer on the back surface.

[0109] The front side of the silicon wafer 1 was textured using a mixture of potassium hydroxide, a texture additive, and water, with the potassium hydroxide content being 2% by weight and the texture additive content being 0.5% by weight. The texture was applied for 10 minutes at a temperature of 75°C.

[0110] Finally, the wafer is cleaned with HF acid (HF aqueous solution) to remove the second mask layer on the back of the wafer 1. The HF acid mass percentage is 1%, the processing temperature is 20°C, and the removal time is 100s.

[0111] S8, forming a third semiconductor layer on the front surface of the silicon wafer 1;

[0112] The third semiconductor layer comprises an intrinsic hydrogenated amorphous silicon layer 6 and an N-type third doped silicon layer 7 (specifically a doped amorphous silicon layer). The third semiconductor layer is formed by plate-type CVD. The intrinsic hydrogenated amorphous silicon layer 6 has a thickness of 5 nm, and the third doped silicon layer 7 has a thickness of 8 nm and an effective doping concentration of 5×10 19 cm -3 .

[0113] S9, forming an anti-reflection layer 8 on the front surface of the silicon wafer 1:

[0114] The anti-reflection layer 8 is made of silicon nitride with a thickness of 80 nm and is deposited by conventional PECVD coating method, and then the back-surface coating is removed by cleaning.

[0115] S10, performing a second etching opening on the back side of the silicon wafer 1 to form a first semiconductor opening region W2;

[0116] The second etching opening can be performed by etching away the second semiconductor layer and the first mask layer 3 above the first semiconductor layer using a laser, thereby forming a first semiconductor opening region. The laser is an ultraviolet laser with a pulse width of 5 ps. The width of the formed second semiconductor opening region is 150 μm.

[0117] S11, depositing a conductive film layer 9 on the back side of the silicon wafer 1:

[0118] A transparent conductive film layer 9 is deposited on the back of the silicon wafer 1 by physical vapor deposition (PVD) or activated plasma deposition (RPD). The conductive film layer 9 has a thickness of 50 nm and is made of a tin-doped indium oxide-based thin film.

[0119] S12, performing a third etching opening on the back side of the silicon wafer 1 to form an insulating groove;

[0120] An insulating trench is formed between the first semiconductor opening region and the second semiconductor opening region by laser etching. The insulating trench width W3 is 20 μm. After etching, the resistance between the first semiconductor opening region and the second semiconductor opening region is greater than 1 kΩ.

[0121] S13. Metal electrodes 5 are formed at the first and second semiconductor opening regions on the back side of the silicon wafer 1. The polarities of the metal electrodes 5 at the first and second semiconductor opening regions are opposite. Specifically, the metal electrodes 5 are formed using screen printing technology to obtain a back-contact cell as shown in FIG2 .

[0122] Example 2

[0123] The method of Example 1 is followed, except that the doping concentration of the first doped polysilicon layer is adjusted to 6.37×10 21 cm -3, so that the effective doping concentration ratio of the first doped polysilicon layer to the second doped polysilicon layer is 75:1. In order to meet the doping concentration of the first doped polysilicon layer, the process needs to be adjusted accordingly: the flow rate of phosphine is increased to 2.6 times the corresponding flow rate of Example 1, and the annealing temperature in S5 is increased to 935°C.

[0124] Example 3

[0125] The method of Example 1 is referred to, except that the thickness of the first doped polysilicon layer is adjusted to 70nm, so that the ratio of the thickness of the first doped polysilicon layer to the second doped polysilicon layer is 0.875:1. In order to meet the thickness of the first doped polysilicon layer, the process needs to be adjusted accordingly: the coating time is reduced to 30% of the corresponding time in Example 1.

[0126] Example 4

[0127] The method of Example 1 is referred to, except that the thickness of the first doped polysilicon layer is adjusted to 40 nm, so that the ratio of the thickness of the first doped polysilicon layer to the second doped polysilicon layer is 0.5:1. In order to meet the thickness of the first doped polysilicon layer, the process needs to be adjusted accordingly: the coating time is reduced to 50% of the corresponding time in Example 1.

[0128] Example 5

[0129] The method of Example 1 is referred to, except that the pressure of the high temperature annealing in S5 is 25000 Pa.

[0130] Example 6

[0131] The method of Example 1 is referred to, except that the width of the laser edge sweeping in S6 is 3 cm.

[0132] Example 7

[0133] The method of Example 1 is referred to, except that the laser etching depth of the laser edge scanning in S6 is 300 nm. To meet this etching depth, the process needs to be adjusted accordingly: the laser power is 45 W.

[0134] Example 8

[0135] The method of Example 1 is referred to, except that the high temperature annealing in S5 adopts multi-stage annealing instead of the single-stage annealing of Example 1. Specifically, annealing is performed at 850°C for 15 minutes, and then the temperature is kept constant for 15 minutes each time the temperature is increased by 25°C until it reaches 925°C and the temperature is kept constant for 15 minutes.

[0136] Comparative Example 1

[0137] A conventional heterojunction back contact cell, the preparation method of which is as follows:

[0138] S101, providing a silicon wafer with a single-side texturing and single-side polishing structure, wherein a protective mask layer needs to be formed in advance on the other side when texturing one side, and the protective mask layer is removed after texturing;

[0139] S102, depositing a first semiconductor layer and a first mask layer on the back side of the silicon wafer in sequence, wherein the first semiconductor layer is formed by plate-type PECVD, and the first semiconductor layer comprises a first intrinsic amorphous silicon layer with a thickness of 6 nm and an N-type doped amorphous silicon layer with a thickness of 12 nm (the doping concentration is the same as in Example 1); the N-type doped amorphous silicon layer is formed by in-situ doping deposition;

[0140] S103, using a laser to open an opening on the back side of the silicon wafer, removing the first mask layer and a portion of the first semiconductor layer, and forming a second semiconductor opening region;

[0141] S104, cleaning the silicon wafer to further remove the remaining first semiconductor layer in the second semiconductor opening area;

[0142] S105. A second semiconductor layer is formed on the back side of the silicon wafer. The second semiconductor layer is formed by tubular PECVD. The second semiconductor layer includes a second intrinsic amorphous silicon layer with a thickness of 7 nm and a P-type doped amorphous silicon layer with a thickness of 14 nm (the doping concentration is the same as in Example 1). The P-type doped amorphous silicon layer is formed by in-situ doping deposition.

[0143] Then proceed according to S8-S13 of Example 1.

[0144] Comparative Example 2

[0145] The method of Comparative Example 1 is referred to, except that a back-contact battery with a TOPCON passivation structure is used. Specifically, a first tunneling silicon oxide layer (with the same thickness as the first tunneling silicon oxide layer in Example 1) is used instead of the first intrinsic amorphous silicon layer in S102, and a second tunneling silicon oxide layer (with the same thickness as the second tunneling silicon oxide layer in Example 1) is used instead of the second intrinsic amorphous silicon layer in S105. Each tunneling silicon oxide layer is formed by plate-type PECVD.

[0146] Comparative Example 3

[0147] The method of Example 1 is referred to, except that conventional multiple annealing is performed. Specifically, in S2, after depositing the first tunneling silicon oxide layer, the first doped polysilicon layer, and the first mask layer, a first annealing is performed, and then the front side coating of the silicon wafer is removed for the first time; in S4, after depositing the second tunneling silicon oxide layer, the second doped polysilicon layer, and the second mask layer, a second annealing is performed, and then the front side coating of the silicon wafer is removed for the second time; S6 is not performed, but subsequent steps such as S7 are directly performed. Among them, the conditions of the first annealing and the second annealing are the same as the high-temperature annealing conditions of S6 in Example 1. The first removal of the front side coating of the silicon wafer and the second removal of the front side coating of the silicon wafer are respectively carried out with a conventional acid solution (specifically a mixed solution of nitric acid and hydrofluoric acid, with a nitric acid concentration of 15wt% and a hydrofluoric acid concentration of 5wt%) at 45°C for 30min. In this comparative example, conventional acid solution is used for removing the front side coating twice, rather than laser removal, because both removals are carried out by laser, which easily causes damage to the body silicon on the front side, making it difficult to passivate subsequently.

[0148] Comparative Example 4

[0149] The method of Example 1 is followed, except that the doping concentration of the first doped polysilicon layer is adjusted to 5×10 19 cm -3 , so that the effective doping concentration ratio of the first doped polysilicon layer to the second doped polysilicon layer is 0.59:1. In order to meet the doping concentration of the first doped polysilicon layer, the process needs to be adjusted accordingly: the flow rate of phosphine is reduced to 0.16 times the corresponding flow rate in Example 1, and the annealing temperature in S5 is lowered to 860°C.

[0150] Comparative Example 5

[0151] The method of Example 1 is referred to, except that, in S6, an acid mixed solution is used to remove the plating layer on the front side of the silicon wafer. Specifically, the acid mixed solution is used to clean the silicon wafer at 45° C. for 30 minutes. The acid mixed solution is a mixed solution of nitric acid and hydrofluoric acid, the solvent is water, the nitric acid concentration is 15wt%, and the hydrofluoric acid concentration is 5wt%.

[0152] Test Case

[0153] The back-contact cells obtained in the above-mentioned embodiments and comparative examples were subjected to various performance tests, and the results are shown in Table 1. Among them, the production yield is the product qualification rate when the batch production volume is 1000 cells, and the product reliability is the yield after double 85 test aging. Double 85 test means that the test environment is set to: temperature of 85°C and humidity of 85%, and the battery cells are subjected to constant temperature and humidity aging test for 1000 hours. By comparing the data before and after the experiment, the reliability performance of the battery, such as heat resistance and moisture resistance, is examined. After double 85 aging, the yield test such as conversion efficiency is carried out, which is the yield after double 85 aging. The normalized cost index refers to the cost of Example 1 as the benchmark and is recorded as 1. The corresponding indicators of other embodiments and comparative examples are all calculated relative to the cost benchmark of Example 1.

[0154] Table 1

[0155] It can be seen from the above results that, compared with the comparative example, the embodiment scheme of the present disclosure can greatly improve the production yield and product reliability, while taking into account the reduction of production costs and higher battery conversion efficiency, which is conducive to large-scale production and improving the market competitiveness of products.

[0156] Furthermore, according to Examples 1 and 2-7, it can be seen that the preferred single annealing combined with laser edge sweeping to remove the plating layer and suitable process parameters disclosed in the present invention can further significantly improve the battery conversion efficiency on the basis of appropriately reducing production costs, while taking into account further improving production yield and product reliability.

[0157] The preferred embodiments of the present disclosure are described in detail above, but the present disclosure is not limited thereto. Within the technical concept of the present disclosure, various simple variations of the technical solution of the present disclosure may be made, including combining the various technical features in any other appropriate manner. These simple variations and combinations should also be regarded as disclosed by the present disclosure and fall within the scope of protection of the present disclosure. Industrial Applicability

[0158] The present invention discloses that after the first semiconductor layer and the second semiconductor layer, both of which are passivated with tunneling silicon oxide on the back side, are deposited in a tubular polysilicon deposition furnace, an appropriate ratio of the surface doping indices of the two semiconductor layers is matched so that the two semiconductor layers have a common annealing window, so that they can be annealed together in one step through the S5 high-temperature annealing process. At the common annealing temperature, the two polar semiconductor layers are crystallized and doped and activated together to achieve the effect of having both passivation and conductive properties, avoiding the problem of passivation failure caused by the doping elements of a certain semiconductor layer penetrating into the corresponding oxide layer during a single annealing process. At the same time, the process flow is greatly simplified, the use of plate-type PECVD equipment is reduced, and thus the equipment investment cost is greatly reduced, which has very good industrial application prospects.

Claims

1. A single annealing method for preparing a back contact battery, characterized in that: The steps include: S1, provide double-sided polished silicon wafers; S2, using a tubular polysilicon deposition furnace to sequentially deposit a first semiconductor layer and a first mask layer on the back side of the silicon wafer, wherein the first semiconductor layer comprises a first tunneling silicon oxide layer and a first doped polysilicon layer, and no annealing is performed in this step; S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region; S4, using a tubular polysilicon deposition furnace, sequentially depositing a second semiconductor layer and a second mask layer on the back side obtained in S3, wherein the second semiconductor layer comprises a second tunneling silicon oxide layer and a second doped polysilicon layer; no annealing is performed in this step; the ratio of the surface doping index of the first doped polysilicon layer to the second doped polysilicon layer is 3-115:1, wherein the surface doping index is the ratio of the effective doping concentration of the corresponding doped polysilicon layer to the thickness of the doped polysilicon layer; S5, then high temperature annealing is performed; S6, using laser to remove the coating layer on the front side of the silicon wafer obtained in S5; S7, performing texturing and cleaning on the front side of the silicon wafer obtained in S6, and removing the second mask layer on the back side.

2. The one-time annealing preparation method of a back contact battery according to claim 1, characterized in that: The ratio of the effective doping concentration of the first doped polysilicon layer to the second doped polysilicon layer is 1-100:1, and the ratio of the thickness of the first doped polysilicon layer to the second doped polysilicon layer is 0.5-3:

1.

3. The one-time annealing preparation method of a back contact battery according to claim 1, characterized in that: The effective doping concentration of the first doped polysilicon layer is 1×10 20 cm -3 -5×10 21 cm -3 The effective doping concentration of the second doped polysilicon layer is 1×10 19 cm -3 -5×10 20 cm -3 ; and / or, The thickness of the first doped polysilicon layer is 40-120 nm, and the thickness of the second doped polysilicon layer is The thickness is 40-80nm.

4. The one-time annealing preparation method of a back contact battery according to claim 1, characterized in that: The thickness of the first tunneling silicon oxide layer is 1-2 nm, and the thickness of the second tunneling silicon oxide layer is 1-3 nm; And / or, the thickness of the first mask layer and the second mask layer are independently 40-90 nm.

5. The one-time annealing method for preparing a back contact battery according to claim 1, characterized in that: The deposition temperatures in S2 and S4 are both 400-500° C., and the conditions for high temperature annealing in S5 include: being carried out in the presence of a protective gas, the annealing temperature is 850-950° C., and the pressure is 1000-25000 Pa.

6. The one-time annealing preparation method of a back contact battery according to claim 5, characterized in that: In S2 and S4, the conditions for depositing the first tunneling silicon oxide layer and the second tunneling silicon oxide layer independently include: controlling the mass flow rate of the laughing gas to be 8000-12000sccm, the pressure to be 100-200Pa, the power supply to be 3-20kW, and the time to be 20-100s; the conditions for depositing the first doped polysilicon layer and the second doped polysilicon layer independently include: controlling the mass flow rate of the silane to be 1000-3000sccm, the mass flow rate of the hydrogen to be 700 0-9000sccm, and a mixed gas of hydrogen carrying a doping element gas source is introduced, and the power supply power is controlled to be 5-20kW, and the deposition time is 800-1300s; wherein, when the doping element gas source is a phosphorus source, the mass flow rate of the mixed gas is 1000-2500sccm, and the pressure is controlled to be 400-500Pa; when the doping element gas source is a boron source, the mass flow rate of the mixed gas is 2000-4000sccm, and the pressure is controlled to be 200-800Pa; and / or, The conditions for depositing the first mask layer and the second mask layer independently include: controlling the mass flow rate of silane to 1000-2000sccm, the mass flow rate of nitrogen to 2000-5000sccm, the pressure to 200-300Pa, the power to 3-20kW, and the time to 300-800s.

7. The one-time annealing method for preparing a back contact battery according to claim 5, characterized in that: The high temperature annealing conditions in S5 also include: the mass flow rate of the protective gas is 5000-15000 sccm, and the annealing time is 40-60 min; and / or, The high temperature annealing in S5 is a multi-stage annealing and the process includes: constant temperature annealing at a first temperature, then heating to a second temperature for constant temperature annealing, and then continuing to heat to a third temperature for constant temperature annealing, wherein the adjacent temperature difference between the first temperature and the second temperature and the adjacent temperature difference between the second temperature and the third temperature are independently 20-30°C and each temperature is within 850-950°C, and the annealing time for each stage is 10-20min.

8. The one-time annealing method for preparing a back contact battery according to claim 1, characterized in that: In S6, the coating layer on the front side of the silicon wafer obtained in S5 is removed by laser edge scanning along the edge of the silicon wafer.

9. The one-time annealing method for preparing a back contact battery according to claim 8, characterized in that: The conditions of the laser edge scanning include: the width of the laser edge scanning is 0.5-3 cm, and the depth of the laser etching is 50-500 nm; and / or, The conditions for the laser edge scanning include: the laser is an ultraviolet or green laser, the pulse width is less than 10ns, and the laser power is 15-45W.

10. The one-time annealing method for preparing a back contact battery according to claim 1, characterized in that: The one-time annealing preparation method of the back contact battery also includes: S8, forming a third semiconductor layer on the front side of the silicon wafer obtained in S7, wherein the third semiconductor layer comprises an intrinsic hydrogenated amorphous silicon layer and a third doped silicon layer; S9, then forming an anti-reflection layer on the surface of the third semiconductor layer on the front side of the silicon wafer; S10, performing a second etching opening in a preset area of ​​the second semiconductor layer on the back side obtained in S9, to form a first semiconductor opening area spaced apart from the second semiconductor opening area; S11, depositing a conductive film layer on the back surface obtained in S10; S12, performing a third etching opening on the conductive film layer on the back obtained in S11 to form an insulating groove between the second semiconductor layer and the first semiconductor layer; S13, forming metal electrodes respectively at the first semiconductor opening region and the second semiconductor opening region on the back side obtained in S12.

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