Deep trench capacitor structure and manufacturing method therefor

Abstract

The present invention relates to a deep trench capacitor structure and a manufacturing method therefor. The deep trench capacitor structure comprises: a silicon interposer configured to be internally arranged with a plurality of metal traces, and a deep trench capacitor configured to be mounted to a first surface of the silicon interposer, wherein the deep trench capacitor comprises a wafer, a plurality of contact vias arranged in the wafer, and a first dielectric layer, an upper electrode, a lower electrode, a second dielectric layer, and a plastic packaging layer which are arranged on the first surface of the wafer; and the deep trench capacitor is electrically connected to the plurality of metal traces in the silicon interposer by means of the contact vias. By depositing the electrodes and the dielectric layers on a deep trench array formed by etching, manufacturing the deep trench capacitor in a plastic packaging mode, and integrating the deep trench capacitor on the silicon interposer, better compatibility for through silicon vias is achieved, the manufacturing process is simpler, and the compatibility with the existing process is high.

Description

A deep trench capacitor structure and manufacturing method thereof Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a deep trench capacitor structure and a manufacturing method thereof. Background Art

[0002] With the continuous increase in chip integration, the use of deep trench capacitors (DTCs) to replace traditional surface-mount capacitors has become a major trend. Deep trench capacitors can form very small but very large capacitors and are widely used in integrated circuits such as memory and power devices. The process for forming deep trench capacitors on a semiconductor is as follows: the trench array area is etched, followed by the thermal growth of a SiO2 layer as a protective layer. Then, electrode layers and dielectric layers are alternately deposited using low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD) processes. A photoresist layer is then applied to form the through-hole cavity, and finally, the interconnect dielectric layer and metal pad structure are formed. Since through-silicon vias (TSVs) and deep trench capacitors can coexist on the same silicon wafer, there are two methods for forming deep trench capacitors in a silicon interposer. One is the DTC-first process, in which the DTC is unaffected by the previous process. However, since the deep trench is formed before the TSV process, this method requires ensuring that the TSV thermal budget during the TSV process does not affect the DTC. Another method is TSV-first, which uses a standard TSV process to make TSVs and then forms DTCs.

[0003] The higher the capacitance density of deep trench capacitors, the better the improvement in power integrity. However, some process problems may arise when forming deep trench capacitors in semiconductor devices, such as high sidewall roughness leading to poor film uniformity, and Cu protrusions that are easily generated when DTC and TSV are manufactured on the same silicon wafer.

[0004] Summary of the Invention

[0005] To address some or all of the problems in the prior art, the present invention provides a deep trench capacitor structure, comprising:

[0006] a silicon interposer, wherein the silicon interposer is configured to arrange a plurality of metal traces therein;

[0007] a deep trench capacitor configured to be attached to the first surface of the silicon interposer;

[0008] The deep trench capacitor includes a wafer, a deep trench formed on a first surface of the wafer, a plurality of contact holes arranged in the wafer, and a first dielectric layer, an upper electrode, a lower electrode, a second dielectric layer and a plastic layer arranged on the first surface of the wafer;

[0009] The deep trench capacitor is electrically connected to the plurality of metal traces in the silicon interposer through the contact vias.

[0010] Furthermore, the silicon interposer has a plurality of through silicon vias therein.

[0011] Furthermore, the plastic encapsulation layer covers the first dielectric layer, the upper electrode, the lower electrode and the second dielectric layer.

[0012] Furthermore, the second dielectric layer is preferably made of one of aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, and lanthanum oxide, or a combination thereof.

[0013] The present invention also provides a method for manufacturing a deep trench capacitor structure, the method comprising the following steps:

[0014] bonding the second surface of the wafer to the first surface of the first carrier via the first bonding material;

[0015] Etching the first surface of the wafer to form a deep trench array region;

[0016] Thermally growing a first dielectric layer as a protective layer in the deep trench array region;

[0017] Depositing a lower electrode layer, a second dielectric layer, and an upper electrode layer in sequence on the first surface of the first dielectric layer;

[0018] Etching the first dielectric layer, the lower electrode layer, the second dielectric layer, and the upper electrode layer to form a plurality of first deep trench capacitor arrays;

[0019] Plastic-sealing the region where the plurality of first deep trench capacitor arrays are located to form a plastic-sealed deep trench capacitor array;

[0020] Debonding, peeling off the first carrier and the first bonding material;

[0021] Turning over the plastic-encapsulated deep trench capacitor array, and bonding the first surface of the plastic encapsulation layer to the first surface of the second carrier through a second bonding material;

[0022] etching the second surface of the wafer to form a plurality of through-hole cavities;

[0023] coating a photoresist on the second surface of the wafer, exposing the photoresist to expose a plurality of first through-hole cavities, and etching the upper electrode layer and the second dielectric layer in the plurality of first through-hole cavities to form a plurality of first contact through-holes;

[0024] removing the photoresist to expose the plurality of second through-hole cavities, filling the plurality of first contact through-holes and the plurality of second through-hole cavities with metal, and cutting the wafer and the plastic encapsulation layer;

[0025] The bonding is broken, and the second carrier and the second bonding material are peeled off to form a plurality of independent deep trench capacitors.

[0026] The deep trench capacitor is mounted on a first surface of a silicon interposer including a through silicon via.

[0027] Furthermore, the etching is preferably a Bosch etching process.

[0028] Furthermore, the cross section of the deep trench array is:

[0029] One of the shapes of circle, square, tripod, hexagon, octagon, cross or a combination thereof.

[0030] Furthermore, the lower electrode layer, the second dielectric layer, and the upper electrode layer are deposited by low-pressure chemical vapor deposition or atomic layer deposition.

[0031] Furthermore, the plastic encapsulation is preferably injection molding, and the material of the plastic encapsulation is preferably epoxy resin.

[0032] Furthermore, mounting the deep trench capacitor array on the first surface of the silicon interposer including the through silicon vias further comprises:

[0033] The deep trench capacitor is electrically connected to a plurality of metal traces in the silicon interposer through the contact vias.

[0034] Compared with the prior art, the present invention has the following advantages:

[0035] 1. The deep trench capacitor provided by the present invention has a simple manufacturing process, low cost, and high compatibility with existing processes.

[0036] 2. The present invention manufactures deep trench capacitors by depositing a metal dielectric layer on a deep trench array formed by etching. During the stacked deposition, the transmission rate of gaseous reagents and products is better, and better film uniformity can be achieved.

[0037] 3. The present invention avoids grooving on the silicon interposer and has better compatibility with through-silicon vias.

[0038] 4. The present invention adopts a plastic packaging method to manufacture deep trench capacitors and integrates them into a silicon interposer, which has higher reliability than traditional deep trench capacitors. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more detailed description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings depict only typical embodiments of the present invention and are not to be considered as limiting the scope thereof. In the drawings, for clarity, identical or corresponding components will be represented by the same or similar reference numerals.

[0040] FIG1 is a schematic structural diagram of a deep trench capacitor structure according to an embodiment of the present invention;

[0041] FIG2 is a schematic flow chart of a method for manufacturing a deep trench capacitor structure according to an embodiment of the present invention; and

[0042] 3a-3m are schematic cross-sectional views of a process for forming a deep trench capacitor structure according to one embodiment of the present invention. DETAILED DESCRIPTION

[0043] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that the various embodiments can be implemented without one or more of the specific details or with other alternative and / or additional methods, materials, or components. In other cases, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the inventive aspects of the present invention. Similarly, for the purpose of explanation, specific quantities, materials, and configurations are described to provide a comprehensive understanding of the embodiments of the present invention. However, the present invention is not limited to these specific details. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0044] In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in various places in this specification are not necessarily all referring to the same embodiment.

[0045] In this specification, unless otherwise specified, the phrases "disposed on," "disposed above," and "disposed above" do not exclude the presence of intermediate components. Furthermore, "disposed on or above" merely indicates the relative positional relationship between two components and, in certain circumstances, such as after reversing the product orientation, can be converted to "disposed below or below," and vice versa.

[0046] In this specification, unless otherwise specified, "first surface" and "second surface" are used only to describe the surfaces of the same component. In addition, "first", "second", and "third" are used only to distinguish and do not include differences in size.

[0047] In this specification, unless otherwise stated, the quantifiers "a" or "an" do not exclude the presence of a plurality of elements.

[0048] It should be noted that the embodiments of the present invention describe the method steps in a specific order, but this is only for the purpose of illustrating the specific embodiment and does not limit the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual needs.

[0049] The technical solutions in the embodiments of the present invention are described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0050] Figure 1 is a schematic diagram of a deep trench capacitor structure according to an embodiment of the present invention. As shown in Figure 1 , the deep trench capacitor structure includes a wafer 12 , a first dielectric layer 13 , an electrode and dielectric layer 14 , a plastic layer 15 , a silicon interposer 19 , and metal traces 20 .

[0051] A plurality of metal traces 20 are arranged inside the silicon interposer 19. In addition, a plurality of through silicon vias (TSVs) are provided inside the silicon interposer.

[0052] The wafer 12, first dielectric layer 13, electrodes and dielectric layer 14, and plastic encapsulation layer 15 form a deep trench capacitor. As shown in FIG1 , deep trenches are formed on the first surface of the wafer. As shown in FIG1 , the deep trench capacitor is configured to be mounted to the first surface of the silicon interposer, i.e., the upper surface of the silicon interposer 19 shown in FIG1 .

[0053] The wafer is provided with a plurality of contact vias, and the deep trench capacitor is electrically connected to the plurality of metal traces in the silicon interposer through the contact vias. In one embodiment of the present invention, the material of the wafer is preferably one of silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or a combination thereof.

[0054] As shown in Figure 1, the first dielectric layer 13, the electrode and dielectric layer 14, and the plastic encapsulation layer 15 are arranged on the first surface of the wafer, that is, the upper surface of the wafer 12 shown in Figure 1. In one embodiment of the present invention, the first dielectric layer is preferably one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0055] The electrode and dielectric layer 14 includes an upper electrode, a lower electrode, and a second dielectric layer. In one embodiment of the present invention, the upper and lower electrodes are preferably selected from the group consisting of copper, tungsten, aluminum, a copper alloy, and titanium, or a combination thereof. In one embodiment of the present invention, the second dielectric layer is preferably made of a material with a high dielectric constant, such as aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, and lanthanum oxide, or a combination thereof.

[0056] As shown in Figure 1 , the plastic encapsulation layer covers the first dielectric layer, the upper electrode, the lower electrode, and the second dielectric layer. In one embodiment of the present invention, the plastic encapsulation is preferably injection molding, and the plastic encapsulation material is preferably epoxy resin.

[0057] Figure 2 is a schematic flow diagram of a method for manufacturing a deep trench capacitor structure according to one embodiment of the present invention. Figures 3a-3m are schematic cross-sectional diagrams of a process for forming a deep trench capacitor structure according to one embodiment of the present invention. The method for manufacturing a deep trench capacitor structure according to the present invention will be described below with reference to Figures 2 and 3.

[0058] First, the second surface of the wafer is bonded to the first surface of the first carrier by a first bonding material. As shown in FIG3a, the wafer 12 is bonded to the first surface of the first carrier 10 by a first bonding material 11. In one embodiment of the present invention, the material of the wafer is preferably one of silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or a combination thereof. In one embodiment of the present invention, the first bonding material is a bonding adhesive, which can be a bonding agent from TMAT, BSI, 3M (excluding separation) and DuPont. In one embodiment of the present invention, the first carrier is preferably glass or a silicon wafer.

[0059] Next, the first surface of the wafer is etched to form a deep trench array region. As shown in FIG3b , the wafer is etched to form a deep trench array, i.e., a wafer column array. In one embodiment of the present invention, the etching is preferably a Bosch etching process. In one embodiment of the present invention, the cross-section of the deep trench array can be one of circular, square, tripod, hexagonal, octagonal, cross-shaped, or a combination thereof.

[0060] Next, a first dielectric layer is thermally grown in the deep trench array region as a protective layer. As shown in FIG3c , a first dielectric layer 14 is thermally grown on the deep trench array. In one embodiment of the present invention, the first dielectric layer 14 is formed by low-pressure chemical vapor deposition or atomic layer deposition. In one embodiment of the present invention, the first dielectric layer is preferably silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0061] Next, a lower electrode layer, a second dielectric layer, and an upper electrode layer are sequentially deposited on the first surface of the first dielectric layer. As shown in Figure 3d, the electrode and dielectric layer 14 includes an upper electrode, a lower electrode, and a second dielectric layer. In one embodiment of the present invention, the upper and lower electrodes are preferably selected from copper, tungsten, aluminum, a copper alloy, and titanium, or a combination thereof. In one embodiment of the present invention, the second dielectric layer is preferably selected from aluminum oxide and zirconium oxide, or a combination thereof. In one embodiment of the present invention, the lower electrode layer, the second dielectric layer, and the upper electrode layer are deposited by low-pressure chemical vapor deposition or atomic layer deposition.

[0062] Next, the first dielectric layer, the lower electrode layer, the second dielectric layer, and the upper electrode layer are etched to form a plurality of first deep trench capacitor arrays. As shown in FIG3e , the first dielectric layer, the lower electrode layer, the second dielectric layer, and the upper electrode layer are separated by etching. In one embodiment of the present invention, the etching is preferably a Bosch etching process.

[0063] Next, the region where the plurality of first deep trench capacitor arrays are located is plastic-encapsulated to form a plastic-encapsulated deep trench capacitor array. As shown in FIG3f , a plastic encapsulation layer 15 covers the first dielectric layer, the upper electrode, the lower electrode, and the second dielectric layer. In one embodiment of the present invention, the plastic encapsulation is preferably performed by injection molding, and the plastic encapsulation material is preferably epoxy resin.

[0064] Next, the bonding is broken, and the first carrier and the first bonding material are peeled off. As shown in FIG3g , the first carrier 10 and the first bonding material 11 are removed. In one embodiment of the present invention, the bonding is broken by mechanical separation, thermal sliding or laser separation.

[0065] Next, the plastic-encapsulated deep trench capacitor array is flipped over, and the first surface of the plastic encapsulation layer is bonded to the first surface of the second carrier wafer via a second bonding material. As shown in FIG3h , the deep trench capacitor array is bonded to the first surface of the second carrier wafer 17 via a second bonding material 16. In one embodiment of the present invention, the second bonding material is a bonding adhesive, which can be a bonding agent from TMAT, BSI, 3M (excluding separation), and DuPont. In one embodiment of the present invention, the second carrier wafer is preferably glass or silicon wafer.

[0066] Next, the second surface of the wafer is etched to form a plurality of through-hole cavities. As shown in FIG3i , through-hole cavities A, B, C, and D are formed by etching. In one embodiment of the present invention, the etching is preferably a Bosch etching process.

[0067] Next, photoresist is coated on the second surface of the wafer and exposed to expose a plurality of first through-hole cavities. The upper electrode layer and the second dielectric layer within the plurality of first through-hole cavities are then etched to form a plurality of first contact through-holes. As shown in Figure 3j, A and C are first through-holes. After etching the upper electrode layer and the second dielectric layer within the first through-hole cavities A and C, the surfaces of through-holes A and C become the lower electrode film layer. In one embodiment of the present invention, the etching process is preferably a Bosch etching process.

[0068] Next, the photoresist is removed, exposing the plurality of second through-hole cavities. Metal is then filled into the plurality of first contact through-holes and the plurality of second through-hole cavities, and the wafer and the plastic encapsulation layer are cut. As shown in Figure 3k, B and D are second through-holes, and the surfaces of through-holes B and D form the top electrode film layer. In one embodiment of the present invention, the filler metal is preferably selected from copper, tungsten, aluminum, a copper alloy, titanium, or a combination thereof.

[0069] Next, the bonding is removed, and the second carrier and the second bonding material are peeled off to form a plurality of independent deep trench capacitors. As shown in FIG31 , the second carrier 17 and the second bonding material 16 are removed. In one embodiment of the present invention, the bonding is removed by mechanical separation, thermal slip, or laser separation.

[0070] Finally, the deep trench capacitor is mounted to the first surface of the silicon interposer containing TSVs. As shown in Figure 3m, the deep trench capacitor is arranged on the silicon interposer 19 containing TSVs in an SMD (Surface Mounted Device) manner. The deep trench capacitor is electrically connected to multiple metal traces 20 in the silicon interposer through the contact vias. In one embodiment of the present invention, the silicon interposer has multiple TSVs.

[0071] The present invention provides a deep trench capacitor structure and a manufacturing method thereof. By depositing electrodes and a dielectric layer on a deep trench array formed by etching, a deep trench capacitor is manufactured by plastic packaging and integrated into a silicon interposer. This structure has better compatibility with through-silicon vias, a simpler manufacturing process, and a higher degree of compatibility with existing processes.

[0072] Although various embodiments of the present invention have been described above, it should be understood that they are presented by way of example only and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications, and variations may be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely in accordance with the appended claims and their equivalents.

Claims

1. A deep trench capacitor structure, characterized in that: include: A silicon interposer, wherein the silicon interposer is configured to arrange a plurality of metal traces therein; a deep trench capacitor configured to be attached to the first surface of the silicon interposer; The deep trench capacitor comprises a wafer, a deep trench formed on a first surface of the wafer, a plurality of contact through holes arranged in the wafer, and a first dielectric layer, an upper electrode, a lower electrode, a second dielectric layer and a plastic packaging layer arranged on the first surface of the wafer; The deep trench capacitor is electrically connected to the plurality of metal traces in the silicon interposer through the contact vias.

2. The deep trench capacitor structure according to claim 1, characterized in that: The silicon interposer has a plurality of through silicon vias therein.

3. The deep trench capacitor structure according to claim 1, wherein: The plastic encapsulation layer covers the first dielectric layer, the upper electrode, the lower electrode and the second dielectric layer.

4. The deep trench capacitor structure according to claim 1, wherein: The second dielectric layer is preferably made of one of aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, and lanthanum oxide, or a combination thereof.

5. A method for manufacturing a deep trench capacitor structure, characterized in that: The steps include: bonding the second surface of the wafer to the first surface of the first carrier through the first bonding material; Etching the first surface of the wafer to form a deep trench array region; Thermally grow a first dielectric layer as a protective layer in the deep trench array region; Depositing a lower electrode layer, a second dielectric layer, and an upper electrode layer in sequence on a first surface of the first dielectric layer; Etching the first dielectric layer, the lower electrode layer, the second dielectric layer and the upper electrode layer to form a plurality of first deep trench capacitor arrays; Plastic-sealing the regions where the plurality of first deep trench capacitor arrays are located to form a plastic-sealed deep trench capacitor array; Debonding, peeling off the first carrier sheet and the first bonding material; Turning over the plastic-encapsulated deep trench capacitor array, and bonding the first surface of the plastic encapsulation layer to the first surface of the second carrier through a second bonding material; etching the second surface of the wafer to form a plurality of through-hole cavities; Coating a photoresist on the second surface of the wafer, exposing the photoresist to expose a plurality of first through-hole cavities, and etching the upper electrode layer and the second dielectric layer in the plurality of first through-hole cavities to form a plurality of first contact through-holes; Removing the photoresist to expose a plurality of second through-hole cavities, filling metal in the plurality of first contact through-holes and the plurality of second through-hole cavities, and cutting the wafer and the plastic encapsulation layer; The bonding is broken, and the second carrier and the second bonding material are peeled off to form a plurality of independent deep trench capacitors. The deep trench capacitor is mounted to a first surface of a silicon interposer including a through silicon via.

6. The manufacturing method according to claim 5, characterized in that: The etching is preferably a Bosch etching process.

7. The manufacturing method according to claim 5, characterized in that: The cross section of the deep trench array is: One of the shapes of circle, square, tripod, hexagon, octagon, cross or a combination thereof.

8. The manufacturing method according to claim 5, characterized in that: The lower electrode layer, the second dielectric layer and the upper electrode layer are deposited by low pressure chemical vapor deposition or atomic layer deposition.

9. The manufacturing method according to claim 5, characterized in that: The plastic encapsulation is preferably injection molding, and the material of the plastic encapsulation is preferably epoxy resin.

10. The manufacturing method according to claim 5, characterized in that: Mounting the deep trench capacitor array to the first surface of the silicon interposer including through silicon vias further comprises: The deep trench capacitor is connected to a plurality of gold strips in the silicon interposer through the contact through hole. It is a wiring electrical connection.

Images