Chip packaging structure and packaging method therefor, and circuit board assembly and terminal

Abstract

The embodiments of the present application relate to the technical field of semiconductors. Provided are a chip packaging structure and a packaging method therefor, and a circuit board assembly and a terminal, which are used for reducing the size of a chip packaging structure. The chip packaging structure comprises a substrate, a first rewiring layer, a first device, a second rewiring layer and at least one deep trench capacitor, wherein a plurality of accommodating cavities are provided on a first side of the substrate; each deep trench capacitor is arranged on the first side of the substrate and extends into at least two accommodating cavities; each protrusion of the deep trench capacitor extends into one accommodating cavity; the first rewiring layer and the second rewiring layer are arranged on two opposite sides of the substrate; the first rewiring layer is directly coupled to the deep trench capacitor; and the first device is arranged on the side of the first rewiring layer away from the substrate, and is coupled to the deep trench capacitor by means of the first rewiring layer. By directly forming a deep trench capacitor in a substrate, the layout area originally required for placing an independent capacitor device is reduced, thereby reducing the size of the chip packaging structure, and having a relatively low process accuracy requirement and a high yield.

Description

Chip packaging structure and packaging method thereof, circuit board assembly, and terminal

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on December 18, 2023, with application number 202311754868.6 and invention name “Chip packaging structure and its packaging method, circuit board assembly, terminal”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a chip packaging structure and a packaging method thereof, a circuit board assembly, and a terminal. Background Art

[0003] With the rapid increase in the popularity of electronic devices and the booming electronic device market, there is an increasing demand for electronic products to evolve towards miniaturization and thinness while maintaining high performance, multi-functions, high reliability, and convenience. This demand places higher demands on chip packaging, which requires better, lighter, thinner packaging, higher packaging density, better electrical and thermal performance, higher reliability, and higher cost-performance.

[0004] In some application scenarios, chip packaging structures inevitably need to integrate passive components such as capacitors. However, how to minimize the size of the chip packaging structure while integrating capacitors remains a key issue that continues to be studied by those skilled in the art.

[0005] Summary of the Invention

[0006] Embodiments of the present application provide a chip packaging structure and a packaging method thereof, a circuit board assembly, and a terminal, which are used to reduce the size of the chip packaging structure while taking into account the yield rate.

[0007] To achieve the above objectives, this application adopts the following technical solutions:

[0008] A first aspect of an embodiment of the present application provides a chip packaging structure, comprising a substrate, a first redistribution layer, a first device, a second redistribution layer, and at least one deep trench capacitor. A first side of the substrate is provided with multiple accommodating cavities, the deep trench capacitors are disposed on the first side of the substrate, and the deep trench capacitors extend into at least two of the accommodating cavities; the first redistribution layer is disposed on the first side of the substrate and directly coupled to the deep trench capacitors; the first device is disposed on a side of the first redistribution layer away from the substrate, and the first device is coupled to the deep trench capacitors via the first redistribution layer; and the second redistribution layer is disposed on a second side of the substrate away from the first redistribution layer.

[0009] The chip packaging structure provided by the embodiment of the present application has trench capacitors encapsulated inside, but the trench capacitors extend into the substrate, and there is no need to reserve space separately for deep trench capacitors in the thickness direction. Therefore, the trench capacitors are arranged in the substrate to reduce the size of the chip packaging structure along the thickness direction. Moreover, the number of devices arranged inside the substrate is usually relatively small, and there is sufficient free space inside the substrate to accommodate deep trench capacitors, which will not increase the size in the horizontal direction alone. Therefore, the trench capacitors are arranged in the substrate to reduce the size of the chip packaging structure along the horizontal direction. In other words, the trench capacitors are arranged in the substrate, which reduces the layout area originally required for placing independent capacitor devices, thereby reducing the size of the chip packaging structure. On this basis, a accommodating cavity is opened on the substrate, and deep trench capacitors are formed directly on the surface of the substrate and are accommodated by the accommodating cavity. In the chip packaging structure of the present application, when preparing the deep trench capacitors, the shape of the deep trench capacitors matches the shape of the accommodating cavity, and each accommodating cavity accommodates a protrusion of a deep trench capacitor. There is no requirement for the dimensional accuracy of the accommodating cavity, and the product yield is high. Moreover, a first redistribution layer directly coupled to the deep trench capacitor can be formed directly on the surface of the deep trench capacitor, without the need to perform the steps of pre-processing of the external device packaging, and without the need to form other transfer structures, which can reduce the process. If the prepared capacitor device is integrated and packaged in the substrate, the entire capacitor device is placed in a accommodating cavity, and the size of the accommodating cavity formed on the substrate needs to be strictly matched with the capacitor device, the precision requirement is relatively high, and the yield loss is large. Moreover, after the capacitor device is integrated in the substrate, it is still necessary to perform pre-processing before packaging to prepare the first redistribution layer, and the process is complicated. Therefore, the chip packaging structure provided in the embodiment of the present application can reduce the size of the chip packaging structure on the basis of taking into account the yield.

[0010] In one possible implementation, the deep trench capacitor is in contact with the inner surface of the accommodating cavity, which can improve the problem caused by the gap between the deep trench capacitor and the inner surface of the accommodating cavity.

[0011] In one possible implementation, a deep trench capacitor includes a first electrode and a second electrode, wherein the first electrode is coupled to a first device, and the second electrode is coupled to a first ground network of a first redistribution layer. The first electrode is coupled to the first device, and the second electrode is coupled to the ground network, and the deep trench capacitor can function as a filter capacitor.

[0012] In one possible implementation, a deep trench capacitor includes a first electrode and a second electrode, wherein the first electrode is coupled to the first device and the second electrode is coupled to the second ground network of the second redistribution layer. The first electrode is coupled to the first device and the second electrode is coupled to the ground network, and the deep trench capacitor can function as a filter capacitor.

[0013] In one possible implementation, the deep trench capacitor includes a first electrode and a second electrode, wherein the first electrode is coupled to the first device, and the second electrode is coupled to both the first ground network of the first redistribution layer and the second ground network of the second redistribution layer. The second electrode is coupled to the first redistribution layer and the second redistribution layer, respectively, which is equivalent to the first redistribution layer and the second redistribution layer being coupled via the second electrode. The second electrode can act as a via in the substrate, interconnecting the first ground network and the second ground network, thereby reducing the number of vias in the substrate, thereby reducing the area of ​​the chip packaging structure and reducing costs.

[0014] In one possible implementation, the first electrode and the second electrode form at least two protrusions, and the deep trench capacitor extends into at least two accommodating cavities. Specifically, the protrusions extend into the accommodating cavities. The protrusions and accommodating cavities correspond one to one, which can reduce the difficulty of the process.

[0015] In one possible implementation, the second electrode is directly coupled to the first ground network. In this application, a trench capacitor is formed in the substrate by fabrication integration, which can reduce the number of steps and the thickness of the chip packaging structure compared to placing the capacitor in the substrate by integration.

[0016] In one possible implementation, the accommodating cavity extends through the substrate, and the second electrode is directly coupled to the second ground network. In this application, a trench capacitor is formed in the substrate using a fabrication integration approach. Compared to placing the capacitor in the substrate using an integrated approach, this can reduce the number of steps and the thickness of the chip packaging structure.

[0017] In one possible implementation, the deep trench capacitor is arranged along the edge of the substrate. By placing the deep trench capacitor at the edge of the substrate, the layout of the central area can be maintained, and the change in the overall layout of the chip packaging structure is relatively small. Moreover, when the second electrode T2 of the deep trench capacitor is coupled to both the first ground network and the second ground network, the deep trench capacitor, on the basis of its own capacitance function, can also perform electromagnetic shielding on the external radiation of the package intermediate layer device, that is, the deep trench capacitor has an external radiation suppression effect. At the location where the deep trench capacitor is provided, the chip packaging structure can sputter a conformal shielding layer on the side surface without the need for a special process, thereby reducing the packaging cost and simplifying the packaging steps.

[0018] In one possible implementation, the chip package structure further includes a second device and a third device; the second and third devices are disposed within the substrate, with at least one deep trench capacitor positioned between the second and third devices. In this manner, the deep trench capacitor can provide cavity shielding and internal isolation, shielding electromagnetic interference between the second and third devices. For example, if the second device is an interference source and the third device is a recipient, the deep trench capacitor can shield the second device from electromagnetic interference with the third device.

[0019] In one possible implementation, the second device and the third device have different magnetic field strengths, which may generate electromagnetic interference between the two devices. However, the presence of the deep trench capacitor can shield the electromagnetic interference of the second device on the third device.

[0020] In one possible implementation, the second device includes a radio frequency transmitting device, and the third device includes a radio frequency receiving device. This is a common scenario.

[0021] In one possible implementation, the second device includes a digital circuit device, and the third device includes an analog circuit device. This is a common scenario.

[0022] In one possible implementation, the magnetic field strength of the second device is greater than or equal to 50dBμV / m, and the magnetic field strength of the third device is less than 50dBμV / m. Magnetic field strengths above 50dBμV / m can generate electromagnetic interference. This application provides grounding capacitors between devices that may generate electromagnetic interference, which can optimize the performance of the chip packaging structure.

[0023] In one possible implementation, the magnetic field strength of the first device is less than 50dBμV / m. By disposing a non-high-radiation device on the side of the first redistribution layer away from the substrate, the surface of the chip package structure on the side where the first device is located can be shielded, simplifying the structure and manufacturing process.

[0024] In a possible implementation, the first device includes a radio frequency receiving device or an analog circuit device. This is a common scenario.

[0025] In one possible implementation, the magnetic field strength of the first device is greater than or equal to 50dBμV / m, and the chip package structure further includes a shielding cover and a plastic encapsulation layer. The shielding cover is buckled onto the first redistribution layer, the first device is located within the shielding cover, and the plastic encapsulation layer covers the shielding cover and the first redistribution layer. Even if a high-radiation device is required above the first redistribution layer, by providing a shielding cover with a partial shielding function above the high-radiation first device, the first device is electromagnetically protected by the shielding cover. There is still no need to provide a shielding layer on the outer surface of the chip package structure, and the overall external radiation level of the package can still be controlled.

[0026] In one possible implementation, the first device includes a radio frequency transmitting device or a digital circuit device; the chip package structure further includes a shielding cover and a plastic encapsulation layer, the shielding cover being buckled onto the first redistribution layer, the first device being positioned within the shielding cover, and the plastic encapsulation layer covering the shielding cover and the first redistribution layer. Even if a high-radiating device is required above the first redistribution layer, by providing a shielding cover with a partial shielding function above the high-radiating first device, the first device is electromagnetically protected by the shielding cover, eliminating the need for a shielding layer on the outer surface of the chip package structure, and still achieving controllable external radiation levels from the overall package.

[0027] In one possible implementation, the shielding cover includes cross-arranged bonding wires, which are coupled to the first ground network of the first redistribution layer. This is a shielding cover structure with a simple structure and mature manufacturing process.

[0028] In one possible implementation, the deep trench capacitor has a capacitance greater than or equal to 500pF. Because capacitors greater than 500pF in a chip package are relatively large in both the thickness and horizontal dimensions, they significantly impact the package area. Therefore, integrating capacitors greater than 500pF into the substrate can significantly reduce the chip package area.

[0029] In one possible implementation, the chip package structure further includes a fourth device and / or solder balls, both of which are disposed on a side of the second redistribution layer remote from the substrate and are coupled to the second redistribution layer. Devices may also be disposed on the side of the second redistribution layer remote from the substrate, allowing for various applications.

[0030] According to a second aspect of an embodiment of the present application, a circuit board assembly is provided, comprising a circuit board and a chip packaging structure. The chip packaging structure is arranged on the circuit board, and the chip packaging structure comprises the chip packaging structure of any one of the first aspects.

[0031] The circuit board assembly provided in the second aspect of the embodiment of the present application includes the chip packaging structure of the first aspect, and its beneficial effects are the same as those of the chip packaging structure, which will not be repeated here.

[0032] According to a third aspect of an embodiment of the present application, a terminal is provided, comprising a rear shell and a circuit board assembly, wherein the circuit board assembly is disposed in the rear shell and comprises the circuit board assembly of the second aspect.

[0033] The terminal provided in the third aspect of the embodiment of the present application includes the circuit board assembly of the second aspect, and its beneficial effects are the same as those of the circuit board assembly, which will not be repeated here.

[0034] In a fourth aspect of an embodiment of the present application, a packaging method for a chip packaging structure is provided, including: forming a plurality of accommodating cavities on a first side of a substrate; forming deep trench capacitors on the first side of the substrate, the deep trench capacitors extending into at least two accommodating cavities; forming a first redistribution layer on the first side, the first redistribution layer being directly coupled to the deep trench capacitors; forming a second redistribution layer on a second side of the substrate away from the first redistribution layer; bonding a first device on a side of the first redistribution layer away from the substrate, the first device being coupled to the deep trench capacitors through the first redistribution layer.

[0035] The packaging method of the chip packaging structure provided in the fourth aspect of the embodiment of the present application has the same beneficial effects as the chip packaging structure in the first aspect, and will not be repeated here.

[0036] In one possible implementation, a deep trench capacitor is formed on the first side of a substrate, including: forming a second electrode on the first side of the substrate, the second electrode extending into a receiving cavity and conforming to the inner surface of the cavity; forming a capacitor dielectric layer on the surface of the second electrode; and forming a first electrode on the surface of the capacitor dielectric layer. This process is simple and requires relatively low precision. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] FIG1 is a schematic diagram of the structure of a terminal provided in an embodiment of the present application;

[0038] FIG2 is a cross-sectional view of a chip packaging structure provided in an embodiment of the present application;

[0039] FIG3 is a cross-sectional view of a chip packaging structure provided in an embodiment of the present application;

[0040] FIG4A is a cross-sectional view of a chip packaging structure provided in an embodiment of the present application;

[0041] FIG4B is a cross-sectional view of a chip packaging structure provided in an embodiment of the present application;

[0042] FIG4C is a topological circuit diagram of a deep trench capacitor provided in an embodiment of the present application;

[0043] FIG5 is a cross-sectional view of a chip packaging structure provided in an embodiment of the present application;

[0044] FIG6 is a top view of a deep trench capacitor arrangement provided in an embodiment of the present application;

[0045] FIG7A is a cross-sectional view of a chip packaging structure provided in an embodiment of the present application;

[0046] FIG7B is a cross-sectional view of a chip packaging structure provided in an embodiment of the present application;

[0047] FIG7C is a layout diagram of a device and a deep trench capacitor provided in an embodiment of the present application;

[0048] FIG8 is a cross-sectional view of a chip packaging structure provided in an embodiment of the present application;

[0049] FIG9 is a cross-sectional view of a chip packaging structure provided in an embodiment of the present application;

[0050] FIG10 is a flow chart of a chip packaging method provided in an embodiment of the present application;

[0051] 11A-11G are diagrams showing a process for preparing a chip packaging structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0053] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature qualified as "second," "first," etc. may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0054] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left", and "right" may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative descriptions and clarifications, and may change accordingly according to changes in the orientation of the components in the drawings.

[0055] In the embodiments of this application, unless otherwise specified or limited, the term "connected" should be understood broadly. For example, "connected" can mean fixed connection, detachable connection, or integration; it can mean direct connection or indirect connection through an intermediate medium. In addition, the term "coupled" can mean direct electrical connection or indirect electrical connection through an intermediate medium. The term "contacting" can mean direct contact or indirect contact through an intermediate medium.

[0056] In the embodiments of the present application, "and / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0057] The present application provides a terminal. The terminal is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, or a financial terminal product. Among them, consumer electronic products include mobile phones, tablet computers, laptop computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (for example, smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, servers, etc. Home electronic products include smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (for example, soymilk machines, sweeping robots), switches, etc. Vehicle-mounted electronic products include car navigation systems, car DVDs, etc. Financial terminal products include ATM machines, self-service terminals, etc. The terminal can also be a radio frequency front end, an application processor, a power supply, etc. The present application embodiment does not impose any special restrictions on the specific form of the above-mentioned terminal. For the convenience of explanation, the following embodiments are all illustrated by taking a mobile phone as an example.

[0058] FIG1 is a schematic structural diagram of a terminal provided in an embodiment of the present application.

[0059] As shown in FIG1 , the terminal 1 mainly includes a cover plate 10 , a display module 20 , a middle frame 30 and a rear shell (or battery cover, housing) 40 .

[0060] The display module 20 has a light-emitting side through which the display image can be viewed and a back side opposite the light-emitting side. The cover 10 is located on the light-emitting side of the display module 20, and the rear housing 40 is located on the back side of the display module 20. The display module 20 includes an active area (AA) for displaying images, which includes multiple sub-pixels (SP).

[0061] In one possible embodiment, the display module 20 is a liquid crystal display (LCD). Therefore, the terminal 1 further includes a backlight unit (BLU) located on the back of the LCD. The BLU can provide light to the LCD so that each sub-pixel in the LCD can emit light to display an image.

[0062] In another possible embodiment, the display module 20 is a self-luminous display module such as an organic light emitting diode (OLED) display module, an active-matrix organic light-emitting diode (AMOLED) display module, a mini organic light-emitting diode (Mini-OLED) display module, a micro light-emitting diode (Micro-LED) display module, a micro organic light-emitting diode (Micro-OLED) display module, or a quantum dot light emitting diode (QLED) display module. In this case, the display module 20 can be a rigid display module or a flexible display module.

[0063] The middle frame 30 is located between the display module 20 and the rear housing 40. The space between the middle frame 30 and the rear housing 40 creates an installation space for electronic components such as a printed circuit board (PCB), a battery, a receiver, a speaker, and a camera. The PCB can integrate electronic components such as the terminal's main controller, storage unit, antenna module, and power management module. The battery provides power to these components, including the display module 20, the PCB, the receiver, the speaker, and the camera.

[0064] The cover plate 10 is located on the side of the display module 20 away from the middle frame 30. The cover plate 10 is a light-transmitting structure and serves as a protective layer covering the display surface of the display module 20. In this way, light transmitted by the display surface of the display module 20 can pass through the cover plate 10 and be received by the user. The display surface of the display module 20 involved in the embodiment of the present application is the side of the display module 20 used to display the image to the user. The display surface of the display module 20 is located on the same side as the light-emitting side of the display module 20, and the back side of the display module 20 refers to the side opposite to the display surface of the display module 20. After the display module 20 is assembled with the cover plate 10 and other components, the display module provided in the embodiment of the present application can be formed.

[0065] In some embodiments, the terminal 1 also includes a processor (center processing unit, CPU) chip, a dynamic random access memory (dynamic random access memory, DRAM) chip, a radio frequency chip, a radio frequency power amplifier (power amplifier, PA) chip, a system-level chip (system on a chip, SOC), a power management chip (power management integrated circuits, PMIC), a storage chip (such as high bandwidth memory (high bandwidth memory, HBM)), an audio processor chip, a touch screen control chip, NAND flash (flash memory), an image sensor chip and other chips arranged on the PCB. The PCB is used to carry the above chips and complete signal interaction with the above chips.

[0066] As chips in current terminals are moving towards deep trench capacitor (DTC) density and miniaturization, to meet the development trend of terminal miniaturization, integration, ultra-thinness, and diversified functions, chips in terminal 1 are often integrated in the form of system-in-a-package (SiP). To achieve higher DTC density, current system-in-package (SIP) requires continuous improvement in packaging and chip integration technology. For example, more integrated integrated passive devices (IPD) replace discrete surface mounted devices (SMD) resistors, capacitors, and inductors, finer redistribution layers (RDL) interconnects replace organic substrates, and multi-layer package stacking technology is used.

[0067] FIG2 is a cross-sectional view of a chip packaging structure provided in an embodiment of the present application.

[0068] In some embodiments, as shown in FIG. 2 , the chip package structure includes a first redistribution layer RDL1 , a second redistribution layer RDL2 , a substrate, a chip D, discrete passive components (eg, capacitors, resistors, inductors), solder balls, and a shielding layer.

[0069] The first redistribution layer RDL1 and the second redistribution layer RDL2 are vertically interconnected through vias. The vias may include, for example, through molding vias (TMVs), through glass vias (TGVs), and through silicon vias (TSVs).

[0070] A chip D may be provided on the side of the first redistribution layer RDL1 away from the substrate, a chip D may also be provided on the side of the second redistribution layer RDL2 away from the substrate, or a chip D may also be provided inside the substrate. The chip D is coupled to the solder ball through the first redistribution layer RDL1 and / or the second redistribution layer RDL2.

[0071] Discrete passive components can be provided on the side of the first redistribution layer RDL1 away from the substrate, and on the side of the second redistribution layer RDL2 away from the substrate. Discrete passive components can also be provided inside the substrate. The passive components are coupled to the redistribution layer through SMD technology.

[0072] The solder balls are used to electrically connect to the PCB in the terminal 1, thereby achieving electrical interconnection between the chip package structure and the PCB. Shielding layers are formed on the sides and top of the chip package structure through a sputtering process, and the shielding layers are used to electromagnetically shield external radiation.

[0073] In the chip package structure shown in Figure 2, the capacitors used for filtering and matching are typically ceramic capacitors. Ceramic capacitors are tall and cannot be thinned, resulting in a thicker overall chip package. Furthermore, a specialized process is required to form a conformal shielding layer on the surface of the chip package, increasing the cost of the package.

[0074] FIG3 is a cross-sectional view of a chip packaging structure provided in an embodiment of the present application.

[0075] As shown in Figure 3, the passive components mounted via SMD technology in the chip package are replaced with thinner integrated product development (IPD) devices. IPD planar plate (metal insulator metal, MIM) capacitors can achieve picofarad-level capacitance. Furthermore, thinner DTCs can replace SMD capacitors in the nF range and above to achieve filtering.

[0076] The MIM capacitor includes a lower planar electrode, an insulating layer, and an upper planar electrode stacked in sequence in a direction away from the substrate. The DTC includes a lower electrode, an insulating layer, and an upper electrode stacked in sequence in a direction away from the substrate. Both the lower electrode and the upper electrode are bent into a groove shape.

[0077] While replacing SMD capacitors (nF and above) with DTCs can reduce the height of the chip package, the horizontal area occupied by the DTCs increases, leading to an increase in package area. Furthermore, a specialized process is required to form a conformal shielding layer on the chip package surface, increasing packaging costs.

[0078] 4A and 4B are cross-sectional views of a chip packaging structure provided in an embodiment of the present application, and FIG. 4C is a topological circuit diagram of a deep trench capacitor provided in an embodiment of the present application.

[0079] An embodiment of the present application provides a chip packaging structure, as shown in FIG4A , the chip packaging structure includes: a substrate, a first redistribution layer RDL1 , a first device D1 , a second redistribution layer RDL2 , and at least one deep trench capacitor DTC.

[0080] The substrate can be a glass substrate, a silicon substrate, a ceramic substrate, etc. The embodiment of the present application does not limit the material of the substrate, and the substrates in the related art are all applicable to the embodiment of the present application.

[0081] A first redistribution layer RDL1 is disposed on a first side of the substrate, and a second redistribution layer RDL2 is disposed on a second side of the substrate away from the first redistribution layer RDL. That is, the first redistribution layer RDL1 and the second redistribution layer RDL2 are disposed on opposite sides of the substrate.

[0082] The first redistribution layer RDL1 includes at least one metal interconnect layer, and the second redistribution layer RDL2 may also include at least one metal interconnect layer. Figure 4A illustrates an example in which both the first redistribution layer RDL1 and the second redistribution layer RDL2 include multiple metal interconnect layers, with an insulating dielectric layer disposed between adjacent metal interconnect layers. This embodiment of the present application does not limit the structures of the first redistribution layer RDL1 and the second redistribution layer RDL2; structures in related art are applicable to this embodiment.

[0083] In some embodiments, the chip packaging structure further includes a via extending through the substrate and coupled to the first redistribution layer RDL1 and the second redistribution layer RDL2, respectively. Depending on the substrate material, the via may be, for example, a TMV, TSV, or TGV. The present embodiment does not limit the structure of the via; the via may be used to interconnect the first redistribution layer RDL1 and the second redistribution layer RDL2.

[0084] The first device D1 is disposed on a side of the first redistribution layer RDL1 away from the substrate, and the first device D1 is coupled to the first redistribution layer RDL1. Of course, one or more first devices D1 may be disposed on the side of the first redistribution layer RDL1 away from the substrate. In the case where multiple first devices D1 are disposed on the side of the first redistribution layer RDL1 away from the substrate, the functions of the multiple first devices D1 may be the same, may not be completely the same, or may be completely different.

[0085] The first device D1 can be a digital chip, the first device D1 can also be an analog chip, and the first device D1 can be a chip with any function in the terminal 1. For example, at least one transistor is integrated on the first device D1, and the transistor here can be, for example, a field effect transistor (FET). The field effect transistor can include a planar transistor such as a metal oxide semiconductor field effect transistor (MOSFET) or a junction field effect transistor (JFET), and can also include a fin field effect transistor (FinFET), a gate all around field effect transistor (GAAFET), or a fork sheet field effect transistor (fork sheet FET or FSFET). The embodiments of the present application are not limited to this.

[0086] Of course, in the embodiment of the present application, the first device D1 can be a bare chip (die), the first device can also be a packaged chip (chip), the first device D1 can also be a sealed chip assembly, and the first device D1 can also be a device element.

[0087] For example, the first device D1 can be a radio frequency transmitting device (such as a power amplifier, etc.), a radio frequency receiving device (such as a low noise amplifier, etc.), a digital circuit device (such as an application processor, a memory chip, etc.), or an analog circuit device (such as an operational amplifier, a sensor, etc.).

[0088] The chip packaging structure further includes a first plastic layer, which is disposed on a side of the first redistribution layer RDL1 away from the substrate and covers the first device D1. The material of the first plastic layer may be, for example, molding compound or insulating material.

[0089] In some embodiments, a first side of the substrate defines a plurality of accommodating cavities. A deep trench capacitor (DTC) is disposed on the first side of the substrate and extends into at least two of the cavities. A first redistribution layer (RDL1) is disposed on the first side of the substrate and directly coupled to the deep trench capacitor (DTC). The deep trench capacitor (DTC) is coupled to the first device (D1) via the first redistribution layer (RDL1).

[0090] By adjusting the capacitance of the deep trench capacitor (DTC), the DTC can provide filtering and RF impedance matching functions for the first device D1. For example, deep trench capacitors (DTCs) with capacitance in the picofarad range are often used for RF impedance matching, while those with capacitance in the nanofarad and microfarad ranges are often placed near power supply networks to filter power supply noise.

[0091] For example, a deep trench capacitor DTC has a bent protrusion, and the receiving cavity is used to accommodate the protrusion of the deep trench capacitor DTC (the portion of the deep trench capacitor DTC located in the receiving cavity). Each deep trench capacitor DTC has multiple protrusions, each of which occupies a receiving cavity on the substrate, and each receiving cavity accommodates a protrusion. This can reduce the process difficulty.

[0092] In some embodiments, the deep trench capacitor DTC includes a first electrode T1 , a second electrode T2 , and a capacitor dielectric layer T3 located between the first electrode T1 and the second electrode T2 .

[0093] For example, as shown in FIG4A , the second electrode T2 forms at least two protrusions, and the protrusions extend into the accommodating cavity, so that the deep trench capacitor DTC extends into the accommodating cavity.

[0094] In some embodiments, the first electrode T1 and the first electrode T2 are stacked to form the above-mentioned raised portion. As shown in FIG4A , the portion of the first electrode T1 located within the substrate is surrounded by a groove, and the groove is filled with an insulating dielectric layer. In other embodiments, the portion of the first electrode T1 located within the substrate is a solid structure and is not filled with an insulating dielectric layer. Of course, the deep trench capacitor DTC provided in the embodiment of the present application is only an illustration and is not intended to be limiting. The deep trench capacitor DTC in the related art is applicable to the embodiment of the present application.

[0095] The material of the capacitor dielectric layer T3 includes, for example, polyimide (PI), tetraethyl orthosilicate (C8H20O4Si), carbon-containing silicon oxide (SiOCH), silicon oxynitride (SiON), silicon carbide (SiC) or silicon nitride (SiN), silicon oxide (SiO2), benzocyclobutene (BCB), polybenzoxazole (PBO), etc. The material of the capacitor dielectric layer T3 may also include silicon glass (*SG) such as undoped silicon glass (USG), phosphorus silicate glass (PSG), fluorinated silica glass (FSG), and boron phosphor silicate glass (BPSG). The material of the first electrode T1 includes a conductive material such as titanium nitride (TiN), and the material of the second electrode T2 includes a conductive material such as nitrogen-doped silicon, phosphorus-doped silicon, arsenic-doped silicon, boron-doped silicon, and aluminum-doped silicon.

[0096] The first electrode T1 is coupled to the first device D1 through the first redistribution layer RDL1, as shown in FIG4C . The second electrode T2 can be coupled to the ground network GND in the chip package structure. In this case, the deep trench capacitor DTC can be used as a filter capacitor, for example.

[0097] 4A , the second electrode T2 is coupled to the first ground network GND1 in the first redistribution layer RDL1 . For example, the receiving cavity is groove-shaped, and a portion of the deep trench capacitor DTC is received in the groove. The second electrode T2 is directly coupled to the first ground network GND1 .

[0098] 4B , the second electrode T2 is coupled to the second ground network GND2 in the second redistribution layer RDL2 . For example, the receiving cavity penetrates the substrate, and the second electrode T2 is directly coupled to the second ground network GND2 in the second redistribution layer RDL2 .

[0099] Alternatively, for example, the second electrode T2 of the deep trench capacitor DTC may also be coupled to other devices in the chip packaging structure. For example, the second electrode T2 may be coupled to a chip, capacitor, resistor, inductor, microstrip line, or other device in the chip packaging structure. This embodiment of the present application does not limit this, and the enumeration in the embodiment of the present application is merely for illustration.

[0100] In some embodiments, as shown in FIG4A , the chip package structure further includes solder balls, and the chip package structure can be coupled to the PCB via the solder balls. The solder balls can be made of, for example, copper, tin, silver, etc.

[0101] 4A , the solder balls are disposed on the side of the second redistribution layer RDL2 away from the substrate. Alternatively, the solder balls are disposed on the side of the first redistribution layer RDL1 away from the substrate.

[0102] The chip packaging structure provided by the embodiments of the present application has trench capacitors DTC encapsulated internally, but the trench capacitors DTC are located within the substrate, eliminating the need to reserve space for deep trench capacitors DTC in the thickness direction. Therefore, arranging the trench capacitors DTC within the substrate can reduce the size of the chip packaging structure along the thickness direction. Furthermore, the number of devices arranged within the substrate is typically relatively small, leaving ample free space within the substrate to accommodate the deep trench capacitors DTC without increasing the size in the horizontal direction alone. Therefore, arranging the trench capacitors DTC within the substrate can reduce the size of the chip packaging structure along the horizontal direction. In other words, arranging the trench capacitors DTC within the substrate reduces the layout area originally required for placing independent capacitor components, thereby reducing the size of the chip packaging structure. On this basis, a receiving cavity is provided on the substrate, and deep trench capacitors DTC are formed directly on the substrate surface and accommodated by the receiving cavity. In the chip packaging structure of the present application, the shape of the deep trench capacitors DTC matches the shape of the receiving cavity, eliminating the need for dimensional accuracy of the receiving cavity and resulting in a high product yield. Furthermore, the first redistribution layer RDL1 can be formed directly on the surface of the deep trench capacitors DTC, eliminating the need for pre-processing of external device packaging and reducing the number of steps required. If the prepared capacitor device is integrated and packaged within a substrate, the size of the accommodating cavity formed on the substrate needs to match the capacitor device, which requires high precision and results in significant yield loss. Furthermore, after integrating the capacitor device into the substrate, pre-packaging processing is required to prepare the first redistribution layer RLD1, which is a complex process. Therefore, the chip packaging structure provided by the embodiments of the present application can reduce the size of the chip packaging structure while maintaining good yield.

[0103] FIG5 is a cross-sectional view of a chip packaging structure provided in an embodiment of the present application.

[0104] In some embodiments, as shown in FIG. 5 , the second electrode T2 of the deep trench capacitor DTC is coupled to the first ground network GND1 of the first redistribution layer RDL1 , and the second electrode T2 is further coupled to the second ground network GND2 of the second redistribution layer RDL2 .

[0105] The second electrode T2 is coupled to the first redistribution layer RDL1 and the second redistribution layer RDL2 respectively, which is equivalent to the first redistribution layer RDL1 and the second redistribution layer RDL2 being coupled through the second electrode T2. The second electrode T2 can act as a via in the substrate, interconnecting the first ground network GND1 and the second ground network GND2, and can reduce the number of vias in the substrate to reduce the area of ​​the chip packaging structure while reducing costs.

[0106] Regarding the coupling method of the second electrode T2 and the first ground network GND1 of the first redistribution layer RDL1, as shown in FIG4A , the second electrode T2 and the first ground network GND1 can be spliced ​​and coupled. In this way, the first redistribution layer RDL1 can be fabricated after the deep trench capacitor DTC is fabricated, which can simplify the process steps.

[0107] Alternatively, as shown in Figure 5, the second electrode T2 can be connected to the first ground network GND1, with the first ground network GND1 located below the second electrode T2. During fabrication, the first ground network GND1 layer of the first redistribution layer RDL1 is first fabricated, followed by the deep trench capacitor DTC, and then the other wiring layers of the first redistribution layer RDL1. This can reduce the requirements for process precision and improve product yield.

[0108] In some embodiments, the capacitance of the trench capacitor DTC is greater than or equal to 500 pF.

[0109] Because capacitors larger than 500pF in a chip package are relatively large in both thickness and horizontal dimensions, significantly impacting the package area, integrating capacitors larger than 500pF into the substrate can significantly reduce the chip package area.

[0110] FIG6 is a top view of a deep trench capacitor arrangement provided in an embodiment of the present application.

[0111] In some embodiments, as shown in FIG. 6 , the trench capacitor DTC is disposed along the edge of the substrate.

[0112] For example, as shown in FIG5 , the edge of the deep trench capacitor DTC may coincide with the edge of the substrate. Alternatively, for example, as shown in FIG6 , there is a gap between the edge of the deep trench capacitor DTC and the edge of the substrate.

[0113] FIG6 is only a block diagram illustrating the location of the deep trench capacitor DTC, and does not mean that the top view of the deep trench capacitor DTC is the structure shown in the figure.

[0114] By placing the deep trench capacitor DTC at the edge of the substrate, the layout of the central area can be maintained, and the overall layout of the chip packaging structure can be changed relatively little. Moreover, when the second electrode T2 of the deep trench capacitor DTC is coupled to both the first ground network GND1 and the second ground network GND2, the deep trench capacitor DTC, in addition to its own capacitance function, can also provide electromagnetic shielding for the external radiation of the package intermediate layer device, that is, the deep trench capacitor DTC has an external radiation suppression effect. Therefore, at the location where the deep trench capacitor DTC is provided, there is no need to use a special process to sputter a conformal shielding layer on the side surface, reducing packaging costs and simplifying packaging steps.

[0115] In some embodiments, the trench capacitor DTC is disposed around the edge of the substrate.

[0116] This allows for larger DTC capacitance within the same footprint, while eliminating the need for common shielding layers on the sides of the chip package.

[0117] For example, the deep trench capacitor DTC has a ring structure, which has a good shielding effect.

[0118] Alternatively, for example, as shown in FIG6 , the deep trench capacitors DTC are discontinuously arranged around the edge of the substrate.

[0119] In this way, by controlling the gap between adjacent capacitors, the deep trench capacitor (DTC) can still shield the entire side of the chip package structure. Moreover, the process is relatively simple and easy to implement.

[0120] Alternatively, for example, the deep trench capacitors DTC are arranged in a staggered overlapping manner around the edge of the substrate. The present application embodiment does not limit the arrangement of the deep trench capacitors DTC, and the overall trend is ring-shaped, which can shield the entire side of the chip package structure.

[0121] 7A and 7B are cross-sectional views of a chip packaging structure provided in an embodiment of the present application, and FIG. 7C is a layout diagram of a device and a deep trench capacitor provided in an embodiment of the present application.

[0122] In some embodiments, as shown in FIG7A , the chip package structure further includes a second device D2 and a third device D3 , wherein the second device D2 and the third device D3 are disposed in the substrate, and at least one deep trench capacitor DTC is disposed between the second device D2 and the third device D3 .

[0123] For example, the second device D2 is coupled to the first redistribution layer RDL1 and / or the second redistribution layer RDL2, and the third device D3 is coupled to the first redistribution layer RDL1 and / or the second redistribution layer RDL2. FIG7A illustrates the case where both the second device D2 and the third device D3 are coupled to the second redistribution layer RDL2.

[0124] That is, in the embodiment of the present application, deep trench capacitors DTC are provided along the edge of the substrate, and deep trench capacitors DTC may also be provided in the middle area of ​​the substrate.

[0125] In some embodiments, the second electrode T2 of the deep trench capacitor DTC is coupled to both the first ground network GND1 and the second ground network GND2. This allows the deep trench capacitor DTC to provide cavity shielding and internal isolation, shielding against electromagnetic interference between the second device D2 and the third device D3. For example, if the second device D2 is an interference source and the third device D3 is a victim, the deep trench capacitor DTC can shield the electromagnetic interference from the second device D2 to the third device D3.

[0126] For example, the second device D2 and the third device D3 are devices with different magnetic field strengths.

[0127] For example, if the second device D2 includes a device with a magnetic field strength greater than or equal to 50dBμV / m, the second device D2 is a strong radiation device and is an interference source. If the third device D3 includes a device with a magnetic field strength less than 50dBμV / m, the third device D3 is a radiation sensitive device and is a victim.

[0128] For example, the second device D2 includes a radio frequency transmitting device (e.g., a power amplifier, etc.), and the third device D3 includes a radio frequency receiving device (e.g., a low-noise amplifier, etc.). Alternatively, the second device D2 includes a digital circuit device (e.g., an application processor, a memory chip, etc.), and the third device D3 includes an analog circuit device (e.g., an operational amplifier, a sensor, etc.).

[0129] In the present application, the interfering device and the disturbed device are isolated by the deep trench capacitor DTC, which eliminates the need for a special shielding structure and simplifies the structure.

[0130] In some embodiments, as shown in FIG. 7B , the chip package structure includes a deep trench capacitor DTC disposed around the substrate, and further includes a deep trench capacitor DTC disposed between the second device D2 and the third device D3 .

[0131] As shown in FIG7C , from a top view, the second device D2 and the third device D3 are located in an isolation region surrounded by the deep trench capacitor DTC, and the deep trench capacitor DTC is spaced between the second device D2 and the third device D3.

[0132] In this way, there is no need to set a separate shielding layer on the side or the side and top surface of the chip packaging structure, and there is no need to set a separate shielding layer between adjacent interference sources and radiation sensitive objects. The structure is simple and the radiation shielding effect is good.

[0133] FIG8 is a cross-sectional view of a chip packaging structure provided in an embodiment of the present application.

[0134] In some embodiments, as shown in FIG8 , the chip package structure further includes a fourth device D4 . The fourth device D4 is disposed on a side of the second redistribution layer RDL2 away from the substrate, and the fourth device D4 is coupled to the second redistribution layer RDL2 .

[0135] For example, the chip packaging structure further includes a second plastic packaging layer, which is arranged on a side of the second redistribution layer RDL2 away from the substrate. The second plastic packaging layer covers the fourth device D4 and exposes the solder balls.

[0136] In some embodiments, the solder balls are located outside the fourth device D4, so that the solder balls can play a shielding role and reduce the radiation interference of the fourth device D4.

[0137] In some embodiments, the magnetic field strength of the first device D1 is less than 50 dBμV / m, and the first device D1 is a non-strong radiation device.

[0138] By arranging non-strong radiation devices on the side of the first redistribution layer RDL1 away from the substrate, a shielding layer is not required on the surface of the chip package structure where the first device D1 is located, thereby simplifying the structure and manufacturing process.

[0139] In some embodiments, the magnetic field strength of the first device D1 is smaller than the magnetic field strengths of the second device D2 , the third device D3 , and the fourth device D4 .

[0140] The second, third, and fourth devices D2, D3, and D4 are surrounded by a first redistribution layer (RDL1), a second redistribution layer (RDL2), deep trench capacitors (DTC), and solder balls as electromagnetic shielding protection layers. The side surfaces of the chip package structure can be specifically sputtered to form a shielding layer. Since the first device D1 is a non-high-radiation device, the top surface of the chip package structure also does not need to be specifically sputtered to form a shielding layer. This eliminates the need for a shielding layer on the outer surface of the entire chip package structure, while still achieving controllable external radiation levels from the entire package. This simplifies the process and reduces costs.

[0141] FIG9 is a cross-sectional view of a chip packaging structure provided in an embodiment of the present application.

[0142] In other embodiments, as shown in FIG9 , the magnetic field strength of the first device D1 is greater than or equal to 50 dBμV / m, and the first device D1 is a strong radiation device.

[0143] In this case, for example, a shielding layer may be provided on the surface of the chip package structure on the side where the first device D1 is located to form electromagnetic shielding.

[0144] Alternatively, as shown in FIG9 , the chip package structure further includes a shielding cover, which is buckled onto the first redistribution layer RDL1, and the first device D1 is located within the shielding cover. The first plastic encapsulation layer covers the shielding cover and the first redistribution layer RDL1, so that the shielding cover is encapsulated within the chip package structure.

[0145] For example, the shielding cover is an open cavity, and the open cavity is buckled on the first redistribution layer RDL1.

[0146] 9 , the shielding cover includes cross-arranged bonding wires coupled to the first ground network GND1 of the first redistribution layer RDL1. For example, the shielding cover is a wire cage formed by cross-arranged bonding wires.

[0147] Even if a strong radiation device needs to be set above the first redistribution layer RDL1, a shielding cover with a local shielding function can be provided above the first strong radiation device D1. The first device D1 is electromagnetically protected by the shielding cover, and there is still no need to provide a shielding layer on the outer surface of the chip packaging structure. The overall external radiation level of the package can still be controlled.

[0148] Below, the packaging process of the chip packaging structure provided in the embodiment of the present application is schematically described.

[0149] The present invention provides a packaging method for a chip packaging structure. Taking the chip packaging structure shown in FIG. 9 as an example, as shown in FIG. 10 , the packaging method includes:

[0150] S1. As shown in FIG11A , a hole is drilled on the second side of the substrate, and a second device D2 and a third device D3 are embedded therein.

[0151] As shown in FIG11A , the second device D2 and the third device D3 are disposed in the substrate, and the second side surface of the substrate exposes the active surfaces of the second device D2 and the third device D3 .

[0152] S2. As shown in FIG11B , a plurality of receiving cavities are formed on the first side of the substrate.

[0153] Of course, the accommodating cavity may be a groove-shaped structure, or may pass through the substrate. FIG11B is merely an illustration and does not limit the structure in any way.

[0154] S3. As shown in FIG11C , a deep trench capacitor DTC is formed on the first side of the substrate. The deep trench capacitor DTC extends from the first side of the substrate into at least two accommodating cavities.

[0155] For example, the deep trench capacitor DTC includes a first electrode T1 , a second electrode T2 , and a capacitor dielectric layer T3 located between the first electrode T1 and the second electrode T2 .

[0156] Step S3 includes:

[0157] S31 . Form a second electrode T2 on the first side of the substrate. The second electrode T2 extends into the accommodating cavity and adheres to the inner surface of the accommodating cavity.

[0158] S32 , forming a capacitor dielectric layer T3 on the surface of the second electrode T2 .

[0159] S33 , forming a first electrode T1 on the surface of the capacitor dielectric layer T3 .

[0160] For example, if the trench capacitor DTC is located above the first ground network GND1 and is connected to the first ground network GND1, the first ground network GND1 is formed before the trench capacitor DTC. If the trench capacitor DTC is spliced ​​to the first ground network GND1, the trench capacitor DTC can be formed first, and then the first ground network GND1 is formed.

[0161] A first electrode T1 of the deep trench capacitor DTC is coupled to other networks in the first redistribution layer RDL1, and a second electrode T2 is coupled to the first ground network GND1 of the first redistribution layer RDL1. For example, the deep trench capacitor DTC may penetrate the substrate, exposing the second electrode T2 on the second side of the substrate. Subsequently, a second ground network GND2 in the second redistribution layer RDL2 is coupled to the second electrode T2.

[0162] S4. As shown in FIG. 11D , a temporary bonding carrier is placed on the second side of the substrate, and a first redistribution layer RDL1 is formed on the first side of the substrate. The first redistribution layer RDL1 is directly coupled to the deep trench capacitor DTC.

[0163] The embodiment of the present application does not limit the process of forming the first redistribution layer RDL1 and the structure of the first redistribution layer RDL1. The redistribution layers in the related art are all applicable to the embodiment of the present application.

[0164] S5. As shown in FIG. 11E , the temporary bonding carrier on the second side of the substrate is removed, and a temporary bonding carrier is replaced on the surface of the first redistribution layer RDL1 to form a second redistribution layer RDL2 on the second side of the substrate.

[0165] S6. As shown in FIG11F , the temporary bonding carrier is removed, and the first device D1 is bonded to the side of the first redistribution layer RDL1 away from the substrate to form a shielding cover, and a first plastic encapsulation layer is formed.

[0166] S7. As shown in FIG11G , a fourth device D4 is bonded on the surface of the second redistribution layer RDL2 and a second plastic encapsulation layer is formed.

[0167] S8. As shown in FIG9 , solder balls are planted.

[0168] If the chip package structure does not include a shielding cover, the step of forming the shielding cover can be omitted. If the chip package structure does not include the fourth device D4, the steps of forming the fourth device D4 and the second plastic encapsulation layer can be omitted, and solder balls can be directly implanted on the surface of the second redistribution layer RDL2. If the chip package structure does not include the second device D2 and the third device D3, the step of embedding the second device D2 and the third device D3 in the substrate can be omitted, and the deep trench capacitor DTC can be directly formed.

[0169] After the chip packaging structure provided in the embodiments of the present application is coupled to a circuit board via solder balls, it can form the circuit board assembly provided in the embodiments of the present application. Of course, the chip packaging structure can also be coupled to other chips or device structures via solder balls, all of which fall within the scope of application of the chip packaging structure provided in the embodiments of the present application. The chip packaging structure or circuit board assembly provided in the embodiments of the present application can be applied to any of the above-mentioned terminals provided in the embodiments of the present application.

[0170] The above are only specific embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any changes or replacements within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A chip packaging structure, characterized in that: include: A substrate, wherein a first side of the substrate is provided with a plurality of accommodating cavities; at least one deep trench capacitor, the deep trench capacitor being disposed on the first side of the substrate and extending into at least two of the accommodating cavities; A first redistribution layer is disposed on a first side of the substrate and is directly coupled to the deep trench capacitor; A first device is arranged on a side of the first redistribution layer away from the substrate and coupled to the deep trench capacitor through the first redistribution layer; The second redistribution layer is arranged on a second side of the substrate away from the first redistribution layer.

2. The chip packaging structure according to claim 1, characterized in that: The deep trench capacitor is in contact with the inner surface of the accommodating cavity.

3. The chip packaging structure according to claim 1 or 2, characterized in that: The deep trench capacitor includes a first electrode and a second electrode. The first electrode is coupled to the first device, and the second electrode is coupled to both a first ground network of the first redistribution layer and a second ground network of the second redistribution layer.

4. The chip packaging structure according to claim 3, characterized in that: The first electrode and the second electrode form at least two protrusions, and the deep trench capacitor extends into at least two of the accommodating cavities, specifically: the protrusion extends into the accommodating cavity.

5. The chip packaging structure according to any one of claims 1 to 4, characterized in that: The second electrode is directly coupled to the first ground network.

6. The chip packaging structure according to any one of claims 1 to 5, characterized in that: The accommodating cavity penetrates the substrate, and the second electrode is directly coupled to the second ground network.

7. The chip packaging structure according to any one of claims 2 to 6, characterized in that: The deep trench capacitor is arranged along the edge of the substrate.

8. The chip packaging structure according to any one of claims 1 to 7, characterized in that: The chip packaging structure also includes a second device and a third device; The second device and the third device are arranged in the substrate, and at least one of the deep trench capacitors is located between the second device and the third device.

9. The chip packaging structure according to claim 8, characterized in that: The magnetic field strengths of the second device and the third device are different.

10. The chip packaging structure according to claim 8 or 9, characterized in that: The second device includes a radio frequency transmitting device, and the third device includes a radio frequency receiving device; or, The second device includes a digital circuit device, and the third device includes an analog circuit device; or, The magnetic field strength of the second device is greater than or equal to 50 dBμV / m, and the magnetic field strength of the third device is less than 50 dBμV / m.

11. The chip packaging structure according to any one of claims 1 to 10, characterized in that: The magnetic field strength of the first device is less than 50dBμV / m; or, The first device includes a radio frequency receiving device or an analog circuit device.

12. The chip packaging structure according to any one of claims 1 to 10, characterized in that: The magnetic field strength of the first device is greater than or equal to 50dBμV / m; or, the first device includes a radio frequency transmitting device or a digital circuit device; The chip packaging structure further includes a shielding cover and a plastic sealing layer. The shielding cover is buckled on the first redistribution layer, and the first device is located in the shielding cover. The plastic sealing layer covers the shielding cover and the first redistribution layer.

13. The chip packaging structure according to claim 12, characterized in that: The shielding cover includes cross-arranged bonding wires, and the bonding wires are coupled to the first ground network of the first redistribution layer.

14. The chip packaging structure according to any one of claims 1 to 13, characterized in that: The capacitance of the deep trench capacitor is greater than or equal to 500 pF.

15. A circuit board assembly, characterized in that: It comprises a circuit board and a chip packaging structure, wherein the chip packaging structure is arranged on the circuit board, and the chip packaging structure comprises the chip packaging structure according to any one of claims 1 to 14.

16. A terminal, characterized in that: It comprises a rear shell and a circuit board assembly, wherein the circuit board assembly is arranged in the rear shell, and the circuit board assembly comprises the circuit board assembly according to claim 15.

17. A packaging method for a chip packaging structure, characterized in that: include: forming a plurality of receiving cavities on a first side of the substrate; forming a deep trench capacitor on the first side of the substrate, wherein the deep trench capacitor extends into at least two of the accommodating cavities; forming a first redistribution layer on a first side of the substrate, the first redistribution layer being directly coupled to the deep trench capacitor; forming a second redistribution layer on a second side of the substrate away from the first redistribution layer; A first device is bonded to a side of the first redistribution layer away from the substrate, and the first device is coupled to the deep trench capacitor through the first redistribution layer.

18. The packaging method according to claim 17, characterized in that: A deep trench capacitor is formed on a first side of the substrate, comprising: forming a second electrode on the first side of the substrate, wherein the second electrode extends into the accommodating cavity and adheres to the inner surface of the accommodating cavity; forming a capacitor dielectric layer on the surface of the second electrode; A first electrode is formed on the surface of the capacitor dielectric layer.

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