Semiconductor device and manufacturing method therefor, and electronic device
By designing vertically stacked transistor structures in semiconductor devices, the challenge of manufacturing more devices on a limited substrate is solved, achieving lower costs and higher manufacturing efficiency.
Patent Information
- Application Number
- PCT/CN2024/118076
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-12-22
- Filing Date
- 2024-09-10
- Publication Date
- 2025-08-21
AI Technical Summary
With the development of integrated circuit technology, the critical size of devices is reduced, and the impact of slight differences on device performance increases. How to manufacture more devices on limited substrates becomes a challenge.
A semiconductor device is designed, including a vertically stacked first transistor and a second transistor, by forming a multi-layer memory cell array in a vertical direction on the substrate, and forming a vertical planar channel using a deposition process of a non-oxygen-rich environment, simplifying the process flow and reducing costs.
Making more devices on a limited substrate is achieved, reducing contact resistance and process costs, improving manufacturing efficiency and reducing process time.
Smart Images
Figure CN2024118076_21082025_PF_FP_ABST
Abstract
Description
Semiconductor device, manufacturing method thereof, and electronic equipment
[0001] This application claims priority to the Chinese patent application filed on December 22, 2023, with application number 202311789654.2, and invention name “A semiconductor device, a manufacturing method thereof, and an electronic device”, the contents of which should be understood as incorporated into this application by reference. Technical Field
[0002] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art
[0003] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.
[0004] To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.
[0005] Summary of the Invention
[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
[0007] An embodiment of the present disclosure provides a semiconductor device, comprising: a first transistor and a second transistor stacked on a substrate in a direction perpendicular to the substrate;
[0008] The first transistor includes: a first electrode, a second electrode arranged on a side of the first electrode facing away from the substrate, a first semiconductor layer arranged on a side of the second electrode facing away from the first electrode, and a first gate electrode arranged on a side of the first semiconductor layer facing away from the second electrode; the first semiconductor layer connects the first electrode and the second electrode;
[0009] The second transistor includes: a third electrode provided on a side of the first gate electrode facing away from the substrate, a second semiconductor layer provided on a side of the third electrode facing away from the first gate electrode, and a second gate electrode provided on a side of the second semiconductor layer facing away from the third electrode; the second semiconductor layer connects the third electrode and the first gate electrode;
[0010] The first semiconductor layer includes a first semiconductor sublayer extending in a direction intersecting the substrate, a second semiconductor sublayer extending from one end of the first semiconductor sublayer in a direction parallel to the substrate, and a third semiconductor sublayer extending from the other end of the first semiconductor sublayer in a direction parallel to the substrate and away from the second semiconductor sublayer.
[0011] The second semiconductor layer includes a fourth semiconductor sublayer whose extension direction intersects with the substrate, a fifth semiconductor sublayer extending from one end of the fourth semiconductor sublayer in a direction parallel to the substrate, and a sixth semiconductor sublayer extending from the other end of the fourth semiconductor sublayer in a direction parallel to the substrate and away from the fifth semiconductor sublayer.
[0012] In some embodiments, the first electrode is connected to a side of the second semiconductor sublayer facing the substrate.
[0013] In some embodiments, the second electrode is connected to a side of the third semiconductor sublayer facing the substrate, and is connected to a side of the first semiconductor sublayer facing the third semiconductor sublayer.
[0014] In some embodiments, the first gate electrode is connected to a side of the fifth semiconductor sublayer facing the substrate.
[0015] In some embodiments, the third electrode is connected to a side of the sixth semiconductor sublayer facing the substrate, and is connected to a side of the fourth semiconductor sublayer facing the sixth semiconductor sublayer.
[0016] In some embodiments, the first transistor further includes a first gate insulating layer, the first gate insulating layer covers a surface of the first semiconductor layer facing away from the substrate, and the first gate electrode covers a surface of the first gate insulating layer facing away from the substrate.
[0017] In some embodiments, the first gate electrode includes a first parallel portion parallel to the substrate and a first inclined portion extending from the first parallel portion toward the substrate.
[0018] In some embodiments, the second gate electrode includes a second parallel portion parallel to the substrate and a second inclined portion extending from the second parallel portion toward the substrate.
[0019] In some embodiments, the second transistor further includes a second gate insulating layer, the second gate insulating layer covers a surface of the second semiconductor layer facing away from the substrate, and the second gate electrode covers a surface of the second gate insulating layer facing away from the substrate.
[0020] In some embodiments, the semiconductor device includes at least one layer of memory cell array, the memory cell array includes a plurality of memory cells distributed in an array along a first direction and a second direction, the first direction and the second direction intersect and are both parallel to the substrate, the memory cell includes the first transistor and the second transistor, the first electrodes of the memory cells in the same row are connected to form a first bit line extending along the first direction, the second electrodes of the memory cells in the same column are connected to form a first word line extending along the second direction, the third electrodes of the memory cells in the same column are connected to form a second bit line extending along the second direction, and the second gate electrodes of the memory cells in the same row are connected to the same second word line.
[0021] An embodiment of the present disclosure provides an electronic device, comprising any of the semiconductor devices described above.
[0022] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, comprising:
[0023] Providing a substrate, forming a first electrode on the substrate, and forming a second electrode on a side of the first electrode away from the substrate;
[0024] forming a first trench, wherein a bottom wall of the first trench exposes the first electrode, and a side wall of the first trench exposes the second electrode;
[0025] Depositing a first semiconductor film, a first gate insulating film, and a first conductive film in sequence, wherein the first semiconductor film covers a surface of the second electrode away from the substrate and an inner wall of the first trench, the first gate insulating film covers a surface of the first semiconductor film away from the substrate, and the first conductive film fills the first trench;
[0026] forming a second trench, the second trench penetrating the first semiconductor film, the first gate insulating film, and the first conductive film, the second trench dividing the first semiconductor film, the first gate insulating film, and the first conductive film into two parts along an extension direction of the bottom wall of the second trench, thereby forming a first semiconductor layer covering a surface of the second electrode away from the substrate and a side wall and a portion of the bottom wall of the first trench, a first gate insulating layer covering the first semiconductor layer, and a first gate electrode covering the first gate insulating layer;
[0027] forming a third electrode on a side of the first gate electrode away from the substrate;
[0028] forming a third trench, wherein a bottom wall of the third trench exposes the first gate electrode and a side wall of the third trench exposes the third electrode;
[0029] depositing a second semiconductor film, a second gate insulating film, and a second conductive film in sequence, wherein the second semiconductor film covers a surface of the second electrode away from the substrate and an inner wall of the first trench, the second gate insulating film covers a surface of the second semiconductor film away from the substrate, and the second conductive film fills the third trench;
[0030] A fourth trench is formed, wherein the fourth trench penetrates the second semiconductor film, the second gate insulating film and the second conductive film, and the fourth trench divides the second semiconductor film, the second gate insulating film and the second conductive film into two parts along the extension direction of the bottom wall of the third trench, thereby forming a second semiconductor layer covering the surface of the third electrode away from the substrate and a side wall and a part of the bottom wall of the third trench, a second gate insulating layer covering the second semiconductor layer, and a second gate electrode covering the second gate insulating layer.
[0031] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained through the solutions described in the description and the drawings.
[0032] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.
[0033] Summary of the Figures
[0034] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.
[0035] FIG1A is a top view of a semiconductor device according to some embodiments, FIG1B is a cross-sectional view perpendicular to the substrate along the AA′ direction in FIG1A , and FIG1C is a cross-sectional view perpendicular to the substrate along the BB′ direction in FIG1A ;
[0036] FIG1D is an equivalent circuit diagram of a semiconductor device provided in some embodiments;
[0037] FIG2A is a cross-sectional view perpendicular to the substrate along the AA' direction after forming a first bit line and a first word line according to some embodiments; FIG2B is a cross-sectional view perpendicular to the substrate along the BB' direction after forming a first bit line and a first word line according to some embodiments;
[0038] 3A is a cross-sectional view perpendicular to the substrate along the AA' direction after forming a first trench according to some embodiments; FIG. 3B is a cross-sectional view perpendicular to the substrate along the BB' direction after forming a first trench according to some embodiments;
[0039] 4A is a cross-sectional view perpendicular to the substrate along the AA' direction after forming a first semiconductor structure layer, a first gate insulating structure layer, and a first gate electrode layer, according to some embodiments; FIG. 4B is a cross-sectional view perpendicular to the substrate along the BB' direction after forming the first semiconductor structure layer, the first gate insulating structure layer, and the first gate electrode layer, according to some embodiments;
[0040] FIG5A is a cross-sectional view perpendicular to the substrate along the AA' direction after forming a first semiconductor layer, a first gate insulating layer, and a first gate electrode, according to some embodiments; FIG5B is a cross-sectional view perpendicular to the substrate along the BB' direction after forming the first semiconductor layer, the first gate insulating layer, and the first gate electrode, according to some embodiments;
[0041] 6A is a cross-sectional view perpendicular to the substrate along the AA' direction after forming the first insulating layer according to some embodiments; FIG. 6B is a cross-sectional view perpendicular to the substrate along the BB' direction after forming the first insulating layer according to some embodiments;
[0042] 7A is a cross-sectional view perpendicular to the substrate along the AA' direction after forming a second bit line according to some embodiments; FIG. 7B is a cross-sectional view perpendicular to the substrate along the BB' direction after forming a second bit line according to some embodiments;
[0043] 8A is a cross-sectional view perpendicular to the substrate along the AA' direction after forming the third trench according to some embodiments; FIG. 8B is a cross-sectional view perpendicular to the substrate along the BB' direction after forming the third trench according to some embodiments;
[0044] FIG9A is a cross-sectional view perpendicular to the substrate along the AA' direction after forming the second semiconductor structure layer, the second gate insulating structure layer, and the second gate electrode layer, according to some embodiments; FIG9B is a cross-sectional view perpendicular to the substrate along the BB' direction after forming the second semiconductor structure layer, the second gate insulating structure layer, and the second gate electrode layer, according to some embodiments;
[0045] FIG10A is a cross-sectional view perpendicular to the substrate along the AA' direction after forming a second semiconductor layer, a second gate insulating layer, and a second gate electrode according to some embodiments; FIG10B is a cross-sectional view perpendicular to the substrate along the BB' direction after forming a second semiconductor layer, a second gate insulating layer, and a second gate electrode according to some embodiments;
[0046] FIG11A is a top view of a semiconductor device provided in some embodiments; FIG11B is a cross-sectional view perpendicular to the substrate along the AA′ direction in FIG11A provided in some embodiments.
[0047] Details
[0048] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Unless there is a conflict, the embodiments of the present disclosure and the features therein may be combined with each other in any manner.
[0049] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the same meaning as commonly understood by a person having ordinary skills in the field to which the present disclosure belongs.
[0050] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically illustrate ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.
[0051] In the present disclosure, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.
[0052] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in this disclosure are not limited and may be appropriately replaced according to the circumstances.
[0053] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to physical or signal connections, contact connections, or integral connections. They can be direct connections, indirect connections through intermediaries, or internal connections between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.
[0054] In this disclosure, a transistor refers to an element comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.
[0055] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of the "source electrode" and "drain electrode" may be reversed when using transistors with opposite polarities or when the direction of current changes during circuit operation. Therefore, in the present disclosure, the terms "source electrode" and "drain electrode" may be reversed.
[0056] In this disclosure, "connection" includes the connection of components via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.
[0057] In this disclosure, "parallel" means approximately parallel or nearly parallel. For example, the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the angle of greater than 85° and less than 95°.
[0058] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there are no distinct microstructural boundaries, such as gaps or discontinuities. Generally, a film layer patterned to form a connection is considered integrated. For example, A and B may be formed using the same material into a single film layer and simultaneously formed into a connected structure through the same patterning process.
[0059] In the embodiment of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
[0060] Figure 1A is a top view of a semiconductor device provided in some embodiments, Figure 1B is a cross-sectional view perpendicular to substrate 1 along the AA' direction in Figure 1A, and Figure 1C is a cross-sectional view perpendicular to substrate 1 along the BB' direction in Figure 1A. Figure 1A shows only a top view of some components of the semiconductor device. As shown in Figures 1A, 1B, and 1C, embodiments of the present disclosure may provide a semiconductor device, which may include a first transistor and a second transistor disposed on substrate 1 and stacked in a direction perpendicular to substrate 1;
[0061] The first transistor may include: a first electrode 51, a second electrode 52 disposed on a side of the first electrode 51 facing away from the substrate 1, a first semiconductor layer 21 disposed on a side of the second electrode 52 facing away from the first electrode 51, and a first gate electrode 26 disposed on a side of the first semiconductor layer 21 facing away from the second electrode 52; the first semiconductor layer 21 connects the first electrode 51 and the second electrode 52; a distance between the second electrode 52 and the substrate 1 along a direction perpendicular to the substrate 1 is greater than a distance between the first electrode 51 and the substrate 1 along a direction perpendicular to the substrate 1;
[0062] The second transistor may include: a third electrode 53 disposed on a side of the first gate electrode 26 facing away from the substrate 1, a second semiconductor layer 22 disposed on a side of the third electrode 53 facing away from the first gate electrode 26, and a second gate electrode 27 disposed on a side of the second semiconductor layer 22 facing away from the third electrode 53; the second semiconductor layer 22 connects the third electrode 53 and the first gate electrode 26; that is, the first gate electrode 26 can be reused as an electrode of the second transistor; the distance between the third electrode 53 and the substrate 1 along a direction perpendicular to the substrate 1 is greater than the distance between the first gate electrode 26 and the substrate 1 along the direction perpendicular to the substrate 1;
[0063] The first semiconductor layer 21 may include a first semiconductor sublayer 211 extending in a direction intersecting the substrate 1, a second semiconductor sublayer 212 extending from one end of the first semiconductor sublayer 211 in a direction parallel to the substrate 1, and a third semiconductor sublayer 213 extending from the other end of the first semiconductor sublayer 211 in a direction parallel to the substrate 1 and away from the second semiconductor sublayer 212; the distance between the third semiconductor sublayer 213 and the substrate 1 in a direction perpendicular to the substrate 1 may be greater than the distance between the second semiconductor sublayer 212 and the substrate 1 in a direction perpendicular to the substrate 1;
[0064] The second semiconductor layer 22 may include a fourth semiconductor sublayer 221 extending in a direction intersecting the substrate 1, a fifth semiconductor sublayer 222 extending from one end of the fourth semiconductor sublayer 221 in a direction parallel to the substrate 1, and a sixth semiconductor sublayer 223 extending from the other end of the fourth semiconductor sublayer 221 in a direction parallel to the substrate 1 and away from the fifth semiconductor sublayer 222. The distance between the sixth semiconductor sublayer 223 and the substrate 1 along a direction perpendicular to the substrate 1 may be greater than the distance between the fifth semiconductor sublayer 222 and the substrate 1 along the direction perpendicular to the substrate 1.
[0065] In the solution provided by this embodiment, the first electrode and the second electrode are stacked in a direction perpendicular to the substrate, the first semiconductor layer forms a vertical planar channel, and the second transistor is similar to the first transistor, and the second semiconductor layer forms a vertical planar channel. This structure has a small aspect ratio and has little restriction on the deposition process for forming the semiconductor layer. The semiconductor layer can be formed using a deposition process in a non-oxygen-rich environment, thereby avoiding oxidation of the source and drain electrodes of the transistor, forming a good ohmic contact, reducing contact resistance, and using a lower-cost and more efficient deposition process to reduce costs and process time.
[0066] In some embodiments, the first semiconductor sublayer 211, the second semiconductor sublayer 212, and the third semiconductor sublayer 213 can be connected to form an integrated structure. The solution provided in this embodiment can form the first semiconductor layer 21 in one step, simplifying the process and reducing costs.
[0067] In some embodiments, the fourth semiconductor sublayer 221, the fifth semiconductor sublayer 222, and the sixth semiconductor sublayer 223 can be connected to form an integrated structure. The solution provided in this embodiment can form the second semiconductor layer 22 in one step, simplifying the process and reducing costs.
[0068] In some embodiments, the first electrode 51 may extend in a direction parallel to the substrate 1 .
[0069] In some embodiments, the second electrode 52 may extend in a direction parallel to the substrate 1 .
[0070] In some embodiments, the third electrode 53 may extend in a direction parallel to the substrate 1 .
[0071] In some embodiments, the first transistor may further include a first gate insulating layer 24, the first gate insulating layer 24 covering a surface of the first semiconductor layer 21 facing away from the substrate 1, and the first gate electrode 26 covering a surface of the first gate insulating layer 24 facing away from the substrate 1. The shape of the first gate insulating layer 24 is adapted to the shape of the first semiconductor layer 21, that is, the extension direction of the first gate insulating layer 24 is consistent with the extension direction of the first semiconductor layer 21.
[0072] In some embodiments, the first gate electrode 26 may include a first parallel portion parallel to the substrate 1 and a first inclined portion extending from the first parallel portion toward the substrate 1 .
[0073] In some embodiments, the second transistor may further include a second gate insulating layer 25, the second gate insulating layer 25 covering a surface of the second semiconductor layer 22 facing away from the substrate 1, and a second gate electrode 27 covering a surface of the second gate insulating layer 25 facing away from the substrate 1. The shape of the second gate insulating layer 25 is adapted to the shape of the second semiconductor layer 22, that is, the extension direction of the second gate insulating layer 25 is consistent with the extension direction of the second semiconductor layer 22.
[0074] In some embodiments, the second gate electrode 27 may include a second parallel portion parallel to the substrate 1 and a second inclined portion extending from the second parallel portion toward the substrate 1 .
[0075] In some embodiments, the first electrode 51 may be connected to the side of the second semiconductor sublayer 212 facing the substrate 1. However, the embodiments of the present disclosure are not limited thereto. The first electrode 51 may also be connected to the first semiconductor sublayer 211, for example, to the side of the first semiconductor sublayer 211 facing the second electrode 52, etc. When the first electrode 51 is connected only to the side of the second semiconductor sublayer 212 facing the substrate 1, it is easier to implement in terms of process.
[0076] In some embodiments, the second electrode 52 may be connected to the side of the third semiconductor sublayer 213 facing the substrate 1, and to the side of the first semiconductor sublayer 211 facing the third semiconductor sublayer 213. However, the present disclosure is not limited thereto, and the second electrode 52 may be connected to only one of the side of the third semiconductor sublayer 213 facing the substrate 1 and the side of the first semiconductor sublayer 211 facing the third semiconductor sublayer 213.
[0077] In some embodiments, the first semiconductor layer 21 may cover the surface of the second electrode 52 facing away from the substrate 1 and the side wall of the second electrode 52 facing the first semiconductor layer 21 (here, the side wall of the second electrode 52 facing the first semiconductor sublayer 211).
[0078] In some embodiments, the first gate electrode 26 may be connected to the side of the fifth semiconductor sublayer 222 facing the substrate 1. However, the present disclosure is not limited thereto. The first gate electrode 26 may also be connected to the fourth semiconductor sublayer 221, for example, to the side of the fourth semiconductor sublayer 221 facing the third electrode 53, etc. When the first gate electrode 26 is connected only to the side of the fifth semiconductor sublayer 222 facing the substrate 1, the process is easier to implement.
[0079] In some embodiments, the third electrode 53 may be connected to the side of the sixth semiconductor sublayer 223 facing the substrate 1, and to the side of the fourth semiconductor sublayer 221 facing the sixth semiconductor sublayer 223. However, the embodiments of the present disclosure are not limited thereto, and the third electrode 53 may be connected to only one of the side of the sixth semiconductor sublayer 223 facing the substrate 1 and the side of the fourth semiconductor sublayer 221 facing the sixth semiconductor sublayer 223.
[0080] In some embodiments, the second semiconductor layer 22 may cover the surface of the third electrode 53 facing away from the substrate 1 and the side wall of the third electrode 53 facing the second semiconductor layer 22 (here, the side wall of the third electrode 53 facing the fourth semiconductor sublayer 221).
[0081] In some embodiments, the orthographic projections of the first semiconductor layer 21 and the second semiconductor layer 22 on the substrate 1 may overlap. This embodiment provides a solution that allows for mask reuse during the fabrication of the first semiconductor layer 21 and the second semiconductor layer 22, thereby reducing costs. Furthermore, the area occupied by the first and second transistors on the substrate can be reduced, thereby reducing device area.
[0082] In some embodiments, the orthographic projections of the second electrode 52 and the third electrode 53 on the substrate 1 may overlap. This embodiment provides a solution that allows for the reuse of masks when manufacturing the second electrode 52 and the third electrode 53, thereby reducing costs. Furthermore, the area occupied by the first and second transistors on the substrate can be reduced, thereby reducing the device area.
[0083] In some embodiments, along the second direction Y, a size of the first semiconductor layer 21 may be larger than a size of the first electrode 51 .
[0084] In some embodiments, along the second direction Y, a size of the first gate electrode 26 may be larger than a size of the first electrode 51 .
[0085] In some embodiments, the orthographic projections of the first gate electrode 26 and the second gate electrode 27 on the substrate 1 may overlap. This embodiment provides a solution that allows for mask reuse during the fabrication of the first gate electrode 26 and the second gate electrode 27, thereby reducing costs. Furthermore, the area occupied by the first and second transistors on the substrate 1 can be reduced, thereby reducing the device area.
[0086] In some embodiments, the semiconductor device may include a multi-layer memory cell array stacked in a direction perpendicular to substrate 1. As shown in FIG1A , the memory cell array may include multiple memory cells arranged in an array along a first direction X and a second direction Y (the area outlined by the dashed lines in FIG1B represents a single memory cell). The first direction X and the second direction Y intersect and are both parallel to substrate 1. The memory cell may include a first transistor and a second transistor. Multiple first electrodes 51 of multiple memory cells arranged in a row along the first direction X are connected to form a first bit line 31 extending along the first direction X. Multiple second electrodes 52 of multiple memory cells arranged in a column along the second direction Y are continuously formed to form a first word line 41 extending along the second direction. Multiple third electrodes 53 of multiple memory cells in a column are connected to form a second bit line 32 extending along the second direction. The second gate electrodes 27 of multiple memory cells in a row are connected to the same second word line. In some embodiments, the first direction X and the second direction Y may be perpendicular. The second word line may be disposed on the side of the second transistor facing away from substrate 1.
[0087] In some embodiments, two columns of memory cells can be grouped together, with the second semiconductor sublayers 212 of the first semiconductor layer 21 of adjacent memory cells in the same group along the first direction X adjacent to each other, and the third semiconductor sublayer 213 disposed on the side of the second semiconductor sublayer 212 facing away from the adjacent memory cell. The fifth semiconductor sublayers 222 of the second semiconductor layer 22 of adjacent memory cells along the first direction X are adjacent to each other, and the sixth semiconductor sublayer 223 is disposed on the side of the fifth semiconductor sublayer 222 facing away from the adjacent memory cell. That is, the layout of the second semiconductor sublayer 212 and the third semiconductor sublayer 213 of the first semiconductor layer 21 of adjacent memory cells in the same group along the first direction X can be opposite. The solution provided in this embodiment can form two columns of transistors using a single trench, reducing the number of trenches during the manufacturing process and simplifying the process.
[0088] In some embodiments, as shown in FIG11A and FIG11B , in adjacent memory cells along the first direction X, the second semiconductor sublayer 212 is close to the third semiconductor sublayer 213 of the adjacent memory cell, that is, the second semiconductor sublayer 212 and the third semiconductor sublayer 213 of the first semiconductor layer 21 of the adjacent memory cells may have the same layout along the first direction X. The fifth semiconductor sublayer 222 is close to the sixth semiconductor sublayer 223 of the adjacent memory cell, that is, the fifth semiconductor sublayer 222 and the sixth semiconductor sublayer 223 of the second semiconductor layer 22 of the adjacent memory cells may have the same layout along the first direction X.
[0089] In some embodiments, adjacent memory cells along the first direction X may be mirror-symmetrical.
[0090] Figure 1D is an equivalent circuit diagram of a semiconductor device provided in some embodiments. In this embodiment, the first transistor may be a read transistor Tr_r, the second transistor may be a write transistor Tr_w, the first word line 41 may be a read word line RWL, the second word line may be a write word line WWL, the first bit line 31 may be a read bit line, and the second bit line 32 may be a write bit line. As shown in Figure 1D, this embodiment provides a storage circuit including a write transistor Tr_w and a read transistor Tr_r. The read transistor Tr_r includes a first electrode 51, a second electrode 52, and a first gate electrode 26. The write transistor Tr_w includes a third electrode 53, a fourth electrode, and a second gate electrode 27. The first gate electrode 26 is connected to the fourth electrode of the write transistor Tr_w, or the first gate electrode 26 is reused as the fourth electrode. The first gate electrode 26 serves as a storage node SN. The first electrode 51 is connected to the read bit line RBL, the second electrode 52 is connected to the read word line RWL, the third electrode 53 is connected to the write bit line WBL, and the second gate electrode 26 is connected to the write word line WWL. The read and write process is as follows: 1) When writing "1", a conduction voltage is applied to the write word line WWL, the write transistor Tr_w channel is turned on, and the third electrode 53 and the fourth electrode are connected. The write bit line WBL applies the voltage corresponding to the data "1", and the third electrode 53 injects the charge corresponding to the data "1" into the storage node SN; when reading "1", a read voltage is applied to the read word line RWL. Since there is a certain charge in the storage node SN, a current flows between the read bit line RBL and the read word line RWL. After amplification and recognition by the peripheral circuit, the reading process of "1" is completed. (2) When writing "0", a voltage lower than the threshold voltage is applied to the write bit line WBL to extract the charge, and the write transistor is not turned on; when reading "0", a read voltage is applied to the read word line RWL. Since there is no charge in the storage node SN, no or a small current flows between the read bit line RBL and the read word line RWL. After amplification and recognition by the peripheral circuit, the reading process of "0" is completed. In addition, during the non-read and write phase, data can be written back to the storage node SN.
[0091] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes processes such as depositing a film layer, applying a photoresist, mask exposure, development, etching, and stripping the photoresist, and is a mature manufacturing process in the relevant art. Deposition can be carried out using known processes such as sputtering, evaporation, and chemical vapor deposition, coating can be carried out using known coating processes, and etching can be carried out using known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film produced by depositing or coating a certain material on a substrate. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" also requires a patterning process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".
[0092] In some embodiments, the manufacturing process of the semiconductor device may include:
[0093] 1) forming a first bit line 31 and a first word line 41;
[0094] Providing a substrate 1, depositing a first conductive film on the substrate 1, patterning to form a plurality of first bit lines 31 extending along a first direction X, wherein the plurality of first bit lines 31 are spaced apart along a second direction Y; and covering the first bit lines 31 with an insulating film;
[0095] A second conductive film is deposited and patterned to form a plurality of first word lines 41 extending along a second direction Y, as shown in Figures 2A and 2B . Figure 2A is a cross-sectional view perpendicular to the substrate 1 along the AA' direction after forming the first bit line 31 and the first word line 41, as provided in some embodiments. Figure 2B is a cross-sectional view perpendicular to the substrate 1 along the BB' direction after forming the first bit line 31 and the first word line 41, as provided in some embodiments. The first word lines 41 extend along the second direction Y, and the plurality of first word lines 41 are spaced apart along the first direction X.
[0096] In some embodiments, the first conductive film may be one or more of the following different types of materials:
[0097] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; or it may be a metal alloy containing the aforementioned metals;
[0098] Alternatively, it may be a conductive metal oxide, metal nitride, metal silicide, metal carbide, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO) and other conductive metal oxide materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other conductive metal nitride materials;
[0099] Alternatively, it may be polysilicon, silicon, germanium, silicon germanium, etc. that are conductive after doping.
[0100] The second conductive film and the subsequent third conductive film, fourth conductive film, and fifth conductive film are made of similar materials to the first conductive film and are not described in detail.
[0101] 2) forming a first trench T1;
[0102] A first trench T1 is formed; the sidewalls of the first trench T1 expose the adjacent first word line 41, and the bottom wall exposes the first bit line 31; as shown in Figures 3A and 3B, where Figure 3A is a cross-sectional view perpendicular to the substrate 1 along the AA' direction after forming the first trench T1, provided in some embodiments, and Figure 3B is a cross-sectional view perpendicular to the substrate 1 along the BB' direction after forming the first trench T1, provided in some embodiments. The first trench T1 extends along the second direction Y.
[0103] 3) forming a first semiconductor structure layer 21 a, a first gate insulating structure layer 24 a and a first gate electrode layer 26 a;
[0104] A first semiconductor film, a first gate insulating film and a third conductive film are sequentially deposited on the substrate 1 forming the aforementioned structure to form a first semiconductor structure layer 21a, a first gate insulating structure layer 24a and a first gate electrode layer 26a, and the third conductive film fills the first trench T1; the first semiconductor film covers the surface of the first word line 41 facing away from the substrate 1, and covers the inner wall of the first trench T1 (including the bottom wall and side walls of the first trench T1), and the first gate insulating film covers the surface of the first semiconductor film facing away from the substrate 1, as shown in Figures 4A and 4B, wherein Figure 4A is a cross-sectional view perpendicular to the substrate 1 along the AA' direction after the first semiconductor structure layer 21a, the first gate insulating structure layer 24a and the first gate electrode layer 26a are formed, provided in some embodiments, and Figure 4B is a cross-sectional view perpendicular to the substrate 1 along the BB' direction after the first semiconductor structure layer 21a, the first gate insulating structure layer 24a and the first gate electrode layer 26a are formed, provided in some embodiments.
[0105] In an exemplary embodiment of the present disclosure, the material of the first semiconductor film may be silicon or polysilicon with a band gap less than 1.65 eV, or may be a wide band gap material, such as a metal oxide material with a band gap greater than 1.65 eV.
[0106] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen and silicon, or contain other small amounts of doping elements.
[0107] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific adjustment can be made according to the actual situation.
[0108] These materials have a wide band gap and a low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of dynamic memory.
[0109] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic ratio in the material and the film quality of the material.
[0110] In an exemplary embodiment of the present disclosure, the material of the first gate insulating film may include one or more layers of High-K dielectric material, such as a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.
[0111] The subsequent second semiconductor film is made of a material similar to that of the first semiconductor film, and the second gate insulating film is made of a material similar to that of the first gate insulating film, and thus will not be described in detail.
[0112] In this embodiment, the width of the first trench T1 along the first direction X can be a partial area occupied by the semiconductor layers of the two transistors. Therefore, the width of the first trench T1 can be larger, the depth-width ratio is smaller, and the restriction on the deposition process is smaller. For example, a physical vapor deposition (PVD) process can be used, such as a sputtering process to grow and form the first semiconductor layer 21. This process can be carried out in an argon (Ar)-rich atmosphere to avoid oxidation of the first bit line 31 and the first word line 41, and to form an ohmic contact between the first semiconductor layer 21 and the first bit line 31 and the first word line 41, thereby reducing the contact resistance. In addition, compared with the atomic layer deposition (ALD) process used when the depth-width ratio is large, this process can also reduce costs and process time. The subsequent deposition of the second semiconductor layer is similar and will not be repeated.
[0113] 4) forming a first semiconductor layer 21, a first gate insulating layer 24 and a first gate electrode 26;
[0114] The first semiconductor film, the first gate insulating film and the third conductive film are patterned to form a first semiconductor layer 21, a first gate insulating layer 24 and a first gate electrode 26; at this time, the first semiconductor structure layer 21a, the first gate insulating structure layer 24a and the first gate electrode layer 26a are divided into a plurality of independent first semiconductor layers 21, first gate insulating layers 24 and first gate electrodes 26 along the second direction Y and the first direction X; a first sub-trench T21 extending along the first direction X exists between adjacent first bit lines 31, disconnecting the first semiconductor layer 21, the first gate insulating layer 24 and the first gate electrode 26 of adjacent transistors along the second direction Y, and separating the first semiconductor layer 21, the first gate insulating layer 24 and the first gate electrode 26 of adjacent transistors along the first direction X. A second sub-trench T22 extending along the second direction Y exists between the adjacent transistors. The bottom wall of the second sub-trench T22 exposes the first bit line 31, disconnecting the first semiconductor layer 21, first gate insulating layer 24, and first gate electrode 26 of the adjacent transistors along the first direction X, as shown in Figures 5A and 5B. Figure 5A is a cross-sectional view perpendicular to the substrate 1 along the AA' direction after forming the first semiconductor layer 21, first gate insulating layer 24, and first gate electrode 26, as provided in some embodiments. Figure 5B is a cross-sectional view perpendicular to the substrate 1 along the BB' direction after forming the first semiconductor layer 21, first gate insulating layer 24, and first gate electrode 26, as provided in some embodiments. The first semiconductor layer 21, first gate insulating layer 24, and first gate electrode 26 on both sides of the second sub-trench T22 can be mirror-symmetrical, but the embodiments of the present disclosure are not limited thereto and do not need to be mirror-symmetrical. The first semiconductor film, first gate insulating film, and third conductive film are removed from the region where the second sub-trench T22 and the first sub-trench T21 intersect.
[0115] 5) forming a first insulating layer 10;
[0116] A first insulating film is deposited and polished to form a first insulating layer 10 filling the first sub-trench T21 and the second sub-trench T22. The first insulating layer 10 is flush with the first gate electrode 26, as shown in Figures 6A and 6B, wherein Figure 6A is a cross-sectional view perpendicular to the substrate 1 along the AA' direction after the first insulating layer 10 is formed, as provided in some embodiments, and Figure 6B is a cross-sectional view perpendicular to the substrate 1 along the BB' direction after the first insulating layer 10 is formed, as provided in some embodiments.
[0117] In some embodiments, the first insulating film may be made of a Low-K material, such as silicon dioxide, etc. The subsequent second insulating film is similar and will not be described in detail.
[0118] 6) forming a second bit line 32;
[0119] An insulating film and a fourth conductive film are sequentially deposited on the substrate 1 forming the aforementioned structure, and patterned to form a plurality of second bit lines 32; the second bit lines 32 extend along the second direction Y, and the plurality of second bit lines 32 are spaced apart along the first direction X; an insulating film is deposited to fill the gaps between adjacent second bit lines 32 and is smoothed, as shown in FIG7A and FIG7B , where FIG7A is a cross-sectional view perpendicular to the substrate 1 along the AA' direction after the second bit lines 32 are formed, provided in some embodiments, and FIG7B is a cross-sectional view perpendicular to the substrate 1 along the BB' direction after the second bit lines 32 are formed, provided in some embodiments.
[0120] 7) forming a third trench T3;
[0121] A third trench T3 is formed; the sidewalls of the third trench T3 expose the adjacent second bit line 32, and the bottom wall exposes the first gate electrode 26 of the adjacent transistor and the first insulating layer 10 along the first direction X, as shown in Figures 8A and 8B , where Figure 8A is a cross-sectional view perpendicular to the substrate 1 along the AA' direction after forming the third trench T3, provided in some embodiments, and Figure 8B is a cross-sectional view perpendicular to the substrate 1 along the BB' direction after forming the third trench T3, provided in some embodiments. The third trench T3 extends along the second direction Y.
[0122] 8) forming a second semiconductor structure layer 22a, a second gate insulating structure layer 25a and a second gate electrode layer 27a;
[0123] A second semiconductor film, a second gate insulating film and a fifth conductive film are sequentially deposited on the substrate 1 forming the aforementioned structure to form a second semiconductor structure layer 22a, a second gate insulating structure layer 25a and a second gate electrode layer 27a; the fifth conductive film fills the third trench T3; the second semiconductor film covers the surface of the second bit line 32 facing away from the substrate 1, and covers the inner wall of the third trench T3 (including the bottom wall and side walls of the third trench T3); the second gate insulating film covers the surface of the second semiconductor film facing away from the substrate 1, as shown in Figures 9A and 9B, wherein Figure 9A is a cross-sectional view perpendicular to the substrate 1 along the AA' direction after the second semiconductor structure layer 22a, the second gate insulating structure layer 25a and the second gate electrode layer 27a are formed, provided in some embodiments, and Figure 9B is a cross-sectional view perpendicular to the substrate 1 along the BB' direction after the second semiconductor structure layer 22a, the second gate insulating structure layer 25a and the second gate electrode layer 27a are formed, provided in some embodiments.
[0124] 9) forming a second semiconductor layer 22, a second gate insulating layer 25 and a second gate electrode 27;
[0125] The second semiconductor film, the second gate insulating film and the fifth conductive film are patterned to form a second semiconductor layer 22, a second gate insulating layer 25 and a second gate electrode 27. At this time, the second semiconductor structure layer 22a, the second gate insulating structure layer 25a and the second gate electrode layer 27a are divided into a plurality of independent second semiconductor layers 22, second gate insulating layers 25 and second gate electrodes 27 along the second direction Y and the first direction X. A third sub-trench T41 extending along the first direction X exists between adjacent first bit lines 31, which disconnects the second semiconductor layer 22, the second gate insulating layer 25 and the second gate electrode 27 of adjacent transistors along the second direction Y. A fourth sub-trench T42 extending along the second direction Y exists between transistors adjacent along the first direction X, disconnecting the second semiconductor layer 22, the second gate insulating layer 25, and the second gate electrode 27 of the transistors adjacent along the first direction X, as shown in Figures 10A and 10B. Figure 10A is a cross-sectional view perpendicular to the substrate 1 along the AA' direction after forming the second semiconductor layer 22, the second gate insulating layer 25, and the second gate electrode 27, as provided in some embodiments. Figure 10B is a cross-sectional view perpendicular to the substrate 1 along the BB' direction after forming the second semiconductor layer 22, the second gate insulating layer 25, and the second gate electrode 27, as provided in some embodiments. The second semiconductor layer 22, the second gate insulating layer 25, and the second gate electrode 27 on both sides of the fourth sub-trench T42 can be mirror-symmetrical, but the embodiments of the present disclosure are not limited thereto and need not be mirror-symmetrical.
[0126] 10) forming a second insulating layer 11;
[0127] A second insulating film is deposited on the substrate 1 forming the aforementioned structure and polished to form a second insulating layer 11 filling the third sub-trench T41 and the fourth sub-trench T42 . The second insulating layer 11 is flush with the second gate electrode 27 , as shown in FIG. 1B and FIG. 1C .
[0128] The present disclosure also provides an electronic device comprising the semiconductor device described in any of the preceding embodiments, or a semiconductor device formed by the method for manufacturing a semiconductor device described in any of the preceding embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include, for example, computer memory, and is not limited here.
[0129] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of patent protection of the present invention shall remain subject to the scope defined by the appended claims.
Claims
1. A semiconductor device comprising: A first transistor and a second transistor are provided on a substrate and stacked in a direction perpendicular to the substrate; The first transistor includes: a first electrode, a second electrode arranged on a side of the first electrode facing away from the substrate, a first semiconductor layer arranged on a side of the second electrode facing away from the first electrode, and a first gate electrode arranged on a side of the first semiconductor layer facing away from the second electrode; the first semiconductor layer connects the first electrode and the second electrode; The second transistor includes: a third electrode provided on a side of the first gate electrode facing away from the substrate, a second semiconductor layer provided on a side of the third electrode facing away from the first gate electrode, and a second gate electrode provided on a side of the second semiconductor layer facing away from the third electrode; the second semiconductor layer connects the third electrode and the first gate electrode; The first semiconductor layer includes a first semiconductor sublayer extending in a direction intersecting the substrate, a second semiconductor sublayer extending from one end of the first semiconductor sublayer in a direction parallel to the substrate, and a third semiconductor sublayer extending from the other end of the first semiconductor sublayer in a direction parallel to the substrate and away from the second semiconductor sublayer. The second semiconductor layer includes a fourth semiconductor sublayer whose extension direction intersects with the substrate, a fifth semiconductor sublayer extending from one end of the fourth semiconductor sublayer in a direction parallel to the substrate, and a sixth semiconductor sublayer extending from the other end of the fourth semiconductor sublayer in a direction parallel to the substrate and away from the fifth semiconductor sublayer.
2. The semiconductor device according to claim 1, wherein The first electrode is connected to a side of the second semiconductor sublayer facing the substrate.
3. The semiconductor device according to claim 1, wherein The second electrode is connected to a side of the third semiconductor sublayer facing the substrate, and is connected to a side of the first semiconductor sublayer facing the third semiconductor sublayer.
4. The semiconductor device according to claim 1, wherein The first gate electrode is connected to a side of the fifth semiconductor sublayer facing the substrate. The semiconductor device according to claim 1 , wherein The third electrode is connected to a side of the sixth semiconductor sublayer facing the substrate, and is connected to a side of the fourth semiconductor sublayer facing the sixth semiconductor sublayer. The semiconductor device according to claim 1 , wherein: The first transistor further includes a first gate insulating layer, which covers a surface of the first semiconductor layer facing away from the substrate, and the first gate electrode covers a surface of the first gate insulating layer facing away from the substrate.
7. The semiconductor device according to claim 6, wherein The first gate electrode includes a first parallel portion parallel to the substrate and a first inclined portion extending from the first parallel portion toward the substrate.
8. The semiconductor device according to claim 1, wherein The second transistor further includes a second gate insulating layer, which covers a surface of the second semiconductor layer facing away from the substrate, and the second gate electrode covers a surface of the second gate insulating layer facing away from the substrate.
9. The semiconductor device according to claim 8, wherein The second gate electrode includes a second parallel portion parallel to the substrate and a second inclined portion extending from the second parallel portion toward the substrate.
10. The semiconductor device according to any one of claims 1 to 9, wherein: The semiconductor device includes at least one layer of memory cell array, the memory cell array includes a plurality of memory cells distributed in an array along a first direction and a second direction, the first direction and the second direction intersect and are both parallel to the substrate, the memory cell includes the first transistor and the second transistor, the first electrodes of the memory cells in the same row are connected to form a first bit line extending along the first direction, the second electrodes of the memory cells in the same column are connected to form a first word line extending along the second direction, the third electrodes of the memory cells in the same column are connected to form a second bit line extending along the second direction, and the second gate electrodes of the memory cells in the same row are connected to the same second word line.
11. An electronic device comprising the semiconductor device according to any one of claims 1 to 10.
12. A method for manufacturing a semiconductor device, comprising: Providing a substrate, forming a first electrode on the substrate, and forming a second electrode on a side of the first electrode away from the substrate; forming a first trench, wherein a bottom wall of the first trench exposes the first electrode, and a side wall of the first trench exposes the second electrode; Depositing a first semiconductor film, a first gate insulating film, and a first conductive film in sequence, wherein the first semiconductor film covers a surface of the second electrode away from the substrate and an inner wall of the first trench, the first gate insulating film covers a surface of the first semiconductor film away from the substrate, and the first conductive film fills the first trench; forming a second trench, the second trench penetrating the first semiconductor film, the first gate insulating film, and the first conductive film, the second trench dividing the first semiconductor film, the first gate insulating film, and the first conductive film into two parts along an extension direction of the bottom wall of the second trench, thereby forming a first semiconductor layer covering a surface of the second electrode away from the substrate and a side wall and a portion of the bottom wall of the first trench, a first gate insulating layer covering the first semiconductor layer, and a first gate electrode covering the first gate insulating layer; and forming a third electrode on a side of the first gate electrode away from the substrate; forming a third trench, wherein a bottom wall of the third trench exposes the first gate electrode and a side wall of the third trench exposes the third electrode; depositing a second semiconductor film, a second gate insulating film, and a second conductive film in sequence, wherein the second semiconductor film covers a surface of the second electrode away from the substrate and an inner wall of the first trench, the second gate insulating film covers a surface of the second semiconductor film away from the substrate, and the second conductive film fills the third trench; A fourth trench is formed, wherein the fourth trench penetrates the second semiconductor film, the second gate insulating film and the second conductive film, and the fourth trench divides the second semiconductor film, the second gate insulating film and the second conductive film into two parts along the extension direction of the bottom wall of the third trench, thereby forming a second semiconductor layer covering the surface of the third electrode away from the substrate and a side wall and a part of the bottom wall of the third trench, a second gate insulating layer covering the second semiconductor layer, and a second gate electrode covering the second gate insulating layer.