Semiconductor device, manufacturing method therefor, and electronic apparatus

Abstract

The present application provides a semiconductor device, a manufacturing method therefor, and an electronic apparatus. The semiconductor device comprises: a channel layer, a barrier layer, a first dielectric layer, a second dielectric layer, a gate electrode and a field plate, wherein the first dielectric layer is provided with a first through hole and a second through hole that run through the first dielectric layer; the gate electrode is arranged between the barrier layer and the second dielectric layer and is connected with the barrier layer by means of the first through hole; the second through hole is filled with the second dielectric layer, such that a recess is formed in the position on the surface of the second dielectric layer that corresponds to the second through hole; and the recess is filled with the field plate. In this way, by means of filling, a recess can be correspondingly formed in the surface of the side of the second dielectric layer that is away from a substrate, and the recess and the second through hole are arranged corresponding to each other, and thus the etching of the second dielectric layer is not required during the formation of the recess, and the recess can be naturally formed by filling the second through hole, so that the manufacturing process of semiconductor devices is simplified, and the manufacturing difficulty thereof is reduced, thereby reducing the manufacturing costs and facilitating an improvement to the manufacturing yield of the semiconductor devices.

Description

Semiconductor device, manufacturing method thereof and electronic equipment

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on December 20, 2023, with application number 202311770127.7 and application name "A semiconductor device, its manufacturing method and electronic device", all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0004] A transistor, as a semiconductor device, generally includes: a substrate, a channel layer, a barrier layer, a first dielectric layer, a second dielectric layer, and a third dielectric layer sequentially located above the substrate. A first through-hole is provided in the first dielectric layer, and a gate disposed between the second dielectric layer and the barrier layer is connected to the barrier layer via the first through-hole. A second through-hole is provided in the second dielectric layer, and a field plate disposed between the second and third dielectric layers fills the second through-hole, such that the portion of the field plate filled in the second through-hole is referred to as a sinker. The transistor also includes: a third through-hole and a fourth through-hole that penetrate the third dielectric layer, the second dielectric layer, and the first dielectric layer, respectively. The source is connected to the source region in the barrier layer via the third through-hole, and the drain is connected to the drain region in the barrier layer via the fourth through-hole. The sinker is provided between the gate and the drain, and the field plate is connected to the source. The sinker can adjust the electric field distribution between the gate and the drain, thereby reducing the parasitic capacitance between the gate and the drain and improving the performance of the transistor.

[0005] However, to form the second through-hole in the second dielectric layer to form the sunken portion, the second dielectric layer must be etched. This etching process must avoid the location of the first through-hole to avoid adversely affecting the gate electrode, requiring high etching accuracy. Furthermore, when the etching selectivity of the materials used in the first and second dielectric layers is similar, overetching the second dielectric layer is prone to occur, potentially damaging the barrier layer and thus impairing transistor performance, making transistor manufacturing more difficult and reducing manufacturing yield.

[0006] Summary of the Invention

[0007] The present application provides a semiconductor device, a manufacturing method thereof, and an electronic device for reducing the manufacturing difficulty and manufacturing cost of the semiconductor device and improving the manufacturing yield of the semiconductor device.

[0008] In a first aspect, an embodiment of the present application provides a semiconductor device, which may include: a channel layer, a barrier layer, a first dielectric layer, and a second dielectric layer stacked in sequence, wherein the first dielectric layer is provided with a first through-hole and a second through-hole; the semiconductor device also includes a gate and a field plate, the gate is provided between the barrier layer and the second dielectric layer, the gate is connected to the barrier layer through the first through-hole, the second dielectric layer fills the second through-hole, so that a groove is formed on the surface of the second dielectric layer corresponding to the position of the second through-hole, and the field plate is provided on the side surface of the second dielectric layer facing away from the first dielectric layer, and the field plate fills the groove.

[0009] In this way, when the second dielectric layer fills the second through hole, a groove is correspondingly formed on the surface of the second dielectric layer on the side facing away from the substrate. Therefore, the groove is arranged corresponding to the second through hole, and the shape of the groove is similar to the shape of the second through hole. Therefore, when forming the groove, there is no need to etch the second dielectric layer. The groove can be naturally formed by filling the second through hole. This can simplify the manufacturing process of the semiconductor device, reduce the manufacturing difficulty, thereby reducing the manufacturing cost, and is conducive to improving the manufacturing yield of the semiconductor device.

[0010] Moreover, when the field plate is filling the groove, the portion of the field plate filled in the groove can be referred to as a sinking portion, and the portion of the field plate disposed outside the groove can be referred to as a main body, so that the main body and the sinking portion constitute the field plate. At this time, by filling the groove, a sinking portion can be naturally formed in the field plate, thereby helping to reduce the parasitic capacitance of the semiconductor device through the sinking portion, thereby helping to improve the performance of the semiconductor device.

[0011] Optionally, because the shape of the groove is similar to the shape of the second through hole, and the field plate filled in the groove forms a sinking portion, the shape of the sinking portion is the same as the shape of the groove, and thus the shape of the sinking portion is similar to the shape of the second through hole. The shape of the second through hole can be set according to actual needs, for example but not limited to: circular or quadrilateral and other shapes, no specific limitation is made here.

[0012] Optionally, the field plate extends along the first direction, and a plurality of sinkers are provided and arranged at intervals, and each sinker is arranged along the first direction. In this way, when a drain is included in the semiconductor device and the sinker is provided in the space between the gate and the drain, a plurality of sinkers are provided between the gate and the drain, and the electric field distribution between the gate and the drain can be adjusted by these sinkers, thereby reducing the parasitic capacitance between the gate and the drain. In addition, a plurality of grooves can be provided and arranged at intervals, wherein the number of grooves provided can be the same as the number of sinkers provided. In this case, the sinkers and the grooves can be provided in a one-to-one correspondence, so that each sinker can be naturally formed when the grooves are filled, thereby reducing the difficulty of manufacturing the sinkers and simplifying the manufacturing process.

[0013] Alternatively, the field plate extends along the first direction, a groove is provided and extends along the first direction, and the sinker completely fills the groove. This can reduce the number of grooves provided, thereby reducing the number of second through-holes provided. Since the first dielectric layer needs to be patterned before etching when forming the first through-hole and the second through-hole, the simplified structure of the second through-hole can simplify the difficulty of patterning, thereby reducing the difficulty of manufacturing the semiconductor device. In addition, the sinker extends to opposite ends of the body (or field plate) provided along the first direction, that is, the length of the body in the first direction is equal to the length of the sinker in the first direction. In this way, the field plate can be fully utilized to provide the sinker between the gate and the drain, further reducing the parasitic capacitance between the gate and the drain, thereby further improving the performance of the semiconductor device.

[0014] Optionally, the semiconductor device may further include a source and a drain. The semiconductor device may further include: a third through-hole and a fourth through-hole respectively penetrating the second dielectric layer, the first dielectric layer, and the barrier layer, the source being connected to the source region in the channel layer via the third through-hole, and the drain being connected to the drain region in the channel layer via the fourth through-hole; the source, drain, and field plate being disposed on the same layer, and the source, drain, and field plate being made of the same material. In this way, the source, drain, and field plate can be formed simultaneously using a single fabrication process, thereby allowing the source, drain, and field plate to be located on the same dielectric layer (i.e., the second dielectric layer). Compared to the prior art in which the source, drain, and field plate are formed using different fabrication processes, allowing the source, drain, and field plate to be located on different dielectric layers, the difficulty in fabricating the semiconductor device can be further simplified, the fabrication process can be further simplified, and the fabrication cost of the semiconductor device can be further reduced.

[0015] Among them, the field plate and the source are electrically connected through a connecting part, so that the sinker in the field plate has the same potential as the source. When the sinker is arranged between the gate and the drain, the presence of the sinker can adjust the electric field distribution between the gate and the drain, thereby reducing the parasitic capacitance between the gate and the drain and improving the stability of the semiconductor device.

[0016] Optionally, the distance between the bottom of the groove and the barrier layer can be defined as a first distance, that is, the distance between the surface of the sinker facing the substrate and the barrier layer can be defined as the first distance, and the distance between the surface of the gate facing away from the barrier layer and the barrier layer can be defined as the second distance, and the first distance can be set to be no greater than the second distance; if the surface of the gate facing away from the barrier layer is called the upper surface, the bottom of the groove is closer to the barrier layer than the upper surface, so the sinker can be located between the opposite areas of the gate and the drain in the second direction, thereby effectively adjusting the electric field distribution between the gate and the drain, and further reducing the parasitic capacitance between the gate and the drain. Among them, the first distance can be designed according to actual needs and is not specifically limited here. The second direction can be understood as: a direction perpendicular to the first direction and parallel to the substrate surface.

[0017] Furthermore, since the groove is naturally formed by filling the second through-hole when it is formed, there is no need to etch the second dielectric layer, so the difference in thickness of the second dielectric layer at different locations is no more than 500nm, that is, the thickness of the second dielectric layer at different locations is relatively close. In addition, the second dielectric layer is generally set thicker, and the first dielectric layer is generally set thinner, so the thickness of the second dielectric layer at any location is greater than the thickness of the first dielectric layer. In this way, the voltage resistance of the end of the field plate close to the drain can be improved, and the breakdown when the second dielectric layer is thin can be avoided, resulting in a short circuit between the end of the field plate close to the drain and the drain, thereby improving the reliability and safety of the semiconductor device. Among them, the thickness of the second dielectric layer can be set to 300nm, and the thickness of the first dielectric layer can be set to 50nm.

[0018] Optionally, the materials for making each structure in the semiconductor device may be set in the following manner, but not limited to:

[0019] The channel layer may be made of materials including but not limited to: GaN, etc.

[0020] The barrier layer may be made of, but is not limited to, semiconductor materials such as AlGaN, AlN, InGaN, and ScAlN.

[0021] The material of the first dielectric layer may include but is not limited to: AlN, SiN, Al2O3, SiO2 and other dielectric materials;

[0022] The second dielectric layer may be made of, but not limited to, AlN, SiN, Al2O3, SiO2, and other dielectric materials, and the first dielectric layer and the second dielectric layer may be made of the same or different materials;

[0023] The gate may be made of, but not limited to, at least one of the following conductive materials: Ni, TiN, W, Pt, etc.

[0024] The source, drain and field plate may be made of, but not limited to, at least one of conductive materials such as Ti, Au, Al, and TiN.

[0025] Among them, the gate, source, drain and field plate can be a multi-layer composite structure; taking the source as an example, the source can be set to the following structure: a composite structure consisting of a stacked Ti layer and an Au layer, or a composite structure consisting of a Ti layer, an Al layer and a Ti layer stacked in sequence, or a composite structure consisting of a TiN layer, an Al layer and a TiN layer stacked in sequence, or a composite structure consisting of a TiN layer, a Ti layer, an Al layer, a Ti layer and a TiN layer stacked in sequence, etc. Other composite structures are not listed here one by one.

[0026] In a second aspect, embodiments of the present application further provide a method for fabricating a semiconductor device, the method being used to fabricate the semiconductor device described in the first aspect and any of the embodiments of the first aspect. The method may include: forming a channel layer on a substrate; forming a barrier layer on the channel layer; forming a first dielectric layer on the barrier layer; forming a first through-hole and a second through-hole penetrating the first dielectric layer; forming a gate on the first dielectric layer, the gate being connected to the barrier layer via the first through-hole; forming a second dielectric layer on the first dielectric layer having the gate formed thereon, the second dielectric layer filling the second through-hole so that a groove is formed in a surface of the second dielectric layer corresponding to the second through-hole; and forming a field plate on the second dielectric layer, the field plate filling the groove. Thus, when the second dielectric layer fills the second through-hole, a groove is correspondingly formed on a surface of the second dielectric layer facing away from the substrate. The groove is disposed correspondingly to the second through-hole, and the shape of the groove is similar to that of the second through-hole. Consequently, when forming the groove, etching of the second dielectric layer is not required; the groove is naturally formed by filling the second through-hole. This simplifies the semiconductor device fabrication process, reduces fabrication difficulty, and thus reduces fabrication cost, thereby facilitating improved fabrication yield of the semiconductor device.

[0027] Optionally, the manufacturing method may further include: after forming the second dielectric layer and before forming the field plate, etching the second dielectric layer, the first dielectric layer and the barrier layer respectively to form a third through hole and a fourth through hole, wherein the third through hole exposes the source region in the channel layer, and the fourth through hole exposes the drain region in the channel layer. Based on this, forming the field plate may specifically include: forming a source, a drain and a field plate simultaneously on the second dielectric layer, the source being connected to the source region through the third through hole, and the drain being connected to the drain region through the fourth through hole. In this way, the source, the drain and the field plate can be formed simultaneously using one manufacturing process, thereby making the source, the drain and the field plate located on the same dielectric layer (i.e., the second dielectric layer). Compared with the prior art in which the source, the drain and the field plate are formed by different manufacturing processes, so that the source, the drain and the field plate are located on different dielectric layers, the manufacturing difficulty of the semiconductor device can be further simplified, the manufacturing process can be further simplified, and the manufacturing cost of the semiconductor device can be further reduced.

[0028] It should be understood that since the principle of solving the problem of the semiconductor device manufactured by this manufacturing method is similar to the principle of solving the problem by the aforementioned semiconductor device, the implementation and technical effects of this manufacturing method can refer to the implementation and technical effects of the aforementioned semiconductor device, and the repeated parts will not be repeated.

[0029] In a third aspect, embodiments of the present application further provide an electronic device, which may include: a housing, and a semiconductor device as described in the first aspect and any embodiment thereof, wherein the semiconductor device is disposed within the housing. Thus, while simplifying the manufacturing process of the semiconductor device, reducing manufacturing difficulty and cost, the manufacturing process of the electronic device can also be simplified, reducing manufacturing difficulty and cost.

[0030] It should be understood that since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the aforementioned semiconductor device, the implementation and technical effects of the electronic device can refer to the implementation and technical effects of the aforementioned semiconductor device, and the repeated parts will not be repeated. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0032] FIG2 is a schematic structural diagram of a semiconductor device in the prior art;

[0033] FIG3 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0034] FIG4 is a cross-sectional view along the x1-x2 direction in FIG3;

[0035] FIG5 is a cross-sectional view along the x3-x4 direction in FIG3;

[0036] FIG6 is another cross-sectional view along the x3-x4 direction in FIG3;

[0037] FIG7 is a flowchart of the manufacturing process of the semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of this application clearer, this application will be further described in detail below with reference to the accompanying drawings.

[0039] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be modified as needed, and such modifications are included in the scope of protection of this application. The drawings of this application are only for illustrating relative positional relationships and do not represent true proportions.

[0040] In order to facilitate understanding of the technical solution provided by the embodiments of the present application, its application scenario is first explained below.

[0041] The semiconductor devices provided in the embodiments of the present application can be widely used in various electronic devices, and the electronic devices provided in the embodiments of the present application can include various terminal devices and electronic devices. Among them, the terminal devices can include, but are not limited to, smartphones, smart TVs, smart TV set-top boxes, smart watches, personal computers (PCs), wearable devices, smart broadband and other devices. Electronic devices can include, but are not limited to, telecommunications equipment such as wireless networks, fixed networks, and servers, as well as chip modules, memories and other devices, which are not listed here one by one.

[0042] FIG1 exemplarily shows a schematic diagram of the structure of a semiconductor device when it is applied to an electronic device. Referring to FIG1 , the electronic device includes a housing 100 and a circuit board 200 arranged in the housing 100, and a semiconductor device 300 is arranged on the circuit board 200. The semiconductor device 300 is the core of the electronic device. With the continuous development of technology, higher requirements are put forward for the energy consumption, power, efficiency and miniaturization of the semiconductor device 300. Among them, materials such as GaN, GaAs, SiC, Ga2O3, AlN, diamond, etc. have a wider bandgap and have significant advantages in high-power, high-frequency and other applications. When these materials are used to make the semiconductor device 300, the semiconductor device 300 can meet the performance requirements. However, taking the semiconductor device 300 as a transistor as an example, there is a parasitic capacitance between the gate and the drain in the transistor. The presence of parasitic capacitance may cause the transistor output power, gain, efficiency and other performance to be limited, making it impossible to effectively improve the performance of the transistor.

[0043] In order to solve this problem, a sinker can be provided in the field plate, and the sinker is provided between the gate and the drain, so as to reduce the parasitic capacitance between the gate and the drain and improve the performance of the transistor. For example, as shown in FIG2 , the transistor includes: a substrate, a GaN layer, an AlGaN layer, a first dielectric layer 41, a second dielectric layer 42 and a third dielectric layer 43 sequentially located on the substrate, and the transistor also includes: a gate 51, a source 52, a drain 53 and a field plate 54. A first through hole T1 is provided in the first dielectric layer 41, and the gate 51 provided between the second dielectric layer 42 and the AlGaN layer is connected to the AlGaN layer through the first through hole T1; a second through hole T2 is provided in the second dielectric layer 42, and the field plate 54 provided between the second dielectric layer 42 and the third dielectric layer 43 fills the second through hole T2, so that the portion filled in the second through hole T2 is filled. The field plate 54 is referred to as a sinker 54a. The transistor further includes a third through hole (not shown in FIG. 2 ) and a fourth through hole (not shown in FIG. 2 ) that penetrate the third dielectric layer 43, the second dielectric layer 42, and the first dielectric layer 41, respectively. The source 52 is connected to the source region 61 in the AlGaN layer through the third through hole, and the drain 53 is connected to the drain region 62 in the AlGaN layer through the fourth through hole. The sinker 54a is disposed between the gate 51 and the drain 53, and the field plate 54 is connected to the source 52. The sinker 54a can adjust the electric field distribution between the gate 51 and the drain 53, thereby reducing the parasitic capacitance between the gate 51 and the drain 53. However, in order to form the second through hole T2 in the second dielectric layer 42 to form the sinker 54a, the second dielectric layer 42 needs to be etched. At this time, the etching needs to avoid the location of the first through hole T1 to avoid adversely affecting the gate 51. This requires high etching accuracy during etching. Moreover, when the etching selectivity of the materials used to make the first dielectric layer 41 and the second dielectric layer 42 is similar, over-etching is likely to occur during the etching of the second dielectric layer 42, which may damage the AlGaN layer and thus damage the performance of the transistor, making the transistor manufacturing more difficult and reducing the manufacturing yield.

[0044] The present invention provides a semiconductor device that reduces the difficulty and cost of manufacturing the semiconductor device and improves the manufacturing yield of the semiconductor device.

[0045] Figures 3 to 5 exemplarily show a schematic structural diagram of a semiconductor device provided by the present application. As shown in Figures 3 to 5, Figure 4 is a cross-sectional view along the x1-x2 direction in Figure 3, and Figure 5 is a cross-sectional view along the x3-x4 direction in Figure 3. The semiconductor device includes: a substrate 10, and a channel layer 20, a barrier layer 30, a first dielectric layer 41 and a second dielectric layer 42 stacked in sequence on the substrate 10, and the first dielectric layer 41 is provided with a first through hole T1 and a second through hole T2 that penetrates the first dielectric layer 41 along its thickness direction; the semiconductor device may also include a gate 51 and a field plate 54, the gate 51 is provided between the barrier layer 30 and the second dielectric layer 42, and the gate 51 is connected to the barrier layer 30 through the first through hole T1. The barrier layer 30 is connected; the second dielectric layer 42 fills the second through hole T2, so that a groove T0 is formed in the surface of the second dielectric layer 42 at a position corresponding to the second through hole T2. In other words, when the second dielectric layer 42 fills the second through hole T2, a groove T0 is correspondingly formed on the surface of the second dielectric layer 42 facing away from the substrate 10. Therefore, the groove T0 is provided corresponding to the second through hole T2, and the shape of the groove T0 is similar to the shape of the second through hole T2. Therefore, when forming the groove T0, there is no need to etch the second dielectric layer 42. The groove T0 can be naturally formed by filling the second through hole T2. This can simplify the manufacturing process of the semiconductor device, reduce the manufacturing difficulty, thereby reducing the manufacturing cost, and is conducive to improving the manufacturing yield of the semiconductor device. The field plate 54 is provided on a surface of the second dielectric layer 42 facing away from the first dielectric layer 41 . The field plate 54 fills the groove T0 . The portion of the field plate 54 filled in the groove T0 can be referred to as a sinking portion 54 a . Filling the groove T0 can naturally form the sinking portion 54 a in the field plate 54 . The sinking portion 54 a can help reduce the parasitic capacitance of the semiconductor device, thereby improving the performance of the semiconductor device.

[0046] Among them, since the shape of the groove T0 is similar to the shape of the second through hole T2, and the field plate 54 filled in the groove T0 forms a sinking portion 54a, the shape of the sinking portion 54a is the same as the shape of the groove T0, and thus the shape of the sinking portion 54a is similar to the shape of the second through hole T2. The shape of the second through hole T2 can be set according to actual needs, for example but not limited to: circular or quadrilateral and other shapes, which are not specifically limited here.

[0047] 4 , the semiconductor device may further include a source 52 and a drain 53. The semiconductor device may further include: a third through hole (not shown in FIG. 4 ) and a fourth through hole (not shown in FIG. 4 ) respectively penetrating the second dielectric layer 42 , the first dielectric layer 41 , and the barrier layer 30 . The source 52 is connected to the source region 61 in the channel layer 20 through the third through hole, and the drain 53 is connected to the drain region 62 in the channel layer 20 through the fourth through hole. The source 52 , the drain 53 , and the field plate 54 are arranged in the same layer, and the source 52 , the drain 53 , and the field plate 54 may be made of the same material. In this way, the source 52, the drain 53 and the field plate 54 can be formed simultaneously using one manufacturing process, so that the source 52, the drain 53 and the field plate 54 are located on the same dielectric layer (i.e., the second dielectric layer 42). Compared with the prior art in which the source 52, the drain 53 and the field plate 54 are formed by different manufacturing processes, so that the source 52, the drain 53 and the field plate 54 are located on different dielectric layers, the manufacturing difficulty of the semiconductor device can be further simplified, the manufacturing process can be further simplified, and the manufacturing cost of the semiconductor device can be further reduced.

[0048] In addition, as shown in Figure 3, the field plate 54 and the source 52 are electrically connected through the connecting portion 55, so that the sinker 54a in the field plate 54 has the same potential as the source 52. When the sinker 54a is provided between the gate 51 and the drain 53, the presence of the sinker 54a can adjust the electric field distribution between the gate 51 and the drain 53, thereby reducing the parasitic capacitance between the gate 51 and the drain 53 and improving the stability of the semiconductor device.

[0049] Furthermore, the distance between the bottom of the groove T0 and the barrier layer 30 can be defined as a first distance d1, that is, the distance between the surface of the sinker 54a facing the substrate 10 and the barrier layer 30 can be defined as the first distance d1, and the distance between the surface of the gate 51 facing away from the barrier layer 30 and the barrier layer 30 can be defined as a second distance d2. The first distance d1 can be set to be no greater than the second distance d2. If the surface of the gate 51 facing away from the barrier layer 30 is referred to as the upper surface, the groove bottom is closer to the barrier layer 30 than the upper surface. Therefore, the sinker 54a can be located between the regions directly opposite the gate 51 and the drain 53 in the x-direction, thereby effectively adjusting the electric field distribution between the gate 51 and the drain 53 and further reducing the parasitic capacitance between the gate 51 and the drain 53. The first distance d1 can be designed according to actual needs and is not specifically limited here.

[0050] 3 and 5 , the field plate 54, source 52, drain 53, and gate 51 all extend along a first direction (i.e., the y direction). The field plate 54 includes a connected body 54b and a sinker 54a. The sinker 54a is located within the groove T0, and the body 54b is located in an area outside the groove T0. The sinker 54a and the body 54b can be integrally formed. There are multiple sinkers 54a and they are spaced apart. Each sinker 54a is arranged along the first direction. In this way, multiple sinkers 54a are provided between the gate 51 and the drain 53. These sinkers 54a can reduce the electric field distribution between the gate 51 and the drain 53, thereby reducing the parasitic capacitance between the gate 51 and the drain 53. Furthermore, a plurality of grooves T0 can be provided and arranged at intervals, wherein the number of grooves T0 provided can be the same as the number of sinking portions 54a provided. In this case, the sinking portions 54a and the grooves T0 can be provided in a one-to-one correspondence, so that each sinking portion 54a can be naturally formed when the grooves T0 are filled, thereby reducing the difficulty of manufacturing the sinking portions 54a and simplifying the manufacturing process.

[0051] Continuing with FIG. 4 , since the groove T0 is naturally formed by filling the second through-hole T2 when forming the groove T0, etching of the second dielectric layer 42 is unnecessary. Therefore, the thickness difference of the second dielectric layer 42 at different locations is no more than 500 nm, that is, the thickness of the second dielectric layer 42 at different locations is relatively close. Furthermore, the second dielectric layer 42 is generally thicker, while the first dielectric layer 41 is generally thinner. Therefore, the thickness of the second dielectric layer 42 at any location is greater than the thickness of the first dielectric layer 41. This improves the withstand voltage capability of the end of the field plate 54 near the drain 53 (as shown within the dotted circle p1 in FIG. 4 ), preventing breakdown when the second dielectric layer 42 is thin, which would cause the end of the field plate 54 near the drain 53 to short-circuit with the drain 53, thereby improving the reliability and safety of the semiconductor device. The thickness d3 of the second dielectric layer 42 can be set to 300 nm, and the thickness d4 of the first dielectric layer 41 can be set to 50 nm.

[0052] It should be understood, as shown in FIG4 , that in the x-direction, the distance between the right end of the field plate 54 and the drain 53 is generally in the micrometer range, while the thicknesses of the second dielectric layer 42 and the first dielectric layer 41 are generally in the nanometer range. Therefore, the position encircled by the dotted circle p1 in the field plate 54 is closer to the drain 53. If the second dielectric layer 42 is set too thin, the breakdown resistance of the second dielectric layer 42 will be lower, which in turn will cause the position encircled by the dotted circle p1 in the field plate 54 to be short-circuited with the drain 53. Therefore, making the second dielectric layer 42 thicker can increase the breakdown resistance of the second dielectric layer 42, thereby improving the reliability and safety of the semiconductor device.

[0053] For example, the materials for manufacturing various structures in the semiconductor device may be, but are not limited to, arranged in the following manner:

[0054] The channel layer 20 may be made of, but is not limited to, GaN, etc.

[0055] The barrier layer 30 may be made of, but is not limited to, semiconductor materials such as AlGaN, AlN, InGaN, and ScAlN.

[0056] The material of the first dielectric layer 41 may include, but is not limited to, AlN, SiN, Al2O3, SiO2 and other dielectric materials;

[0057] The second dielectric layer 42 may be made of, but not limited to, dielectric materials such as AlN, SiN, Al2O3, and SiO2. The materials used to make the first dielectric layer 41 and the second dielectric layer 42 may be the same or different.

[0058] The gate 51 may be made of, but is not limited to, at least one of the following conductive materials: Ni, TiN, W, Pt, etc.

[0059] The source 52 , the drain 53 and the field plate 54 may be made of, but are not limited to, at least one of conductive materials such as Ti, Au, Al, and TiN.

[0060] Among them, the gate 51, the source 52, the drain 53 and the field plate 54 can be a multi-layer composite structure; taking the source 52 as an example, the source 52 can be set to the following structure: a composite structure composed of a stacked Ti layer and an Au layer, or a composite structure composed of a Ti layer, an Al layer and a Ti layer stacked in sequence, or a composite structure composed of a TiN layer, an Al layer and a TiN layer stacked in sequence, or a composite structure composed of a TiN layer, a Ti layer, an Al layer, a Ti layer and a TiN layer stacked in sequence, etc. Other composite structures are not listed here one by one.

[0061] FIG6 exemplarily shows a schematic structural diagram of a semiconductor device provided by the present application. As shown in FIG6 , the structure of the semiconductor device in this embodiment is substantially similar to the structure of the semiconductor device shown in FIG3 to FIG5 in the aforementioned embodiments, except that: both the sinking portion 54a and the groove T0 are provided with one. For example, when the field plate 54 extends along the first direction (i.e., the y-direction), the groove T0 is provided with one and extends along the y-direction, and the sinking portion 54a completely fills the groove T0, so that the portion of the field plate 54 filled in the groove T0 forms the sinking portion 54a, and the portion of the field plate 54 located outside the groove T0 forms the body 54b. In this way, the number of grooves T0 provided can be reduced, thereby reducing the number of second through holes provided. Since the first dielectric layer needs to be patterned and then etched when forming the first through hole and the second through hole, the simplified structure of the second through hole can simplify the difficulty of the patterning process, thereby reducing the difficulty of manufacturing the semiconductor device. Furthermore, the sinker 54a extends to the opposite ends of the body 54b arranged along the y direction, that is, the length of the body 54b in the y direction is equal to the length of the sinker 54a in the y direction. In this way, the field plate 54 can be fully utilized to set the sinker 54a between the gate 51 and the drain 53, further reducing the parasitic capacitance between the gate 51 and the drain 53, thereby further improving the performance of the semiconductor device.

[0062] It should be understood that the structure of the semiconductor device in this embodiment is similar to that of the semiconductor device shown in Figures 3 to 5 in the aforementioned embodiment. Please refer to the relevant introduction of the semiconductor device shown in Figures 3 to 5 in the aforementioned embodiment, and the repeated parts will not be repeated.

[0063] FIG7 exemplarily shows a schematic diagram of a method for manufacturing a semiconductor device provided by the present application. Referring to FIG7 , the method for manufacturing a semiconductor device may include:

[0064] Step S1, as shown in FIG7 (a), using but not limited to physical vapor deposition, using but not limited to GaN, epitaxially grows a GaN layer on the substrate, and the GaN layer can serve as a channel layer; then, using but not limited to physical vapor deposition, using but not limited to AlGaN, epitaxially grows an AlGaN layer on the GaN layer, and the AlGaN layer can serve as a barrier layer 30;

[0065] Step S2, as shown in FIG7 (a), Si ions are implanted by ion implantation to form a source region 61 and a drain region 62 in the GaN layer;

[0066] It is worth noting that when Si ions are implanted, Si ions are also implanted into the AlGaN layer, but they are not shown in (a) in FIG7 . However, since the ion implantation position will be subsequently etched away to expose the source region 61 and the drain region 62 , the ion implantation position in the AlGaN layer has little effect on the source region 61 and the drain region 62 in the GaN layer.

[0067] Step S3, as shown in FIG. 7 (a), a SiO2 layer is formed on the barrier layer 30 using, but not limited to, a physical vapor deposition method, using, but not limited to, SiO2, and the SiO2 layer serves as the first dielectric layer 41;

[0068] Step S4, as shown in FIG. 7( b ), etching the SiO 2 layer to form a first through hole T1 and a second through hole T2 , wherein both the first through hole T1 and the second through hole T2 penetrate the SiO 2 layer to expose the barrier layer 30 ;

[0069] Of course, when forming the first through hole T1 and the second through hole T2 , they can be obtained simultaneously through one etching process, or they can be obtained separately through two etching processes.

[0070] Step S5, as shown in FIG7(c), using but not limited to physical vapor deposition, using but not limited to Ni and Au, sequentially depositing a Ni layer and an Au layer on the SiO2 layer, so that the Ni layer and the Au layer constitute a first composite layer; and sequentially patterning and etching the first composite layer, so that the remaining structure fills the first through hole T1 and contacts the barrier layer 30, while the second through hole T2 is exposed. At this time, the remaining structure can serve as the gate 51;

[0071] Step S6, as shown in (d) of FIG7 , a SiN layer is formed by using, but not limited to, physical vapor deposition (PVD) and SiN. The SiN layer covers the gate 51 and the first dielectric layer 41 and fills the second through hole T2. At this time, a groove T0 is formed on the surface of the SiN layer at a position corresponding to the second through hole T2 due to filling the second through hole T2. The groove T0 is naturally formed and does not need to be formed by etching. The SiN layer serves as the second dielectric layer 42.

[0072] Step S7, as shown in (e) of FIG. 7 , patterning and etching the SiN layer, the SiO2 layer, and the AlGaN layer to form a third through hole T3 and a fourth through hole T4 that sequentially penetrate the SiN layer, the SiO2 layer, and the AlGaN layer, and the gate 51 and the second through hole T2 are both provided between the third through hole T3 and the fourth through hole T4, the third through hole T3 exposes the source region 61 in the GaN layer, and the fourth through hole T4 exposes the drain region 62 in the GaN layer;

[0073] Step S8, as shown in (f) of Figure 7, a physical vapor deposition method is used, but not limited to, and Ti and Au are used, to deposit a Ti layer and an Au layer in sequence on the SiN layer, so that the Ti layer and the Au layer constitute a second composite layer; and the second composite layer is patterned and etched in sequence, so that the structure filling the groove T0 and located on the portion of the SiN layer is a field plate 54, the structure filling the third through hole T3 is a source electrode 52, and the source electrode 52 is in contact with the source region 61 through the third through hole T3, and the structure filling the fourth through hole T4 is a drain electrode 53, and the drain electrode 53 is in contact with the drain region 62 through the fourth through hole T4, and the source electrode 52 is connected to the field plate 54, thereby forming a semiconductor device.

[0074] First, because the groove T0 in the second dielectric layer 42 is naturally formed rather than formed by etching, one etching process can be eliminated, simplifying the semiconductor device manufacturing steps and reducing manufacturing costs. It also avoids the problem of reduced manufacturing yield caused by etching deviation when forming the groove T0 by etching, thereby improving the semiconductor device manufacturing yield and the stability of the manufacturing process. Second, when etching the SiO2 layer to form the first through hole T1 and the second through hole T2, the AlGaN layer can be used as an etch stop layer due to the large difference in etching selectivity between the AlGaN layer and the SiO2 layer. This provides strong controllability and avoids over-etching during etching that could damage the GaN layer. This also improves the semiconductor device manufacturing yield and the stability of the manufacturing process. Third, the source 52, drain 53, and field plate 54 are formed simultaneously. Compared to forming the source 52, drain 53, and field plate 54 separately, this simplifies the semiconductor device manufacturing process and reduces manufacturing costs. Fourthly, the portion of the field plate 54 filled in the groove T0 is a sinking portion, which can reduce the parasitic capacitance between the gate 51 and the drain 53 , thereby improving the performance of the semiconductor device.

[0075] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include such modifications and variations.

Claims

1. A semiconductor device, characterized in that: include: A channel layer, a barrier layer, a first dielectric layer and a second dielectric layer are stacked in sequence, wherein the first dielectric layer is provided with a first through hole and a second through hole penetrating therein; The semiconductor device also includes a gate and a field plate. The gate is arranged between the barrier layer and the second dielectric layer. The gate is connected to the barrier layer through the first through hole. The second dielectric layer fills the second through hole so that a groove is formed on the surface of the second dielectric layer corresponding to the position of the second through hole. The field plate is arranged on a side surface of the second dielectric layer away from the first dielectric layer, and the field plate fills the groove.

2. The semiconductor device according to claim 1, wherein The field plate extends along a first direction; The portion of the field plate filled in the groove is a sinking portion; The sinking parts are provided in plurality and arranged at intervals, and the sinking parts are arranged along the first direction.

3. The semiconductor device according to claim 2, wherein: There are a plurality of grooves, and the grooves are arranged at intervals.

4. The semiconductor device according to claim 1, wherein The field plate extends along a first direction; The portion of the field plate filled in the groove is a sinking portion; The groove is provided with one groove and extends along the first direction, and the sinking portion completely fills the groove.

5. The semiconductor device according to claim 4, wherein: The sinking portion extends to two opposite ends of the field plate arranged along the first direction.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that: The semiconductor device also includes a source and a drain; The semiconductor device further comprises: a third through hole and a fourth through hole respectively penetrating the second dielectric layer, the first dielectric layer and the barrier layer, the source electrode being connected to the source region in the channel layer through the third through hole, and the drain electrode being connected to the drain region in the channel layer through the fourth through hole; The source, the drain and the field plate are arranged in the same layer.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that: The distance between the bottom of the groove and the barrier layer is a first distance, the distance between the surface of the gate facing away from the barrier layer and the barrier layer is a second distance, and the first distance is not greater than the second distance.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that: The thickness difference of the second dielectric layer at different positions is no more than 500 nm.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that: The thickness of the second dielectric layer at any position is greater than the thickness of the first dielectric layer.

10. A method for manufacturing a semiconductor device, characterized in that: include: forming a channel layer on a substrate; forming a barrier layer on the channel layer; forming a first dielectric layer on the barrier layer; forming a first through hole and a second through hole penetrating the first dielectric layer; forming a gate on the first dielectric layer, wherein the gate is connected to the barrier layer through the first through hole; forming a second dielectric layer on the first dielectric layer on which the gate is formed, wherein the second dielectric layer fills the second through hole, so that a groove is formed in a position corresponding to the second through hole on the surface of the second dielectric layer; A field plate is formed on the second dielectric layer, and the field plate fills the groove.

11. The method according to claim 10, characterized in that: Also includes: After forming the second dielectric layer and before forming the field plate, respectively etching the second dielectric layer, the first dielectric layer and the barrier layer to form a third through hole and a fourth through hole, wherein the third through hole exposes the source region in the channel layer, and the fourth through hole exposes the drain region in the channel layer; Forming the field plate specifically includes: forming a source electrode, a drain electrode and the field plate simultaneously on the second dielectric layer, the source electrode is connected to the source region through the third through hole, and the drain electrode is connected to the drain region through the fourth through hole.

12. An electronic device, characterized in that: The invention comprises: a shell, and a semiconductor device according to any one of claims 1 to 9, wherein the semiconductor device is arranged in the shell.

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