Semiconductor assembly and method for producing a semiconductor chip

Abstract

A semiconductor assembly comprises a carrier wafer and a layer stack arranged on the carrier wafer. The layer stack comprises a metamaterial layer. The metamaterial layer is formed from one or more constituent materials. The metamaterial layer comprises a stiffness in the plane of the metamaterial layer that is larger than a natural stiffness of the constituent materials.

Description

[0001] SEMICONDUCTOR ASSEMBLY AND METHOD FOR PRODUCING A

[0002] SEMICONDUCTOR CHIP

[0003] DESCRIPTION

[0004] The present invention relates to a semiconductor assembly and to a method for producing a semiconductor chip.

[0005] This patent application claims the priority of German patent application 10 2023 136 028.0, the disclosure content of which is hereby incorporated by reference.

[0006] Wafer bow is a challenge in the fabrication of semiconductor chips. Wafer bow occurs due to strain arising from lattice mismatches and different thermal expansions of deposited layers as well as different process conditions. In order to reduce wafer bow, it is known in the state of the art to provide wafers with stiff layers.

[0007] It is an object of the present invention to provide a semiconductor assembly. It is a further object of the present invention to provide a method for producing a semiconductor chip. These objectives are achieved by a semiconductor assembly and by a method for producing a semiconductor chip according to the independent claims. Further variants are disclosed in the dependent claims.

[0008] A semiconductor assembly comprises a carrier wafer and a layer stack arranged on the carrier wafer. The layer stack comprises a metamaterial layer. The metamaterial layer is formed from one or more constituent materials. The metamaterial layer comprises a stiffness in the plane of the metamaterial layer that is larger than a natural stiffness of the constituent materials.

[0009] The metamaterial layer of the layer stack of this semiconductor assembly may serve to reduce a wafer bow during the fabrication of the semiconductor assembly. Advantageously, the metamaterial layer can comprise a very high stiffness. In addition, the metamaterial layer may comprise a low weight. The metamaterial layer may also comprise other properties that are tailored to specific needs, such as a thermal expansion coefficient that is adjusted to those of other layers of the layer stack of the semiconductor assembly.

[0010] In a variant of the semiconductor assembly, the metamaterial layer is structured in the plane of the metamaterial layer. The metamaterial layer is constant in a direction perpendicular to the plane of the metamaterial layer. Advantageously, a metamaterial layer that is only structured in the plane of the metamaterial layer can be fabricated in a simple and cost-effective way.

[0011] In a variant of the semiconductor assembly, the metamaterial layer comprises first regions and second regions alternating in the plane of the metamaterial layer. The first regions have a positive Poisson' s ratio and the second regions have a negative Poisson's ratio. It has been shown that a two- dimensional arrangement of alternating regions having positive and negative Poisson' s ratios provides an enhanced inplane stiffness because a strain in one region is counteracted by an opposite strain in another region. This causes the effective stiffness of the layer as a whole to be higher than the stiffness of the constituent materials.

[0012] In a variant of the semiconductor assembly, the first regions comprise a first effective Young's modulus and the second regions comprise a second effective Young' s modulus. A ratio between the smaller of the first effective Young's modulus and the second effective Young's modulus and the larger of the first effective Young' s modulus and the second effective Young' s modulus is larger than 0.11. It has been shown that first regions and second regions comprising such effective Young' s moduli are suitable for forming a metamaterial that comprises an enhanced stiffness. In a variant of the semiconductor assembly, each second region is rectangular in the plane of the metamaterial layer. Advantageously, this allows for forming a simple and regular pattern of first regions and second regions.

[0013] In a variant of the semiconductor assembly, the first regions and the second regions are arranged in a checkerboard pattern. This provides a simple and regular pattern.

[0014] In a variant of the semiconductor assembly, an edge length of each second region is between 1 pm and 100 pm. Advantageously, second regions having such an edge length are large enough to be fabricated in a simple and reliable way and are also small enough to ensure homogeneous properties of the resulting metamaterial layer.

[0015] In a variant of the semiconductor assembly, the second regions comprise a substructure formed from cells in the plane of the metamaterial layer. This substructure can be designed to adjust the Poisson' s ratio of the second regions to a desired value.

[0016] In a variant of the semiconductor assembly, each cell comprises a width and a height. The width and the height are both smaller than half of the edge length. This means that the relative sizes of the cells and the second regions are such that each second region comprises a plurality of cells.

[0017] In a variant of the semiconductor assembly, each cell comprises lattice bars forming a 2D re-entrant honeycomb cell. It has been shown that 2D re-entrant honeycomb cells are suitable for achieving a negative Poisson' s ratio.

[0018] In a variant of the semiconductor assembly, the lattice bars comprise TiW. Advantageously, TiW already comprises a large inherent stiffness, allowing to form a metamaterial layer having an even larger in-plane stiffness. In a variant of the semiconductor assembly, areas between the lattice bars are filled with a material that is different from a material of the lattice bars. That material may comprise a lower stiffness than the material of the lattice bars. The areas between the lattice bars may be filled with SiO2or air, for example.

[0019] In a variant of the semiconductor assembly, the second regions comprise first subregions and second subregions alternating in the plane of the metamaterial layer. The first subregions and the second subregions comprise different substructures. Dividing the second regions into subregions having different substructures allows to reduce an anisotropy in the effective stiffness of the metamaterial layer.

[0020] In a variant of the semiconductor assembly, the substructure of the first subregions is rotated around 90° with respect to the substructure of the second subregions. Advantageously, this may provide a simple and effective compensation of an anisotropy caused by a pattern of the substructures.

[0021] In a variant of the semiconductor assembly, the metamaterial layer does not comprise a substructure in the first regions. This allows for a simple design of the metamaterial layer.

[0022] In another variant of the semiconductor assembly, the first regions comprise a substructure in the plane of the metamaterial layer. A substructure of the first regions provides additional freedom to tune properties of the metamaterial layer in a desired way. The substructure of the first regions may be designed such that the metamaterial layer comprises a desired coefficient of thermal expansion, for example.

[0023] In a variant of the semiconductor assembly, each first region comprises TiW and at least one opening that is filled with a material different from TiW. Other patterns are possible as well . In a variant of the semiconductor assembly, the layer stack is arranged on the carrier wafer such that the metamaterial layer is arranged between the carrier wafer and an epitaxial layer of the layer stack. Advantageously, a position of the metamaterial layer between the carrier wafer and epitaxial layer allows the metamaterial layer to effectively reduce a wafer bow of the semiconductor assembly.

[0024] A method for producing a semiconductor chip comprises providing a carrier wafer and arranging a layer stack on the carrier wafer. The layer stack comprises a metamaterial layer. The metamaterial layer is formed from one or more constituent materials. The metamaterial layer comprises a stiffness in the plane of the metamaterial layer that is larger than a natural stiffness of the constituent materials. The method further comprises dividing the carrier wafer and the layer stack to singulate the semiconductor chip.

[0025] The metamaterial layer may help to reduce a wafer bow of the carrier wafer and the layer stack that occurs during the production of the semiconductor chip. To this end, the metamaterial layer may advantageously comprise a very high stiffness in the plane of the metamaterial layer.

[0026] In a variant of the method, arranging the layer stack comprises providing a growth wafer, arranging the layer stack on the growth wafer, bonding the layer stack to the carrier wafer, and removing the growth wafer. In this variant, the metamaterial layer may reduce a wafer bow of both the growth wafer and the carrier wafer.

[0027] The above-described properties, features, and advantages of the invention, as well as the way in which they are achieved, will become more clearly and comprehensively understandable in connection with the following description of exemplary variants, which will be explained in more detail in connection with the drawings, in which, in schematic representation : Figure 1 shows a sectional drawing of a semiconductor assembly comprising a metamaterial layer before removing a growth wafer;

[0028] Figure 2 shows the semiconductor assembly after removing the growth wafer;

[0029] Figure 3 shows a top view of a variant of the metamaterial layer ;

[0030] Figure 4 shows a cellular substructure of second regions of the metamaterial layer;

[0031] Figure 5 shows a top view of a variant of the metamaterial layer; and

[0032] Figure 6 shows a top view of a further variant of the met- amaterial layer.

[0033] Figure 1 shows a schematic sectional drawing of a part of a semiconductor assembly 100. The depicted semiconductor assembly 100 is an unfinished product during a production of semiconductor chips.

[0034] The semiconductor assembly 100 comprises a growth wafer 160. A layer stack 120 has been arranged on the growth wafer 160. The layer stack 120 comprises an epitaxial layer 130 and a metamaterial layer 200. The epitaxial layer 130 is arranged between the growth wafer 160 and the metamaterial layer 200. The epitaxial layer 130 may have been produced by epitaxial growth, for example. The epitaxial layer 130 may comprise active layers of the final semiconductor chips.

[0035] In the example depicted in Figure 1, the layer stack 120 further comprises a metal layer 140 that is arranged between the epitaxial layer 130 and the metamaterial layer 200. The metal layer 140 may serve to provide an electrical connection to the epitaxial layer 130.

[0036] The layer stack 120 is bonded to a carrier wafer 110 by means of a bonding metal layer 150 which is arranged between the carrier wafer 110 and the metamaterial layer 200. Bonding the layer stack 120 to the carrier wafer 110 has happened after arranging the layer stack 120 on the growth wafer 160.

[0037] Figure 2 shows a schematic depiction of the semiconductor assembly 100 in a processing state that follows the depiction of Figure 1. The growth wafer 160 has been removed from the layer stack 120 such that the layer stack 120 remains on the carrier wafer 110. Removing the growth wafer 160 may have been carried out by a laser-lift-off method, for example.

[0038] Afterwards, the epitaxial layer 130 has been structured and the carrier wafer 110 has been thinned. Then an additional metal layer 170 has been arranged on the side of the carrier wafer 110 that is opposed to the layer stack 120.

[0039] In a following production step, the carrier wafer 110 and the layer stack 120 may be divided to singulate a plurality of semiconductor chips 101.

[0040] The production steps described above with reference to Figures 1 and 2 only serve as an example. The fabrication of the semiconductor assembly 100 may follow a different procedure. For example, the layer stack 120 may be arranged directly on the carrier wafer 110 without using a separate growth wafer. The layer stack 120 may include other or further layers. The ordering of the layers may differ from the depiction of Figure 1.

[0041] In any case, however, the layer stack 120 includes the metamaterial layer 200. The metamaterial layer 200 may be arranged at a different position in the layer stack 120, howev- er . The metamaterial layer 200 is provided to stabilise the semiconductor assembly 100 during the fabrication of the semiconductor chips 101. In particular, the metamaterial layer 200 is provided to reduce or completely prevent a wafer bow of the semiconductor assembly 100 during the fabrication procedure. A wafer bow may be prevented in a production state before attaching the carrier wafer 110, in the production state depicted in Figure 1 or in a production state after removing the growth wafer 160.

[0042] The metamaterial layer 200 is arranged in a plane 10 that extends in a first in-plane direction 11 and a second in-plane direction 12. The plane 10 of the metamaterial layer 200 is parallel to an upper side of the carrier wafer 110 and to an upper side of the growth wafer 160. A direction 13 is perpendicular to the plane 10 of the metamaterial layer 200.

[0043] In the perpendicular direction 13, the metamaterial layer 200 comprises a layer thickness 201. The layer thickness 201 may be between 300 nm and 450 nm, for example. The layer thickness 201 may be around 370 nm, for example.

[0044] The metamaterial layer 200 is formed from one or more constituent materials. In the plane 10 of the metamaterial layer 200, the metamaterial layer 200 comprises a stiffness that is larger than a natural stiffness of the constituent materials. This means that the stiffness of the metamaterial layer 200 in the plane 10 is larger than a homogeneous layer of any of the constituent materials of the metamaterial layer 200.

[0045] The metamaterial layer 200 may comprise an electrically conductive material such as a metal. In this case, the metamaterial layer 200 may support a current transport through the metamaterial layer 200. An electrical conductivity of the metamaterial layer 200 may be such that it does not significantly increase a series resistance. To obtain the enhanced stiffness of the metamaterial layer 200 in the plane 10, the metamaterial layer 200 is structured in the plane 10. In the perpendicular direction 13, the metamaterial layer 200 is constant in the examples described here. In other variants, however, the metamaterial layer 200 may also be structured in the perpendicular direction 13.

[0046] Figure 3 shows a schematic top view of a section of a first variant of the metamaterial layer 200. The metamaterial layer 200 comprises first regions 300 and second regions 400. The first regions 300 and the second regions 400 alternate in the plane 10 of the metamaterial layer 200.

[0047] In the example of Figure 3, each first region 300 and each second region 400 is rectangular in the plane 10 of the metamaterial layer 200. The first regions 300 and the second regions 400 are arranged in a checkerboard pattern 210. An edge length 401 of each second region 400 may be between 1 pm and 100 pm, for example. A perpendicular edge of each second region 400 may comprise a similar edge length. The first regions 300 may comprise similar edge lengths as well.

[0048] In the example of Figure 3, the edges of each first region 300 and each second region 400 are oriented in parallel to the first in-plane direction 11 and the second in-plane direction 12.

[0049] In other variants, the first regions 300 and the second regions 400 may comprise different shapes and may be arranged in a different pattern.

[0050] The first regions 300 have a positive Poisson' s ratio. The second regions 400 are structured such that they have a negative Poisson's ratio. The first regions 300 having a positive Poisson' s ratio and the second regions 400 having a negative Poisson' s ratio have the effect that a strain in a first region 300 is counteracted by an opposite strain in a second region 400 and vice versa. This causes the effective stiff- ness of the entire metamaterial layer 200 to be higher than the stiffness of the constituent materials of the metamaterial layer 200.

[0051] In order for this effect to be significant, it may be convenient that the first regions 300 comprise a first effective Young' s modulus and the second regions 400 comprise a second effective Young' s modulus and a ratio between the smaller of the first effective Young' s modulus and the second effective Young' s modulus and the larger of the first effective Young' s modulus and the second effective Young's modulus is larger than 0.11. In other words, the smaller effective Young's modulus should be larger than 0.11 of the larger effective Young' s modulus in order to achieve an enhanced effective stiffness that is larger than the natural constituent value.

[0052] The second regions 400 may occupy between 40% and 70% of the area of the metamaterial layer 200 in the plane 10, for example, such that the first regions 300 occupy between 30% and 60% of the area of the metamaterial layer 200.

[0053] In order to achieve a negative Poisson's ratio, the second regions 400 comprise a cellular substructure 410 formed from cells 420 in the plane 10 of the metamaterial layer 200. Figure 4 shows a schematic depiction of one cell 420 of the cellular substructure 410. Each cell 420 comprises a width 421 measured in the first in-plane direction 11 and a height 422 measured in the second in-plane direction 12. It is convenient if both the width 421 and the height 422 are smaller than half of the edge length 401 of the second regions 400 such that each second region 400 comprises at least two cells in both the first in-plane direction 11 and the second inplane direction 12.

[0054] Each cell 420 comprises lattice bars 440 that form a 2D reentrant honeycomb cell 430. The 2D re-entrant honeycomb cell 430 comprises a re-entrant angle 431 that is smaller than The lattice bars 440 comprise a bar thickness 441 measured in the plane 10. The bar thickness 441 may be chosen such that a square of the bar thickness 441 is larger than 1% of the product of the width 421 and the height 422 of the cell 420, for example.

[0055] The lattice bars 440 comprise a material 445. The material 445 may be TiW, for example. The material 445 may comprise 10% Ti and 90% W, for example.

[0056] Intermediate areas 450 between the lattice bars 440 are filled with a material 455 that is different from the material 445 of the lattice bars 440. The material 455 may be less stiff than the material 445 of the lattice bars 440. The material 455 may be SiO2or air, for example.

[0057] The metamaterial layer 200 may be produced by an additive fabrication method using a mask, for example. Alternatively, a method such as direct laser writing can be used.

[0058] The first regions 300 of the metamaterial layer 200 do not comprise a substructure in the example depicted in Figure 3. The first regions 300 comprise a material 305 that may be the same as the material 445 of the lattice bars 440, for example .

[0059] Figure 5 shows a schematic top view of a second variant of the metamaterial layer 200. The second variant of the metamaterial layer 200 is similar to the first variant of the metamaterial layer 200 depicted in Figure 3. The following description of the second variant of the metamaterial layer 200 focusses on the differences between both variants. Otherwise, the description of the first variant of the metamaterial layer 200 also applies to the second variant of the metamaterial layer 200. In the second variant of the metamaterial layer 200, the second regions 400 comprise first subregions 500 and second subregions 600 alternating in the plane 10 of the metamaterial layer 200. The first subregions 500 comprise a substructure 510 and the second subregions 600 comprise a different substructure 610.

[0060] Both the first subregions 500 and the second subregions 600 comprise rectangular shapes in the plane 10 of the metamaterial layer 200 and at least one edge length of each first subregion 500 and each second subregion 600 may be in the range between 10 pm and 100 pm. The first subregions 500 of the second regions 400, the second subregions 600 of the second regions 400 and the first regions 300 may be arranged in different patterns in the plane 10, depending on the relative sizes of the first regions 300 and subregions 500, 600. It is convenient if the first regions 300, the first subregions 500 and the second subregions 600 form a pattern with a high degree of symmetry.

[0061] In the example depicted in Figure 5, the substructure 610 of the second subregions 600 is the same as the substructure 410 of the second regions 400 of the first variant of the metamaterial layer 200 depicted in Figure 3. The substructure 510 of the first subregions 500 is rotated around 90% in the plane 10 with respect to the substructure 610 of the second subregions 600. In this way, an anisotropy of the effective stiffness of the second regions 400 in the plane 10 may be reduced or overcome.

[0062] In other variants of the metamaterial layer 200, the substructure 610 of the second subregion 600 is not rotationally symmetric to the substructure 510 of the first subregion 500. In further variants of the metamaterial layer 200, the second regions 400 comprise more than two different subregions 500, 600 with different substructures Figure 6 shows a schematic top view of a third variant of the metamaterial layer 200. The third variant of the metamaterial layer 200 is similar to the first variant of the metamaterial layer 200 depicted in Figure 3. The following description will focus on the differences between these variants of the metamaterial layer 200. Otherwise, the description of the first variant of the metamaterial layer 200 also applies to the third variant of the metamaterial layer 200.

[0063] In the third variant of the metamaterial layer 200, the first regions 300 comprise a substructure 310 in the plane 10 of the metamaterial layer 200. In this example, each first region 300 comprises openings 320 that are filled with a material 325 that is different from the material 305 of the other areas of the first regions 300. The openings 320 extend through the metamaterial layer 200 in the perpendicular direction 13. In the example depicted in Figure 6, each first region 300 comprises nine openings 320 arranged in a

[0064] 3x3 matrix pattern. However, a different number and different arrangements of the openings 320 are possible.

[0065] The material 325 arranged in the openings 320 may be chosen to adjust a desired property of the metamaterial layer 200, for example a thermal expansion coefficient of the metamaterial layer 200.

[0066] In other variants of the metamaterial layer 200, the first regions 300 are divided into different subregions having different substructures. In further variants of the metamaterial layer 200, the first regions 300 are designed as explained in conjunction with Figure 6 while the second regions 400 are designed as explained in conjunction with Figure 5.

[0067] The invention has been illustrated and described in more detail with the aid of exemplary variants. The invention is not, however, restricted to the examples disclosed. Rather, other variants may be derived therefrom by the person skilled in the art . REFERENCE SYMBOLS

[0068] 10 plane o f the metamaterial layer

[0069] 11 f irst in-plane direction

[0070] 12 second in-plane direction

[0071] 13 perpendicular direction

[0072] 100 semiconductor assembly

[0073] 101 semiconductor chip

[0074] 110 carrier wafer

[0075] 120 layer stack

[0076] 130 epitaxial layer

[0077] 140 metal layer

[0078] 150 bonding metal layer

[0079] 160 growth wafer

[0080] 170 metal layer

[0081] 200 metamaterial layer

[0082] 201 layer thickness

[0083] 210 checkerboard pattern

[0084] 300 f irst region

[0085] 305 material

[0086] 310 substructure

[0087] 320 opening

[0088] 325 material

[0089] 400 second region

[0090] 401 edge length

[0091] 410 substructure

[0092] 420 cel l

[0093] 421 width

[0094] 422 height

[0095] 430 2D re-entrant honeycomb cel l

[0096] 431 re-entrant angle

[0097] 440 lattice bars

[0098] 441 bar thickness 445 material

[0099] 450 intermediate area

[0100] 455 material 500 f irst subregion

[0101] 510 substructure

[0102] 600 second subregion

[0103] 610 substructure

Claims

CLAIMS1. A semiconductor assembly (100) comprising a carrier wafer (110) and a layer stack (120) arranged on the carrier wafer (110) , wherein the layer stack (120) comprises a metamaterial layer (200) , wherein the metamaterial layer (200) is formed from one or more constituent materials (305, 325, 445, 455) , wherein the metamaterial layer (200) comprises a stiffness in the plane (10) of the metamaterial layer (200) that is larger than a natural stiffness of the constituent materials (305, 325, 445, 455) .

2. The semiconductor assembly (100) as claimed in claim 1, wherein the metamaterial layer (200) is structured in the plane (10) of the metamaterial layer (200) , wherein the metamaterial layer (200) is constant in a direction (13) perpendicular to the plane (10) of the metamaterial layer (200) .

3. The semiconductor assembly (100) as claimed in one of the preceding claims, wherein the metamaterial layer (200) comprises first regions (300) and second regions (400) alternating in the plane (10) of the metamaterial layer (200) , wherein the first regions (300) have a positive Poisson's ratio and the second regions (400) have a negative Poisson' s ratio .

4. The semiconductor assembly (100) as claimed in claim 3, wherein the first regions (300) comprise a first effective Young's modulus and the second regions (400) comprise a second effective Young's modulus, wherein a ratio between the smaller of the first effective Young's modulus and the second effective Young's modulus and the larger of the first effective Young' smodulus and the second effective Young's modulus is larg- er than 0.11.

5. The semiconductor assembly (100) as claimed in one of claims 3 and 4, wherein each second region (400) is rectangular in the plane (10) of the metamaterial layer (200) .

6. The semiconductor assembly (100) as claimed in claim 5, wherein the first regions (300) and the second regions (400) are arranged in a checkerboard pattern (210) .

7. The semiconductor assembly (100) as claimed in one of claims 5 and 6, wherein an edge length (401) of each second region (400) is between 1 gm and 100 pm.

8. The semiconductor assembly (100) as claimed in one of claims 3 to 7, wherein the second regions (400) comprise a substructure (410, 510, 610) formed from cells (420) in the plane (10) of the metamaterial layer (200) .

9. The semiconductor assembly (100) as claimed in claims 7 and 8 , wherein each cell (420) comprises a width (421) and a height ( 422 ) , wherein the width (421) and the height (422) are smaller than half of the edge length (401) .

10. The semiconductor assembly (100) as claimed in one of claims 8 and 9, wherein each cell (420) comprises lattice bars (440) forming a 2D re-entrant honeycomb cell (430) .

11. The semiconductor assembly (100) as claimed in claim 10, wherein the lattice bars (440) comprise TiW.

12. The semiconductor assembly (100) as claimed in one of claims 10 and 11, wherein areas (450) between the lattice bars (440) are filled with a material (455) that is different from a material (445) of the lattice bars (440) .

13. The semiconductor assembly (100) as claimed in one of claims 3 to 12, wherein the second regions (400) comprise first subregions (500) and second subregions (600) alternating in the plane (10) of the metamaterial layer (200) , wherein the first subregions (500) and the second subregions (600) comprise different substructures (510, 610) .

14. he semiconductor assembly (100) as claimed in claim 13, wherein the substructure (510) of the first subregions (500) is rotated around 90° with respect to the substructure (610) of the second subregions (600) .

15. he semiconductor assembly (100) as claimed in one of claims 3 to 14, wherein the metamaterial layer (200) does not comprise a substructure in the first regions (300) .

16. The semiconductor assembly (100) as claimed in one of claims 3 to 14, wherein the first regions (300) comprise a substructure (310) in the plane (10) of the metamaterial layer (200) .

17. The semiconductor assembly (100) as claimed in claim 16, wherein each first region (300) comprises TiW and at least one opening (320) that is filled with a material (325) different from TiW.

18. The semiconductor assembly (100) as claimed in one of the preceding claims, wherein the layer stack (120) is arranged on the carrier wafer (110) such that the metamaterial layer (200) is ar-ranged between the carrier wafer (110) and an epitaxial layer (130) of the layer stack (120) .

19. A method for producing a semiconductor chip (101) , comprising- providing a carrier wafer (110) ;- arranging a layer stack (120) on the carrier wafer (110) , wherein the layer stack (120) comprises a metamaterial layer (200) , wherein the metamaterial layer (200) is formed from one or more constituent materials (305, 325, 445, 455) , wherein the metamaterial layer (200) comprises a stiffness in the plane (10) of the metamaterial layer (200) that is larger than a natural stiffness of the constituent materials (305, 325, 445, 455) ;- dividing the carrier wafer (110) and the layer stack (120) to singulate the semiconductor chip (101) .

20. The method as claimed in claim 19, wherein arranging the layer stack (120) comprises- providing a growth wafer (160) ;- arranging the layer stack (120) on the growth wafer (160) ;- bonding the layer stack (120) to the carrier wafer (110) ;- removing the growth wafer (160) .

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