A CFET structure with a frontside power routing line and a backside power rail

Abstract

The present disclosure refers to a complementary field effect transistor (CFET) structure and to a method of fabricating such a CFET structure. The CFET structure comprises a dielectric wall (25) and a first CFET element, which comprises a first transistor structure (21) and a second transistor structure (22), a first power rail (13), and a power routing line (16). The first and the second transistor structure are both arranged on a first side of the dielectric wall, and the second transistor structure is arranged above the first transistor structure. The first power rail is arranged below the first transistor structure and is electrically connected to a source and / or drain structure of the first transistor structure from the bottom, and the power routing line is arranged above the second transistor structure.

Description

[0001] A CFET STRUCTURE WITH A FRONTSIDE POWER ROUTING LINE AND A BACKSIDE POWER RAIL

[0002] TECHNICAL FIELD

[0003] The present disclosure refers to a complementary field effect transistor (CFET) structure and to a method of fabricating such a CFET structure. The CFET structure proposed in this disclosure comprises a CFET element, a frontside power routing line, and a backside power rail.

[0004] BACKGROUND

[0005] In a CFET device or structure, different transistor structures, for instance NMOS and PMOS transistors, maybe stacked on top of each other compared, for example, to a nanosheet device, which comprises NMOS and PMOS transistors arranged side by side with a spacing in between them. The stacking of the transistor structures in the CFET device enables increasing an effective channel width.

[0006] A CFET device can contain many CFET elements or cells, which can be formed by a number of stacked NMOS and PMOS transistors. The CFET cells can form logic cells of the CFET device (e.g., inverter cells or NAND cells). An exemplary implementation of a CFET cell may comprise two NMOS transistor structures and two PMOS transistor structures, which are processed in a stacked manner.

[0007] An issue in an exemplary conventional CFET device is related to the power supply to the stacked transistor structures. Depending on the configuration, a bottom transistor structure is supplied by a VDD voltage while a top transistor structure (above the bottom structure) is supplied by a VSS voltage, or vice versa. The VSS and VDD voltages are typically provided by buried power rails (BPR), which are arranged below the CFET cells. However, it is difficult to route the power from such a BPR to the top transistor structures in the CFET cells. A possible solution for supplying the top transistor structures are so-called tap cells. Tap cells are dedicated cells which connect a backside power supply to a local power supply of a cell, e.g., a BPR or a metal intermediate (Mint) VSS. However, tap cells are usually arranged in regular columns covering the whole height of the chip and require a significant portion of the overall CFET device area (typically 4- 5%). This causes an area penalty and reduces the total number of otherwise usable CFET logic cells.

[0008] SUMMARY

[0009] Thus, an objective is to provide an improved CFET structure and an improved method of fabricating a CFET structure. In particular, the above-mentioned disadvantages should be avoided.

[0010] These and other objectives are achieved by the solutions provided in the independent claims. Advantageous implementations are further defined in the dependent claims.

[0011] A first aspect of this disclosure provides a CFET structure, which comprises: a dielectric wall; a first CFET element comprising a first transistor structure and a second transistor structure, wherein the first and the second transistor structure are both arranged on a first side of the dielectric wall, and wherein the second transistor structure is arranged above the first transistor structure; a first power rail arranged below the first transistor structure and electrically connected to a source and / or drain structure of the first transistor structure from the bottom; and a power routing line arranged above the second transistor structure.

[0012] The CFET structure of the first aspect has the advantage that a power supply to the stacked first and second transistor structures of the first CFET element is facilitated. In particular, a power supply of the first transistor structure can be routed from the first power rail located at the backside of the CFET structure, while a power supply of the second transistor structure can be routed from the power routing line located at the frontside of the CFET structure. The power routing line can, for instance, supply multiple (top) transistor structures of various CFET elements of the CFET structure with power.

[0013] The dielectric wall has no conductive part. The dielectric wall, for example, may consist of dielectric material. The dielectric wall is not electrically connected to power, for example, it is neither electrically connected to the power routing line, nor to the first power rail (or any other power rail).

[0014] The first power rail can accordingly be a backside power rail. The first power rail can be a VSS or VDD power rail. Thus, the first power rail can supply a VSS or VDD voltage to the first transistor structure. The power routing line may likewise be used for providing a VSS or VDD voltage to the second transistor structure. The first power rail may be shared by multiple CFET elements.

[0015] The first transistor structure can be referred to as a bottom transistor structure of the CFET element, and the second transistor structure can be referred to as a top transistor structure. For example, the first (or bottom) transistor structure maybe arranged in a first tier (or level), and the second (or top) transistor structure may be arranged in a second tier (or level) of the CFET structure, wherein the second tier is arranged above the first tier. This may result in the stacked transistor structure arrangement of the CFET element. The first and second transistor structure can comprise respective channel layers, as well as respective gate structures or a common gate structure, and source / drain structures alternatively arranged along a channel direction.

[0016] The first and second transistor structure of the CFET element may be vertically aligned (i.e., directly on top of each other with no vertical and / or horizontal displacement). The CFET element may comprise further transistor structures or other elements, which could respectively be directly above or beneath the first and second transistor structure.

[0017] The CFET element can be a CFET cell or can be a part of a CFET cell. For instance, the transistor structures of the CFET element can be components of the CFET cell. The CFET cell can form a logic cell or a unit cell of the CFET structure (e.g., an inverter or NAND cell). The CFET structure may comprise a plurality of CFET elements and / or CFET cells.

[0018] Notably, throughout this disclosure the terms “below” and “above”, “bottom” and “top”, “front”, “frontside”, “back” and “backside”, or similar terms, are to be interpreted relative to each other. In particular, these terms describe opposite sides of the CFET structure, or opposite sides of any element of the CFET structure. The terms may describe a relationship of elements (e.g., transistor structures, signal routing lines, power rails, etc.) of the CFET structure along the direction of stacking of the tiers (or levels) of the CFET structure. The stacking direction may thus align with the arrangement of the two tiers (or even more than two tiers) of the CFET structure. That is, the two or more tiers (or levels), which are arranged above each other, are arranged one after the other along a certain direction (the stacking direction).

[0019] A transistor structure in this disclosure may be or may comprise a transistor, for example, a field effect transistor (FET), or maybe or may comprise a more complex semiconductor-based structure, which functions like a transistor. For instance, the semiconductor-based structure may be a nanosheet structure, a fin structure, or a forksheet structure, for example, provided with a gate partly wrapping around or fully wrapping around channel portions. The latter may be a gate-all-around structure.

[0020] A source and / or drain structure may comprise a source region and / or a drain region. A gate structure may comprise a gate, for instance, comprising a gate dielectric and gate metal.

[0021] The transistor structures of the CFET structure of the first aspect may be NMOS and PMOS transistor structures. For instance, the first transistor structure maybe an NMOS transistor structure, and the second transistor structure a PMOS transistor structure, or vice versa. In an exemplary embodiment of the CFET structure, the power routing line is electrically connected to a source and / or drain structure of the second transistor structure from the top.

[0022] Thus, a frontside power supply is provided to the second transistor structure, and a backside power supply is provided to the first transistor structure, which allows making the CFET structure compact.

[0023] In an exemplary embodiment of the CFET structure, the CFET structure further comprises: a second CFET element comprising a third transistor structure and a fourth transistor structure, wherein the third and the fourth transistor structure are both arranged on a second side of the dielectric wall, and wherein the fourth transistor structure is arranged above the third transistor structure; wherein the first power rail is arranged below the third transistor structure and is electrically connected to a source and / or drain structure of the third transistor structure from the bottom; and wherein the power routing line is arranged above the fourth transistor structure.

[0024] The first and the second CFET element may be fabricated in a forksheet architecture, which may improve transistor scaling. In the forksheet architecture, NMOS and PMOS transistor structures of the two CFET elements may respectively be separated by the dielectric wall.

[0025] In an exemplary embodiment of the CFET structure, the power routing line is electrically connected to a source and / or drain structure of the fourth transistor structure from the top.

[0026] The power routing line maybe connected electrically in this way to none of, one of, or both of the second transistor structure and the fourth transistor structure. The power routing line may also be connected to further transistors in the CFET element (e.g., further transistors in the CFET cell), and even to transistors of further CFET cells. In an exemplary embodiment of the CFET structure, the power routing line is arranged directly above the dielectric wall and / or runs in parallel to the dielectric wall.

[0027] This may mean that the power routing line is laterally centered with the dielectric wall, for instance, by fabricating it in a self-aligning manner to the dielectric wall, as explained later in this disclosure.

[0028] In an exemplary embodiment of the CFET structure, the CFET structure further comprises: a second power rail arranged below the first transistor structure; and a tap connection structure, which is arranged to electrically connect the second power rail with the source and / or drain structure of the second transistor structure; wherein the tap connection structure is arranged to bypass the first transistor structure on one side.

[0029] The CFET element, which comprises the tap connection structures, can otherwise maintain its full logic functionality in a CFET cell. In particular, no dedicated tap cells are required in the CFET structure.

[0030] The second power rail can be a backside power rail. The second power rail can be a VSS or VDD power rail. Thus, the second power rail can supply a VSS or VDD voltage to the second transistor structure, and possibly also to the top power routing line via the tap connection structure. The second power rail is not electrically connected to the dielectric wall. The second power rail may be shared by multiple CFET elements.

[0031] For example, a CFET element can have one or a plurality of tap connection structures.

[0032] In an exemplary embodiment of the CFET structure, a section of the source and / or drain structure of the second transistor structure protrudes beyond the first transistor structure; and wherein the tap connection structure contacts the protruding section of the source and / or drain structure from the bottom. This facilitates connecting the tap connection structure. For example, the tap connection structure may be arranged on one side of the CFET element, while the power routing line is connected to the source and / or drain structure at the other (opposite) side of the CFET element.

[0033] In an exemplary embodiment of the CFET structure, the CFET structure further comprises: a side routing structure, which is arranged to electrically connect the first transistor structure with a further transistor structure of the first CFET element, the further transistor structure being arranged above the first transistor structure; wherein the side routing structure is arranged on the same side of the first CFET element as the tap connection structure, and is not in physical contact with the tap connection structure.

[0034] In an exemplary embodiment of the CFET structure, the CFET structure further comprises a connection via, which is arranged to electrically connect the power routing line to the source and / or drain structure of, respectively, the second transistor structure and / or the fourth transistor structure.

[0035] In an exemplary embodiment of the CFET structure, the CFET structure further comprises at least one further CFET element which is electrically connected to the second power routing line, wherein the at least one further CFET element is not directly connected to the second power rail.

[0036] In an exemplary embodiment of the CFET structure, the at least one further CFET element does not comprise a dedicated tap connection structure which electrically connects the at least one further CFET element to the second power rail.

[0037] A second aspect of this disclosure provides a method of fabricating a CFET structure, the method comprising: forming a first CFET element comprising a first transistor structure and a second transistor structure, wherein the second transistor structure is formed above the first transistor structure; forming a dielectric wall, wherein the first and the second transistor structure are both arranged on a first side of the dielectric wall; forming a first power rail below the first transistor structure, wherein the first power rail is electrically connected to a source and / or drain structure of the first transistor structure from the bottom; and forming a power routing line above the second transistor structure.

[0038] The steps of the method of the second aspect do not necessarily have to be performed in the order they are described.

[0039] In an exemplary embodiment of the method, the method further comprises forming a second CFET element comprising a third transistor structure and a fourth transistor structure, wherein the third and the fourth transistor structure are arranged on a second side of the dielectric wall, and wherein the fourth transistor structure is formed above the third transistor structure; wherein the power rail is formed below the third transistor structure and is electrically connected to a source and / or drain structure of the third transistor structure from the bottom; and wherein the power routing line is formed above the fourth transistor structure.

[0040] In an exemplary embodiment of the method, the power routing line is electrically connected from the top to a source and / or drain structure of neither of, or one of, or both of the second transistor structure and the fourth transistor structure.

[0041] That is, the power routing line may be connected to a transistor structure on one side of the dielectric wall, or on both sides of the dielectric wall.

[0042] In an exemplary embodiment of the method, one of or both of the second and the fourth transistor are electrically connected to the power routing line by: forming a via hole directly above and aligned with the dielectric wall; filling the via hole with a conductive material to form a connection via, which electrically connects to the respective source and / or drain structure of the second transistor structure and / or the fourth transistor structure; and forming the power routing line above and electrically connected to the connection via.

[0043] This allows aligning the power routing line vertically with the dielectric wall. In an exemplary embodiment of the method, the power rail is formed by: removal and / or processing of a backside substrate, on which the first and the second CFET element are formed; and backside processing a respective connection structure to electrically connect the power rail to both the first and the third transistor structure.

[0044] The power rail can also be connected to a backside power delivery network (BSPDN), or can be a component of a larger BSPDN. The BSPDN can also be connected to or comprise the second power rail. Fabricating such a BSPDN may involve removing and / or processing the backside substrate. For example, forming the power rail by processing of the backside substrate may involve forming a buried power rail (BPR) and / or a buried power delivery network. A BPR comprises a metal line construct buried below the transistors, for instance, partially within the Si substrate, and partially within a STI oxide.

[0045] In an exemplary embodiment of the method, the dielectric wall and the first and the second CFET element are formed by: forming a plurality of transistor layers, for example, a plurality of nanosheets and dielectric layers; forming a dummy gate structure around the plurality of transistor layers; forming a source contact region and a drain contact region electrically connected to the plurality of transistor layers, respectively; etching a trench through the plurality of transistor layers and through the source and drain contact regions, thereby creating the first and the second transistor structure on a first side of the trench and the third and the fourth transistor structure on a second side of the trench; and filling the trench with a dielectric material.

[0046] Filling the dielectric material into the trench forms the dielectric wall, which may be the dielectric wall in a forksheet architecture. The plurality of transistor layers may comprise channel layers of the transistor structures, which may be separated (if more than one channel layer per transistor structure) by dielectric layers.

[0047] The method of the second aspect may have further exemplary embodiments, which correspond to exemplary embodiment of the CFET structure of the first aspect. The method of the second aspect and its exemplary embodiments achieve the effects and advantages described above with respect to the CFET structure of the first aspect and its exemplary embodiments.

[0048] BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The above described aspects and implementations are explained in the following description of specific embodiments with respect to the enclosed drawings:

[0050] FIGs. 1A-B show schematic views of an exemplary CFET structure according to this disclosure;

[0051] FIGs. 2A-B show schematic views of an exemplary CFET structure according to this disclosure;

[0052] FIGs. 3A-B show schematic views of an exemplary CFET structure according to this disclosure;

[0053] FIGs. 4A-B show schematic top views of different exemplary CFET structures according to this disclosure;

[0054] FIGs. 5A-B show the results of simulations with different exemplary CFET structures according to this disclosure;

[0055] FIG. 6 shows a schematic diagram of an exemplary CFET structure according to this disclosure;

[0056] FIG. 7 shows a flow-diagram of a method of fabricating an exemplary

[0057] CFET structure according to this disclosure;

[0058] FIGs. 8A-L show steps of a method of fabricating an exemplary CFET structure according to this disclosure. DETAILED DESCRIPTION OF EMBODIMENTS

[0059] FIGs. 1A and 1B show schematic views of an exemplary CFET structure io according to an embodiment. Thereby, FIG. 1A shows a top view and FIG. 1B shows a cross-sectional view of the same CFET structure io, wherein the section lines A- A’ indicate the position of the cross-section.

[0060] The CFET structure io comprises at least one CFET element, and the CFET element comprises a first transistor structure 21 and a second transistor structure 22. The second transistor structure 22 is arranged above the first transistor 21 structure (i.e., is displaced along the z-axis of the shown coordinate system). The first transistor structure 21 comprises a source and / or drain structure 11b, and the second transistor structure 22 comprises a source and / or drain structure 12b. The first and the second transistor structure 21, 22 are both arranged on a first side (namely the right side in FIG. 1B) of a dielectric wall 25 of the CFET structure 10.

[0061] The CFET structure 10 further comprises a (first) power rail 13 arranged below the first transistor structure 21 (displaced along the z-axis), and a power routing line 16 arranged above the second transistor structure 22 (displaced along the z-axis), as illustrated. The power rail 13 is electrically connected to the source and / or drain structure 11b of the first transistor structure 21 from the bottom, i.e., from below. The power routing line 16 could be electrically connected to the source and / or drain structure 12b of the second transistor structure 22 from the top, i.e., from above. However, this is not mandatory, since the power routing line 16 could be associated with another CFET element of the CFET structure 10. The power rail 13 can be arranged directly below the first transistor structure 21, in particular, below the source and / or drain structure 11b of the first transistor structure 21 (i.e., without lateral displacement along the x-axis).

[0062] The CFET element can form a CFET cell, e.g. a logic cell, or can be a part of such a CFET cell. The CFET element can comprise multiple first (bottom) transistor structures 21 and multiple second (top) transistor structures 22, wherein the second transistor structures 22 are arranged above the first transistor structures 21. For example, the first (bottom) transistor structures 21 can be arranged in a first tier or level of the CFET structure 10, and the second (top) transistor structures 22 can be arranged in a second tier or level of the CFET structure 10, above the first tier. Thereby, for example as illustrated, a respective second transistor structure 21 is stacked above (along the z-axis, as indicated by the coordinate system) a respective first transistor structure 22.

[0063] The size of the CFET element and, in particular, the number of its first and second (or bottom and top) transistor structures 21, 22 can depend on its function. For instance, the CFET element of the CFET structure 10 in FIGS. 1A-B is an inverter (INV) cell, which comprises one first transistor structure 21 and one second transistor structure 22.

[0064] The first transistor structure 21 and the second transistor structure 22 can each comprise a respective channel structure 11a, 12a, wherein each channel structure 11a, 12a can comprise a number of channel layers (which extend along a y-axis, as indicated by the coordinate system). Furthermore, each of the first transistor structure 21 and the second transistor structure 22 can comprise at least two source and / or drain structures 11b, 12b and a gate structure 12c. The source and / or drain structures 11b, 12b can be formed from metal zero (Mo) layers, e.g., the top source and / or drain structures 12b from a MoAT layer and the bottom source and / or drain structures 11b from a Mo AB layer.

[0065] As exemplarily illustrated, the CFET structure 10 may optionally comprise a number of signaling lines 15, which may be arranged above the second transistor structure 22. The CFET element can be connected to individual signaling lines 15 via an input I and an output ZN, as exemplarily shown in in FIG. 1A. The signaling lines 15 and the power routing line 16 can be formed from horizontal metal layers, e.g. metal intermediate (Mint) layers. The power routing line 16 can be arranged adjacent to the signaling lines 15, e.g., can be arranged in the same plane as the signaling lines 15.

[0066] As further shown in FIGs. 1A and 1B, the power rail 13 may supply a supply voltage, e.g. a VDD voltage, to the first (bottom) transistor structure 21, and the power routing line 16 may supply a supply voltage, e.g. a VSS voltage, to the second (top) transistor structure 22. To this end, just as an example, the CFET element can comprise a connection structure 24 (e.g., a connection via, as explained later), which is arranged to electrically connect the power routing line 16 with the source and / or drain structure 12b of the second transistor structure 22. The CFET element may comprise another connection structure 26, which is arranged to electrically connect the power rail 13 with the source and / or drain structure 11b of the first transistor structure 21. Alternatively, the power rail 13 could also supply a VSS voltage, and the power routing line 16 a VDD voltage.

[0067] FIGs. 2A and 2B show a top view and a cross-sectional view of the CFET structure 10 according to an exemplary embodiment. The CFET structure 10 in the FIGs. 2A- 2B (as well as the CFET structure 10 in the FIGs. 1A-B) comprises the dielectric wall 25, which may be a forksheet wall. That is, the CFET structure 10 may have a forksheet architecture, in which transistor structures (e.g., NMOS and PMOS structures) can be arranged on both sides of the dielectric wall 25.

[0068] The CFET element shown in FIGs. 2A and 2B further comprises a second power rail 14, which is arranged below the first transistor structure 21 of the CFET element, and comprises a tap connection structure 23. The tap connection structure 23 is arranged to electrically connect the second power rail 14 with the source and / or drain structure 12b of the second transistor structure 22. Thereby, the tap connection structure 23 is arranged to bypass the first transistor structure 21 on one side, in FIG. 2B on the first side (i.e. the right side).

[0069] Notably, throughout this disclosure the relative terms “top” and “bottom” (or “above” and “below”) indicate a vertical arrangement along the z-axis (as indicated by the Cartesian coordinate system). For instance, the first transistor structure 21 can be a bottom transistor structure and the second transistor structure 22 can be a top transistor structure offset along the z-axis.

[0070] The tap connection structure 23 can comprises a vertical line structure, for example, a metallic via. While the CFET element in FIGs. 2A-B has one tap connection structure 23, bigger CFET elements could comprise multiple tap connection structures 23. The top source and / or drain structures 12b can comprise a source and / or drain extension, which is contacted by the tap connection structure 23. For example, as shown in FIG. 2B, a section of the source and / or drain structure 12b of the second transistor structure 22 can protrude beyond the first transistor structure 21 below (in direction along the x-axis). The tap connection structure 23 can contact this protruding section of the source and / or drain structure 12b from the bottom. In this way, the tap connection structure 23 can bypass the first transistor structure 21. For instance, the source and / or drain structures 11b, 12b of the first and second transistor structure 21, 22 can be arranged in a staggered configuration (e.g., staggered in the x-z plane), to allow the tap connection structure 23 to bypass the bottom source and / or drain structures 11b and, thus, the first (bottom) transistor structure 21. The gate structure 12c can be a common gate structure of the bottom and top transistor structures 21, 22.

[0071] The supply voltage provided by the second power rail 14 can be routed from the second power rail 14 via the tap connection structure 23 to the source and / or drain structure 12b. Said supply voltage may be further routed via the connection structure 24 to the power routing line 16. For example, the connection structure 24 can be a short metallic via. The tap connection structure 23 thus allows connecting the second (bottom) power rail 14 with the (top) power routing line 16, while keeping the logic function of the cell (which comprises the CFET element) fully intact. In particular, there is no more need for dedicated tap cells to establish such a front -to-back connection.

[0072] As in FIG. 1B, also in FIG. 2B the first and the second transistor structure 21, 22 of the CFET element are arranged on the same side of the dielectric wall 25. However, as already mentioned there can also be transistor structures on the other side of the dielectric wall 25 (but are not shown in FIG. 2B). For example, any CFET structure 10 of this disclosure may further comprise a second CFET element, wherein this second CFET element may be similar or identical to the (first) CFET element on the opposite side of the dielectric wall. For instance, the second CFET element may comprise a third transistor structure and a fourth transistor structure. In this exemplary scenario, the third and the fourth transistor structure are both arranged on a second side of the dielectric wall 25, i.e., on the other side than the first CFET element (this would be the left side in FIG. 2B). Further, the fourth transistor structure is arranged above the third transistor structure. In this case, the power rail 13 can also be arranged below the third transistor structure and can be electrically connected to a source and / or drain structure of the third transistor structure from the bottom. The power routing line 16 can be arranged above the fourth transistor structure, and may electrically connect a source and / or drain structure of the fourth transistor structure from the top (but does not have to).

[0073] In an example, the dielectric wall 25 can support a number of nanosheet layers, which comprise the channel layers 11a, 12a of the transistor structures 21, 22. The two gray areas around some of the nanosheet layers in FIG. 2B can, for instance, indicate an active nanosheet part of the first and second transistor structure 21, 22.

[0074] As further shown in FIG. 2B, the power rail 14 can be connected to a BSPDN of the CFET structure 10. This BSPDN can also comprise the power rail 13.

[0075] In an example, the (top) power routing line 16 can be arranged directly above the dielectric wall 25 and / or can run in parallel to the dielectric wall 25 (e.g., along the y-axis, as indicated by the coordinate system). In this way, the (top) transistor structures, which may be arranged on one or both sides of the dielectric wall 25 - e.g. of the CFET element and the second CFET element as descried above - can be supplied by the same power routing line 16.

[0076] Supplying the first (top) transistor structure 21 from the bottom and the second (bottom) transistor structure 22 from the top allows for a compact design of the CFET element. Furthermore, such a CFET element can be better co-integrated with side routing. Notably, the optional tap connection structure 23 described above, may be positioned to one side (e.g. the first side) of the CFET element, while the power routing line 16 is positioned and connected to the source and / or drain structure 12b at the other side (e.g. second side) of the CFET element. Having a dedicated power routing line 16 for either VSS or VDD on a top side (frontside power) of the CFET structure 10 - i.e., above the top transistor structure 22 - offers certain advantages, such as easier processing and wider active transistor channel width with respect to conventional architectures that use tall and wide vias for connecting a BSPDN to a top device, or use a backside power rail to provide power to the top transistor device.

[0077] FIGs. 3A and 3B show a top view and a cross-sectional view of the CFET structure 10 according to an example. Thereby, the CFET structure 10 has a nanosheet architecture without a dielectric wall 25. In the nanosheet architecture, the gate can surround the channel layers of the channel structures 11a, 12a on all sides (gate all around).

[0078] As can be seen in all the FIGs. 1A-3B, the power routing line 16 can be wider than the signaling lines 15, and / or can be arranged laterally displaced to one side of the CFET element. This facilitates the connection of CFET elements on both sides of the power routing line 16 (in x-axis direction) to the power routing line 16. Furthermore, a plurality of CFET elements, which are arranged along the power routing line 16 (along the y-axis or the channel direction) can be connected to the power routing line 16.

[0079] The tap connection structure 23 can connect a MoAT layer (top source and / or drain structure 12b) with the BSPDN, in this way connecting the frontside power routing line 16 to the second power rail 14 of the BSPDN. Such a design does not require conventional tap cells.

[0080] The FIGs. 2A-3B show CFET structures 10 with an inverter cell (INVD1). In each case, the tap connection structure 23 can be arranged in an area of this inverter cell, which is otherwise not used, i.e., not occupied by another structure. For instance, the tap connection structure 23 can be arranged adjacent to a top source and / or drain structure 12b, which is also connected to the power routing line 16, as shown by the dashed rectangle 23 in FIGs. 1A, 2A and 3A. Alternatively, the tap connection structure 23 could be arranged in other areas of a CFET element, where there is an “empty” area which is not occupied by another structure. FIGs. 4A and 4B compare a conventional CFET design to a CFET structure 10 comprising tap connection structures 23 (as e.g., shown in any one of FIGS. 2A- 3C). Both of these CFET structure designs feature an architecture with a frontside power supply for the respective top transistor structures via a power line or rail arranged above the top transistor structures. In general, such a frontside power supply allows for easier processing and a wider active area with respect to other power delivery options. In the conventional CFET structure, the frontside power delivery requires special cells, so-called tap cells. These tap cells provide an electrical connection of the backside power rail to a frontside rail.

[0081] FIG. 4A shows a schematic top view of the conventional CFET structure with tap cells. To reduce the resistivity, the tap cells are typically placed in regularly arranged columns and at a certain fixed distance (e.g., at a distance of 48 CPP = Contacted Poly Pitch). This periodic arrangement reduces the voltage drop across the VSS line in the FEOL (front-end-of-line). The tap cells can occupy between 4% and 5% of the total design area. Thus, the tap cells cause an area penalty, because the area which is occupied by the tap cells cannot be used by other (logic) cells of the CFET. For instance, a tap cell can comprise a contact structure (e.g., a MoAT layer) which is arranged between two dummy gate structures in close proximity to a top channel structure. This contact structure can be electrically connected to the power rail 14 below.

[0082] In contrast, FIG. 4B shows a schematic top view of a CFET structure 10 (as e.g., shown in FIGS. 2A-3C) which comprises a plurality of cells with tap connection structures 23 instead of tap cells. As shown in FIG. 4B, the tap connection structures 23 can be directly integrated in at least a fraction of the CFET elements (as indicated by the black boxes). The CFET elements with the tap connection structures 23 can still maintain their main function as logic cells (e.g., inverter cells) and / or standard cells (or parts of such cells). For instance, the cells with tap connection structures 23 can be of different types and can have varying sizes.

[0083] The CFET elements with the tap connection structures 23 do not have to be arranged periodically as the tap cells, and can be distributed randomly instead. The CFET structure 10 can comprise further CFET elements (indicated by white boxes in FIG. 4B) which do not comprise dedicated tap connection structures 23 and are thus not directly connected to the power rail 14 below. These further CFET elements, in particular their respective second (top) transistor structures 22, can however be connected to the power routing line 16 above and receive the supply voltage (VSS or VDD) from this line 16.

[0084] For instance, these further CFET elements do not allow for tap connection structures 23 due to their configuration and / or arrangement (e.g., cells with multiple input or output signals), but can still receive the supply voltage from the top thus benefitting from the tap connections structures 23 of other CFET elements (e.g., INVDX / BUFFDX cells withX>2) which bring the supply voltage to the power routing line 16.

[0085] FIGS. 5A-B show the results of simulations with different CFET structures according to exemplary embodiments. In particular, FIGS. 5A and 5B compare the results of block level place and route simulations of a conventional CFET design featuring tap cells with a CFET design featuring the tap connection structures 23.

[0086] The chart in FIG. 5A shows a relative cell count or cell area of taped and non-tapped cells. In the conventional design (left bar), ca. 4-5% of cells are tap cells. However, in a CFET structure 10 as e.g. shown in any one of FIGS. 1A-3C, the majority of cells can have a tap connection structure 23.

[0087] In the simulated example, ca. 83% of cells can have a tap connection structures 23 making up an area of ca. 80% of the total cell area (middle and right bar in FIG. 5A). Thus, as shown in FIG. 5B, the number of tap connections per pm2can be 14 times higher when using tap connections structures 23 as compared to a conventional CFET design with tap cells.

[0088] These simulation results demonstrate the advantages of integrated tap connection structures 23, as the high density of the front -to-backside connections results in a more stable power supply to the front-side (in addition to the area scaling benefit). Thereby, the exact number of CFET elements with and without tap connection structures 23 can vary, e.g., depending on the type and size of cells. For instance, between 65% and 95%, preferably between 75% and 85%, of the total number of CFET elements of the CFET structure 10 can comprise at least one tap connection structure 23.

[0089] FIG. 6 shows a schematic diagram of a CFET structure 10 according to an exemplary embodiment. The CFET structure 10 comprises a CFET element, which has at least an additional transistor structure in a level above the first transistor structure 21 and adjacent to the second transistor structure 22. That is, the additional transistor structure is an additional top transistor structure of the CFET element.

[0090] The CFET element in FIG. 6 further comprises a side routing structure 62 which electrically connects the first transistor structure 21 with the additional transistor structure (which is not necessarily directly on top of the first transistor structure 21).

[0091] The tap connection structure 23 (which is connected to the second transistor structure 22) can be arranged on the same side of the CFET element as the side routing structure 62, and is thereby not in physical contact with the side routing structure 62. For instance, the tap connection structure 23 maybe arranged in an empty space on the side of the CFET element, which is not occupied by any other structure (e.g., the space 61 indicated by a dashed rectangle in FIG. 6). The power routing line 16 may connect the source and / or drain structure 12b from the other side of the CFET element, that is, the opposite side of where the tap connection structure 23 and side routing structure 62 are arranged.

[0092] For instance, the side routing structure 62 can contact the source and / or drain structure 11b of a bottom transistor structure and a source and / or drain structure of a top transistor structure 22 from one side and, in this way, electrically connect the top and bottom transistor structure 21, 22. Thereby, the source and / or drain structures can be displaced along the channel direction (i.e., not arranged directly on top of each other).

[0093] Thus, a tap connection structure 23 can be used in some CFET elements which have a side routing architecture, as long as there is an unoccupied space adjacent to a top transistor structure source or drain 12b.

[0094] The CFET element in FIG. 6 further shows possible interconnections 63 of the top transistor structures to a top signal routing line 15 and / or to each other. The exact configuration and arrangement of such interconnections can depend on the cell type.

[0095] FIG. 7 shows a flow diagram of a method 70 of fabricating an exemplary CFET structure 10 according to this disclosure. For instance, the method 70 can be used to fabricate any one of the previously described CFET structures 10, with or without tap connection structure 23.

[0096] The method 70 comprises a step 71 of forming a first CFET element, which includes a first transistor structure 21 and a second transistor structure 22, wherein the second transistor structure 22 is formed above the first transistor structure 21. The method 70 further comprises a step 72 of forming a dielectric wall 25, wherein the first and the second transistor structure 21, 22 are both arranged on a first side of the dielectric wall 25. The two steps 71 and 72 do not have to be performed in the given order. Further, the method 70 comprises a step 73 of forming a first power rail 13 below the first transistor structure 21, wherein the first power rail 13 is electrically connected to a source and / or drain structure 11b of the first transistor structure 21 from the bottom. The method 70 also comprises a step 74 of forming a power routing line 16 above the second transistor structure 22. The two steps 73 and 74 do not have to be performed in the given order.

[0097] FIGs. 8A-L show specific steps of the method 70, in particular, steps of a processing flow suitable for processing the CFET structure(s) 10. The FIGs. 8A-L show section views according to a cross-section through an x-z plane and a y-z plane (as indicated by the Cartesian coordinate system). As shown in FIG. 8A, initially the processing flow comprises forming a plurality of transistors layers, for example, nanosheet layers. The plurality of transistors layers may include one or more first channel structures or layers na, which will e.g. be used for the first transistors structure 21, and one or more second channel structures or layers 12a, which will e.g. be used for the second transistor structure 22. However, in a forksheet architecture they may also be used for the third and fourth transistor structures, as will be explained. The transistor layers can be formed by depositing a grating (e.g., a layer stack) on a substrate 81. For instance, the grating can comprise alternating layers of a first material (e.g., SiGei5%) and a second material (e.g., Si), wherein the second material layers may form the channel layers or structures 11a, 12a. Furthermore, one or multiple middle dielectric isolation (MDI) layers can be formed between the top and bottom channel layers or structures 12a, 11a. The substrate 81 can be a silicon substrate or a silicon-on- insulator (SOI) substrate. A top layer 82, e.g. a dielectric layer, can be arranged above the grating.

[0098] As further shown in FIG. 8B, the processing flow may include nanosheet patterning (i.e., patterning of the previously produced grating), which may involve active patterning. This patterning step may result in a shallow trench isolation (STI).

[0099] As shown in FIG. 8C, a dielectric material 83 can be deposited in the STI.

[0100] FIG. 8D shows the structure after several further steps of the processing flow. These further steps may, in particular, involve a dummy gate pattering step. Thereby, a dummy gate material 84 is deposited on the grating (i.e., on the nanosheet layer stack). Extreme ultraviolet (EUV) lithography and one or more suitable EUV masks may be used in this step. Further, the steps may involve conventional CFET / nanosheet processing steps. For instance, a middle dielectric isolation (MDI) and inner spacers 85 can be formed, and a spacer / active recess (e.g., gate spacer, inner spacer) may be created. Further, bottom source and / or drain structures 11b (i.e., source and / or drain structures for the first transistor structure 21) can be formed. The source and / or drain structures 11b can be formed by an epitaxial growth process. During the formation of the source and / or drain structures nb, the top transistor channels 12a can be covered by a cover spacer.

[0101] FIG. 8E shows the structure after several further steps of the processing flow. These further steps may involve a metal zero (Mo) material 86 patterning. The Mo material 86 can be multi-patterned, as scaled dimensions maybebeyond the single print limit. A self-alignment of the Mo material 86 to the dummy gate may enable a lower mask-count. For example, three masks may be used for this step. For instance, the Mo material 86 can be identical to the material used for the power rails 13 and / or 14. After the Mo metallization, a recess can be made. Further, an isolation layer can be formed and top source and / or drain structures 12b can be deposited, e.g. via an epitaxial growth process.

[0102] FIG. 8F shows the structure after a step of forming the dielectric wall 25. The dielectric wall 25 can be formed by etching a trench through the plurality of transistor layers 11a, 12a and the source and / or drain contact regions, respectively, thereby creating the first and the second transistor structure 21, 22 on a first side of the trench, and creating the third and the fourth transistor structure on a second side of the trench. The etching step may be referred to as “Wall Cut”. The shown process implementation maybe referred to as “Wall Middle”, as the dielectric wall 25 is created after the source and drain regions are formed in FIG. 8D and FIG. 8E, but before a replacement metal gate (RMG) step in FIG. 8G. In other possible implementations of the process, the dielectric wall 25 could be created before the source and drain regions (“Wall First”), i.e., before FIG. 8D, or after the RMG (“Wall Last”), i.e. after FIG. 8G.

[0103] The Wall Cut maybe a deep unselective etch, cutting through dummy gate material (e.g., amorphous Si), the source and / or drain material (e.g., for the top it maybe phosphor-doped silicon, Si:P, and for the bottom it may be boron-doped silicon, SiGe:B), inner spacer material (e.g., silicon nitride, SiN) and isolation layers (e.g., silicon oxide, Si02). The bottom contact metal should be avoided by layout. No metal should be open as the trench is etched. The Wall Cut may divide the original printed nanosheet grating into two forks. The width of the forks maybe defined by the difference between two edges, i.e. it is overlay defined. The trench can then be filled with a dielectric material to create the dielectric wall 25.

[0104] FIG. 8G shows the structure after several following process steps. In particular, these following process steps involve a RMG process. Thereby, the previously generated dummy gate material 84 can be replaced by a metal gate structure 87. A single diffusion break with active cutting can be part of this process. Further, a VMM patterning (1 mask) and MoT patterning (3 masks) maybe carried out.

[0105] As shown in FIG. 8H, Vo patterning and metallization (1 mask) maybe carried out next. Also, top side vias 88 can be formed. The top side vias 88 can be connected to a bottom metallization, a top metallization, and / or gate structures. The top side vias 88 can be formed from either single damascene metal filled or just from holes.

[0106] As shown in FIG. 81, VGT patterning (1 mask) and VoT patterning (1 mask) may be performed. This may include via patterning for forming vias that connect power to the transistor structures, wherein one or more vias may be formed overlapping and self-aligned to the dielectric wall 25. In particular, for connecting one of or both of the second and the fourth transistor (on the two sides of the dielectric wall 25) electrically to the power routing line 16, at least one via hole 89 maybe formed directly above and aligned with the dielectric wall 25.

[0107] As further shown in FIG. 8J, the process may then involve filling the at least one via hole 89 with a conductive material, in order to form at least one connection via 90. The connection via 90 electrically connects to the respective source and / or drain structure 12b of the second transistor structure 22 and / or of the fourth transistor structure. Further, the power routing line 16 above and electrically connected to the connection via 90 maybe formed. For instance, this may involve Mi patterning. For instance, a method of Ru integration maybe used.

[0108] As illustrated, both sides of the fork may be connected to power, so that the connection via 90 is on both sides of the dielectric wall 25. There may be cases where only one side of the dielectric wall 25 will receive a power connection. FIG. 8K shows that further the backside silicon substrate 81 can be removed. A stop layer can be used to mitigate unwanted variations. While most of the silicon substrate 81 can be removed, the bottom source and / or drain contact structures nb (e.g., SiGe) can stay intact. The backside etching to remove the silicon may be selective to a gate oxide. A backside isolation can also be carried out. Therefore, a backside oxide filling can be performed, followed by a CMP and an oxide etch back step. Then, the backside isolation can be etched in the source and / or drain structures where a power connection is needed.

[0109] Also, a backside power metallization 91 can be carried out. The backside metallization 91 can form the backside connection structure 26 shown in FIG. 1, which is arranged below the first transistor structure 21, and which electrically connects the first transistor structure 21 to the first power rail 13.

[0110] Fig. 8L further shows the connection of the backside metallization 91 with BEOL vias (vias not visible in the cross-sectional view).

[0111] With the above processing steps, a CFET structure 10 which comprises the stacked first and second transistor structures 21, 22 can be fabricated. Channels layers 11a, 12a of the transistor structures 21, 22 maybe in contact with a side surface of the dielectric wall 25. The power rail 13 can be arranged below the first transistor structure 21 and electrically connected to a source and / or drain structure 11b of the first transistor structure 21 from the bottom. The power routing line 16 can be arranged above the second transistor structure 22, and can be electrically connected from the top to a source and / or drain structure 12a of neither of, or one of, or both of the second transistor structure and the fourth transistor structure, for instance by the connection via 90.

[0112] In the claims as well as in the description of this disclosure, the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality. A single element may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

Claims1. A complementary field effect transistor, CFET, structure, (io) comprising: a dielectric wall (25); a first CFET element comprising a first transistor structure (21) and a second transistor structure (22), wherein the first and the second transistor structure (21, 22) are both arranged on a first side of the dielectric wall (25), and wherein the second transistor structure (22) is arranged above the first transistor structure (21); a first power rail (13) arranged below the first transistor structure (21) and electrically connected to a source and / or drain structure (11b) of the first transistor structure (21) from the bottom; and a power routing line (16) arranged above the second transistor structure (22).

2. The CFET structure (10) of claim 1, wherein the power routing line (16) is electrically connected to a source and / or drain structure (12b) of the second transistor structure (22) from the top.

3. The CFET structure (10) of claim 1 or 2, further comprising: a second CFET element comprising a third transistor structure and a fourth transistor structure, wherein the third and the fourth transistor structure are both arranged on a second side of the dielectric wall (25), and wherein the fourth transistor structure is arranged above the third transistor structure; wherein the first power rail (13) is arranged below the third transistor structure and is electrically connected to a source and / or drain structure (11b) of the third transistor structure from the bottom; and wherein the power routing line (16) is arranged above the fourth transistor structure.

4. The CFET structure (10) of claim 3, wherein the power routing line (16) is electrically connected to a source and / or drain structure (12b) of the fourth transistor structure from the top.

5. The CFET structure (10) of any one of the claims 1 to 4, wherein the power routing line (16) is arranged directly above the dielectric wall (25) and / or runs in parallel to the dielectric wall (25).

6. The CFET structure (10) of any one of the claims 1 to 5, further comprising a second power rail (14) arranged below the first transistor structure (21); and a tap connection structure (23), which is arranged to electrically connect the second power rail (14) with the source and / or drain structure (12b) of the second transistor structure (22); wherein the tap connection structure (23) is arranged to bypass the first transistor structure (21) on one side.

7. The CFET structure (10) of claim 6, wherein a section of the source and / or drain structure (12b) of the second transistor structure (22) protrudes beyond the first transistor structure (21); and wherein the tap connection structure (23) contacts the protruding section of the source and / or drain structure (12b) from the bottom.

8. The CFET structure (10) of claim 6 or 7, further comprising a side routing structure (62), which is arranged to electrically connect the first transistor structure (21) with a further transistor structure of the first CFET element, the further transistor structure being arranged above the first transistor structure (21); wherein the side routing structure (62) is arranged on the same side of the first CFET element as the tap connection structure (23), and is not in physical contact with the tap connection structure (23).

9. The CFET structure (10) of any one of the preceding claims, further comprising a connection via (90), which is arranged to electrically connect the power routing line (16) to the source and / or drain structure (12b) of, respectively, the second transistor structure (22) and / or the fourth transistor structure.

10. A method (70) of fabricating a complementary field effect transistor, CFET, structure (10), the method (70) comprising: forming (71) a first CFET element comprising a first transistor structure (21) and a second transistor structure (22), wherein the second transistor structure (22) is formed above the first transistor structure (21); forming (72) a dielectric wall (25), wherein the first and the second transistor structure (21, 22) are both arranged on a first side of the dielectric wall (25); forming (73) a first power rail (13) below the first transistor structure (21), wherein the first power rail (13) is electrically connected to a source and / or drain structure (11b) of the first transistor structure (21) from the bottom; and forming (74) a power routing line (16) above the second transistor structure (22).

11. The method (70) of claim 10, further comprising: forming a second CFET element comprising a third transistor structure and a fourth transistor structure, wherein the third and the fourth transistor structure are arranged on a second side of the dielectric wall (25), and wherein the fourth transistor structure is formed above the third transistor structure; wherein the first power rail (13) is formed below the third transistor structure and is electrically connected to a source and / or drain structure (11b) of the third transistor structure from the bottom; and wherein the power routing line (16) is formed above the fourth transistor structure.

12. The method (70) of claim 10 or 11, wherein the power routing line (16) is electrically connected from the top to a source and / or drain structure (12b) of neither of, or one of, or both of the second transistor structure (22) and the fourth transistor structure.

13. The method (70) of claim 12, wherein one of or both of the second and the fourth transistor structure are electrically connected to the power routing line (16) by:forming a via hole (89) directly above and aligned with the dielectric wall(25); filling the via hole (89) with a conductive material to form a connection via (90), which electrically connects to the respective source and / or drain structure (12b) of the second transistor structure (22) and / or the fourth transistor structure; and forming the power routing line (16) above and electrically connected to the connection via (90).

14. The method (70) of claim 13, wherein the first power rail (13) is formed by: removal and / or processing of a backside substrate (81), on which the first and the second CFET element are formed; and backside processing a respective connection structure (26) to electrically connect the power rail (13) to both the first and the third transistor structure (21).

15. The method (70) of any one of the claims 10 to 14, wherein the dielectric wall (25) and the first and the second CFET element are formed by: forming a plurality of transistor layers (11a, 12a), for example, a plurality of nanosheets and dielectric layers; forming a dummy gate structure (84) around the plurality of transistor layers (11a, 12a); forming a source contact region and a drain contact region (11b, 12b) electrically connected to the plurality of transistor layers (11a, 12a), respectively; etching a trench through the plurality of transistor layers (11a, 12a) and through the source and drain contact regions (11b, 12b), thereby creating the first and the second transistor structure (21, 22) on a first side of the trench and the third and the fourth transistor structure on a second side of the trench; and filling the trench with a dielectric material.

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