Semiconductor device

Abstract

The purpose of the present invention is to provide, in a semiconductor device, a technology that makes it possible to inhibit temperature gradient to be caused in a surface of a semiconductor substrate. The semiconductor device is provided with: a semiconductor substrate 1 in which a cell region 2 that comprises a plurality of cells including cells corresponding to an IGBT part 4 and an FWD part 5 and an end region 3 that surrounds the outer periphery side of the cell region 2 are defined; and an emitter wire which is connected to an emitter electrode 24 formed in Z direction surfaces of the IGBT part 4 and the FWD part 5. The IGBT part 4 and the FWD part 5 are disposed in a hounds-tooth check form in the surface of the semiconductor substrate 1. The IGBT part 4 includes a gate electrode 26 having a trench structure. Gate wiring 6 is disposed in the boundary between the cell region 2 and the end region 3 and in a region along the X-axis direction in the boundary between the IGBT part 4 and the FWD part 5. The gate electrode 26 is connected to the gate wiring 6. A connection part 10 between the emitter electrode 24 and the emitter wire is formed in either the IGBT part 4 or the FWD part 5.

Description

Semiconductor Devices

[0001] The present disclosure relates to a semiconductor device.

[0002] The power cycle life is an important indicator of the reliability of a power module as a semiconductor device. The failure mechanism of the power cycle life is that when temperature changes occur at the connection between the semiconductor substrate and the wire due to the operation of the power module, stress is generated due to the difference in the linear expansion coefficient between the semiconductor substrate and the wire. As a result, cracks occur at the connection between the semiconductor substrate and the wire, causing the wire to peel off.

[0003] To improve the power cycle life, it is necessary to suppress the temperature rise at the connection between the semiconductor substrate and the wire. However, because a temperature gradient exists on the top surface of the semiconductor substrate, the temperature at certain connection points between the semiconductor substrate and the wire increases, which causes a problem of deteriorating the power cycle life.

[0004] For example, Patent Document 1 describes a semiconductor device having a structure in which an IGBT section and an FWD section are arranged in a stripe pattern within the surface of a semiconductor substrate.

[0005] International Publication No. 2020 / 059285

[0006] In the structure described in Patent Document 1, heat diffusion is actively carried out in a direction perpendicular to the direction in which the IGBT section and FWD section, which are arranged in a stripe pattern, extend. However, because the same region is continuous in the direction in which the IGBT section and the FWD section extend, heat diffusion is smaller in the direction in which the IGBT section and the FWD section extend than in the perpendicular direction, and a temperature gradient occurs within the surface of the semiconductor substrate.

[0007] Therefore, an object of the present disclosure is to provide a technique capable of suppressing a temperature gradient occurring within the surface of a semiconductor substrate in a semiconductor device.

[0008] A semiconductor device according to the present disclosure includes a semiconductor substrate defining a cell region including a plurality of cells including cells corresponding to an IGBT section and an FWD section, and a termination region surrounding the outer periphery of the cell region; and an emitter wire connected to an emitter electrode formed on an upper surface of the IGBT section and the FWD section, wherein the IGBT section and the FWD section are arranged in a houndstooth pattern within the plane of the semiconductor substrate, the IGBT section includes a gate electrode having a trench structure, and a gate wiring is arranged in a region along a first direction at a boundary between the cell region and the termination region and at a boundary between the IGBT section and the FWD section, the gate electrode is connected to the gate wiring, and a connection portion between the emitter electrode and the emitter wire is formed in either the IGBT section or the FWD section.

[0009] According to the present disclosure, the IGBT section and the FWD section are arranged in a staggered pattern within the plane of the semiconductor substrate, and therefore, compared to when the IGBT section and the FWD section are arranged in a striped pattern, the cross-sectional area between the IGBT section and the FWD section is increased, thereby increasing thermal diffusion and enabling more efficient heat dissipation, thereby suppressing the temperature gradient occurring within the plane of the semiconductor substrate.

[0010] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0011] 1 is a top view of a semiconductor device according to a first embodiment. FIG. 2 is a partially enlarged top view of a corner of the semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view in the Y-axis direction of a central portion of an IGBT portion and an FWD portion included in the semiconductor device according to the first embodiment. FIG. 4 is a partially enlarged top view of a corner of a semiconductor device according to a second embodiment. FIG. 5 is a partially enlarged top view of a corner of a semiconductor device according to a third embodiment. FIG. 6 is a top view of a semiconductor device according to a fourth embodiment. FIG. 7 is a top view of a semiconductor device according to a fifth embodiment. FIG. 8 is a partially enlarged top view of a corner of a semiconductor device according to the fifth embodiment. FIG. 9 is a cross-sectional view in the Y-axis direction of a central portion of an IGBT portion and an FWD portion included in the semiconductor device according to the fifth embodiment. FIG. 10 is a cross-sectional view in the Y-axis direction of a region other than the central portions of the IGBT portion and the FWD portion included in the semiconductor device according to the fifth embodiment.

[0012] First Preferred Embodiment A first preferred embodiment will be described below with reference to the drawings. Fig. 1 is a top view of a semiconductor device according to the first preferred embodiment. Fig. 2 is an enlarged top view of a corner of the semiconductor device according to the first preferred embodiment.

[0013] In FIG. 1, the X direction, Y direction, and Z direction are perpendicular to one another. The X direction, Y direction, and Z direction shown in the following figures are also perpendicular to one another. Hereinafter, the direction including the X direction and the −X direction, which is the opposite direction of the X direction, will also be referred to as the “X-axis direction.” Hereinafter, the direction including the Y direction and the −Y direction, which is the opposite direction of the Y direction, will also be referred to as the “Y-axis direction.” Hereinafter, the direction including the Z direction and the −Z direction, which is the opposite direction of the Z direction, will also be referred to as the “Z-axis direction.”

[0014] As shown in FIG. 1, the semiconductor device is a reverse conducting IGBT (RC-IGBT: Insulated Gate Bipolar Transistor) and includes a semiconductor substrate 1.

[0015] A cell region 2 and a termination region 3 are defined in the semiconductor substrate 1. The cell region 2 is a region consisting of a plurality of cells 7, including cells 7 corresponding to the IGBT section 4 and the FWD (Free Wheeling Diode) section 5, respectively, and is formed in a rectangular shape when viewed from the Z direction. In the first embodiment, the plurality of cells 7 are arranged in groups of five within the plane of the semiconductor substrate 1 along the X-axis direction (corresponding to a first direction) and the Y-axis direction (corresponding to a second direction) orthogonal to the X-axis direction. The termination region 3 is a region adjacent to the outer periphery of the cell region 2, i.e., a region surrounding the outer periphery of the cell region 2, and is formed in a frame shape when viewed from the Z direction.

[0016] The IGBT section 4 and the FWD section 5 are formed in a rectangular shape when viewed from the Z direction and are arranged in a staggered pattern within the surface of the semiconductor substrate 1. That is, the IGBT section 4 and the FWD section 5 are adjacent to different types of cells 7 in the X-axis direction and the Y-axis direction. Therefore, compared to a conventional structure in which the IGBT section and the FWD section are arranged in a striped pattern and the number of cells in the X-axis direction (in other words, the number of divisions in the X-axis direction) is the same, the cross-sectional area between the IGBT section 4 and the FWD section 5 is increased without increasing the effective area of ​​the cell region 2. This increases thermal diffusion in the semiconductor substrate 1, enabling efficient heat dissipation. As a result, the temperature gradient occurring within the surface of the semiconductor substrate 1 can be suppressed. Here, the cross-sectional area between the IGBT section 4 and the FWD section 5 is obtained by multiplying the number of divisions by the cell width by the cell thickness.

[0017] Gate wiring 6 is arranged in the region along the X-axis direction at the boundary between the cell region 2 and the termination region 3 and at the boundary between the IGBT section 4 and the FWD section 5. The gate wiring 6 is connected to a gate electrode 26 (see FIG. 4 ) of the IGBT section 4. An emitter electrode 24 to which an emitter wire (not shown) is connected is formed on the upper surfaces (surfaces in the Z direction) of the IGBT section 4 and the FWD section 5. One end of the emitter wire is connected to the emitter electrode 24, and the other end of the emitter wire is connected to an external connection terminal (not shown) provided on the semiconductor substrate 1. The emitter wire is connected by a wire bonding process. In the first embodiment, the wire bond site at one end of the emitter wire, i.e., the connection portion 10 between the emitter electrode 24 and the emitter wire, is formed in either the IGBT section 4 or the FWD section 5. 2, the connection portion 10 is formed in the IGBT portion 4, but it may be formed in the FWD portion 5 instead of the IGBT portion 4. By forming the connection portion 10 in either the IGBT portion 4 or the FWD portion 5, the number of wire bond points can be reduced compared to when the connection portion 10 is formed in both the IGBT portion 4 and the FWD portion 5.

[0018] On the upper surface (surface in the Z direction) of the cell region 2 , the gate wiring 6 and the emitter electrode 24 are insulated by a gate oxide film 27 .

[0019] Next, the cross-sectional structures of the IGBT section 4 and the FWD section 5 will be described. Fig. 3 is a cross-sectional view in the Y-axis direction at the center of the IGBT section 4 and the FWD section 5 provided in the semiconductor device according to the first embodiment. Fig. 4 is a cross-sectional view in the Y-axis direction at the boundary between the IGBT section 4 and the FWD section 5 provided in the semiconductor device according to the first embodiment, in other words, a cross-sectional view of the IGBT section 4 and the FWD section 5 cut along the gate wiring 6 extending in the X-axis direction.

[0020] First, the cross-sectional structures of the IGBT section 4 and the FWD section 5 in the Y-axis direction at the center thereof will be described. As shown in FIG. 3 , a p-type doped channel layer 21 is provided above the n-type drift layer 20 (in the Z-direction). An emitter electrode 24 is provided above the p-type doped channel layer 21 (in the Z-direction), and only the emitter electrode 24 is exposed on the upper surface (surface in the Z-direction) of the semiconductor substrate 1. A gate electrode 26 having a trench structure is provided in the IGBT section 4. The gate electrode 26 extends from the p-type doped channel layer 21 to the center of the n-type drift layer 20 in the Z-axis direction. A gate oxide film 27 is provided on the outer periphery of the gate electrode 26, and the gate electrode 26 is insulated by the gate oxide film 27 from the emitter electrode 24 provided above the p-type doped channel layer 21 (in the Z-direction). An emitter section 28 is provided on the outer periphery of the gate oxide film 27. The emitter section 28 is connected to the emitter electrode 24.

[0021] In the IGBT section 4, the n-type drift layer 20 is provided on the lower side (−Z direction) of the n-type drift layer 20. ＋ The n-type collector layer 22 is provided in the FWD section 5. ＋ A cathode layer 23 is provided. ＋ collector layer 22 and n ＋ A collector electrode 25 is provided below (in the −Z direction) the cathode layer 23 .

[0022] Next, only the differences from FIG. 3 will be described regarding the cross-sectional structure in the Y-axis direction at the boundary between the IGBT section 4 and the FWD section 5. As shown in FIG. 4, the structure near the top surface of the semiconductor substrate 1 is different from that of FIG. 3. Specifically, a gate wiring 6 is provided above (in the Z direction) the p-type channel doped layer 21 instead of the emitter section 28. In other words, the emitter electrode 24 is not exposed on the top surface of the semiconductor substrate 1, and only the gate wiring 6 is exposed. The gate wiring 6 is connected to the gate electrode 26 of the IGBT section 4. Because the gate electrodes 26 of each IGBT section 4 across the entire semiconductor substrate 1 are connected to the gate wiring 6, they can be driven with the same signal.

[0023] As described above, the semiconductor device according to the first embodiment includes a semiconductor substrate 1 in which are defined a cell region 2 made up of a plurality of cells 7 including cells 7 corresponding to the IGBT section 4 and the FWD section 5, a termination region 3 surrounding the outer periphery of the cell region 2, and an emitter wire connected to an emitter electrode 24 formed on the upper surface (surface in the Z direction) of the IGBT section 4 and the FWD section 5. The IGBT section 4 and the FWD section 5 are arranged in a houndstooth pattern within the surface of the semiconductor substrate 1, the IGBT section 4 includes a gate electrode 26 having a trench structure, a gate wiring 6 is arranged in a region along the X-axis direction at the boundary between the cell region 2 and the termination region 3 and at the boundary between the IGBT section 4 and the FWD section 5, the gate electrode 26 is connected to the gate wiring 6, and a connection portion 10 between the emitter electrode 24 and the emitter wire is formed in either the IGBT section 4 or the FWD section 5.

[0024] Therefore, since the IGBT section 4 and the FWD section 5 are arranged in a staggered pattern within the surface of the semiconductor substrate 1, the cross-sectional area between the IGBT section 4 and the FWD section 5 is increased, which increases thermal diffusion and enables more efficient heat dissipation compared to when the IGBT section 4 and the FWD section 5 are arranged in a striped pattern. As a result, the temperature gradient occurring within the surface of the semiconductor substrate 1 can be suppressed.

[0025] Furthermore, the number of wire bonding locations can be reduced compared to when the connection portion 10 is formed in both the IGBT portion 4 and the FWD portion 5. As a result, the cost required for the wire bonding process can be reduced.

[0026] Second Preferred Embodiment Next, a semiconductor device according to a second preferred embodiment will be described. Fig. 5 is a partially enlarged top view of a corner of the semiconductor device according to the second preferred embodiment. Note that in the second preferred embodiment, the same components as those described in the first preferred embodiment are denoted by the same reference numerals and will not be described again.

[0027] 5 , in the second embodiment, the connection portion 10 is formed across the boundary between the IGBT portion 4 and the FWD portion 5 in the X-axis direction and its surrounding area. More specifically, the connection portion 10 is formed across one boundary between the top surface (Z-direction surface) of the IGBT portion 4 and the top surface (Z-direction surface) of the FWD portion 5 in the X-axis direction and its surrounding area. Here, the surrounding area does not refer to the entire top surfaces (Z-direction surfaces) of the IGBT portion 4 and the FWD portion 5, but rather to a partial area of ​​the top surfaces (Z-direction surfaces) of the IGBT portion 4 and the FWD portion 5.

[0028] As described above, in the second embodiment, similarly to the first embodiment, the temperature gradient occurring within the surface of the semiconductor substrate 1 can be suppressed.

[0029] Furthermore, since the connection portion 10 is formed across the boundary between the IGBT portion 4 and the FWD portion 5 in the X-axis direction and the surrounding area thereof, the number of wire bond locations can be reduced compared to when the connection portion 10 is formed in both the IGBT portion 4 and the FWD portion 5. As a result, the cost required for the wire bond process can be reduced. Furthermore, compared to the first embodiment, the area of ​​each connection portion 10 is increased, which leads to an improvement in the power cycle life.

[0030] Third Preferred Embodiment Next, a semiconductor device according to a third preferred embodiment will be described. Fig. 6 is a partially enlarged top view of a corner of the semiconductor device according to the third preferred embodiment. Note that in the third preferred embodiment, the same components as those described in the first and second preferred embodiments are denoted by the same reference numerals and will not be described again.

[0031] In the second embodiment, the connection portion 10 is formed across one boundary between the IGBT portion 4 and the FWD portion 5 in the X-axis direction and its surrounding area. In contrast, as shown in FIG. 6 , in the third embodiment, the connection portion 10 is formed continuously across multiple boundaries between the IGBT portion 4 and the FWD portion 5 in the X-axis direction and their surrounding areas. More specifically, the connection portion 10 is formed continuously across two boundaries between the top surface (Z-direction surface) of the IGBT portion 4 and the top surface (Z-direction surface) of the FWD portion 5 in the X-axis direction and their surrounding areas. Note that the connection portion 10 may be formed continuously across three or more boundaries and their surrounding areas. The surrounding area does not refer to the entire top surfaces (Z-direction surfaces) of the IGBT portion 4 and the FWD portion 5, but rather to a partial area of ​​the top surfaces (Z-direction surfaces) of the IGBT portion 4 and the FWD portion 5.

[0032] As described above, in the third embodiment, similarly to the first embodiment, the temperature gradient occurring within the surface of the semiconductor substrate 1 can be suppressed.

[0033] Furthermore, since the connection portion 10 is formed continuously over multiple boundaries between the IGBT portion 4 and the FWD portion 5 in the X-axis direction and their surrounding areas, the number of wire bond locations can be further reduced compared to the second embodiment. As a result, the cost of the wire bond process can be further reduced. Furthermore, since the area of ​​each connection portion 10 is further increased compared to the second embodiment, this leads to an improvement in the power cycle life.

[0034] <Fourth Embodiment> Next, a semiconductor device according to a fourth embodiment will be described. Fig. 7 is a top view of the semiconductor device according to the fourth embodiment. Note that in the fourth embodiment, the same components as those described in the first to third embodiments are denoted by the same reference numerals and description thereof will be omitted.

[0035] In the first embodiment, five cells 7 are arranged along each of the X-axis direction and the Y-axis direction in the plane of the semiconductor substrate 1. In contrast to this, as shown in Fig. 7 , in the fourth embodiment, ten or more cells 7 are arranged along each of the X-axis direction and the Y-axis direction in the plane of the semiconductor substrate 1. However, the area ratio between the IGBT section 4 and the FWD section 5 in the fourth embodiment is the same as that in the first embodiment.

[0036] As described above, in the fourth embodiment, the cells 7 are divided into smaller sections than in the first embodiment, which allows for uniform heat diffusion and more efficient heat dissipation. As a result, the temperature gradient occurring within the surface of the semiconductor substrate 1 can be further suppressed.

[0037] The structure of the fourth embodiment can be adopted in the second and third embodiments. Similarly, it can also be adopted in the fifth embodiment described below.

[0038] Fifth Embodiment Next, a semiconductor device according to a fifth embodiment will be described. Fig. 8 is a top view of the semiconductor device according to the fifth embodiment. Fig. 9 is a partially enlarged top view of a corner of the semiconductor device according to the fifth embodiment. Note that in the fifth embodiment, the same components as those described in the first to fourth embodiments are designated by the same reference numerals, and description thereof will be omitted.

[0039] As shown in FIGS. 8 and 9 , the fifth embodiment differs from the first to fourth embodiments in the arrangement of the gate wiring 6. Specifically, in the first to fourth embodiments, the gate wiring 6 is arranged in the region along the X-axis direction on the boundary between the cell region 2 and the termination region 3 and on the boundary between the IGBT section 4 and the FWD section 5. In contrast, in the fifth embodiment, the gate wiring 6 is arranged in the center of each IGBT section 4. More specifically, the gate wiring 6 is arranged in the center of the Y-axis direction on the top surface (surface in the Z-direction) of each IGBT section 4, and extends in the X-axis direction. A gate oxide film 27 is provided around the gate wiring 6 on the top surface (surface in the Z-direction) of the IGBT section 4. The gate wiring 6 is insulated from the emitter electrode 24 by the gate oxide film 27.

[0040] 9 , a gate wiring 6 is connected to another gate wiring 6 located in the vicinity thereof via a gate wire 12. The connection of the gate wire 12 is performed by a wire bonding process. A connection portion 11 between the gate wiring 6 and the gate wire 12 is formed on the gate wiring 6 and its peripheral region. A connection portion 10 between the emitter electrode 24 and the emitter wire is formed in the FWD portion 5 adjacent to the termination region 3. More specifically, the connection portion 10 is formed in a region adjacent to the termination region 3 in the FWD portion 5 adjacent to the termination region 3. The reason for forming the connection portion 10 in this location is that the temperature gradient is smaller in the region adjacent to the termination region 3, which is the periphery of the semiconductor substrate 1, compared to the central portion of the semiconductor substrate 1.

[0041] Next, the cross-sectional structures of the IGBT section 4 and the FWD section 5 will be described. Fig. 10 is a cross-sectional view in the Y-axis direction at the center of the IGBT section 4 and the FWD section 5 provided in the semiconductor device according to the fifth embodiment. In other words, it is a cross-sectional view of the IGBT section 4 and the FWD section 5 cut along the gate wiring 6 extending in the X-axis direction. Fig. 11 is a cross-sectional view in the Y-axis direction at a region other than the center of the IGBT section 4 and the FWD section 5 provided in the semiconductor device according to the fifth embodiment.

[0042] First, the cross-sectional structures of the IGBT section 4 and the FWD section 5 in the Y-axis direction at their central portions will be described. In FIG. 3 , an emitter electrode 24 is provided above (in the Z direction) the p-type channel doped layer 21. In contrast, as shown in FIG. 10 , in the fifth embodiment, the emitter electrode 24 is provided only in the FWD section 5, not in the IGBT section 4. In the IGBT section 4, a gate wiring 6 is provided instead of the emitter electrode 24. In other words, only the gate wiring 6 is exposed on the upper surface (in the Z direction) of the IGBT section 4 in the semiconductor substrate 1. Also, only the emitter electrode 24 is exposed on the upper surface (in the Z direction) of the FWD section 5 in the semiconductor substrate 1. The gate wiring 6 is connected to the gate electrode 26 of the IGBT section 4 and is also connected to other gate wirings 6 located near the gate wiring 6 via gate wires 12. With this structure, the gate electrodes 26 of the IGBT sections 4 across the entire semiconductor substrate 1 are connected to the gate wiring 6, and therefore can be driven with the same signal.

[0043] Next, the cross-sectional structure in the Y-axis direction at the boundary between the IGBT section 4 and the FWD section 5 will be described. In FIG. 4 , the gate wiring 6 is provided above the p-type channel doped layer 21 (in the Z direction). In contrast, as shown in FIG. 11 , in the fifth embodiment, an emitter electrode 24 is provided. In other words, only the emitter electrode 24 is exposed on the upper surface (surface in the Z direction) of the semiconductor substrate 1. The gate electrode 26 is not exposed on the upper surface (surface in the Z direction) of the semiconductor substrate 1, but is buried inside the semiconductor substrate 1. The emitter section 28 is connected to the emitter electrode 24. The emitter section 28 is insulated from the gate wiring 6 and the gate electrode 26 by a gate oxide film 27.

[0044] As described above, the semiconductor device according to the fifth embodiment includes a semiconductor substrate 1 in which are defined a cell region 2 consisting of a plurality of cells 7 including cells 7 corresponding to the IGBT section 4 and the FWD section 5, a termination region 3 surrounding the outer periphery of the cell region 2, and an emitter wire connected to an emitter electrode 24 formed on the Z-direction surfaces of the IGBT section 4 and the FWD section 5. The IGBT section 4 and the FWD section 5 are arranged in a houndstooth pattern within the surface of the semiconductor substrate 1, the IGBT section 4 includes a gate electrode 26 having a trench structure, a gate wiring 6 connected to the gate electrode 26 is arranged in the center of the IGBT section 4, the emitter electrode 24 is formed in a region other than the center of the IGBT section 4 and in the FWD section 5, the gate electrode 26 of the IGBT section 4 is connected by a gate wire 12, and a connection portion 10 between the emitter electrode 24 and the emitter wire is formed in the FWD section 5 adjacent to the termination region 3.

[0045] Therefore, similarly to the first embodiment, the temperature gradient occurring in the plane of the semiconductor substrate 1 can be suppressed.

[0046] Furthermore, since connection portion 10 is formed in a region adjacent to termination region 3, i.e., in FWD portion 5 adjacent to termination region 3, where the temperature gradient is smaller than in the central portion of semiconductor substrate 1, the emitter wire can be connected in a location where the temperature gradient is more stable. This leads to an improvement in power cycle life. In particular, by forming connection portion 10 in a region adjacent to termination region 3 in FWD portion 5 adjacent to termination region 3, the above-mentioned effects are further improved.

[0047] Although this disclosure has been described in detail, the above description is illustrative in all respects and is not restrictive. It is understood that countless variations not illustrated can be envisioned.

[0048] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate.

[0049] REFERENCE SIGNS LIST 1 semiconductor substrate, 2 cell region, 3 termination region, 4 IGBT section, 5 FWD section, 6 gate wiring, 7 cell, 10 connection section, 12 gate wire, 24 emitter electrode, 26 gate electrode

Claims

1. A semiconductor device comprising: a cell region composed of a plurality of cells each including a cell corresponding to an IGBT part and an FWD part; a semiconductor substrate in which a terminal region surrounding the outer peripheral side of the cell region is defined; an emitter wire connected to an emitter electrode formed on the upper surfaces of the IGBT part and the FWD part; wherein the IGBT part and the FWD part are arranged in a staggered pattern in the plane of the semiconductor substrate; the IGBT part includes a gate electrode having a trench structure; a gate wiring is arranged in a region along a first direction among a boundary between the cell region and the terminal region and a boundary between the IGBT part and the FWD part; the gate electrode is connected to the gate wiring; and a connection portion between the emitter electrode and the emitter wire is formed in either one of the IGBT part and the FWD part.

2. A semiconductor device comprising: a cell region composed of a plurality of cells each including a cell corresponding to an IGBT part and an FWD part; a semiconductor substrate in which a terminal region surrounding the outer peripheral side of the cell region is defined; an emitter wire connected to an emitter electrode formed on the upper surfaces of the IGBT part and the FWD part; wherein the IGBT part and the FWD part are arranged in a staggered pattern in the plane of the semiconductor substrate; the IGBT part includes a gate electrode having a trench structure; a gate wiring is arranged in a region along a first direction among a boundary between the cell region and the terminal region and a boundary between the IGBT part and the FWD part; the gate electrode is connected to the gate wiring; and a connection portion between the emitter electrode and the emitter wire is formed across a boundary between the IGBT part and the FWD part in the first direction and a peripheral region thereof.

3. A semiconductor device comprising: a cell region composed of a plurality of cells including cells corresponding to an IGBT section and an FWD section respectively; a semiconductor substrate in which a terminal region surrounding the outer peripheral side of the cell region is defined; an emitter wire connected to an emitter electrode formed on the upper surfaces of the IGBT section and the FWD section; wherein the IGBT section and the FWD section are arranged in a staggered pattern in the plane of the semiconductor substrate; the IGBT section includes a gate electrode having a trench structure; gate wiring is arranged in a region along a first direction among the boundary between the cell region and the terminal region and the boundary between the IGBT section and the FWD section; the gate electrode is connected to the gate wiring; and the connection portion between the emitter electrode and the emitter wire is continuously formed across a plurality of boundaries between the IGBT section and the FWD section in the first direction and their peripheral regions.

4. The semiconductor device according to any one of claims 1 to 3, wherein a plurality of the cells are arranged in numbers of 10 or more along the first direction and a second direction orthogonal to the first direction.

5. A semiconductor device comprising: a cell region composed of a plurality of cells including cells corresponding to an IGBT section and an FWD section respectively; a semiconductor substrate in which a terminal region surrounding the outer peripheral side of the cell region is defined; an emitter wire connected to an emitter electrode formed on the upper surfaces of the IGBT section and the FWD section; wherein the IGBT section and the FWD section are arranged in a staggered pattern in the plane of the semiconductor substrate; the IGBT section includes a gate electrode having a trench structure; gate wiring connected to the gate electrode is arranged at the central portion of the IGBT section; the emitter electrode is formed in a region other than the central portion of the IGBT section and in the FWD section; the gate electrode of the IGBT section is connected by a gate wire; and the connection portion between the emitter electrode and the emitter wire is formed in the FWD section adjacent to the terminal region.

6. The semiconductor device according to claim 5, wherein the connection portion is formed in a region adjacent to the terminal region in the FWD section adjacent to the terminal region.

7. The semiconductor device according to claim 5 or claim 6, wherein a plurality of the cells are arranged in numbers of 10 or more along a first direction and a second direction orthogonal to the first direction in the plane of the semiconductor substrate.

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