Semiconductor device and electronic apparatus

Abstract

This semiconductor device 100 comprises: a first semiconductor region 5; a second semiconductor region 32 on the first semiconductor region; a third semiconductor region 30 on the second semiconductor region; a fourth semiconductor region 7 on the third semiconductor region; a fifth semiconductor region 8 on the fourth semiconductor region; first trenches 14 extending to the first semiconductor region; gate electrodes 14a provided in the first trenches; a sixth semiconductor region 4 on the first semiconductor region; a seventh semiconductor region 2 on the sixth semiconductor region; at least two second trenches 16 provided between the first trenches in a plan view; auxiliary electrodes 16a provided in the second trenches; an upper main electrode 11 connected to the fourth semiconductor region and the fifth semiconductor region; a lower main electrode connected to the seventh semiconductor region; an eighth semiconductor region 28 having a Schottky connection with the upper main electrode and arranged on the first semiconductor region between the second trenches; and a ninth semiconductor region 28C connecting the third semiconductor region between the first trenches and the second trenches and the eighth semiconductor region between the second trenches.

Description

Semiconductor devices and electronic devices

[0001] The present invention relates to a semiconductor device and an electronic device.

[0002] In recent years, switching elements with an insulated gate structure, such as insulated gate bipolar transistors (IGBTs) and metal oxide semiconductor field effect transistors (MOSFETs), have been adopted as power semiconductor elements. Furthermore, a reverse conducting (RC) IGBT with a Schottky and multi-layered anode (SMA) structure has recently been disclosed.

[0003] JP 2020-47723 A JP 2016-164952 A

[0004] Yusuke Yamashita, Satoru Machida, Jun Saito and Masaru Senoo, “Novel Diode Structure for Ultra-Low-Loss RC-IGBTs”, Proceedings of the 35th International Symposium on Power Semiconductor Devices & ICs, May 28 - June 1, 2023, Hong Kong, China.

[0005] The embodiments of the present invention provide a semiconductor device (RC-IGBT) capable of reducing the reverse recovery charge and reverse recovery time and improving the turn-off characteristics.

[0006] The semiconductor device of the embodiment includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type on the first semiconductor region, a third semiconductor region of the first conductivity type on the second semiconductor region, a fourth semiconductor region of the second conductivity type on the third semiconductor region, a fifth semiconductor region of the first conductivity type on the fourth semiconductor region, a first trench reaching the first semiconductor region, a gate electrode provided in the first trench via a first insulating film, a sixth semiconductor region of the first conductivity type on the first semiconductor region on the opposite side to the second semiconductor region, and a seventh semiconductor region of the second conductivity type on the sixth semiconductor region. The semiconductor device includes at least two second trenches provided between the first trenches, an auxiliary electrode provided in the second trenches via a second insulating film, an upper main electrode electrically connected to the fourth semiconductor region and the fifth semiconductor region, a lower main electrode electrically connected to the seventh semiconductor region, an eighth semiconductor region of the first conductivity type that is Schottky-connected to the upper main electrode and is provided on the first semiconductor region between the second trenches, and a ninth semiconductor region of the first conductivity type that connects the third semiconductor region between the first trench and the second trench and the eighth semiconductor region between the second trenches.

[0007] According to the embodiments of the present invention, it is possible to provide a semiconductor device (RC-IGBT) capable of reducing the reverse recovery charge and reverse recovery time and improving the turn-off characteristics.

[0008] 6B is a cross-sectional view of a semiconductor device according to a comparative example; a bird's-eye view of an IGBT portion of the semiconductor device according to the embodiment; a plan view of the IGBT portion of the semiconductor device according to the embodiment; a cross-sectional view taken along line II in FIG. 2B; a cross-sectional view taken along line II-II in FIG. 2B; a cross-sectional view taken along line III-III in FIG. 2B; a bird's-eye view of an FWD portion of the semiconductor device according to the embodiment; a plan view of the FWD portion of the semiconductor device according to the embodiment; a cross-sectional view taken along line IV-IV in FIG. 6B; a cross-sectional view of a semiconductor device according to a first modification of the embodiment, taken along line II-II in FIG. 2B; a bird's-eye view of an IGBT portion of a semiconductor device according to a second modification of the embodiment; a plan view of an IGBT portion of a semiconductor device according to a second modification of the embodiment; a cross-sectional view taken along line V-V in FIG. 9B; a cross-sectional view of a semiconductor device according to a third modification of the embodiment, taken along line VI-VI in FIG. 9B; a bird's-eye view of an IGBT portion of a semiconductor device according to a fourth modification of the embodiment. 14 is a cross-sectional view taken along line VII-VII in FIG. 12. FIG. 15 is a top view of the overall structure of the semiconductor device according to the embodiment. FIG.

[0009] Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of lengths of each part, etc., may differ from the actual ones. Therefore, specific dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0010] Furthermore, the embodiments described below are merely examples of devices embodying the technical concept of this invention, and the technical concept of this invention does not limit the shape, structure, or arrangement of the components to those described below. Various modifications can be made to the embodiments of this invention within the scope of the claims. In this invention, terms specifying "upper" and "lower," such as "upper" and "lower," are used for convenience of description. Even if a component is provided on a side surface, it falls within the scope of the present invention as long as it is substantially identical to the constituent features of this invention. Furthermore, "upper" includes not only a component formed in contact with an object but also a component formed via another layer. Furthermore, in this invention, "connection" and "electrical connection" are not limited to direct connection; even if a connection is made via an intervening resistor or other element, it falls within the scope of the present invention as long as it is substantially identical to the constituent features of this invention.

[0011] In the following description, N + , N, N - and P + , P, P - When the notations are used, these notations represent the relative levels of impurity concentration in each conductivity type. + has a relatively higher N-type impurity concentration than N, - indicates that the N-type impurity concentration is relatively lower than that of N. + Is, P + The P-type impurity concentration is relatively higher than that of - indicates that the P-type impurity concentration is relatively lower than that of P. + Type, N - The type is simply N type, P + Type, P - The type may be simply referred to as P type.

[0012] In the following description, the directions of the semiconductor device are defined by the X, Y, and Z axes. In a cross-sectional view, the left-right direction is the X-axis direction, the direction perpendicular to the paper surface is the Y-axis direction, and the direction perpendicular to the XY plane is the Z-axis direction. Note that these directions are merely examples. They may be changed as appropriate depending on the pattern arrangement. Furthermore, in the following description, the semiconductor device will be primarily described as an insulated gate bipolar transistor (IGBT). However, instead of an IGBT, other transistor elements with an insulated gate structure, such as an electron injection enhanced insulated gate transistor (IEGT), may also be used. Furthermore, the material of the semiconductor layer is not limited to silicon (Si). Other semiconductor materials, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (GaO), and germanium oxide (GeO), may also be used.

[0013] 1 is a cross-sectional view of an IGBT section 100A of a semiconductor device (RC-IGBT) according to a comparative example. The IGBT section 100A has an SMA structure.

[0014] 1, the IGBT section 100A includes a semiconductor substrate 101A, an emitter electrode 11A, and a collector electrode 1A. The emitter electrode 11A is disposed on an upper surface 20aA of the semiconductor substrate 101A. The collector electrode 1A is disposed on a lower surface 20bA of the semiconductor substrate 101A.

[0015] A plurality of trenches 14A are formed in the upper surface 20aA of the semiconductor substrate 101A. When the upper surface 20aA of the semiconductor substrate 101A is viewed in a plan view, the trenches 14A are aligned at intervals in the X direction. When the upper surface 20aA of the semiconductor substrate 101A is viewed in a plan view, the trenches 14A extend linearly in the Y direction.

[0016] The inner surface of the trench 14A is covered with an insulating film 14bA. An intra-trench electrode 14aA is disposed within the trench 14A. The intra-trench electrode 14aA faces the semiconductor substrate 101A via the insulating film 14bA. The intra-trench electrode 14aA is insulated from the semiconductor substrate 101A by the insulating film 14bA. The upper surface of the intra-trench electrode 14aA is covered with an interlayer insulating layer 13A. The upper surface 20aA of the semiconductor substrate 101A near the trench 14A is also covered with the interlayer insulating layer 13A. An emitter electrode 11A is disposed to cover the interlayer insulating layer 13A. The intra-trench electrode 14aA is insulated from the emitter electrode 11A by the interlayer insulating layer 13A. The emitter electrode 11A contacts the upper surface 20aA of the semiconductor substrate 101A within the opening 79A where the interlayer insulating layer 13A is not provided.

[0017] Between the trenches 14A, an emitter region 8A, a body contact region 7A, an isolation body region 27A, a pillar region 28A, a barrier region 30A, and a lower body region 32A are arranged.

[0018] The pillar region 28A is made of an N-type semiconductor with a low concentration of N-type impurities, and is in Schottky contact with the emitter electrode 11A within the opening 79A.

[0019] The body contact region 7A is made of a P-type semiconductor with a high concentration of P-type impurities. As shown in FIG. 1, the body contact region 7A is disposed in an area exposed on the upper surface 20aA of the semiconductor substrate 101A. The body contact region 7A is in electrical contact with the emitter electrode 11A on the upper surface 20aA within the opening 79A.

[0020] The emitter regions 8A are made of an N-type semiconductor with a high concentration of N-type impurities. As shown in Fig. 1, the emitter regions 8A are disposed on the side surfaces of the trenches 14A. As shown in Fig. 1, a portion of each emitter region 8A is disposed within the opening 79A, and the other portion of each emitter region 8A is disposed outside the opening 79A (i.e., the area covered by the interlayer insulating layer 13A). Each emitter region 8A is in ohmic contact with the emitter electrode 11A within the opening 79A.

[0021] The isolation body region 27A is made of a P-type semiconductor with a lower P-type impurity concentration than the body contact region 7A. The isolation body region 27A is disposed below the emitter region 8A and the body contact region 7A. The isolation body region 27A contacts the emitter region 8A and the body contact region 7A from below. The isolation body region 27A extends over the entire area in the X and Y directions, except for the lower portion of the pillar region 28A. The pillar region 28A extends downward (in the minus Z direction) from the upper surface 20aA and penetrates the isolation body region 27A. The isolation body region 27A contacts the trench 14A below the emitter region 8A and functions as a channel.

[0022] The barrier region 30A is made of an N-type semiconductor with a lower concentration of N-type impurities than the emitter region 8A. The barrier region 30A is disposed below the isolation body region 27A and the pillar region 28A. The barrier region 30A contacts the isolation body region 27A and the pillar region 28A from below. The barrier region 30A extends in the X and Y directions. The barrier region 30A contacts the trench 14A below the isolation body region 27A.

[0023] The lower body region 32A is made of a P-type semiconductor with a lower P-type impurity concentration than the body contact region 7A. The lower body region 32A is disposed below the barrier region 30A. The lower body region 32A contacts the barrier region 30A from below. The lower body region 32A extends in the X and Y directions. The lower body region 32A contacts the trench 14A below the barrier region 30A.

[0024] The semiconductor substrate 101A has a drift region 5A and a collector region 2A. The drift region 5A and the collector region 2A are arranged in the negative Z direction from the lower body region 32A.

[0025] The drift region 5A is made of an N-type semiconductor having a lower N-type impurity concentration than the barrier region 30A and the pillar region 28A. The drift region 5A is disposed below the lower body region 32A. The drift region 5A contacts the lower body region 32A from below. The drift region 5A extends in the X and Y directions of the semiconductor substrate 101A. The drift region 5A contacts the lower end of each trench 14A.

[0026] The collector region 2A is made of a P-type semiconductor having a higher P-type impurity concentration than the isolation body region 27A and the lower body region 32A. A field stop layer may be disposed between the collector region 2A and the drift region 5A. The collector region 2A is disposed in an area exposed on the lower surface 20bA of the semiconductor substrate 101A. The collector region 2A is in ohmic contact with the collector electrode 1A.

[0027] In the IGBT section 100A according to the comparative example, the pillar regions 28A connected to the barrier regions 30A are formed between the trenches 14A. The pillar regions 28A form a PN junction with the body contact regions 7A or the isolation body regions 27A.

[0028] In the semiconductor device 100A according to the comparative example, an isolation body region 27A and a pillar region 28A are provided adjacent to each other so that the portion facing the trench 14A functions as a channel.

[0029] When the structure of the pillar region 28A connected to the barrier region 30A and the body contact region 7A or the isolation body region 27A is formed using ion implantation technology and thermal diffusion technology, the barrier region 30A and the pillar region 28A may not be well connected. In particular, the pillar region 28A is connected to the emitter electrode 11A via a Schottky contact, and the impurity concentration of the pillar region 28A needs to be kept low. If the barrier region 30A and the pillar region 28A are not well connected, the barrier region 30A will be at an electrically floating potential, and it will be impossible to suppress the injection of holes from the isolation body region 27A into the N-type drift region 5A during diode operation.

[0030] Although the above problem can be improved by thickening the barrier region 30A, if the barrier region 30A is formed thick, which has a relatively high impurity concentration, it becomes difficult to ensure a sufficient breakdown voltage. Therefore, in the SMA structure, it is difficult to provide both the active region and the low-concentration pillar region 28A adjacent to each other in the region sandwiched between the trench structures of the gate potential.

[0031] (IGBT Section) Fig. 2A is a bird's-eye view of the IGBT section 100 of the semiconductor device according to the embodiment. Fig. 2B is a plan view of the IGBT section 100 of the semiconductor device according to the embodiment.

[0032] 2A and 2B and 3 to 5, the IGBT section 100 of the semiconductor device according to the embodiment includes an N-type drift region 5, a P-type lower body region 32 on the N-type drift region 5, an N-type barrier region 30 on the P-type lower body region 32, a P-type upper body region 7 on the N-type barrier region 30, an N-type emitter region 8 on the P-type upper body region 7, a first trench (gate trench) 14 reaching the N-type drift region 5, a gate electrode (G) 14a provided in the first trench 14 via an insulating film 14b, an N-type field stop region 4 of the first conductivity type on the N-type drift region 5 on the opposite side of the P-type lower body region 32, a P-type collector region 2 on the N-type field stop region 4, and a planar the N-type drift region 5 between the second trenches 16; and an N-type pillar connection region 28C connecting an N-type barrier region 30 between the first trenches 14 and the second trenches 16 to the N-type pillar region 28 or the N-type barrier region 30 between the second trenches 16.

[0033] 2A and 2B , in a plan view, the second trenches 16 are provided at intervals in the longitudinal direction (Y direction). By spacing the second trenches 16 apart, an N-type pillar connection region 28C can be provided, and the N-type barrier region 30 between the first trench 14 and the second trench and the N-type pillar region 28 between the second trenches can be connected.

[0034] FIG. 3 is a cross-sectional view taken along line II in FIG. 2B.

[0035] As shown in FIG. 3 , in the IGBT section 100 of the semiconductor device according to the embodiment, the distance in the X direction between adjacent second trenches 16 is WE, which is the same as the distance in the X direction WG between adjacent first trenches 14 and second trenches 16, for example.

[0036] FIG. 4 is a cross-sectional view taken along line II-II in FIG. 2B.

[0037] FIG. 5 is a cross-sectional view taken along line III-III in FIG. 2B.

[0038] 2A , 2B , and 5 , the IGBT section 100 of the semiconductor device according to the embodiment further includes, at longitudinal (Y-direction) ends of the second trenches 16, a tenth semiconductor region (deep P-type region) 31 of the second conductivity type that is connected to a P-type lower body region 32 located on the N-type drift region 5 between the second trenches 16. In addition, an N-type pillar connection region 28C is provided between longitudinal ends of the second trenches 16. In plan view, the tenth semiconductor region 31 may be formed to surround the second trench 16.

[0039] In the IGBT section 100 of the semiconductor device according to the embodiment, at least two second trenches 16 of the emitter potential are provided between the trenches 14 of the gate potential. The area between the first trench 14 of the gate potential and the second trench 16 of the emitter potential is defined as an active region. A region (a region not forming a channel region) for an N-type pillar region 28 connected to the N-type barrier region 30 is provided between the trenches 16 of the emitter potential, and this region is Schottky-connected to the upper main electrode 11. Furthermore, the second trenches 16 are shorter than the first trenches 14 in the Y direction, and multiple second trenches 16 are arranged in the Y direction. An N-type pillar connection region 28C is provided so as to bypass the outside of the end of the second trench 16 in the longitudinal direction (Y direction). The N-type pillar connection region 28C is provided between the second trenches 16 in the Y direction. The N-type pillar region 28 or the N-type barrier region 30 between the second trenches 16 at the emitter potential and the N-type barrier region 30 below the active region are connected via an N-type pillar connection region 28C.

[0040] This allows the N-type pillar region 28, which is lightly doped to provide resistance and forms a Schottky junction with the emitter electrode 11, to be reliably connected to the N-type barrier region 30 in the active region. Note that the N-type barrier region 30 may also be formed between the second trenches 16 at the emitter potential, or only the N-type pillar region 28 may be present.

[0041] Furthermore, the N-type pillar connection region 28C may be formed by extending at least a portion of the N-type pillar region 28, or may be formed by extending at least a portion of the N-type barrier region 30, or may be formed by extending at least a portion (a portion in the thickness direction) of both the N-type barrier region 30 and the N-type pillar region 28.

[0042] Furthermore, a P-type semiconductor region similar to the P-type lower body region 32 may be formed on the N-type drift region 5 between the second trenches 16 of the emitter potential. This allows a depletion layer to expand between the P-type semiconductor region similar to the P-type lower body region 32 and the N-type drift region 5, thereby ensuring the breakdown voltage between the second trenches 16 of the emitter potential.

[0043] In the case of the IGBT region, a P-type collector region 2 electrically connected to the lower main electrode 1 extends to the lower portions of the active region and the N-type pillar region 28, and in the case of the FWD region described below, an N-type cathode region 33 extends to the active region and the N-type pillar region 28. The FWD will be described in detail with reference to FIGS. 6A, 6B and 7.

[0044] (Explanation of Operation) Next, the operation of the IGBT section 100 will be described. A voltage that makes the collector electrode 1 positive is applied between the collector electrode 1 and the emitter electrode 11. When a voltage equal to or greater than the gate threshold is applied to the gate electrode 14a, the isolation body region 27 and the lower body region 32 in contact with the gate insulating film 14b are inverted to N-type, forming a channel. For example, in the cross section shown in FIG. 3, a channel is formed in the isolation body region 27 and the lower body region 32 in contact with the gate insulating film 14b of the trench 14. When the channel is formed, electrons flow from the emitter electrode 11 through the emitter region 8 and the channel into the drift region 5. At the same time, holes flow from the collector electrode 1 through the collector region 2 into the drift region 5. As a result, the electrical resistance of the drift region 5 decreases due to the conductivity modulation phenomenon. The electrons that flow into the drift region 5 pass through the drift region 5 and the collector region 2 and flow to the collector electrode 1A. In this way, electrons flow from the emitter electrode 11 A to the collector electrode 1 , causing a current to flow through the IGBT section 100 .

[0045] Furthermore, holes that have flowed into the drift region 5 pass through the lower body region 32 and the barrier region 30 and flow into the isolation body region 27, and then flow from the body contact region 7 to the emitter electrode 11. At this time, the barrier region 30 acts as a barrier that blocks the flow of holes. This increases the concentration of holes in the drift region 5, further reducing the electrical resistance of the drift region 5. This reduces the on-voltage of the IGBT 100. Since the N-type pillar region 28 or the N-type barrier region 30 between the second trenches 16 is connected to the N-type barrier region 30 in the active region via the N-type pillar connection region 28C, a depletion layer extends between the P-type lower body region 32 between the second trenches 16 and the N-type drift region 5.

[0046] When the IGBT section 100 switches from on to off, the N-type pillar region 28 is connected to the lower body region 32, so a depletion layer spreads from the interface between the lower body region 32 and the drift region 5, and no current flows through the IGBT section 100. In the region sandwiched between the second trenches 16, the N-type barrier region 30 is connected to the N-type pillar region 28, and the N-type pillar region 28 is in a reverse bias state with the upper main electrode 11. The depletion layer also spreads from the wall surfaces of the second trenches 16. The depletion layer also spreads further between the P-type lower body region 32 and the N-type drift region 5 between the second trenches 16.

[0047] When a voltage is applied between collector electrode 1 and emitter electrode 11 such that collector electrode 1 becomes negative, holes are injected from lower body region 32, which is PN-connected to barrier region 30, which is Schottky-connected to emitter electrode 11, into drift region 5 in IGBT section 100. Here, the impurity concentration of lower body region 32 is lower than the impurity concentration of isolation body region 27, so the amount of holes injected into drift region 5 in IGBT section 100 can be reduced.

[0048] In the IGBT section 100 of the semiconductor device (RC-IGBT) according to the embodiment, the pillar regions 28 are formed between the second trenches 16. The distance between adjacent second trenches 16 in the X direction is WE, which is the same as the distance WG between adjacent first trenches 14 and second trenches 16 in the X direction, for example. The second trenches 16 sandwiching the pillar regions 28 spread the depletion layer toward the drift layer 5 in the same way as the first trenches 14, and therefore the depletion layer in the IGBT section 100 can be made flatter.

[0049] Furthermore, after forming the second trench 16, the second trench 16 is formed so as to be connected to the barrier region 30 by ion implantation and thermal diffusion. The second trench 16 inhibits the diffusion of N-type impurities that form the pillar region 28, suppressing the N-type impurities from affecting the channel of the P-type isolation body region 27, and thus the pillar region 28 and the barrier region 30 can be well connected while keeping the impurity concentration of the pillar region 28 low. Note that the upper surface of the pillar region 28 does not need to form a PN junction with the P-type upper body region 7 or the P-type isolation body region 27. On the other hand, it is desirable that the lower body region 32 be formed on the lower surface of the pillar region 28.

[0050] (Embodiment: FWD Section) FIG. 6A is a bird's-eye view of the FWD section 200 of the semiconductor device according to the embodiment. The FWD (Freewheeling Diode) is a freewheeling diode. In the semiconductor device according to the embodiment, the FWD section 200 is formed on the same semiconductor substrate as the IGBT section 100. In the semiconductor device according to the embodiment, the FWD section 200 is electrically connected in reverse conduction with respect to the IGBT section 100. An example of a top view of the overall structure of the semiconductor device according to the embodiment is shown in FIG. 14. As is clear from comparison with FIG. 2A, the FWD section 200 shown in FIG. 6A can be formed with substantially the same structure as the IGBT section 100. That is, while the structure on the back surface side is different in FIG. 6A, it is not necessary to provide an N-type emitter region 8 on the front surface side. Also, instead of the trench 14 for the gate potential, a trench 14E for the emitter potential is provided. In the semiconductor device according to the embodiment, the IGBT section 100 and the FWD section 200 have substantially the same pattern configuration on the front surface side.

[0051] 6B is a plan view of the FWD portion of the semiconductor device 200 according to the embodiment, and FIG. 7 is a cross-sectional view taken along line IV-IV in FIG.

[0052] 6A, 6B, and 7, the FWD section 200 of the semiconductor device according to the embodiment includes an N-type drift region 5, a P-type lower body region 32 on the N-type drift region 5, an N-type barrier region 30 on the P-type lower body region 32, a P-type isolation body region 27 and a P-type upper body region 7 on the N-type barrier region 30, a first trench 14E reaching the N-type drift region 5, a field electrode 14aE provided in the first trench 14E via an insulating film 14bE, an N-type field stop region 4 on the N-type drift region 5 on the opposite side of the P-type lower body region 32, and at least two third field electrodes 14aE provided between the first trenches 14E in a plan view. an auxiliary electrode 16aE provided in the second trench 16E via an insulating film 16bE; an upper main electrode 11 electrically connected to the P-type upper body region 7; an N-type pillar region 28 that is in Schottky contact with the upper main electrode 11 and connects to the P-type lower body region 32 above the N-type drift region 5 between the second trenches 16E; an N-type pillar connection region 28C that connects the N-type barrier region 30 between the first trenches 14E and the N-type pillar region 28 between the second trenches 14E; an N-type cathode region 33 above the N-type field stop region 4; and a lower main electrode 1 electrically connected to the N-type cathode region 33.

[0053] 6A and 6B , in a plan view, the second trenches (emitter trenches) 16E are provided at intervals in the longitudinal direction (Y direction). By spacing the second trenches (emitter trenches) 16E apart, an N-type pillar connection region 28C can be provided, and the N-type barrier region 30 between the first trenches 14E and the N-type pillar region 28 between the second trenches 16E can be connected.

[0054] When a voltage that makes the upper main electrode 11 positive with respect to the lower main electrode 1 is applied to the FWD section 200, holes flow from the upper main electrode 11 to the P-type upper body region 7 or the P-type isolation body region 27 between the first trench 14E and the second trench 16E, the N-type barrier region 30, the P-type lower body region 32, the N-type drift region 5, the N-type field stop region 4, and the N-type cathode region 33, and the lower main electrode 1. Here, in the region sandwiched between the second trenches 16E, the N-type pillar region 28 is connected to the upper main electrode 11 by a Schottky connection. On the other hand, in the region sandwiched between the first trench 14E and the second trench 16E, the P-type isolation body region 27 and the upper main electrode 11 are connected by a low resistance, and the N-type barrier region 30 is connected to the N-type pillar region 28 sandwiched between the second trenches 16E via the N-type pillar connection region 28C. Therefore, the voltage drop across the N-type barrier region 30 is sufficiently smaller than the built-in voltage of the pn diode between the P-type isolation body region 27 and the N-type barrier region 30. This makes it difficult for the region sandwiched between the first trench 14E and the second trench 16E to turn on. Therefore, the movement of holes from this region to the N-type drift region 5 is reduced. Furthermore, because the N-type barrier region 30 is connected to the N-type pillar region 28 between the second trenches 16E, holes also flow to the N-type pillar region 28, the P-type lower body region 32, the N-type drift region 5, the N-type field stop region 4, the N-type cathode region 33, and the lower main electrode 1. Meanwhile, electrons flow to the N-type cathode region 33, the N-type field stop region 4, the N-type barrier region 30, and the N-type pillar region 28.

[0055] When a voltage that makes the upper main electrode 11 negative with respect to the lower main electrode 1 is applied to the FWD section 200 and the IGBT section is off, a depletion layer spreads from the interface between the N-type drift region 5 and the P-type lower body region 32, the interface between the P-type upper body region 7 or the P-type isolation body region 27 and the N-type barrier region 30, and the wall surfaces of the first trench 14E and the second trench 16E. Furthermore, a depletion layer spreads from the second trench 16E side in the N-type pillar region 28 sandwiched between the second trenches 16E, and a depletion layer due to the Schottky bias between the upper main electrode 11 and the N-type pillar region 28 also spreads. Here, a reverse recovery operation occurs in which holes remaining in the N-type drift region 5 move to the upper main electrode 11. However, because there are few holes in the N-type drift region 5 when a voltage that makes the upper main electrode 11 positive with respect to the lower main electrode 1 is applied to the FWD section 200, the number of holes that move from the FWD section 200 to the upper main electrode 11 also decreases. Therefore, the FWD section 200 can operate at high speed.

[0056] When a voltage that makes the upper main electrode 11 negative with respect to the lower main electrode 1 is applied and the IGBT section is turned on, the N-type barrier region 30 between the first trench 14E and the second trench 16E and the N-type pillar region 28 between the second trenches 16E are connected to the N-type pillar region 28 of the IGBT section via the upper main electrode 11, and therefore a depletion layer spreads from the interface between the P-type lower body region 32 between the first trench 14E and the second trench 16E and the N-type drift region 5 and the P-type lower body region 32 between the second trenches 16E.

[0057] 6A and 6B , the FWD section 200 of the semiconductor device according to the embodiment further includes a tenth semiconductor region (deep P-type region) 31 at the longitudinal (Y-direction) end of the second trenches 16, the tenth semiconductor region 31 being connected to the P-type lower body region 32 located on the N-type drift region 5 between the second trenches 16. In plan view, the tenth semiconductor region 31 may be formed to surround the second trench 16. In addition, an N-type pillar connection region 28C is provided between the longitudinal ends of the second trenches 16.

[0058] FIG. 7 is a cross-sectional view taken along line IV-IV in FIG. 6B.

[0059] As shown in FIG. 7 , in the FWD section 200 of the semiconductor device according to the embodiment, the distance in the X direction between the second trenches (emitter trenches) 16E is WD. This value WD is compared to the distance WE ( FIG. 3 ) in the X direction between the second trenches (emitter trenches) 16 in the IGBT section 100, such that WE < WD holds. Furthermore, it is desirable that the distance WD in the X direction between the second trenches 16E is shorter than the distance WF in the X direction between the first trench 14E and the second trench 16E. This makes it possible to suppress leakage current flowing through the N-type pillar region 28 sandwiched between the second trenches 16E.

[0060] According to the embodiment, it is possible to provide a semiconductor device that does not require lifetime control, reduces reverse recovery charge and reverse recovery time, and improves turn-off characteristics.

[0061] (Modification 1) Figure 8 is a cross-sectional view of the IGBT section 102 of a semiconductor device according to Modification 1 of the embodiment, taken along line II-II in Figure 2B. As shown in Figure 8, in the IGBT section 102, an N-type barrier region 30 is also formed between the trenches 16 at the emitter potential. The N-type pillar connection region 28C may be formed by extending at least a portion of both the N-type barrier region 30 and the N-type pillar region 28. The other configurations are the same as those of the embodiment.

[0062] By providing an N-type barrier region 30 also between the trenches 16 at the emitter potential, holes that have moved from the collector region 2 into the drift region 5 can be prevented from moving to the emitter electrode 11 by the junction barrier of the N-type barrier region 30, thereby allowing more holes to exist in the drift region 5 and increasing the conductivity modulation of the IGBT section 102.

[0063] If the P-type body region 32 is present, a channel is also generated in the P-type body region 32 when the IGBT is turned on, reducing the injection of electrons from the emitter region 8 to the drift region 5. Although the effect of conductivity modulation is reduced, the turn-off characteristics of the IGBT are greatly improved.

[0064] According to the first modification of the embodiment, it is possible to provide a semiconductor device capable of improving the turn-off characteristics. Similarly, an N-type barrier region 30 may be formed between the N-type pillar region 28 and the P-type lower body region 32 between the second trenches 16E in the FWD section 200 in FIG.

[0065] (Modification 2) Fig. 9A is a bird's-eye view of an IGBT portion 103 of a semiconductor device according to Modification 2 of the embodiment. Fig. 9B is a plan view of the IGBT portion 103. Fig. 10 is a cross-sectional view taken along line V-V in Fig. 9B. Fig. 11 is a cross-sectional view taken along line VI-VI in Fig. 9B.

[0066] As shown in FIGS. 9A , 9B , and 10 , the IGBT section 103 includes a groove 35 shallower than the N-pillar connection region 28C between the Y-direction ends of the second trench 16. The surface of the N-pillar connection region 28C is connected to the upper main electrode 11 via a Schottky contact. The groove 35 is formed in a cross-shaped region indicated by the reference numeral 35 in FIGS. 9A and 9B . As shown in FIG. 10 , an N-type barrier region 30 and a P-type body region 32 are provided below the N-pillar connection region 28C between the Y-direction ends of the second trench 16 in which the groove 35 is formed. According to the second modification of the embodiment, a semiconductor device capable of improving turn-off characteristics can be provided. Similarly, a groove 35 shallower than the N-pillar connection region 28C, as shown in the IGBT section 103 in FIGS. 9A , 9B , and 10 , may be formed between the Y-direction ends of the second trench 16 in the FWD section 200 of FIG. 7 . In addition, an N-type barrier region 30 and a P-type body region 32 may be provided below the N-type pillar connection region 28C below the shallow trench 35.

[0067] (Modification 3) Fig. 12 is a bird's-eye view of the IGBT portion 105 of a semiconductor device according to Modification 3 of the embodiment. Fig. 13 corresponds to a cross-sectional view taken along line VII-VII in Fig. 12.

[0068] As shown in FIGS. 12 and 13 , the IGBT section 105 includes a shallow trench STG extending in the Y direction above the P-type upper body region 7, and a shallow trench STE extending in the Y direction above the N-type pillar region 28. A P-type region 36 is formed on the upper surface of the N-type pillar region 28, excluding the shallow trench STE portion. The P-type region 36 further extends in the first trench direction (plus and minus X direction) and is connected to the P-type upper body region 7. The depth of the shallow trench STG is shallower than the junction depth of the P-type upper body region 7. The depth of the shallow trench STE is approximately the same as that of the shallow trench STG.

[0069] The upper main electrode 11 is also formed in the shallow trench STE and the shallow trench STG. The upper main electrode 11 forms a Schottky barrier with the N-type pillar region 28 on the sidewall and bottom of the shallow trench STE. Furthermore, a P-type region 37 may be provided so as to surround the sidewall of the shallow trench STE. By forming the P-type region 37 on the sidewall of the shallow trench STE, it is possible to alleviate electric field concentration at the bottom of the shallow trench STE and improve the breakdown voltage characteristics.

[0070] According to the fourth modification of the embodiment, it is possible to provide a semiconductor device capable of improving the turn-off characteristics.

[0071] (Overall Structure) FIG. 14 is a top view of the overall structure of the semiconductor device 10 according to the embodiment.

[0072] 14, the semiconductor device 10 according to the embodiment constitutes an RC-IGBT in which a semiconductor substrate 101, an FWD section 200 extending in the X direction on the semiconductor substrate 101 and arranged in a stripe pattern, and an IGBT section arranged adjacent to the FWD section 200 in the plus and minus Y directions on the semiconductor substrate 101 are formed on the single semiconductor substrate 101. The IGBT section 100 has, for example, a structure similar to the IGBT section shown in FIGS. 2A and 2B. The FWD section 200 has, for example, a structure similar to the FWD section shown in FIGS. 6A and 6B.

[0073] A termination region 40 on the periphery of the semiconductor device 10, surrounding the IGBT section 100 and the FWD section 200, is provided with a region called a resurf region for improving breakdown voltage. The IGBT section 100 extends in the X direction and is arranged in a stripe pattern adjacent to the FWD section 200 in the plus and minus Y directions, which extends in the X direction on the semiconductor substrate 101. A boundary region may be provided between the FWD section 200 and the IGBT section 100, but this is not shown. In the example shown in FIG. 16 , a control pad section 500 is also provided on the semiconductor substrate 101. Although not shown in FIG. 16 , an emitter pad 51 is provided on the IGBT section 100 and / or the FWD section 200.

[0074] The control pad section 500 includes a current sense pad 50, a gate pad 52, and temperature sense pads 53 and 54. The current sense pad 50 is a control pad for detecting the current flowing in the cell region of the semiconductor device 10.

[0075] The gate pad 52 is a control pad to which a gate drive voltage is applied for controlling the on / off of the semiconductor device 10. The temperature sense pads 53 and 54 are control pads electrically connected to the anode and cathode of a temperature sense diode provided in the semiconductor device 10, for example.

[0076] The semiconductor device 10 according to the embodiment includes an IGBT section 100 and an FWD section 200 arranged on the same semiconductor substrate 101. The cross-sectional area of ​​the N-type pillar region 28 of the IGBT section 100 in a plane (X-Y plane) perpendicular to the thickness direction (Z direction) of the semiconductor substrate 101 is smaller than the cross-sectional area of ​​the N-type pillar region 28 of the FWD section 200 in the X-Y plane.

[0077] The semiconductor device also includes an IGBT section 100 and an FWD section 200 arranged on the same semiconductor substrate 101, and the second trenches 16 of the IGBT section 100 extend in a first direction (Y direction) and are spaced apart by W E in a second direction (X direction) perpendicular to the first direction, and the second trenches 16E of the FWD section 200 extend in the first direction and are spaced apart by W E in the second direction (X direction) perpendicular to the first direction (Y direction), where W E < W D .

[0078] (Resurf Structure) FIG. 15 is a cross-sectional view taken along line VIII-VIII in FIG.

[0079] The semiconductor device (RC-IGBT) 10 according to the embodiment includes a first resurf region 220 and a second resurf region 230 in the termination region 40. The first resurf region 220 is connected to a P-type base region 270 to improve breakdown voltage. The second resurf region 230 is connected to the first resurf region 220 via a depletion layer. A dashed line BLL extending in the Z direction indicates the boundary between the IGBT section 100 and the termination region 40. The lower main electrode 1 is connected to a P-type collector region 2 of the IGBT section 100. The lower main electrode 1 is also connected to an N-type semiconductor region 33P in the termination region 40. The N-type semiconductor region 33P is at the same potential as the N-type cathode region 33 of the FWD section 200. The N-type semiconductor region 33P is also at the same potential as an N-type stopper layer 260 in the termination section. The boundary between the P-type collector region 2 of the IGBT section 100 and the N-type semiconductor region 33P is indicated by BLC3.

[0080] The semiconductor substrate 101 has an N-type drift region 5 constituting one surface thereof. A plurality of resurf regions 220, 230 are composed of P-type semiconductor regions having a lower impurity concentration than the P-type base region 270, and are formed in the surface region of the N-type drift region 5 so as to surround the IGBT section 100. The junction depths of the resurf regions 220, 230 are shallower than the first trench 14 and deeper than the P-type base region 270. Floating limiting ring (FLR) diffusion layers 240, 250 are disposed on the outer periphery of the second resurf region 230. Furthermore, an N-type stopper layer 260 is disposed at the termination portion. A stopper electrode 130 is connected to the stopper layer 260.

[0081] The floating limiting ring diffusion layers 240, 250 are provided to smooth the shape of the depletion layer and alleviate electric field concentration. The floating limiting ring diffusion layers 240, 250 are formed from P-type diffusion layers that are equivalent to or shallower than the resurf regions 220, 230. The impurity concentrations of the floating limiting ring diffusion layers 240, 250 are set to be equivalent to or higher than the impurity concentrations of the resurf regions 220, 230. The IGBT section 100 shown in FIG. 15 illustrates a portion of the IGBT section 100 of the semiconductor device (RC-IGBT) 10 according to the embodiment.

[0082] The semiconductor device (RC-IGBT) 10 according to the embodiment is provided with the resurf regions 220 and 230, and thus can easily achieve a high breakdown voltage.

[0083] (Other Embodiments) While several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be substituted or replaced with components of another embodiment. These embodiments and their modifications are within the scope and spirit of the invention, and are also encompassed by the inventions and their equivalents as set forth in the claims. The present invention may also be an electronic device equipped with the semiconductor device according to any one of claims 1 to 8. Examples of electronic devices equipped with the semiconductor device according to any one of claims 1 to 8 include inverters that drive electric motors used as power sources for electric vehicles (including hybrid vehicles), trains, industrial robots, etc., and power modules for inverter circuits that convert power generated by power conditioners in solar power generation systems, wind power generators, and other power generation devices (especially private power generation devices) into commercial power.

[0084] The semiconductor device of this embodiment can be used in various semiconductor technologies such as IGBT (Si, SiC, GaN, AlN, gallium oxide, germanium oxide), and can be used in a wide range of applications, such as inverters that drive electric motors used as power sources for electric vehicles (including hybrid vehicles), trains, industrial robots, etc., and power modules for inverter circuits that convert power generated by power conditioners in solar power generation systems, wind power generators, and other power generation devices (especially private power generation devices) into power from a commercial power source.

[0085] 1, 34...Lower main electrode (collector electrode, cathode electrode) 2...Seventh semiconductor region (P-type collector region) 4...Sixth semiconductor region (N-type field stop region) 5...First semiconductor region (N-type drift region) 7...Fourth semiconductor region (P-type upper body region) 8...Fifth semiconductor region (N-type emitter region) 10...Semiconductor device (RC-IGBT) 11...Upper main electrode (emitter electrode, anode electrode) 13...Interlayer insulating layer 14, 14E...First trench 14a...Gate electrode 14aE...Field electrode 14b, 14bE, 16b, 16bE...Insulating film 16, 16E...Second trench 16a...Auxiliary electrode 27...P-type isolation body region 28...Eighth semiconductor region (N-type pillar region) 28C...Ninth semiconductor region (N-type pillar connection region) 30...Third semiconductor region (N-type barrier region) 31...Eleventh semiconductor region (deep P-type region) 36, 37...P-type region 32...Second semiconductor region (P-type lower body region) 33...Tenth semiconductor region (N-type cathode region) 33P...N-type semiconductor region 35...Shallow trench (SBD) 40...Termination region 50, 52, 53, 54...Pad 100, 102, 103, 104, 105, 106...IGBT section 101...Semiconductor substrate 130...Stopper electrode 200...FWD section 220, 230...Resurf region 240, 250...Floating limiting ring (FLR) region 260...Stopper layer 270...P-type base region 500...Control pad section

Claims

1. A first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type over the first semiconductor region, a third semiconductor region of the first conductivity type over the second semiconductor region, a fourth semiconductor region of the second conductivity type over the third semiconductor region, a fifth semiconductor region of the first conductivity type over the fourth semiconductor region, a first trench reaching the first semiconductor region, a gate electrode provided in the first trench via a first insulating film, a sixth semiconductor region of the first conductivity type over the first semiconductor region on the opposite side of the second semiconductor region, a seventh semiconductor region of the second conductivity type over the sixth semiconductor region, at least two second trenches provided between the first trenches when viewed in plan, an auxiliary electrode provided in the second trenches via a second insulating film, an upper main electrode electrically connected to the fourth semiconductor region and the fifth semiconductor region, a lower main electrode electrically connected to the seventh semiconductor region, an eighth semiconductor region of the first conductivity type that is Schottky-connected to the upper main electrode and provided over the first semiconductor region between the second trenches, and a ninth semiconductor region of the first conductivity type that connects the third semiconductor region between the first trench and the second trench and the eighth semiconductor region between the second trenches. A semiconductor device comprising the above components.

2. A first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type on the first semiconductor region, a third semiconductor region of the first conductivity type on the second semiconductor region, a fourth semiconductor region of the second conductivity type on the third semiconductor region, a first trench reaching the first semiconductor region, a field electrode provided in the first trench via a third insulating film, a sixth semiconductor region of the first conductivity type on the first semiconductor region on the opposite side of the second semiconductor region, at least two second trenches provided between the first trenches when viewed in a plane, an auxiliary electrode provided in the second trenches via a fourth insulating film, an upper main electrode electrically connected to the fourth semiconductor region, a first conductivity type eighth semiconductor region that is Schottky-connected to the upper main electrode and provided on the first semiconductor region between the second trenches, a first conductivity type ninth semiconductor region connecting the third semiconductor region between the first trench and the second trench and the eighth semiconductor region between the second trenches, a first conductivity type tenth semiconductor region on the sixth semiconductor region, and a lower main electrode electrically connected to the tenth semiconductor region, a semiconductor device.

3. The semiconductor device according to claim 1 or 2, wherein, when viewed in a plane, the second trenches are provided at a plurality of intervals in the longitudinal direction.

4. The semiconductor device according to claim 3, further comprising an eleventh semiconductor region of the second conductivity type that is deeper than the second trench and connected to the second semiconductor region on the first semiconductor region between the second trenches at an end portion in the longitudinal direction of the second trench.

5. The semiconductor device according to claim 4, wherein the ninth semiconductor region is provided between end portions in the longitudinal direction of the second trench.

6. The semiconductor device according to claim 4, wherein a groove shallower than the junction depth of the eleventh semiconductor region is provided between end portions in the longitudinal direction of the second trench.

7. An IGBT section of the semiconductor device according to claim 1 and an FWD section of the semiconductor device according to claim 2 are provided on the same semiconductor substrate, and the intervals between the first trench and the second trench in each of the IGBT section and the FWD section are equal to the intervals between the second trenches in each of the IGBT section and the FWD section, a semiconductor device.

8. An IGBT section of the semiconductor device according to claim 1 and an FWD section of the semiconductor device according to claim 2, which are arranged on the same semiconductor substrate, wherein the second trench of the IGBT section extends in a first direction, and a distance WE between the second trenches arranged in a second direction orthogonal to the first direction is narrower than a distance WD between the second trenches of the FWD section, where the second trenches of the FWD section extend in the first direction and are arranged in the second direction orthogonal to the first direction.

9. An electronic device including the semiconductor device according to any one of claims 1 to 8.

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