Tracker circuit and high-frequency circuit

Abstract

The present invention comprises a plurality of control input terminals (43) that respectively receive a plurality of DCL signals, at least one switch that is included in a switched capacitor circuit (20) that is configured to generate a plurality of discrete voltages from an input voltage, a power supply modulation circuit (31) that is configured to selectively output at least one of the plurality of discrete voltages to a power amplifier (71) on the basis of the plurality of DCL signals, a power supply modulation circuit (32) that is configured to selectively output at least one of the plurality of discrete voltages to a power amplifier (72) on the basis of the plurality of DCL signals, and a delay circuit (622) that is connected between the plurality of control input terminals (43) and the power supply modulation circuit (31).

Description

Tracker circuit and high frequency circuit

[0001] The present invention relates to a tracker circuit and a high-frequency circuit.

[0002] In recent years, efforts have been made to improve power efficiency by applying envelope tracking (ET) to power amplifier circuits. Patent Document 1 discloses a digital envelope tracking (D-ET) mode that selectively supplies a plurality of discrete voltages to a power amplifier based on an envelope signal.

[0003] U.S. Patent No. 9,755,672

[0004] However, in the D-ET mode, when a power supply voltage is supplied to a plurality of power amplifiers simultaneously, the power supply voltage may not be able to follow the envelope of the high frequency signal as well, resulting in a decrease in power efficiency.

[0005] Therefore, the present invention provides a tracker circuit and a high frequency circuit that can improve power efficiency in the D-ET mode.

[0006] A tracker circuit according to one aspect of the present invention comprises a plurality of external connection terminals each receiving a plurality of digital control level signals, at least one switch included in a switched capacitor circuit configured to generate a plurality of discrete voltages from an input voltage, a first power supply modulation circuit configured to selectively output at least one of the plurality of discrete voltages to a first power amplifier based on the plurality of digital control level signals, a second power supply modulation circuit configured to selectively output at least one of the plurality of discrete voltages to a second power amplifier based on the plurality of digital control level signals, and a first delay circuit connected between the plurality of external connection terminals and the first power supply modulation circuit.

[0007] A high-frequency circuit according to one aspect of the present invention includes a plurality of first external connection terminals each receiving a plurality of discrete voltages, a plurality of second external connection terminals each receiving a plurality of digital control level signals, a first power amplifier and a second power amplifier, a first power supply modulation circuit configured to selectively output at least one of the plurality of discrete voltages to the first power amplifier based on the plurality of digital control level signals, a second power supply modulation circuit configured to selectively output at least one of the plurality of discrete voltages to the second power amplifier based on the plurality of digital control level signals, and a first delay circuit connected between the plurality of second external connection terminals and the first power supply modulation circuit.

[0008] According to the present invention, power efficiency can be improved in the D-ET mode.

[0009] FIG. 1A is a graph showing an example of a change in power supply voltage in APT (Average Power Tracking) mode. FIG. 1B is a graph showing an example of a change in power supply voltage in A-ET (Analog Envelope Tracking) mode. FIG. 1C is a graph showing an example of a change in power supply voltage in D-ET mode. FIG. 2 is a circuit configuration diagram of a communication device according to a first embodiment. FIG. 3 is a circuit configuration diagram of a tracker circuit according to the first embodiment. FIG. 4 is a circuit configuration diagram of a digital control circuit according to the first embodiment. FIG. 5 is a circuit configuration diagram of a communication device according to a variation of the first embodiment. FIG. 6 is a circuit configuration diagram of a communication device according to a second embodiment. FIG. 7 is a circuit configuration diagram of a communication device according to a third embodiment.

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangements and connection forms of the components shown in the following embodiments are merely examples and are not intended to limit the present invention.

[0011] It should be noted that the drawings are schematic diagrams in which emphasis, omission, or adjustment of proportions has been appropriately made to illustrate the present invention, and are not necessarily strictly illustrated, and may differ from the actual shapes, positional relationships, and proportions. In the drawings, the same reference numerals are used to denote substantially the same components, and redundant explanations may be omitted or simplified.

[0012] In a circuit configuration, "connected" includes not only direct connection by connection terminals and / or wiring conductors, but also electrical connection via other circuit elements. "A is switchably connected to B" means that the connection and disconnection between A and B can be switched, and A is connected to B via a switch. "A is connected to B" includes "A is switchably connected to B." "C is connected between A and B" means that one end of C is connected to A and the other end of C is connected to B, and C is arranged in series on the path connecting A and B. "The path connecting A and B" means a path made up of a conductor electrically connecting A to B.

[0013] In the following description, "terminal" means a point where a conductor within an element terminates, although it is understood that terminal can refer to any point on the conductor between elements or the entire conductor, not just a single point, provided that the impedance of the conductor between elements is sufficiently low.

[0014] Furthermore, terms indicating the relationship between elements, such as "parallel" and "perpendicular," terms indicating the shape of elements, such as "rectangle," and numerical ranges do not only represent the strict meaning, but also include a substantially equivalent range, for example, an error of a few percent.

[0015] First, as a technology for highly efficient amplification of high-frequency signals, a tracking mode will be described, in which a power amplifier is supplied with a power supply voltage that is dynamically adjusted over time based on the high-frequency signal. Tracking mode is a mode in which the power supply voltage applied to the power amplifier is dynamically adjusted. There are several types of tracking modes, but here, the APT mode, A-ET mode, and D-ET mode will be described with reference to FIGS. 1A, 1B, and 1C. In FIGS. 1A, 1B, and 1C, the horizontal axis represents time, and the vertical axis represents voltage. Furthermore, the thick solid line represents the power supply voltage, and the thin solid line (waveform) represents the modulation signal.

[0016] 1A is a graph showing an example of the transition of the power supply voltage in the APT mode. In the APT mode of FIG. 1A, the power supply voltage is changed to a plurality of discrete voltage levels in units of one frame based on the average power.

[0017] A frame is a unit that constitutes a high-frequency signal (modulated signal). For example, in 5GNR (5th Generation New Radio) and LTE (Long Term Evolution), a frame includes 10 subframes, each subframe includes multiple slots, and each slot includes multiple symbols. The subframe length is 1 ms, and the frame length is 10 ms.

[0018] A mode in which the voltage level is varied in units of one frame or larger based on the average power is called an APT mode, and is distinguished from a mode in which the voltage level is varied in units smaller than one frame (e.g., subframe, slot, or symbol). For example, a mode in which the voltage level is varied in symbol units is called a symbol power tracking (SPT) mode, and is distinguished from the APT mode.

[0019] 1B is a graph showing an example of the transition of the power supply voltage in the A-ET mode. In the A-ET mode, the envelope of the modulated signal is tracked by continuously varying the power supply voltage based on the envelope signal.

[0020] The envelope signal is a signal that indicates the envelope of the modulated signal. The envelope value is, for example, (I ２ +Q ２ ) where (I, Q) represents a constellation point. A constellation point is a point that represents a digitally modulated signal on a constellation diagram. (I, Q) is determined, for example, by a Baseband Integrated Circuit (BBIC) based on the transmitted information.

[0021] 1C is a graph showing an example of the transition of the power supply voltage in the D-ET mode. In the D-ET mode, the envelope of the modulated signal is tracked by varying the power supply voltage to multiple discrete voltage levels within one frame based on the envelope signal. In other words, in D-ET, the power supply voltage varies at shorter time intervals than in APT.

[0022] (First Embodiment) A first embodiment will be described below.

[0023] [1.1 Circuit Configuration of Communication Device 3] First, an exemplary circuit configuration of the communication device 3 according to this embodiment will be described with reference to Fig. 2. Fig. 2 is a circuit configuration diagram of the communication device 3 according to this embodiment.

[0024] 2 is an exemplary circuit configuration, and the communication device 3 may be implemented using any of a wide variety of circuit implementations and circuit technologies, and therefore the description of the communication device 3 provided below should not be construed as limiting.

[0025] The communication device 3 according to the present embodiment can be used to provide wireless connectivity. For example, the communication device 3 can be implemented in user equipment (UE) in a cellular network, such as a mobile phone, a smartphone, a tablet computer, or a wearable device. In another example, the communication device 3 can be implemented to provide wireless connectivity to Internet of Things (IoT) sensor devices, medical / healthcare devices, cars, unmanned aerial vehicles (UAVs) (also known as drones), and automated guided vehicles (AGVs). In yet another example, the communication device 3 can be implemented to provide wireless connectivity in a wireless access point or wireless hotspot.

[0026] As shown in FIG. 2, the communication device 3 includes a tracker circuit 1 and a high-frequency circuit 2 .

[0027] The tracker circuit 1 can simultaneously supply power supply voltage to the power amplifiers 71 and 72 in D-ET mode. Note that the tracker circuit 1 may also supply power supply voltage to the power amplifiers 71 and 72 in APT mode. The tracker circuit 1 can be implemented on a single semiconductor integrated circuit, which is sometimes called a PMIC (Power Management Integrated Circuit). The circuits and terminals within the tracker circuit 1 will be described later using FIG. 3.

[0028] The high-frequency circuit 2 can generate two high-frequency signals of a predetermined band by up-converting an IF (Intermediate Frequency) signal or a baseband signal received from outside the high-frequency circuit 2. Furthermore, the high-frequency circuit 2 can amplify the two generated high-frequency signals and output them to one or more antennas (not shown). The high-frequency circuit 2 can be implemented in a single semiconductor integrated circuit, which is sometimes called an RFIC (Radio Frequency Integrated Circuit).

[0029] Specifically, the high frequency circuit 2 includes power amplifiers 71 and 72 and power supply voltage terminals 81 and 82 .

[0030] The power supply voltage terminal 81 is an external connection terminal that receives the power supply voltage used by the power amplifier 71 from the tracker circuit 1. The power supply voltage terminal 81 is connected to the output terminal 44 of the tracker circuit 1 outside the high-frequency circuit 2, and is connected to the power amplifier 71 inside the high-frequency circuit 2.

[0031] The power supply voltage terminal 82 is an external connection terminal that receives the power supply voltage used by the power amplifier 72 from the tracker circuit 1. The power supply voltage terminal 82 is connected to the output terminal 45 of the tracker circuit 1 outside the high-frequency circuit 2, and is connected to the power amplifier 72 inside the high-frequency circuit 2.

[0032] The power amplifier 71 can amplify high frequency signals in a predetermined band using the power supply voltage supplied from the power supply modulation circuit 31 via the output terminal 44 and the power supply voltage terminal 81 .

[0033] The power amplifier 72 can amplify high frequency signals in a predetermined band using the power supply voltage supplied from the power supply modulation circuit 32 via the output terminal 45 and the power supply voltage terminal 82 .

[0034] The predetermined band is a frequency band for a communication system built using a radio access technology (RAT), and is defined in advance by a standardization organization (e.g., 3GPP (registered trademark) (3rd Generation Partnership Project) and IEEE (Institute of Electrical and Electronics Engineers)). Examples of the communication system include a 5G NR system, an LTE system, and a WLAN (Wireless Local Area Network) system.

[0035] In this embodiment, the 5G NR FR2 (Frequency Range 2) frequency band can be used as the predetermined band. In this case, the two high-frequency signals amplified by the high-frequency circuit 2 may be output to two antennas corresponding to two different polarization directions, for example. In this case, the two antennas may be realized by a single patch antenna.

[0036] 2 is an example and is not limited to this. For example, the communication device 3 may include an IF signal processing circuit that processes signals using an intermediate frequency band lower than the band of the high-frequency signal, and / or a baseband signal processing circuit that processes signals using a frequency band lower than the intermediate frequency band.

[0037] [1.2 Circuit Configuration of Tracker Circuit 1] Next, an exemplary circuit configuration of the tracker circuit 1 will be described with reference to Figures 2 and 3. Figure 3 is a circuit configuration diagram of the tracker circuit 1 according to this embodiment.

[0038] 2 and 3 are exemplary circuit configurations, and tracker circuit 1 may be implemented using any of a wide variety of circuit implementations and circuit techniques, and therefore the circuit descriptions provided below should not be construed as limiting.

[0039] As shown in Figures 2 and 3, the tracker circuit 1 includes a pre-regulator circuit 10, a switched capacitor circuit 20, power supply modulation circuits 31 and 32, an input terminal 41, a plurality of control input terminals 42 and 43, output terminals 44 and 45, and digital control circuits 61 and 62.

[0040] The input terminal 41 is an external connection terminal that receives a DC voltage from a DC power supply (not shown). The input terminal 41 is connected to the DC power supply outside the tracker circuit 1 and is connected to the pre-regulator circuit 10 inside the tracker circuit 1.

[0041] The plurality of control input terminals 42 are a plurality of external connection terminals that receive serial data signals that control the pre-regulator circuit 10 and the switched capacitor from outside the tracker circuit 1. The plurality of control input terminals 42 are connected to a digital control circuit 61 within the tracker circuit 1.

[0042] The control input terminals 43 are external connection terminals that respectively receive digital control level (DCL) signals that control the power supply modulation circuits 31 and 32 from outside the tracker circuit 1. The control input terminals 43 are connected to a digital control circuit 62 within the tracker circuit 1.

[0043] The output terminal 44 is an external connection terminal that supplies a power supply voltage to the power amplifier 71. The output terminal 44 is connected to a power supply voltage terminal 81 of the high frequency circuit 2 outside the tracker circuit 1, and is connected to a power supply modulation circuit 31 inside the tracker circuit 1.

[0044] The output terminal 45 is an external connection terminal that supplies a power supply voltage to the power amplifier 72. The output terminal 45 is connected to a power supply voltage terminal 82 of the high frequency circuit 2 outside the tracker circuit 1, and is connected to a power supply modulation circuit 32 inside the tracker circuit 1.

[0045] The pre-regulator circuit 10 is sometimes called a magnetic regulator or a DC (Direct Current) / DC converter. In this embodiment, the pre-regulator circuit 10 is a one-input, one-output buck-boost converter that can convert a DC voltage into a regulated voltage. The pre-regulator circuit 10 may be a buck converter or a boost converter. The pre-regulator circuit 10 can change the regulated voltage based on serial data signals received at multiple control input terminals 42. A detailed circuit configuration of the pre-regulator circuit 10 will be described later. Note that part or all of the pre-regulator circuit 10 does not need to be included in the tracker circuit 1.

[0046] The switched capacitor circuit 20 can generate a plurality of discrete voltages V1, V2, and V3 based on the regulated voltage supplied by the pre-regulator circuit 10. A detailed circuit configuration of the switched capacitor circuit 20 will be described later. Note that a part of the switched capacitor circuit 20 may not be included in the tracker circuit 1.

[0047] The power supply modulation circuits 31 and 32 are examples of a first power supply modulation circuit and a second power supply modulation circuit, respectively. The power supply modulation circuits 31 and 32 can selectively output at least one of a plurality of discrete voltages generated by the switched capacitor circuit 20 to the power amplifiers 71 and 72, respectively. In other words, the power supply modulation circuits 31 and 32 can select at least one voltage from a plurality of discrete voltages and supply the selected at least one voltage to the power amplifiers 71 and 72. The detailed circuit configurations of the power supply modulation circuits 31 and 32 will be described later.

[0048] The digital control circuit 61 processes serial data signals (CLK, DATA) received at the multiple control input terminals 42 and can generate multiple control signals CS10 and CS20 that control the pre-regulator circuit 10 and the switched capacitor circuit 20. The multiple control signals CS10 are signals that control the opening and closing of switches S101 to S104 included in the pre-regulator circuit 10. The multiple control signals CS20 are signals that control the opening and closing of switches S200 to S211 included in the switched capacitor circuit 20. Some or all of the digital control circuit 61 may not be included in the tracker circuit 1. In addition, a feedback signal for controlling the pre-regulator circuit 10 may be input to the digital control circuit 61.

[0049] The serial data signal may be, for example, a source synchronous digital control signal. Alternatively, a clock-embedded digital control signal may be used as the serial data signal. In this case, the multiple control input terminals 42 may be a single control input terminal 42. The digital control circuit 61 may also generate multiple control signals for controlling the power supply modulation circuits 31 and 32.

[0050] In this embodiment, one set of clock signal (CLK) and data signal (DATA) is shared by the pre-regulator circuit 10 and the switched-capacitor circuit 20, but this is not limiting. For example, one set of clock signal and data signal may be used individually by the pre-regulator circuit 10 and the switched-capacitor circuit 20.

[0051] The digital control circuit 62 processes parallel data signals received at the control input terminals 43 to generate a plurality of control signals CS31 and CS32. The control signals CS31 are an example of a plurality of first control signals, and are signals for controlling the power supply modulation circuit 31. The control signals CS32 are an example of a plurality of second control signals, and are signals for controlling the power supply modulation circuit 32.

[0052] In this embodiment, a plurality of DCL signals (DCL1, DCL2) are used as parallel data signals. The plurality of DCL signals (DCL1, DCL2) are generated based on the envelope signal of the high frequency signal.

[0053] Each of the multiple DCL signals (DCL1, DCL2) is a 1-bit signal. Each of the multiple discrete voltages V1, V2, and V3 is represented by a combination of two 1-bit signals. For example, V1, V2, and V3 are represented by "00," "01," and "10," respectively. Gray code may be used to represent the voltage levels.

[0054] In this embodiment, two DCL signals are used to control the power supply modulation circuits 31 and 32, but the number of DCL signals is not limited to this. For example, any number of DCL signals, one or three or more, may be used depending on the number of voltage levels selectable by each of the power supply modulation circuits 31 and 32. Furthermore, the parallel data signals used to control the power supply modulation circuits 31 and 32 are not limited to DCL signals.

[0055] [1.3 Circuit Configuration of Pre-regulator Circuit 10] Here, we will explain an exemplary circuit configuration of the pre-regulator circuit 10. The pre-regulator circuit 10 includes an input terminal T101, an output terminal T102, switches S101 to S104, a power inductor L101, and a capacitor C101.

[0056] The input terminal T101 is a terminal for receiving a DC voltage. The input terminal T101 is connected to the input terminal 41 of the tracker circuit 1 outside the pre-regulator circuit 10, and is connected to the switch S101 inside the pre-regulator circuit 10.

[0057] The output terminal T102 is a terminal that supplies a regulated voltage to the switched capacitor circuit 20. The output terminal T102 is connected to an input terminal T200 of the switched capacitor circuit 20 outside the pre-regulator circuit 10, and is connected to a switch S103 inside the pre-regulator circuit 10.

[0058] The power inductor L101 is an inductor used to step up and step down a DC voltage. One end of the power inductor L101 is connected to the switches S101 and S102, and the other end of the power inductor L101 is connected to the switches S103 and S104.

[0059] The switch S101 is connected between the input terminal T101 and one end of the power inductor L101. The switch S102 is connected between one end of the power inductor L101 and ground. In this connection configuration, the DC voltage received at the input terminal T101 can be stepped down by exclusively switching the switches S101 and S102 between open and closed.

[0060] The switch S103 is connected between the other end of the power inductor L101 and the output terminal T102. The switch S104 is connected between the other end of the power inductor L101 and the ground. In this connection configuration, the DC voltage received at the input terminal T101 can be boosted by exclusively switching the open and closed states of the switches S103 and S104.

[0061] The capacitor C101 is connected between the path between the switch S103 and the output terminal T102 and ground. Specifically, one of the two electrodes of the capacitor C101 is connected to the switch S103 and the output terminal T102, and the other of the two electrodes of the capacitor C101 is connected to ground.

[0062] 3 is an example and is not limiting. For example, some of the switches S101 to S104 may be replaced with diodes. Also, some or all of the pre-regulator circuit 10 may not be included in the tracker circuit 1.

[0063] [1.4 Circuit Configuration of Switched-Capacitor Circuit 20] Next, an exemplary circuit configuration of the switched-capacitor circuit 20 will be described. The switched-capacitor circuit 20 has a ladder-type circuit configuration and is capable of generating a plurality of discrete voltages V1, V2, and V3. Specifically, the switched-capacitor circuit 20 includes flying capacitors C200 to C203, smoothing capacitors C210 to C212, switches S200 to S211, an input terminal T200, and output terminals T201 to T203. Energy and charge are input from the pre-regulator circuit 10 to node N2 via the input terminal T200, and are extracted from nodes N1, N2, and N3 to power supply modulation circuits 31 and 32 via output terminals T201, T202, and T203.

[0064] The input terminal T200 is a terminal that receives a regulated voltage from the pre-regulator circuit 10. The input terminal T200 is connected to the pre-regulator circuit 10 outside the switched capacitor circuit 20, and is connected to a node N2 inside the switched capacitor circuit 20. Note that the node to which the input terminal T200 is connected is not limited to the node N2. The input terminal T200 may be connected to any of the nodes N1, N2, and N3.

[0065] The output terminals T201, T202, and T203 are terminals that supply a plurality of discrete voltages V1, V2, and V3, respectively, to the power supply modulation circuits 31 and 32. The output terminals T201, T202, and T203 are connected to the power supply modulation circuits 31 and 32 outside the switched capacitor circuit 20, and are connected to nodes N1, N2, and N3, respectively, within the switched capacitor circuit 20.

[0066] Flying capacitors C200, C201, C202, and C203, sometimes referred to as transfer capacitors, are used to boost and / or lower the regulated voltage supplied from the pre-regulator circuit 10. More specifically, flying capacitors C200, C201, C202, and C203 transfer charge between nodes N1, N2, and N3 and ground so that V1, V2, and V3 at three nodes N1, N2, and N3 are maintained such that (V3-V2):(V2-V1):(V1-VG)=1:1:1 and V3 > V2 > V1 > VG is satisfied. Here, VG represents ground potential. Note that (V3-V2):(V2-V1):(V1-VG) is not limited to 1:1:1 and can be designed to have any ratio (e.g., 1:2:3).

[0067] One of the two electrodes of the flying capacitor C200 is connected to one end of the switch S200 and one end of the switch S201, and the other of the two electrodes of the flying capacitor C200 is connected to one end of the switch S204 and one end of the switch S205.

[0068] One of the two electrodes of the flying capacitor C201 is connected to one end of the switch S202 and one end of the switch S203. The other of the two electrodes of the flying capacitor C201 is connected to one end of the switch S206 and one end of the switch S207.

[0069] Flying capacitor C202 is an example of a third flying capacitor. One of two electrodes of flying capacitor C202 is connected to one end of switch S204 and one end of switch S205. The other of two electrodes of flying capacitor C202 is connected to one end of switch S208 and one end of switch S209.

[0070] One of the two electrodes of the flying capacitor C203 is connected to one end of the switch S206 and one end of the switch S207. The other of the two electrodes of the flying capacitor C203 is connected to one end of the switch S210 and one end of the switch S211.

[0071] Smoothing capacitors C210, C211 and C212 are used to hold and smooth the discrete voltages V1, V2 and V3 at nodes N1, N2 and N3.

[0072] The smoothing capacitor C210 is connected between the node N1 and the ground. Specifically, one of the two electrodes of the smoothing capacitor C210 is connected to the node N1. Meanwhile, the other of the two electrodes of the smoothing capacitor C210 is connected to the ground.

[0073] The smoothing capacitor C211 is connected between the nodes N1 and N2. Specifically, one of the two electrodes of the smoothing capacitor C211 is connected to the node N2. Meanwhile, the other of the two electrodes of the smoothing capacitor C211 is connected to the node N1.

[0074] The smoothing capacitor C212 is connected between the nodes N2 and N3. Specifically, one of the two electrodes of the smoothing capacitor C212 is connected to the node N3. Meanwhile, the other of the two electrodes of the smoothing capacitor C212 is connected to the node N2.

[0075] The switch S200 is connected between the flying capacitor C200 and ground. Specifically, one end of the switch S200 is connected to one of the two electrodes of the flying capacitor C200. Meanwhile, the other end of the switch S200 is connected to ground.

[0076] The switch S201 is connected between the flying capacitor C200 and a node N1. Specifically, one end of the switch S201 is connected to one of the two electrodes of the flying capacitor C200. Meanwhile, the other end of the switch S201 is connected to the node N1.

[0077] The switch S202 is connected between the flying capacitor C201 and ground. Specifically, one end of the switch S202 is connected to one of the two electrodes of the flying capacitor C201. Meanwhile, the other end of the switch S202 is connected to ground.

[0078] The switch S203 is connected between the flying capacitor C201 and the node N1. Specifically, one end of the switch S203 is connected to one of the two electrodes of the flying capacitor C201. Meanwhile, the other end of the switch S203 is connected to the node N1.

[0079] The switch S204 is connected between the flying capacitors C200 and C202 and the node N1. Specifically, one end of the switch S204 is connected to the other of the two electrodes of the flying capacitor C200 and one of the two electrodes of the flying capacitor C202. Meanwhile, the other end of the switch S204 is connected to the node N1.

[0080] The switch S205 is connected between the flying capacitors C200 and C202 and the node N2. Specifically, one end of the switch S205 is connected to the other of the two electrodes of the flying capacitor C200 and one of the two electrodes of the flying capacitor C202. Meanwhile, the other end of the switch S205 is connected to the node N2.

[0081] The switch S206 is connected between the flying capacitors C201 and C203 and the node N1. Specifically, one end of the switch S206 is connected to the other of the two electrodes of the flying capacitor C201 and one of the two electrodes of the flying capacitor C203. Meanwhile, the other end of the switch S206 is connected to the node N1.

[0082] The switch S207 is connected between the flying capacitors C201 and C203 and the node N2. Specifically, one end of the switch S207 is connected to the other of the two electrodes of the flying capacitor C201 and one of the two electrodes of the flying capacitor C203. Meanwhile, the other end of the switch S207 is connected to the node N2.

[0083] The switch S208 is connected between the flying capacitor C202 and the node N2. Specifically, one end of the switch S208 is connected to the other of the two electrodes of the flying capacitor C202. Meanwhile, the other end of the switch S208 is connected to the node N2.

[0084] The switch S209 is connected between the flying capacitor C202 and a node N3. Specifically, one end of the switch S209 is connected to the other of the two electrodes of the flying capacitor C202. Meanwhile, the other end of the switch S209 is connected to the node N3.

[0085] The switch S210 is connected between the flying capacitor C203 and the node N2. Specifically, one end of the switch S210 is connected to the other of the two electrodes of the flying capacitor C203. Meanwhile, the other end of the switch S210 is connected to the node N2.

[0086] The switch S211 is connected between the flying capacitor C203 and a node N3. Specifically, one end of the switch S211 is connected to the other of the two electrodes of the flying capacitor C203. Meanwhile, the other end of the switch S211 is connected to the node N3.

[0087] A first set of switches including switches S200, S203, S204, S207, S208 and S211 and a second set of switches including switches S201, S202, S205, S206, S209 and S210 are switched between open and closed states inversely to each other based on a plurality of control signals CS20 from a digital control circuit 61.

[0088] Specifically, in the first phase, the first set of switches are closed and the second set of switches are opened. As a result, one of the two electrodes of the flying capacitor C200 is connected to ground. The other of the two electrodes of the flying capacitor C200, one of the two electrodes of the flying capacitor C201, and one of the two electrodes of the flying capacitor C202 are connected to node N1. The other of the two electrodes of the flying capacitor C201, the other of the two electrodes of the flying capacitor C202, and one of the two electrodes of the flying capacitor C203 are connected to node N2. The other of the two electrodes of the flying capacitor C203 is connected to node N3.

[0089] Conversely, in the second phase, the first set of switches are opened and the second set of switches are closed, thereby connecting one of the two electrodes of the flying capacitor C201 to ground. One of the two electrodes of the flying capacitor C200, the other of the two electrodes of the flying capacitor C201, and one of the two electrodes of the flying capacitor C203 are connected to node N1. The other of the two electrodes of the flying capacitor C200, one of the two electrodes of the flying capacitor C202, and the other of the two electrodes of the flying capacitor C203 are connected to node N2. The other of the two electrodes of the flying capacitor C202 is connected to node N3.

[0090] By repeating such a first phase and a second phase, the flying capacitors C200 to C203 can be charged and discharged in a complementary manner. For example, during one of the first and second phases, the flying capacitors C200 and C202 charge the smoothing capacitors C210, C211, and C212, and during the other of the first and second phases, the flying capacitors C201 and C203 charge the smoothing capacitors C210, C211, and C212. In other words, since the smoothing capacitors C210, C211, and C212 are always charged by one of the flying capacitors C200, C201, C202, and C203, even if a current flows at high speed from one of the nodes N1 to N3 to the power supply modulation circuits 31 and 32, charge is quickly replenished to one of the nodes N1 to N3, thereby suppressing fluctuations in the potential of the nodes N1 to N3.

[0091] By operating in this manner, the switched-capacitor circuit 20 can maintain approximately equal voltages across each of the smoothing capacitors C210, C211, and C212. Specifically, at three nodes N1 to N3 labeled V1 to V3, voltages V1 to V3 are maintained that satisfy the relationship (V3 - V2): (V2 - V1): (V1 - VG) = 1:1:1. VG represents ground potential. For example, if the regulated voltage supplied from the pre-regulator circuit 10 is 2 V, the switched-capacitor circuit 20 can generate multiple discrete voltages (V1, V2, and V3) of 1 V, 2 V, and 3 V.

[0092] It should be noted that (V3-V2):(V2-V1):(V1-VG) is not limited to 1:1:1, and can be designed to have any ratio (for example, 1:2:3, 3:2:1, etc.).

[0093] 3 is an example and is not limiting. Part of the switched capacitor circuit 20 may not be included in the tracker circuit 1. For example, the flying capacitors C200 to C203 and the smoothing capacitors C210 to C212 may not be included in the tracker circuit 1.

[0094] 3, an exemplary circuit configuration of the power supply modulation circuit 31 will be described. The power supply modulation circuit 31 includes input terminals T311 to T313, an output terminal T317, and switches S311 to S313.

[0095] Input terminals T311, T312, and T313 are terminals that respectively receive a plurality of discrete voltages V1, V2, and V3 generated by the switched capacitor circuit 20. The input terminals T311, T312, and T313 are connected to output terminals T201, T202, and T203 of the switched capacitor circuit 20, respectively, outside the power supply modulation circuit 31, and are connected to switches S311, S312, and S313, respectively, within the power supply modulation circuit 31.

[0096] Output terminal T317 is a terminal that selectively supplies at least one of a plurality of discrete voltages V1, V2, and V3 to power amplifier 71. Output terminal T317 is connected to output terminal 44 of tracker circuit 1 outside power supply modulation circuit 31, and is connected to switches S311, S312, and S313 within power supply modulation circuit 31.

[0097] The switch S311 is connected between the input terminal T311 and the output terminal T317. The switch S312 is connected between the input terminal T312 and the output terminal T317. The switch S313 is connected between the input terminal T313 and the output terminal T317.

[0098] These switches S311, S312, and S313 are switched open and closed (on and off) by a plurality of control signals CS31 from the digital control circuit 62. In this embodiment, the switches S311, S312, and S313 are controlled to be exclusively on. That is, only one of the switches S311, S312, and S313 is closed, and the remaining switches S311, S312, and S313 are all controlled to be open. This allows the power supply modulation circuit 31 to supply one voltage selected from a plurality of discrete voltages (V1, V2, and V3) to the power amplifier 71.

[0099] 3 is an example and is not limited to this. In particular, the switches S311, S312, and S313 may have any configuration and may be controlled in any manner as long as they can selectively connect at least one of the three input terminals T311, T312, and T313 to the output terminal T317. For example, two of the switches S311, S312, and S313 may be closed, and the remaining one of the switches S311, S312, and S313 may be opened.

[0100] 3, an exemplary circuit configuration of the power supply modulation circuit 32 will be described. The power supply modulation circuit 32 includes input terminals T321 to T323, an output terminal T327, and switches S321 to S323.

[0101] Input terminals T321, T322, and T323 are terminals that respectively receive a plurality of discrete voltages V1, V2, and V3 generated by the switched capacitor circuit 20. The input terminals T321, T322, and T323 are connected to output terminals T201, T202, and T203 of the switched capacitor circuit 20 outside the power supply modulation circuit 32, and are connected to switches S321, S322, and S323 within the power supply modulation circuit 32, respectively.

[0102] Output terminal T327 is a terminal that selectively supplies at least one of a plurality of discrete voltages V1, V2, and V3 to power amplifier 72. Output terminal T327 is connected to output terminal 45 of tracker circuit 1 outside power supply modulation circuit 32, and is connected to switches S321, S322, and S323 within power supply modulation circuit 32.

[0103] The switch S321 is connected between the input terminal T321 and the output terminal T327. The switch S322 is connected between the input terminal T322 and the output terminal T327. The switch S323 is connected between the input terminal T323 and the output terminal T327.

[0104] These switches S321, S322, and S323 are switched open and closed (on and off) by a plurality of control signals CS32 from the digital control circuit 62. In this embodiment, the switches S321, S322, and S323 are controlled to be exclusively on. That is, only one of the switches S321, S322, and S323 is closed, and the remaining switches S321, S322, and S323 are all controlled to be open. This allows the power supply modulation circuit 32 to supply one voltage selected from a plurality of discrete voltages (V1, V2, and V3) to the power amplifier 72.

[0105] 3 is an example and is not limiting. In particular, the switches S321, S322, and S323 may have any configuration and may be controlled in any manner as long as they can selectively connect at least one of the three input terminals T321, T322, and T323 to the output terminal T327. For example, two of the switches S321, S322, and S323 may be closed, and the remaining one of the switches S321, S322, and S323 may be opened.

[0106] [1.7 Circuit Configuration of Digital Control Circuit 62] An exemplary circuit configuration of the digital control circuit 62 will now be described with reference to Fig. 4. Fig. 4 is a circuit configuration diagram of the digital control circuit 62 according to this embodiment.

[0107] 4 is an exemplary circuit configuration, and digital control circuit 62 may be implemented using any of a wide variety of circuit implementations and circuit technologies, and therefore the description of digital control circuit 62 provided below should not be construed as limiting.

[0108] The digital control circuit 62 includes a conversion circuit 621 , delay circuits 622 and 623 , and DCL decoding circuits 624 and 625 .

[0109] The conversion circuit 621 is connected to the plurality of control input terminals 43 of the tracker circuit 1 outside the digital control circuit 62, and is connected to delay circuits 622 and 623 inside the digital control circuit 62. The conversion circuit 621 can convert the plurality of DCL signals (e.g., DCL1 and DCL2) acquired via the plurality of control input terminals 43 into multi-bit digital signals (e.g., 2-bit digital signals) and output them to the delay circuits 622 and 623.

[0110] The delay circuit 622 is an example of a first delay circuit, and is connected between the multiple control input terminals 43 of the tracker circuit 1 and the power supply modulation circuit 31. Specifically, the delay circuit 622 is connected between the conversion circuit 621 and the DCL decoding circuit 624. The delay circuit 622 can delay the multi-bit digital signal supplied from the conversion circuit 621 and output it to the DCL decoding circuit 624. In other words, the delay circuit 622 can control the delay amount of the multiple control signals CS31. The delay circuit 622 is configured, for example, by a flip-flop circuit or an RC circuit.

[0111] The delay circuit 623 is an example of a second delay circuit, and is connected between the multiple control input terminals 43 of the tracker circuit 1 and the power supply modulation circuit 32. Specifically, the delay circuit 623 is connected between the conversion circuit 621 and the DCL decoding circuit 625. The delay circuit 623 can delay the multi-bit digital signal supplied from the conversion circuit 621 and output it to the DCL decoding circuit 625. In other words, the delay circuit 623 can control the delay amount of the multiple control signals CS32. The delay circuit 623 is configured, for example, by a flip-flop circuit or an RC circuit.

[0112] The DCL decoding circuit 624 is an example of a first decoding circuit, and is connected between the delay circuit 622 and the power supply modulation circuit 31. The DCL decoding circuit 624 can decode the multi-bit digital signal received from the conversion circuit 621 via the delay circuit 622 to generate a plurality of control signals CS31. The plurality of control signals CS31 are supplied to the power supply modulation circuit 31.

[0113] The DCL decoding circuit 625 is an example of a second decoding circuit, and is connected between the delay circuit 623 and the power supply modulation circuit 32. The DCL decoding circuit 625 can decode the multi-bit digital signal received from the conversion circuit 621 via the delay circuit 623 to generate a plurality of control signals CS32. The plurality of control signals CS32 are supplied to the power supply modulation circuit 32.

[0114] 4 is merely an example and is not limiting. For example, the digital control circuit 62 may not include the conversion circuit 621 and / or the delay circuit 623. For example, the delay circuit 622 may be connected between the DCL decoding circuit 624 and the power supply modulation circuit 31, and the delay circuit 623 may be connected between the DCL decoding circuit 625 and the power supply modulation circuit 32.

[0115] [1.8 Summary] As described above, the tracker circuit 1 according to this embodiment includes a plurality of control input terminals 43 that respectively receive a plurality of DCL signals, at least one switch included in a switched capacitor circuit 20 that is configured to generate a plurality of discrete voltages from an input voltage, a power supply modulation circuit 31 that is configured to selectively output at least one of the plurality of discrete voltages to a power amplifier 71 based on the plurality of DCL signals, a power supply modulation circuit 32 that is configured to selectively output at least one of the plurality of discrete voltages to a power amplifier 72 based on the plurality of DCL signals, and a delay circuit 622 connected between the plurality of control input terminals 43 and the power supply modulation circuit 31.

[0116] According to this configuration, a delay circuit 622 is connected between a plurality of control input terminals 43 that respectively receive a plurality of DCL signals and a power supply modulation circuit 31 that supplies a voltage to a power amplifier 71. Therefore, when the voltage supplied to a power amplifier 72 has a larger delay with respect to a high-frequency signal than the voltage supplied to the power amplifier 71, the delay circuit 622 delays a plurality of control signals CS31 that control the power supply modulation circuit 31 that supplies a voltage to the power amplifier 71, thereby equalizing the delays of the power supply voltages in the power amplifiers 71 and 72. As a result, the ability of the power supply voltage to follow the envelope of the high-frequency signal can be improved in both the power amplifiers 71 and 72, thereby improving power efficiency in the D-ET mode. In particular, because the delay circuit 622 is inserted in the control signal line through which the control signal is transmitted, rather than in the power supply voltage line that supplies voltage from the power supply modulation circuit 31 to the power amplifier 71, loss in the power supply voltage line can be suppressed, resulting in a significant improvement in power efficiency.

[0117] Furthermore, for example, in the tracker circuit 1 according to this embodiment, the delay circuit 622 may be a flip-flop circuit.

[0118] This allows the delay circuit 622 to be realized with a simple circuit configuration.

[0119] Furthermore, for example, in the tracker circuit 1 according to this embodiment, the delay circuit 622 may be an RC circuit.

[0120] This allows the delay circuit 622 to be realized with a simple circuit configuration.

[0121] For example, the tracker circuit 1 according to this embodiment may further include a digital control circuit 62 configured to generate a plurality of control signals CS31 for controlling the power supply modulation circuit 31 and a plurality of control signals CS32 for controlling the power supply modulation circuit 32 based on a plurality of DCL signals, and the delay circuit 622 may be included in the digital control circuit 62.

[0122] According to this, the digital control circuit 62 including the delay circuit 622 is included in the same tracker circuit 1 as the power supply modulation circuits 31 and 32. Therefore, it is possible to more accurately control the switching timing of the power supply modulation circuits 31 and 32. As a result, it is possible to improve the ability of the power supply voltage to follow the envelope of the high-frequency signal in both power amplifiers 71 and 72, and it is possible to further improve power efficiency in D-ET mode.

[0123] For example, in the tracker circuit 1 according to this embodiment, the digital control circuit 62 may further include a conversion circuit 621 configured to convert a plurality of DCL signals into multi-bit digital signals, a DCL decoding circuit 624 configured to generate a plurality of control signals CS31 based on the multi-bit digital signals, and a DCL decoding circuit 625 configured to generate a plurality of control signals CS32 based on the multi-bit digital signals, and the delay circuit 622 may be connected between the conversion circuit 621 and the DCL decoding circuit 624.

[0124] According to this, the delay circuit 622 is connected between the conversion circuit 621 and the DCL decoding circuit 624. Therefore, the delay circuit 622 only needs to be configured to delay one multi-bit digital signal, and the circuit configuration of the delay circuit 622 can be simplified compared to when delaying multiple control signals CS31.

[0125] Furthermore, for example, the tracker circuit 1 according to this embodiment may further include a delay circuit 623 connected between the plurality of control input terminals 43 and the power supply modulation circuit 32 .

[0126] According to this, delay circuit 623 is connected between a plurality of control input terminals 43 that respectively receive a plurality of DCL signals and power supply modulation circuit 32 that supplies voltage to power amplifier 72. Therefore, power efficiency in D-ET mode can be improved not only when the voltage supplied to power amplifier 72 has a larger delay with respect to the high-frequency signal than the voltage supplied to power amplifier 71, but also when the voltage supplied to power amplifier 71 has a larger delay with respect to the high-frequency signal than the voltage supplied to power amplifier 72.

[0127] Furthermore, for example, in the tracker circuit 1 according to this embodiment, the delay circuit 623 may be a flip-flop circuit.

[0128] This allows the delay circuit 623 to be realized with a simple circuit configuration.

[0129] Furthermore, for example, in the tracker circuit 1 according to this embodiment, the delay circuit 623 may be an RC circuit.

[0130] This allows the delay circuit 623 to be realized with a simple circuit configuration.

[0131] For example, the tracker circuit 1 according to this embodiment may further include a digital control circuit 62 configured to generate a plurality of control signals CS31 for controlling the power supply modulation circuit 31 and a plurality of control signals CS32 for controlling the power supply modulation circuit 32 based on a plurality of DCL signals, and the delay circuits 622 and 623 may be included in the digital control circuit 62.

[0132] According to this, the digital control circuit 62 including the delay circuits 622 and 623 is included in the same tracker circuit 1 as the power supply modulation circuits 31 and 32. Therefore, it is possible to more accurately control the switching timing of the power supply modulation circuits 31 and 32. As a result, it is possible to improve the ability of the power supply voltage to follow the envelope of the high-frequency signal in both power amplifiers 71 and 72, and it is possible to further improve power efficiency in D-ET mode.

[0133] For example, in the tracker circuit 1 according to this embodiment, the digital control circuit 62 further includes a conversion circuit 621 configured to convert a plurality of DCL signals into multi-bit digital signals, a DCL decoding circuit 624 configured to generate a plurality of control signals CS31 based on the multi-bit digital signals, and a DCL decoding circuit 625 configured to generate a plurality of control signals CS32 based on the multi-bit digital signals, and the delay circuit 622 may be connected between the conversion circuit 621 and the DCL decoding circuit 624, and the delay circuit 623 may be connected between the conversion circuit 621 and the DCL decoding circuit 625.

[0134] According to this, delay circuit 622 is connected between conversion circuit 621 and DCL decoding circuit 624, and delay circuit 623 is connected between conversion circuit 621 and DCL decoding circuit 625. Therefore, each of delay circuits 622 and 623 only needs to be configured to delay one multi-bit digital signal, and the circuit configuration of each of delay circuits 622 and 623 can be simplified compared to when multiple control signals CS31 and CS32 are delayed.

[0135] (Modification of First Embodiment) Next, a modification of the first embodiment will be described. This modification differs from the first embodiment mainly in that the power supply modulation circuit 32 is connected to a plurality of power amplifiers. This modification will be specifically described below with reference to FIG. 5, focusing on the differences from the first embodiment.

[0136] [1.9 Circuit Configuration] Fig. 5 is a circuit configuration diagram of a communication device 3A according to this modification. Note that Fig. 5 is an exemplary circuit configuration, and the communication device 3A can be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the communication device 3A provided below should not be interpreted as limiting.

[0137] The communication device 3A can be used to provide a wireless connection, similar to the first embodiment. As shown in Fig. 5, the communication device 3A includes a tracker circuit 1A and a high-frequency circuit 2A.

[0138] In the D-ET mode, the tracker circuit 1A can simultaneously supply the power supply voltage to the power amplifiers 71, 72, and 73. Note that the tracker circuit 1A may also supply the power supply voltage to the power amplifiers 71, 72, and 73 in the APT mode. The tracker circuit 1A can be implemented on a single semiconductor integrated circuit, which is sometimes called a PMIC.

[0139] Specifically, the tracker circuit 1A includes a pre-regulator circuit 10, a switched capacitor circuit 20, power supply modulation circuits 31 and 32, an input terminal 41, a plurality of control input terminals 42 and 43, output terminals 44, 45 and 46, and digital control circuits 61 and 62.

[0140] The output terminal 46 is an external connection terminal that supplies a power supply voltage to the power amplifier 73. The output terminal 46 is connected to a power supply voltage terminal 83 of the high frequency circuit 2A outside the tracker circuit 1A, and is connected to a power supply modulation circuit 32 inside the tracker circuit 1A.

[0141] The high-frequency circuit 2A can upconvert an IF signal or a baseband signal received from outside the high-frequency circuit 2A to generate two high-frequency signals of a predetermined band. Furthermore, the high-frequency circuit 2A can amplify the two generated high-frequency signals and output them to one or more antennas. The high-frequency circuit 2A can be implemented on a single semiconductor integrated circuit, which is sometimes called an RFIC.

[0142] Specifically, the high frequency circuit 2A includes power amplifiers 71, 72, and 73, and power supply voltage terminals 81, 82, and 83.

[0143] The power supply voltage terminal 83 is an external connection terminal that receives the power supply voltage from the tracker circuit 1A to be used in the power amplifier 73. The power supply voltage terminal 83 is connected to the output terminal 46 of the tracker circuit 1A outside the high-frequency circuit 2A, and is connected to the power amplifier 73 inside the high-frequency circuit 2A.

[0144] The power amplifier 73 can amplify high frequency signals in a predetermined band using the power supply voltage supplied from the power supply modulation circuit 32 via the output terminal 46 and the power supply voltage terminal 83 .

[0145] In FIG. 5, the power supply voltage is supplied from the power supply modulation circuit 32 to a plurality of power amplifiers (power amplifiers 72 and 73), but the power supply voltage may be supplied from the power supply modulation circuit 31 to a plurality of power amplifiers.

[0146] [1.10 Summary] As described above, in the tracker circuit 1A according to this embodiment, the power supply modulation circuit 32 is configured to selectively output at least one of a plurality of discrete voltages to the power amplifiers 72 and 73 based on a plurality of DCL signals.

[0147] This allows the tracker circuit 1A to supply voltage to more power amplifiers 71, 72, and 73 than in the first embodiment.

[0148] (Embodiment 2) Next, embodiment 2 will be described. In this embodiment, the main difference is that the power supply modulation circuits 31 and 32 and the digital control circuit 62 are included in the high-frequency circuit rather than the tracker circuit. Below, this embodiment will be specifically described with reference to FIG. 6, focusing on the differences from embodiment 1.

[0149] [2.1 Circuit Configuration] Fig. 6 is a circuit configuration diagram of a communication device 3B according to this embodiment. Note that Fig. 6 is an exemplary circuit configuration, and the communication device 3B may be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the communication device 3B provided below should not be interpreted as limiting.

[0150] The communication device 3B can be used to provide a wireless connection, similar to the first embodiment. As shown in Fig. 6, the communication device 3B includes a tracker circuit 1B and a high-frequency circuit 2B.

[0151] The tracker circuit 1B can simultaneously supply the power supply voltage to the power amplifiers 71 and 72 in the D-ET mode. Note that the tracker circuit 1B may also supply the power supply voltage to the power amplifiers 71 and 72 in the APT mode. The tracker circuit 1B can be implemented in a single semiconductor integrated circuit, which is sometimes called a PMIC.

[0152] Specifically, the tracker circuit 1B includes a pre-regulator circuit 10, a switched capacitor circuit 20, an input terminal 41, a plurality of control input terminals 42, a plurality of output terminals 47, and a digital control circuit 61.

[0153] The output terminals 47 are external connection terminals that respectively supply discrete voltages to the high-frequency circuit 2 B. The output terminals 47 are connected to discrete voltage terminals 84 of the high-frequency circuit 2 B outside the tracker circuit 1 B, and are connected to the switched-capacitor circuit 20 inside the tracker circuit 1 B.

[0154] The high-frequency circuit 2B is an example of a high-frequency circuit, and includes power supply modulation circuits 31 and 32, a plurality of control input terminals 43 (an example of second external connection terminals), a digital control circuit 62, power amplifiers 71 and 72, and a plurality of discrete voltage terminals 84. The high-frequency circuit 2B can be implemented in a single semiconductor integrated circuit, which may be called an RFIC.

[0155] The plurality of discrete voltage terminals 84 are an example of a plurality of first external connection terminals, and are a plurality of external connection terminals that respectively receive a plurality of discrete voltages from the tracker circuit 1 B. The plurality of discrete voltage terminals 84 are connected to a plurality of output terminals 47 of the tracker circuit 1 B outside the high-frequency circuit 2 B, and are connected to the power supply modulation circuits 31 and 32 inside the high-frequency circuit 2 B.

[0156] [2.2 Summary] As described above, the high-frequency circuit 2B according to this embodiment includes a plurality of discrete voltage terminals 84 that respectively receive a plurality of discrete voltages, a plurality of control input terminals 43 that respectively receive a plurality of DCL signals, power amplifiers 71 and 72, a power supply modulation circuit 31 configured to selectively output at least one of the plurality of discrete voltages to power amplifier 71 based on the plurality of DCL signals, a power supply modulation circuit 32 configured to selectively output at least one of the plurality of discrete voltages to power amplifier 72 based on the plurality of DCL signals, and a delay circuit 622 connected between the plurality of control input terminals 43 and power supply modulation circuit 31.

[0157] According to this configuration, a delay circuit 622 is connected between a plurality of control input terminals 43 that respectively receive a plurality of DCL signals and a power supply modulation circuit 31 that supplies a voltage to a power amplifier 71. Therefore, when the voltage supplied to a power amplifier 72 has a larger delay with respect to a high-frequency signal than the voltage supplied to the power amplifier 71, the delay circuit 622 delays a plurality of control signals CS31 that control the power supply modulation circuit 31 that supplies a voltage to the power amplifier 71, thereby equalizing the delays of the power supply voltages in the power amplifiers 71 and 72. As a result, the ability of the power supply voltage to follow the envelope of the high-frequency signal can be improved in both the power amplifiers 71 and 72, thereby improving power efficiency in the D-ET mode. In particular, because the delay circuit 622 is inserted in the control signal line through which the control signal is transmitted, rather than in the power supply voltage line that supplies voltage from the power supply modulation circuit 31 to the power amplifier 71, loss in the power supply voltage line can be suppressed, resulting in a significant improvement in power efficiency.

[0158] Furthermore, for example, in the high-frequency circuit 2B according to this embodiment, the delay circuit 622 may be a flip-flop circuit.

[0159] This allows the delay circuit 622 to be realized with a simple circuit configuration.

[0160] Furthermore, for example, in the high-frequency circuit 2B according to this embodiment, the delay circuit 622 may be an RC circuit.

[0161] This allows the delay circuit 622 to be realized with a simple circuit configuration.

[0162] For example, the high-frequency circuit 2B according to this embodiment may further include a digital control circuit 62 configured to generate a plurality of control signals CS31 for controlling the power supply modulation circuit 31 and a plurality of control signals CS32 for controlling the power supply modulation circuit 32 based on a plurality of DCL signals, and the delay circuit 622 may be included in the digital control circuit 62.

[0163] According to this, the digital control circuit 62 including the delay circuit 622 is included in the same high-frequency circuit 2B as the power supply modulation circuits 31 and 32. This makes it possible to more accurately control the switching timing of the power supply modulation circuits 31 and 32. As a result, it is possible to improve the ability of the power supply voltage to follow the envelope of the high-frequency signal in both power amplifiers 71 and 72, thereby enabling further improvement in power efficiency in D-ET mode.

[0164] Also, for example, in the high-frequency circuit 2B according to this embodiment, the digital control circuit 62 may further include a conversion circuit 621 configured to convert a plurality of DCL signals into multi-bit digital signals, a DCL decoding circuit 624 configured to generate a plurality of control signals CS31 based on the multi-bit digital signals, and a DCL decoding circuit 625 configured to generate a plurality of control signals CS32 based on the multi-bit digital signals, and the delay circuit 622 may be connected between the conversion circuit 621 and the DCL decoding circuit 624.

[0165] According to this, the delay circuit 622 is connected between the conversion circuit 621 and the DCL decoding circuit 624. Therefore, the delay circuit 622 only needs to be configured to delay one multi-bit digital signal, and the circuit configuration of the delay circuit 622 can be simplified compared to when delaying multiple control signals CS31.

[0166] Furthermore, for example, the high-frequency circuit 2B according to this embodiment may further include a delay circuit 623 connected between the plurality of control input terminals 43 and the power supply modulation circuit 32.

[0167] According to this, delay circuit 623 is connected between a plurality of control input terminals 43 that respectively receive a plurality of DCL signals and power supply modulation circuit 32 that supplies voltage to power amplifier 72. Therefore, power efficiency in D-ET mode can be improved not only when the voltage supplied to power amplifier 72 has a larger delay with respect to the high-frequency signal than the voltage supplied to power amplifier 71, but also when the voltage supplied to power amplifier 71 has a larger delay with respect to the high-frequency signal than the voltage supplied to power amplifier 72.

[0168] Furthermore, for example, in the high-frequency circuit 2B according to this embodiment, the delay circuit 623 may be a flip-flop circuit.

[0169] This allows the delay circuit 623 to be realized with a simple circuit configuration.

[0170] Furthermore, for example, in the high-frequency circuit 2B according to this embodiment, the delay circuit 623 may be an RC circuit.

[0171] This allows the delay circuit 623 to be realized with a simple circuit configuration.

[0172] For example, the high-frequency circuit 2B according to this embodiment may further include a digital control circuit 62 configured to generate a plurality of control signals CS31 for controlling the power supply modulation circuit 31 and a plurality of control signals CS32 for controlling the power supply modulation circuit 32 based on a plurality of DCL signals, and the delay circuits 622 and 623 may be included in the digital control circuit 62.

[0173] According to this, the digital control circuit 62 including the delay circuits 622 and 623 is included in the same high-frequency circuit 2B as the power supply modulation circuits 31 and 32. Therefore, it is possible to more accurately control the switching timing of the power supply modulation circuits 31 and 32. As a result, it is possible to improve the ability of the power supply voltage to follow the envelope of the high-frequency signal in both power amplifiers 71 and 72, and it is possible to further improve power efficiency in D-ET mode.

[0174] Also, for example, in the high-frequency circuit 2B according to this embodiment, the digital control circuit 62 further includes a conversion circuit 621 configured to convert a plurality of DCL signals into a multi-bit digital signal, a DCL decoding circuit 624 configured to generate a plurality of control signals CS31 based on the multi-bit digital signal, and a DCL decoding circuit 625 configured to generate a plurality of control signals CS32 based on the multi-bit digital signal, and the delay circuit 622 may be connected between the conversion circuit 621 and the DCL decoding circuit 624, and the delay circuit 623 may be connected between the conversion circuit 621 and the DCL decoding circuit 625.

[0175] According to this, delay circuit 622 is connected between conversion circuit 621 and DCL decoding circuit 624, and delay circuit 623 is connected between conversion circuit 621 and DCL decoding circuit 625. Therefore, each of delay circuits 622 and 623 only needs to be configured to delay one multi-bit digital signal, and the circuit configuration of each of delay circuits 622 and 623 can be simplified compared to when multiple control signals CS31 and CS32 are delayed.

[0176] Third Embodiment Next, a third embodiment will be described. This embodiment differs from the first embodiment in that the digital control circuit 62 is included in the high-frequency circuit rather than the tracker circuit. The following describes this embodiment in detail, focusing on the differences from the first embodiment, with reference to FIG. 7 .

[0177] [3.1 Circuit Configuration] Fig. 7 is a circuit configuration diagram of a communication device 3C according to this embodiment. Note that Fig. 7 is an exemplary circuit configuration, and the communication device 3C can be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the communication device 3C provided below should not be interpreted as limiting.

[0178] The communication device 3C can be used to provide a wireless connection, similar to the first embodiment. As shown in Fig. 7, the communication device 3C includes a tracker circuit 1C and a high-frequency circuit 2C.

[0179] The tracker circuit 1C can simultaneously supply the power supply voltage to the power amplifiers 71 and 72 in the D-ET mode. Note that the tracker circuit 1C may also supply the power supply voltage to the power amplifiers 71 and 72 in the APT mode. The tracker circuit 1C can be implemented in a single semiconductor integrated circuit, which is sometimes called a PMIC.

[0180] Specifically, the tracker circuit 1C includes a pre-regulator circuit 10, a switched capacitor circuit 20, power supply modulation circuits 31 and 32, an input terminal 41, a plurality of control input terminals 42, 48 and 49, output terminals 44 and 45, and a digital control circuit 61.

[0181] The plurality of control input terminals 48 are a plurality of external connection terminals that respectively receive a plurality of control signals CS31 from the high frequency circuit 2C to control the power supply modulation circuit 31. The plurality of control input terminals 48 are connected to a plurality of control output terminals 85 of the high frequency circuit 2C outside the tracker circuit 1C, and are connected to the power supply modulation circuit 31 inside the tracker circuit 1C.

[0182] The plurality of control input terminals 49 are a plurality of external connection terminals that respectively receive a plurality of control signals CS32 from the high frequency circuit 2C to control the power supply modulation circuit 32. The plurality of control input terminals 49 are connected to a plurality of control output terminals 86 of the high frequency circuit 2C outside the tracker circuit 1C, and are connected to the power supply modulation circuit 32 inside the tracker circuit 1C.

[0183] The radio frequency circuit 2C can upconvert an IF signal or a baseband signal received from outside the radio frequency circuit 2C to generate two radio frequency signals of a predetermined band. Furthermore, the radio frequency circuit 2C can amplify the two generated radio frequency signals and output them to one or more antennas. The radio frequency circuit 2C can be implemented on a single semiconductor integrated circuit, which is sometimes called an RFIC.

[0184] Specifically, the high frequency circuit 2C includes a plurality of control input terminals 43, a digital control circuit 62, power amplifiers 71 and 72, power supply voltage terminals 81 and 82, and a plurality of control output terminals 85 and 86.

[0185] The control output terminals 85 are external connection terminals that respectively supply the tracker circuit 1C with the control signals CS31. The control output terminals 85 are connected to the control input terminals 48 of the tracker circuit 1C outside the high-frequency circuit 2C, and are connected to the digital control circuit 62 inside the high-frequency circuit 2C.

[0186] The control output terminals 86 are external connection terminals that respectively supply the tracker circuit 1 C with the control signals CS 32. The control output terminals 86 are connected to the control input terminals 49 of the tracker circuit 1 C outside the high frequency circuit 2 C, and are connected to the digital control circuit 62 inside the high frequency circuit 2 C.

[0187] [3.2 Summary] As described above, the high-frequency circuit 2C according to this embodiment includes a plurality of control input terminals 43 that respectively receive a plurality of DCL signals, power amplifiers 71 and 72, a plurality of control output terminals 85 that supply a plurality of control signals CS31 to a power supply modulation circuit 31 that is configured to selectively output at least one of a plurality of discrete voltages to power amplifier 71 based on the plurality of DCL signals, a plurality of control output terminals 86 that supply a plurality of control signals CS32 to a power supply modulation circuit 32 that is configured to selectively output at least one of a plurality of discrete voltages to power amplifier 72 based on the plurality of DCL signals, and a delay circuit 622 connected between the plurality of control input terminals 43 and the plurality of control output terminals 85.

[0188] According to this, even if the power supply modulation circuits 31 and 32 are not included in the high frequency circuit 2C, it is possible to achieve the same effect as that of the high frequency circuit 2B according to the second embodiment.

[0189] (Other Embodiments) The tracker circuit and high-frequency circuit according to the present invention have been described above based on the embodiments, but the tracker circuit and high-frequency circuit according to the present invention are not limited to the above embodiments. The present invention also includes other embodiments realized by combining any of the components in the above embodiments, modifications obtained by applying various modifications to the above embodiments that would occur to those skilled in the art without departing from the spirit of the present invention, and various devices incorporating the above tracker circuit and / or the above high-frequency circuit.

[0190] For example, in the circuit configurations of the various circuits according to the above embodiments, other circuit elements and wiring may be inserted between the paths connecting the circuit elements and signal paths disclosed in the drawings. For example, an inductor and / or a capacitor may be inserted between the tracker circuit and the power amplifier.

[0191] Furthermore, for example, the modified example of the first embodiment may be applied to the second and third embodiments.

[0192] In the above embodiments, the number of discrete voltages that the switched capacitor circuit 20 can generate is three, but this is not limiting. For example, the switched capacitor circuit 20 may generate two, four, five, six, or seven or more discrete voltages. In this case, the number of switches included in the power supply modulation circuit may be increased or decreased depending on the number of discrete voltages.

[0193] The features of the tracker circuit and the high-frequency circuit explained based on the above embodiments will be described below.

[0194] <1> A tracker circuit comprising: a plurality of external connection terminals each receiving a plurality of digital control level signals; at least one switch included in a switched capacitor circuit configured to generate a plurality of discrete voltages from an input voltage; a first power supply modulation circuit configured to selectively output at least one of the plurality of discrete voltages to a first power amplifier based on the plurality of digital control level signals; a second power supply modulation circuit configured to selectively output the at least one of the plurality of discrete voltages to a second power amplifier based on the plurality of digital control level signals; and a first delay circuit connected between the plurality of external connection terminals and the first power supply modulation circuit.

[0195] <2> The tracker circuit according to <1>, wherein the first delay circuit is a flip-flop circuit.

[0196] <3> The tracker circuit according to <1>, wherein the first delay circuit is an RC circuit.

[0197] <4> The tracker circuit according to any one of <1> to <3>, further comprising a digital control circuit configured to generate a plurality of first control signals for controlling the first power supply modulation circuit and a plurality of second control signals for controlling the second power supply modulation circuit based on the plurality of digital control level signals, and the first delay circuit is included in the digital control circuit.

[0198] <5> The tracker circuit described in <4>, wherein the digital control circuit further includes: a conversion circuit configured to convert the plurality of digital control level signals into multi-bit digital signals; a first decoding circuit configured to generate the plurality of first control signals based on the multi-bit digital signals; and a second decoding circuit configured to generate the plurality of second control signals based on the multi-bit digital signals, and the first delay circuit is connected between the conversion circuit and the first decoding circuit.

[0199] <6> The tracker circuit according to any one of <1> to <3>, further comprising a second delay circuit connected between the plurality of external connection terminals and the second power supply modulation circuit.

[0200] <7> The tracker circuit according to <6>, wherein the second delay circuit is a flip-flop circuit.

[0201] <8> The tracker circuit according to <6>, wherein the second delay circuit is an RC circuit.

[0202] <9> The tracker circuit according to any one of <6> to <8>, further comprising a digital control circuit configured to generate a plurality of first control signals for controlling the first power supply modulation circuit and a plurality of second control signals for controlling the second power supply modulation circuit based on the plurality of digital control level signals, and the first delay circuit and the second delay circuit are included in the digital control circuit.

[0203] <10> The tracker circuit described in <9>, wherein the digital control circuit further includes: a conversion circuit configured to convert the plurality of digital control level signals into multi-bit digital signals; a first decoding circuit configured to generate the plurality of first control signals based on the multi-bit digital signals; and a second decoding circuit configured to generate the plurality of second control signals based on the multi-bit digital signals, wherein the first delay circuit is connected between the conversion circuit and the first decoding circuit, and the second delay circuit is connected between the conversion circuit and the second decoding circuit.

[0204] <11> A radio frequency circuit comprising: a plurality of first external connection terminals each receiving a plurality of discrete voltages; a plurality of second external connection terminals each receiving a plurality of digital control level signals; a first power amplifier and a second power amplifier; a first power supply modulation circuit configured to selectively output at least one of the plurality of discrete voltages to the first power amplifier based on the plurality of digital control level signals; a second power supply modulation circuit configured to selectively output the at least one of the plurality of discrete voltages to the second power amplifier based on the plurality of digital control level signals; and a first delay circuit connected between the plurality of second external connection terminals and the first power supply modulation circuit.

[0205] <12> The high-frequency circuit according to <11>, wherein the first delay circuit is a flip-flop circuit.

[0206] <13> The high-frequency circuit according to <11>, wherein the first delay circuit is an RC circuit.

[0207] <14> The high-frequency circuit according to any one of <11> to <13>, further comprising a digital control circuit configured to generate a plurality of first control signals for controlling the first power supply modulation circuit and a plurality of second control signals for controlling the second power supply modulation circuit based on the plurality of digital control level signals, and the first delay circuit is included in the digital control circuit.

[0208] <15> The high-frequency circuit according to <14>, wherein the digital control circuit further includes: a conversion circuit configured to convert the plurality of digital control level signals into multi-bit digital signals; a first decoding circuit configured to generate the plurality of first control signals based on the multi-bit digital signals; and a second decoding circuit configured to generate the plurality of second control signals based on the multi-bit digital signals, and the first delay circuit is connected between the conversion circuit and the first decoding circuit.

[0209] <16> The high-frequency circuit according to any one of <11> to <13>, further comprising a second delay circuit connected between the plurality of second external connection terminals and the second power supply modulation circuit.

[0210] <17> The high-frequency circuit according to <16>, wherein the second delay circuit is a flip-flop circuit.

[0211] <18> The high-frequency circuit according to <16>, wherein the second delay circuit is an RC circuit.

[0212] <19> The high-frequency circuit according to any one of <16> to <18>, further comprising a digital control circuit configured to generate a plurality of first control signals for controlling the first power supply modulation circuit and a plurality of second control signals for controlling the second power supply modulation circuit based on the plurality of digital control level signals, and the first delay circuit and the second delay circuit are included in the digital control circuit.

[0213] <20> The high-frequency circuit according to <19>, wherein the digital control circuit further includes: a conversion circuit configured to convert the plurality of digital control level signals into multi-bit digital signals; a first decoding circuit configured to generate the plurality of first control signals based on the multi-bit digital signals; and a second decoding circuit configured to generate the plurality of second control signals based on the multi-bit digital signals, wherein the first delay circuit is connected between the conversion circuit and the first decoding circuit, and the second delay circuit is connected between the conversion circuit and the second decoding circuit.

[0214] The present invention can be widely used in communication devices such as mobile phones as a tracker circuit that supplies a power supply voltage to a power amplifier and / or a high frequency circuit that amplifies a high frequency signal.

[0215] 1, 1A, 1B, 1C Tracker circuit 2, 2A, 2B, 2C High frequency circuit 3, 3A, 3B, 3C Communication device 10 Pre-regulator circuit 20 Switched capacitor circuit 31, 32 Power supply modulation circuit 41, T101, T200, T311, T312, T313, T321, T322, T323 Input terminal 42, 43, 48, 49 Control input terminal 44, 45, 46, 47, T102, T201, T202, T203, T317, T327 Output terminal 61, 62 Digital control circuit 71, 72, 73 Power amplifier 621 Conversion circuit 622, 623 Delay circuit 624, 625 DCL decoding circuit C101 Capacitor C200, C201, C202, C203 Flying capacitors C210, C211, C212 Smoothing capacitors CS10, CS20, CS31, CS32 Control signal L101 Power inductor S101, S102, S103, S104, S200, S201, S202, S203, S204, S205, S206, S207, S208, S209, S210, S211, S311, S312, S313, S321, S322, S323 Switches

Claims

1. A tracker circuit comprising: a plurality of external connection terminals each receiving a plurality of digital control level signals; at least one switch included in a switched capacitor circuit configured to generate a plurality of discrete voltages from an input voltage; a first power supply modulation circuit configured to selectively output at least one of the plurality of discrete voltages to a first power amplifier based on the plurality of digital control level signals; a second power supply modulation circuit configured to selectively output the at least one of the plurality of discrete voltages to a second power amplifier based on the plurality of digital control level signals; and a first delay circuit connected between the plurality of external connection terminals and the first power supply modulation circuit.

2. The tracker circuit of claim 1, wherein the first delay circuit is a flip-flop circuit.

3. The tracker circuit of claim 1, wherein the first delay circuit is an RC circuit.

4. The tracker circuit according to any one of claims 1 to 3, further comprising a digital control circuit configured to generate a plurality of first control signals for controlling the first power supply modulation circuit and a plurality of second control signals for controlling the second power supply modulation circuit based on the plurality of digital control level signals, and the first delay circuit is included in the digital control circuit.

5. The tracker circuit of claim 4, wherein the digital control circuit further includes: a conversion circuit configured to convert the plurality of digital control level signals into a multi-bit digital signal; a first decoding circuit configured to generate the plurality of first control signals based on the multi-bit digital signal; and a second decoding circuit configured to generate the plurality of second control signals based on the multi-bit digital signal, and the first delay circuit is connected between the conversion circuit and the first decoding circuit.

6. A tracker circuit according to any one of claims 1 to 3, further comprising a second delay circuit connected between the plurality of external connection terminals and the second power supply modulation circuit.

7. The tracker circuit of claim 6, wherein the second delay circuit is a flip-flop circuit.

8. The tracker circuit of claim 6, wherein the second delay circuit is an RC circuit.

9. The tracker circuit according to any one of claims 6 to 8, further comprising a digital control circuit configured to generate a plurality of first control signals for controlling the first power supply modulation circuit and a plurality of second control signals for controlling the second power supply modulation circuit based on the plurality of digital control level signals, and the first delay circuit and the second delay circuit are included in the digital control circuit.

10. The tracker circuit of claim 9, wherein the digital control circuit further includes: a conversion circuit configured to convert the plurality of digital control level signals into a multi-bit digital signal; a first decoding circuit configured to generate the plurality of first control signals based on the multi-bit digital signal; and a second decoding circuit configured to generate the plurality of second control signals based on the multi-bit digital signal; wherein the first delay circuit is connected between the conversion circuit and the first decoding circuit; and the second delay circuit is connected between the conversion circuit and the second decoding circuit.

11. A radio frequency circuit comprising: a plurality of first external connection terminals each receiving a plurality of discrete voltages; a plurality of second external connection terminals each receiving a plurality of digital control level signals; a first power amplifier and a second power amplifier; a first power supply modulation circuit configured to selectively output at least one of the plurality of discrete voltages to the first power amplifier based on the plurality of digital control level signals; a second power supply modulation circuit configured to selectively output the at least one of the plurality of discrete voltages to the second power amplifier based on the plurality of digital control level signals; and a first delay circuit connected between the plurality of second external connection terminals and the first power supply modulation circuit.

12. The high frequency circuit according to claim 11, wherein the first delay circuit is a flip-flop circuit.

13. The high frequency circuit according to claim 11, wherein the first delay circuit is an RC circuit.

14. The radio frequency circuit according to any one of claims 11 to 13, further comprising a digital control circuit configured to generate a plurality of first control signals for controlling the first power supply modulation circuit and a plurality of second control signals for controlling the second power supply modulation circuit based on the plurality of digital control level signals, and the first delay circuit is included in the digital control circuit.

15. The high frequency circuit of claim 14, wherein the digital control circuit further includes: a conversion circuit configured to convert the plurality of digital control level signals into a multi-bit digital signal; a first decoding circuit configured to generate the plurality of first control signals based on the multi-bit digital signal; and a second decoding circuit configured to generate the plurality of second control signals based on the multi-bit digital signal; and the first delay circuit is connected between the conversion circuit and the first decoding circuit.

16. The high-frequency circuit according to any one of claims 11 to 13, further comprising a second delay circuit connected between the plurality of second external connection terminals and the second power supply modulation circuit.

17. The high frequency circuit according to claim 16, wherein the second delay circuit is a flip-flop circuit.

18. The high frequency circuit according to claim 16, wherein the second delay circuit is an RC circuit.

19. The radio frequency circuit according to any one of claims 16 to 18, further comprising a digital control circuit configured to generate a plurality of first control signals for controlling the first power supply modulation circuit and a plurality of second control signals for controlling the second power supply modulation circuit based on the plurality of digital control level signals, and the first delay circuit and the second delay circuit are included in the digital control circuit.

20. The high frequency circuit of claim 19, wherein the digital control circuit further includes: a conversion circuit configured to convert the plurality of digital control level signals into a multi-bit digital signal; a first decoding circuit configured to generate the plurality of first control signals based on the multi-bit digital signal; and a second decoding circuit configured to generate the plurality of second control signals based on the multi-bit digital signal, wherein the first delay circuit is connected between the conversion circuit and the first decoding circuit, and the second delay circuit is connected between the conversion circuit and the second decoding circuit.

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