Power supply circuit and control method

Abstract

A power supply circuit (4) is provided with: a control terminal (44) for receiving a digital control signal (DS1); a tracker circuit (1) configured to supply an output voltage (Vout1) to a power amplifier (7) operating in a tracking mode; and a regulator circuit (2) configured to supply an output voltage (Vout2) to a load (for example, a power amplifier (8)). The regulator circuit (2) is provided with: an LDO circuit (40); and a resistor (R40) and a switch (S40) that are connected in series between an output terminal (T40b) of the LDO circuit (40) and the ground.

Description

Power supply circuit and control method

[0001] The present invention relates to a power supply circuit and a control method.

[0002] In recent years, efforts have been made to improve power efficiency by applying envelope tracking (ET) to power amplifier circuits. Patent Document 1 discloses a digital envelope tracking (D-ET) mode that selectively supplies a plurality of discrete voltages to a power amplifier based on an envelope signal.

[0003] U.S. Patent No. 9,755,672

[0004] A power supply circuit capable of supplying a variable voltage to a power amplifier operating in tracking mode may include a regulator circuit when it is necessary to supply a constant voltage to a load. In such cases, load fluctuations can cause the voltage supplied to the load from the regulator circuit to fluctuate. In particular, a temporary voltage drop can occur when the output current to the load increases suddenly.

[0005] Therefore, the present invention provides a power supply circuit and a control method that can suppress a voltage drop when the output current to the load increases.

[0006] A power supply circuit according to one aspect of the present invention comprises a control terminal for receiving a digital control signal, a tracker circuit configured to supply a first output voltage to a first power amplifier operating in a tracking mode, and a regulator circuit configured to supply a second output voltage to a load, wherein the regulator circuit comprises an LDO (Low Drop Out) circuit, and a resistor and a switch connected in series between an output terminal of the LDO circuit and ground.

[0007] A control method according to one aspect of the present invention is a control method for a regulator circuit including an LDO circuit and a resistor and a switch connected in series between an output terminal of the LDO circuit and ground, the control method comprising: acquiring a digital control signal; determining whether the acquired digital control signal includes control data related to an increase in an output current of the regulator circuit; and, if it is determined that the digital control signal includes the control data, (i) closing the switch before the output current increases; and (ii) opening the switch after the output current increases.

[0008] According to the present invention, it is possible to suppress a voltage drop when the output current to the load increases.

[0009] FIG. 1A is a graph showing an example of a transition of a power supply voltage in APT (Average Power Tracking) mode. FIG. 1B is a graph showing an example of a transition of a power supply voltage in A-ET (Analog Envelope Tracking) mode. FIG. 1C is a graph showing an example of a transition of a power supply voltage in D-ET mode. FIG. 2 is a block diagram showing the configuration of a communication system according to a first embodiment. FIG. 3 is a circuit diagram of a tracker circuit according to the first embodiment. FIG. 4 is a circuit diagram of a regulator circuit according to the first and second embodiments. FIG. 5 is a circuit diagram of a control circuit according to the first embodiment. FIG. 6 is a flowchart showing a control method of the regulator circuit according to the first embodiment. FIG. 7 is a graph showing the control state of a switch of the regulator circuit according to the first embodiment. FIG. 8 is a graph showing the output impedance of an output driver of the LDO circuit according to the first embodiment. FIG. 9 is a graph showing the relationship between the output impedance of the output driver and the output voltage of the regulator circuit. FIG. 10 is a circuit diagram of a power supply circuit according to a second embodiment. FIG. 11 is a circuit diagram of a tracker circuit according to the second embodiment.

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangements and connection forms of the components shown in the following embodiments are merely examples and are not intended to limit the present invention.

[0011] It should be noted that the drawings are schematic diagrams in which emphasis, omission, or adjustment of proportions has been appropriately made to illustrate the present invention, and are not necessarily strictly illustrated, and may differ from the actual shapes, positional relationships, and proportions. In the drawings, the same reference numerals are used to denote substantially the same components, and redundant explanations may be omitted or simplified.

[0012] In the following description of the circuit configuration, "connected" includes not only direct connection by connection terminals and / or wiring conductors, but also electrical connection via other circuit elements. "C is connected between A and B" means that one end of C is connected to A and the other end of C is connected to B, and C is arranged in series on the path connecting A and B. "The path connecting A and B" means a path made up of a conductor electrically connecting A to B.

[0013] "Terminal" means a point where a conductor within an element terminates. Note that terminal is understood to mean any point on the conductor between elements or the entire conductor, not just a single point, provided the impedance of the conductor between elements is sufficiently low.

[0014] Terms indicating the relationship between elements, such as "parallel" and "perpendicular," terms indicating the shape of elements, such as "rectangle," and numerical ranges do not only indicate the strict meaning, but also include a substantially equivalent range, for example, an error of a few percent.

[0015] First, as a technology for highly efficient amplification of high-frequency signals, a tracking mode will be described, in which a power amplifier is supplied with a power supply voltage that is dynamically adjusted over time based on the high-frequency signal. Tracking mode is a mode in which the power supply voltage applied to the power amplifier is dynamically adjusted. There are several types of tracking modes, but here, the APT mode, A-ET mode, and D-ET mode will be described with reference to FIGS. 1A, 1B, and 1C. In FIGS. 1A, 1B, and 1C, the horizontal axis represents time, and the vertical axis represents voltage. Furthermore, the thick solid line represents the power supply voltage, and the thin solid line (waveform) represents the modulation signal.

[0016] 1A is a graph showing an example of the transition of the power supply voltage in the APT mode. In the APT mode of FIG. 1A, the power supply voltage is changed to a plurality of discrete voltage levels in units of one frame based on the average power.

[0017] A frame is a unit that constitutes a high-frequency signal (modulated signal). For example, in 5GNR (5th Generation New Radio) and 4G LTE (4th Generation Long Term Evolution), a frame includes 10 subframes, each subframe includes multiple slots, and each slot includes multiple symbols. The subframe length is 1 ms, and the frame length is 10 ms.

[0018] A mode in which the voltage level is varied in units of one frame or larger based on the average power is called an APT mode, and is distinguished from a mode in which the voltage level is varied in units smaller than one frame (e.g., subframe, slot, or symbol). For example, a mode in which the voltage level is varied in symbol units is called a symbol power tracking (SPT) mode, and is distinguished from the APT mode.

[0019] 1B is a graph showing an example of the transition of the power supply voltage in the A-ET mode. In the A-ET mode, the envelope of the modulated signal is tracked by continuously varying the power supply voltage based on the envelope signal.

[0020] The envelope signal is a signal that indicates the envelope of the modulated signal. The envelope value is, for example, (I ２ +Q ２ ) where (I, Q) represents a constellation point. A constellation point is a point that represents a digitally modulated signal on a constellation diagram. (I, Q) is determined, for example, by a Baseband Integrated Circuit (BBIC) based on the transmitted information.

[0021] 1C is a graph showing an example of the transition of the power supply voltage in the D-ET mode. In the D-ET mode, the envelope of the modulated signal is tracked by varying the power supply voltage to multiple discrete voltage levels within one frame based on the envelope signal. In other words, in D-ET, the power supply voltage varies at shorter time intervals than in APT.

[0022] (First Embodiment) A first embodiment will be described below.

[0023] [1.1 Configuration of the Communication System] First, an exemplary configuration of a communication system including the power supply circuit 4 according to this embodiment will be described with reference to FIG.

[0024] Fig. 2 is a block diagram showing the configuration of a communication system according to this embodiment. Note that Fig. 2 is an exemplary configuration, and the communication system is not limited to the configuration shown in Fig. 2. Therefore, the description of the communication system provided below should not be interpreted in a limiting manner.

[0025] The communication system comprises a power supply circuit 4, a transceiver 5, a DC power supply 6, and power amplifiers 7 and 8.

[0026] The power supply circuit 4 can supply a power supply voltage to the power amplifiers 7 and 8. The power supply circuit 4 includes a tracker circuit 1, a regulator circuit 2, a control circuit 3, an input terminal 41, output terminals 42 and 43, and control terminals 44 and 45.

[0027] The tracker circuit 1 can receive an input voltage Vin from a DC power supply 6 via an input terminal 41. Furthermore, the tracker circuit 1 can supply an output voltage Vout1 to a power amplifier 7 operating in D-ET mode via an output terminal 42. Note that if the power amplifier 7 operates in APT mode in addition to D-ET mode, the tracker circuit 1 may be capable of switching between the D-ET mode and the APT mode. Furthermore, the tracker circuit 1 may supply the output voltage Vout1 to one or more other power amplifiers in addition to the power amplifier 7.

[0028] The regulator circuit 2 can receive an input voltage Vin from a DC power supply 6 via an input terminal 41. Furthermore, the regulator circuit 2 can supply an output voltage Vout2 to a power amplifier 8 operating in a fixed voltage mode via an output terminal 43. Note that the regulator circuit 2 may supply the output voltage Vout2 to one or more other power amplifiers in addition to the power amplifier 8. Furthermore, the regulator circuit 2 may supply the output voltage Vout2 to a device of a type different from the power amplifier instead of or in addition to the power amplifier 8.

[0029] The control circuit 3 can receive digital control signals DS1 and DS2 from the transceiver 5 via control terminals 44 and 45. Furthermore, the control circuit 3 can control the tracker circuit 1 and the regulator circuit 2 based on the digital control signals DS1 and DS2.

[0030] The detailed configurations of the tracker circuit 1, regulator circuit 2, and control circuit 3 will be described later with reference to FIGS.

[0031] The transceiver 5 is an example of a signal processing circuit that processes high-frequency signals, and may be implemented as an RFIC (Radio Frequency Integrated Circuit). The transceiver 5 processes a transmission signal input from a BBIC (not shown) or the like by upconversion or the like, and outputs the high-frequency transmission signal generated by the signal processing to the power amplifiers 7 and 8 or the like. Furthermore, the transceiver 5 processes a high-frequency reception signal input via a reception path by downconversion or the like, and outputs the reception signal generated by the signal processing to the BBIC. The transceiver 5 may also have a control unit that controls the power supply circuit 4 or the like. Note that some or all of the functions of the control unit of the transceiver 5 may be included outside the transceiver 5, for example, in the BBIC or the power supply circuit 4.

[0032] The DC power supply 6 can supply a DC voltage to the power supply circuit 4. The DC power supply 6 can be, for example, a rechargeable battery, but is not limited to this.

[0033] The power amplifier 7 is an example of a first power amplifier and can operate in a tracking mode. The power amplifier 7 can amplify, for example, a cellular signal (for example, a 5G NR signal and / or a 4G LTE signal) using the voltage supplied from the power supply circuit 4. As the tracking mode, for example, a D-ET mode can be used. Alternatively, an A-ET mode, an APT mode, or an SPT mode may be used as the tracking mode. Note that the high-frequency signal amplified by the power amplifier 7 is not limited to a 5G NR signal and / or a 4G LTE signal.

[0034] The power amplifier 8 is an example of a load and a second power amplifier, and can operate in a fixed voltage mode. The fixed voltage mode is a mode in which a high-frequency signal is amplified using a constant power supply voltage regardless of the high-frequency signal. The power amplifier 8 can amplify, for example, 2G GSM (2nd Generation Global System for Mobile communications) signals and / or wireless local area network (WLAN) signals using the voltage supplied from the power supply circuit 4. Note that the high-frequency signals amplified by the power amplifier 8 are not limited to 2G GSM signals and / or WLAN signals. For example, the power amplifier 8 may amplify Bluetooth (registered trademark) signals.

[0035] 2 is an example and is not limiting. For example, the power supply circuit 4 may include a plurality of tracker circuits 1. Also, for example, the power supply circuit 4 may include a plurality of regulator circuits 2.

[0036] [1.2 Circuit Configuration of Tracker Circuit 1] Next, an exemplary circuit configuration of the tracker circuit 1 included in the power supply circuit 4 will be described with reference to FIG. 3. FIG. 3 is a circuit configuration diagram of the tracker circuit 1 according to this embodiment. Note that FIG. 3 is an exemplary circuit configuration, and the tracker circuit 1 can be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the tracker circuit 1 provided below should not be interpreted as limiting.

[0037] The tracker circuit 1 includes a multilevel conversion circuit 100 and a power supply modulation circuit 30. The tracker circuit 1 may also include a pulse shaping network (PSN) (not shown) between the power supply modulation circuit 30 and the power amplifier 7, and / or a shunt capacitor and switch (not shown) for the APT mode.

[0038] The multilevel conversion circuit 100 can generate a plurality of discrete voltages V1 to V6 from an input voltage Vin. In this embodiment, the multilevel conversion circuit 100 includes a pre-regulator circuit 10 and a switched-capacitor circuit 20. Note that the circuit configuration of the multilevel conversion circuit 100 is not limited to the configuration shown in FIG. 3. For example, the multilevel conversion circuit 100 may include a plurality of pre-regulator circuits 10.

[0039] The circuit configurations of the pre-regulator circuit 10, the switched capacitor circuit 20, and the power supply modulation circuit 30 will be described below in order.

[0040] [1.2.1 Circuit Configuration of Pre-regulator Circuit 10] First, the circuit configuration of the pre-regulator circuit 10 will be described with reference to FIG.

[0041] The pre-regulator circuit 10 is a buck-boost converter circuit and includes an input terminal T101, an output terminal T102, switches S101 to S104, a power inductor L101, and a capacitor C101.

[0042] The input terminal T101 is a terminal that receives the input voltage Vin. The input terminal T101 is connected to the DC power supply 6 outside the pre-regulator circuit 10, and is connected to the switch S101 inside the pre-regulator circuit 10.

[0043] The output terminal T102 is a terminal that supplies a regulated voltage to the switched capacitor circuit 20. The output terminal T102 is connected to an input terminal T200 of the switched capacitor circuit 20 outside the pre-regulator circuit 10, and is connected to a switch S103 inside the pre-regulator circuit 10.

[0044] The power inductor L101 is an inductor used to step up and step down the input voltage Vin. One end of the power inductor L101 is connected to the switches S101 and S102, and the other end of the power inductor L101 is connected to the switches S103 and S104.

[0045] The switch S101 is connected between the input terminal T101 and one end of the power inductor L101. The switch S102 is connected between one end of the power inductor L101 and ground. In this connection configuration, the switches S101 and S102 are exclusively switched between open and closed based on a control signal CS10 supplied from the control circuit 3, thereby making it possible to step down the input voltage Vin.

[0046] The switch S103 is connected between the other end of the power inductor L101 and the output terminal T102. The switch S104 is connected between the other end of the power inductor L101 and ground. In this connection configuration, the switches S103 and S104 are switched exclusively between open and closed states based on a control signal CS10 supplied from the control circuit 3, thereby boosting the input voltage Vin.

[0047] The capacitor C101 is connected between the path between the switch S103 and the output terminal T102 and ground. Specifically, one of the two electrodes of the capacitor C101 is connected to the switch S103 and the output terminal T102, and the other of the two electrodes of the capacitor C101 is connected to ground.

[0048] 3 is an example and is not limiting. For example, some of the switches S101 to S104 may be replaced with diodes. Also, some or all of the pre-regulator circuit 10 may not be included in the tracker circuit 1.

[0049] [1.2.2 Circuit Configuration of Switched-Capacitor Circuit 20] Next, the circuit configuration of the switched-capacitor circuit 20 will be described with reference to FIG. 3. The switched-capacitor circuit 20 has a ladder-type circuit configuration and is capable of generating multiple discrete voltages V1, V2, V3, V4, V5, and V6. Specifically, the switched-capacitor circuit 20 includes flying capacitors C200 to C209, smoothing capacitors C210 to C215, switches S200 to S223, an input terminal T200, and output terminals T201 to T206. Energy and charge are input from the pre-regulator circuit 10 to node N5 via input terminal T200 and are extracted from nodes N1, N2, N3, N4, N5, and N6 to the power supply modulation circuit 30 via output terminals T201, T202, T203, T204, T205, and T206.

[0050] The input terminal T200 is a terminal that receives a regulated voltage from the pre-regulator circuit 10. The input terminal T200 is connected to the pre-regulator circuit 10 outside the switched capacitor circuit 20, and is connected to a node N5 inside the switched capacitor circuit 20. Note that the node to which the input terminal T200 is connected is not limited to the node N5. The input terminal T200 may be connected to any of the nodes N1, N2, N3, N4, N5, and N6.

[0051] Output terminals T201, T202, T203, T204, T205, and T206 are terminals that supply a plurality of discrete voltages V1, V2, V3, V4, V5, and V6, respectively, to the power supply modulation circuit 30. The output terminals T201, T202, T203, T204, T205, and T206 are connected to the power supply modulation circuit 30 outside the switched capacitor circuit 20, and are connected to nodes N1, N2, N3, N4, N5, and N6, respectively, within the switched capacitor circuit 20.

[0052] Flying capacitors C200, C201, C202, C203, C204, C205, C206, C207, C208, and C209 are sometimes called transfer capacitors, and are used to step up and / or step down the regulated voltage supplied from the pre-regulator circuit 10. More specifically, flying capacitors C200, C201, C202, C203, C204, C205, C206, C207, C208, and C209 are connected to six nodes N1, N2, N3, N4, N5, and N6 in a ratio of (V6-V5):(V5-V4):(V4-V3):(V3-V2):(V2-V1):(V1-VG)=1:1:1:1:1 Charges are transferred between flying capacitors C200, C201, C202, C203, C204, C205, C206, C207, C208, and C209 and nodes N1, N2, N3, N4, N5, and N6 and ground so that V1, V2, V3, V4, V5, and V6 satisfy the following relationships: V6 > V5 > V4 > V3 > V2 > V1 > VG. Here, VG represents the ground potential. Note that the ratios (V6 - V5): (V5 - V4): (V4 - V3): (V3 - V2): (V2 - V1): (V1 - VG) are not limited to 1:1:1:1:1:1 and can be designed to any ratio (e.g., 1:2:3:4:5:6, etc.).

[0053] One of the two electrodes of the flying capacitor C200 is connected to one end of the switch S200 and one end of the switch S201, and the other of the two electrodes of the flying capacitor C200 is switchably connected to one end of the switch S204 and one end of the switch S205.

[0054] One of the two electrodes of the flying capacitor C201 is connected to one end of a switch S202 and one end of a switch S203. The other of the two electrodes of the flying capacitor C201 is switchably connected to one end of a switch S206 and one end of a switch S207.

[0055] One of the two electrodes of the flying capacitor C202 is connected to one end of the switch S204 and one end of the switch S205. The other of the two electrodes of the flying capacitor C202 is connected to one end of the switch S208 and one end of the switch S209.

[0056] One of the two electrodes of the flying capacitor C203 is connected to one end of the switch S206 and one end of the switch S207. The other of the two electrodes of the flying capacitor C203 is connected to one end of the switch S210 and one end of the switch S211.

[0057] One of the two electrodes of the flying capacitor C204 is connected to one end of a switch S208 and one end of a switch S209. The other of the two electrodes of the flying capacitor C204 is connected to one end of a switch S212 and one end of a switch S213.

[0058] One of the two electrodes of the flying capacitor C205 is connected to one end of the switch S210 and one end of the switch S211. The other of the two electrodes of the flying capacitor C205 is connected to one end of the switch S214 and one end of the switch S215.

[0059] One of the two electrodes of the flying capacitor C206 is connected to one end of the switch S212 and one end of the switch S213. The other of the two electrodes of the flying capacitor C206 is connected to one end of the switch S216 and one end of the switch S217.

[0060] One of the two electrodes of the flying capacitor C207 is connected to one end of the switch S214 and one end of the switch S215. The other of the two electrodes of the flying capacitor C207 is connected to one end of the switch S218 and one end of the switch S219.

[0061] One of the two electrodes of the flying capacitor C208 is connected to one end of the switch S216 and one end of the switch S217. The other of the two electrodes of the flying capacitor C208 is connected to one end of the switch S220 and one end of the switch S221.

[0062] One of the two electrodes of the flying capacitor C209 is connected to one end of the switch S218 and one end of the switch S219. The other of the two electrodes of the flying capacitor C209 is connected to one end of the switch S222 and one end of the switch S223.

[0063] Smoothing capacitors C210, C211, C212, C213, C214 and C215 are used to hold and smooth the discrete voltages V1, V2, V3, V4, V5 and V6 at nodes N1, N2, N3, N4, N5 and N6.

[0064] The smoothing capacitor C210 is connected between the node N1 and the ground. Specifically, one of the two electrodes of the smoothing capacitor C210 is connected to the node N1. Meanwhile, the other of the two electrodes of the smoothing capacitor C210 is connected to the ground.

[0065] The smoothing capacitor C211 is connected between the nodes N1 and N2. Specifically, one of the two electrodes of the smoothing capacitor C211 is connected to the node N2. Meanwhile, the other of the two electrodes of the smoothing capacitor C211 is connected to the node N1.

[0066] The smoothing capacitor C212 is connected between the nodes N2 and N3. Specifically, one of the two electrodes of the smoothing capacitor C212 is connected to the node N3. Meanwhile, the other of the two electrodes of the smoothing capacitor C212 is connected to the node N2.

[0067] The smoothing capacitor C213 is connected between the nodes N3 and N4. Specifically, one of the two electrodes of the smoothing capacitor C213 is connected to the node N4. Meanwhile, the other of the two electrodes of the smoothing capacitor C213 is connected to the node N3.

[0068] The smoothing capacitor C214 is connected between the nodes N4 and N5. Specifically, one of the two electrodes of the smoothing capacitor C214 is connected to the node N5. Meanwhile, the other of the two electrodes of the smoothing capacitor C214 is connected to the node N4.

[0069] The smoothing capacitor C215 is connected between the nodes N5 and N6. Specifically, one of the two electrodes of the smoothing capacitor C215 is connected to the node N6. Meanwhile, the other of the two electrodes of the smoothing capacitor C215 is connected to the node N5.

[0070] The switch S200 is connected between the flying capacitor C200 and ground. Specifically, one end of the switch S200 is connected to one of the two electrodes of the flying capacitor C200. Meanwhile, the other end of the switch S200 is connected to ground.

[0071] The switch S201 is connected between the flying capacitor C200 and a node N1. Specifically, one end of the switch S201 is connected to one of the two electrodes of the flying capacitor C200. Meanwhile, the other end of the switch S201 is connected to the node N1.

[0072] The switch S202 is connected between the flying capacitor C201 and ground. Specifically, one end of the switch S202 is connected to one of the two electrodes of the flying capacitor C201. Meanwhile, the other end of the switch S202 is connected to ground.

[0073] The switch S203 is connected between the flying capacitor C201 and the node N1. Specifically, one end of the switch S203 is connected to one of the two electrodes of the flying capacitor C201. Meanwhile, the other end of the switch S203 is connected to the node N1.

[0074] The switch S204 is connected between the flying capacitors C200 and C202 and the node N1. Specifically, one end of the switch S204 is connected to the other of the two electrodes of the flying capacitor C200 and to one of the two electrodes of the flying capacitor C202. Meanwhile, the other end of the switch S204 is connected to the node N1.

[0075] The switch S205 is connected between the flying capacitors C200 and C202 and the node N2. Specifically, one end of the switch S205 is connected to the other of the two electrodes of the flying capacitor C200 and to one of the two electrodes of the flying capacitor C202. Meanwhile, the other end of the switch S205 is connected to the node N2.

[0076] The switch S206 is connected between the flying capacitors C201 and C203 and the node N1. Specifically, one end of the switch S206 is connected to the other of the two electrodes of the flying capacitor C201 and to one of the two electrodes of the flying capacitor C203. Meanwhile, the other end of the switch S206 is connected to the node N1.

[0077] The switch S207 is connected between the flying capacitors C201 and C203 and the node N2. Specifically, one end of the switch S207 is connected to the other of the two electrodes of the flying capacitor C201 and to one of the two electrodes of the flying capacitor C203. Meanwhile, the other end of the switch S207 is connected to the node N2.

[0078] The switch S208 is connected between the flying capacitors C202 and C204 and the node N2. Specifically, one end of the switch S208 is connected to the other of the two electrodes of the flying capacitor C202 and one of the two electrodes of the flying capacitor C204. Meanwhile, the other end of the switch S208 is connected to the node N2.

[0079] The switch S209 is connected between the flying capacitors C202 and C204 and the node N3. Specifically, one end of the switch S209 is connected to the other of the two electrodes of the flying capacitor C202 and one of the two electrodes of the flying capacitor C204. Meanwhile, the other end of the switch S209 is connected to the node N3.

[0080] The switch S210 is connected between the flying capacitors C203 and C205 and the node N2. Specifically, one end of the switch S210 is connected to the other of the two electrodes of the flying capacitor C203 and one of the two electrodes of the flying capacitor C205. Meanwhile, the other end of the switch S210 is connected to the node N2.

[0081] The switch S211 is connected between the flying capacitors C203 and C205 and the node N3. Specifically, one end of the switch S211 is connected to the other of the two electrodes of the flying capacitor C203 and one of the two electrodes of the flying capacitor C205. Meanwhile, the other end of the switch S211 is connected to the node N3.

[0082] The switch S212 is connected between the flying capacitors C204 and C206 and the node N3. Specifically, one end of the switch S212 is connected to the other of the two electrodes of the flying capacitor C204 and one of the two electrodes of the flying capacitor C206. Meanwhile, the other end of the switch S212 is connected to the node N3.

[0083] The switch S213 is connected between the flying capacitors C204 and C206 and the node N4. Specifically, one end of the switch S213 is connected to the other of the two electrodes of the flying capacitor C204 and one of the two electrodes of the flying capacitor C206. Meanwhile, the other end of the switch S213 is connected to the node N4.

[0084] The switch S214 is connected between the flying capacitors C205 and C207 and the node N3. Specifically, one end of the switch S214 is connected to the other of the two electrodes of the flying capacitor C205 and one of the two electrodes of the flying capacitor C207. Meanwhile, the other end of the switch S214 is connected to the node N3.

[0085] The switch S215 is connected between the flying capacitors C205 and C207 and the node N4. Specifically, one end of the switch S215 is connected to the other of the two electrodes of the flying capacitor C205 and one of the two electrodes of the flying capacitor C207. Meanwhile, the other end of the switch S215 is connected to the node N4.

[0086] The switch S216 is connected between the flying capacitors C206 and C208 and the node N4. Specifically, one end of the switch S216 is connected to the other of the two electrodes of the flying capacitor C206 and one of the two electrodes of the flying capacitor C208. Meanwhile, the other end of the switch S216 is connected to the node N4.

[0087] The switch S217 is connected between the flying capacitors C206 and C208 and the node N5. Specifically, one end of the switch S217 is connected to the other of the two electrodes of the flying capacitor C206 and one of the two electrodes of the flying capacitor C208. Meanwhile, the other end of the switch S217 is connected to the node N5.

[0088] The switch S218 is connected between the flying capacitors C207 and C209 and the node N4. Specifically, one end of the switch S218 is connected to the other of the two electrodes of the flying capacitor C207 and one of the two electrodes of the flying capacitor C209. Meanwhile, the other end of the switch S218 is connected to the node N4.

[0089] The switch S219 is connected between the flying capacitors C207 and C209 and the node N5. Specifically, one end of the switch S219 is connected to the other of the two electrodes of the flying capacitor C207 and one of the two electrodes of the flying capacitor C209. Meanwhile, the other end of the switch S219 is connected to the node N5.

[0090] The switch S220 is connected between the flying capacitor C208 and a node N5. Specifically, one end of the switch S220 is connected to the other of the two electrodes of the flying capacitor C208. Meanwhile, the other end of the switch S220 is connected to the node N5.

[0091] The switch S221 is connected between the flying capacitor C208 and a node N6. Specifically, one end of the switch S221 is connected to the other of the two electrodes of the flying capacitor C208. Meanwhile, the other end of the switch S221 is connected to the node N6.

[0092] The switch S222 is connected between the flying capacitor C209 and a node N5. Specifically, one end of the switch S222 is connected to the other of the two electrodes of the flying capacitor C209. Meanwhile, the other end of the switch S222 is connected to the node N5.

[0093] The switch S223 is connected between the flying capacitor C209 and a node N6. Specifically, one end of the switch S223 is connected to the other of the two electrodes of the flying capacitor C209. Meanwhile, the other end of the switch S223 is connected to the node N6.

[0094] A first set of switches including switches S200, S203, S204, S207, S208, S211, S212, S215, S216, S219, S220 and S223 and a second set of switches including switches S201, S202, S205, S206, S209, S210, S213, S214, S217, S218, S221 and S222 are switched between open and closed states inversely based on control signals CS21 and / or CS22 supplied from the control circuit 3.

[0095] Specifically, in the first phase, the first set of switches are closed and the second set of switches are opened. As a result, one of the two electrodes of the flying capacitor C200 is connected to ground. The other of the two electrodes of the flying capacitor C200, one of the two electrodes of the flying capacitor C201, and one of the two electrodes of the flying capacitor C202 are connected to node N1. The other of the two electrodes of the flying capacitor C201, the other of the two electrodes of the flying capacitor C202, one of the two electrodes of the flying capacitor C203, and one of the two electrodes of the flying capacitor C204 are connected to node N2. The other of the two electrodes of the flying capacitor C203, the other of the two electrodes of the flying capacitor C204, one of the two electrodes of the flying capacitor C205, and one of the two electrodes of the flying capacitor C206 are connected to node N3. The other of the two electrodes of flying capacitor C205, the other of the two electrodes of flying capacitor C206, one of the two electrodes of flying capacitor C207, and one of the two electrodes of flying capacitor C208 are connected to node N4. The other of the two electrodes of flying capacitor C207, the other of the two electrodes of flying capacitor C208, and one of the two electrodes of flying capacitor C209 are connected to node N5. The other of the two electrodes of flying capacitor C209 is connected to node N6.

[0096] Conversely, in the second phase, the first set of switches are opened and the second set of switches are closed. As a result, one of the two electrodes of the flying capacitor C201 is connected to ground. One of the two electrodes of the flying capacitor C200, the other of the two electrodes of the flying capacitor C201, and one of the two electrodes of the flying capacitor C203 are connected to node N1. The other of the two electrodes of the flying capacitor C200, one of the two electrodes of the flying capacitor C202, the other of the two electrodes of the flying capacitor C203, and one of the two electrodes of the flying capacitor C205 are connected to node N2. The other of the two electrodes of the flying capacitor C202, one of the two electrodes of the flying capacitor C204, the other of the two electrodes of the flying capacitor C205, and one of the two electrodes of the flying capacitor C207 are connected to node N3. The other of the two electrodes of flying capacitor C204, one of the two electrodes of flying capacitor C206, the other of the two electrodes of flying capacitor C207, and one of the two electrodes of flying capacitor C209 are connected to node N4. The other of the two electrodes of flying capacitor C206, one of the two electrodes of flying capacitor C208, and the other of the two electrodes of flying capacitor C209 are connected to node N5. The other of the two electrodes of flying capacitor C208 is connected to node N6.

[0097] By repeating the first and second phases, the flying capacitors C200 to C209 can be charged and discharged in a complementary manner. For example, in one of the first and second phases, the flying capacitors C200, C202, C204, C206, and C208 charge the smoothing capacitors C210, C211, C212, C213, C214, and C215, and in the other of the first and second phases, the flying capacitors C201, C203, C205, C207, and C209 charge the smoothing capacitors C210, C211, C212, C213, C214, and C215. In other words, since the smoothing capacitors C210 to C215 are always charged from one of the flying capacitors C200 to C209, even if a current flows from one of the nodes N1 to N6 to the power supply modulation circuit 30 at high speed, charge is quickly replenished to one of the nodes N1 to N6, thereby suppressing fluctuations in the potential of the nodes N1 to N6.

[0098] By operating in this manner, the switched-capacitor circuit 20 can maintain approximately equal voltages across each of the smoothing capacitors C210 to C215. Specifically, at six nodes N1 to N6 labeled V1 to V6, voltages V1 to V6 that satisfy the following relationship are maintained: (V6-V5): (V5-V4): (V4-V3): (V3-V2): (V2-V1): (V1-VG) = 1:1:1:1:1:1. Note that VG represents ground potential. For example, if the regulated voltage supplied from the pre-regulator circuit 10 is 5V, the switched-capacitor circuit 20 can generate multiple discrete voltages (V1, V2, V3, V4, V5, V6) of 1V, 2V, 3V, 4V, 5V, and 6V.

[0099] It should be noted that (V6-V5):(V5-V4):(V4-V3):(V3-V2):(V2-V1):(V1-VG) is not limited to 1:1:1:1:1:1:1, and can be designed to have any ratio (for example, 1:2:3:4:5:6, etc.).

[0100] 3 is an example, and the configuration of the switched-capacitor circuit 20 is not limited to this. For example, part or all of the switched-capacitor circuit 20 does not have to be included in the tracker circuit 1.

[0101] [1.2.3 Circuit Configuration of Power Supply Modulation Circuit 30] Next, the circuit configuration of the power supply modulation circuit 30 will be described with reference to Fig. 3. The power supply modulation circuit 30 includes input terminals T301 to T306, an output terminal T307, and switches S301 to S306.

[0102] Input terminals T301, T302, T303, T304, T305 and T306 are terminals that receive a plurality of discrete voltages V1, V2, V3, V4, V5 and V6 generated by the switched capacitor circuit 20. The input terminals T301, T302, T303, T304, T305 and T306 are connected to output terminals T201, T202, T203, T204, T205 and T206 of the switched capacitor circuit 20, respectively, outside the power supply modulation circuit 30, and are connected to switches S301, S302, S303, S304, S305 and S306, respectively, within the power supply modulation circuit 30.

[0103] Output terminal T307 is a terminal that selectively supplies at least one of a plurality of discrete voltages V1, V2, V3, V4, V5, and V6 to power amplifier 7. Output terminal T307 is connected to power amplifier 7 outside power supply modulation circuit 30, and is connected to switches S301, S302, S303, S304, S305, and S306 inside power supply modulation circuit 30.

[0104] The switch S301 is connected between the input terminal T301 and the output terminal T307. The switch S302 is connected between the input terminal T302 and the output terminal T307. The switch S303 is connected between the input terminal T303 and the output terminal T307. The switch S304 is connected between the input terminal T304 and the output terminal T307. The switch S305 is connected between the input terminal T305 and the output terminal T307. The switch S306 is connected between the input terminal T306 and the output terminal T307.

[0105] These switches S301, S302, S303, S304, S305, and S306 are switched open and closed (on and off) by a control signal CS30 supplied from the control circuit 3. In this embodiment, the switches S301, S302, S303, S304, S305, and S306 are controlled to be exclusively on. That is, only one of the switches S301, S302, S303, S304, S305, and S306 is closed, and the remaining switches S301, S302, S303, S304, S305, and S306 are all controlled to be open. This allows the power supply modulation circuit 30 to supply one voltage selected from a plurality of discrete voltages (V1, V2, V3, V4, V5, and V6) to the power amplifier 7.

[0106] Note that the configuration of the power supply modulation circuit 30 shown in FIG. 3 is an example and is not limited thereto. In particular, the switches S301, S302, S303, S304, S305, and S306 may have any configuration and may be controlled in any manner as long as they can selectively connect at least one of the six input terminals T301, T302, T303, T304, T305, and T306 to the output terminal T307. For example, two of the switches S301, S302, S303, S304, S305, and S306 may be closed, and the remaining four of the switches S301, S302, S303, S304, S305, and S306 may be open. Furthermore, for example, some or all of the power supply modulation circuit 30 may not be included in the tracker circuit 1.

[0107] [1.3 Circuit Configuration of Regulator Circuit 2] Next, an exemplary circuit configuration of the regulator circuit 2 included in the power supply circuit 4 will be described with reference to FIG. 4. FIG. 4 is a circuit configuration diagram of regulator circuits 2 and 2A according to embodiments 1 and 2. Note that FIG. 4 is an exemplary circuit configuration, and the regulator circuit 2 can be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the regulator circuit 2 provided below should not be construed as limiting.

[0108] The regulator circuit 2 includes an LDO (Low Drop Out) circuit 40, a resistor R40, and a switch S40.

[0109] The LDO circuit 40 includes an output driver D40, an error amplifier A40, an input terminal T40a, and an output terminal T40b.

[0110] The output driver D40 is an n-type metal-oxide-semiconductor field-effect transistor (nMOSFET). In the output driver D40, the drain terminal is connected to the input terminal T40a, the source terminal is connected to the output terminal T40b, and the gate terminal is connected to the output terminal of the error amplifier A40. Note that the output driver D40 is not limited to an nMOSFET. For example, the output driver D40 may be a p-type metal-oxide-semiconductor field-effect transistor (pMOSFET) or a bipolar junction transistor (BJT).

[0111] The error amplifier A40 compares the output voltage Vout2 with a reference voltage Vref supplied from a reference voltage source, and controls the on-resistance of the output driver D40 so that the output voltage Vout2 becomes a desired voltage. The two input terminals (positive terminal and negative terminal) of the error amplifier A40 are connected to the reference voltage source and the output terminal T40b, respectively. The output terminal of the error amplifier A40 is connected to the gate terminal of the output driver D40.

[0112] The LDO circuit 40 configured in this manner can regulate the output voltage Vout2 from the input voltage Vin by controlling the drain-source resistance of the output driver D40 using a feedback loop.

[0113] The resistor R40 and the switch S40 are connected in series between the output terminal T40b of the LDO circuit 40 and ground. Specifically, the resistor R40 is connected between the output terminal T40b and the switch S40, and the switch S40 is connected between the resistor R40 and ground. Note that the connections of the resistor R40 and the switch S40 may be reversed. In other words, the switch S40 may be connected between the output terminal T40b and the resistor R40, and the resistor R40 may be connected between the switch S40 and ground.

[0114] The opening and closing of the switch S40 connected in this manner is controlled by a control signal CS40 supplied from the control circuit 3. Specifically, the switch S40 is closed before the output current Iout2 increases and is opened after the output current Iout2 increases in accordance with the control signal CS40. A more specific method of controlling the switch S40 will be described later.

[0115] [1.4 Circuit Configuration of Control Circuit 3] Next, an exemplary circuit configuration of the control circuit 3 included in the power supply circuit 4 will be described with reference to FIG. 5. FIG. 5 is a circuit configuration diagram of the control circuit 3 according to this embodiment. Note that FIG. 5 is an exemplary circuit configuration, and the control circuit 3 can be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the control circuit 3 provided below should not be construed as limiting.

[0116] The control circuit 3 includes a digital control circuit 51 and an analog control circuit 52 .

[0117] The digital control circuit 51 is capable of processing the digital control signals DS1 and DS2 supplied from the transceiver 5. The digital control circuit 51 includes a first controller 511 and a second controller 512.

[0118] The first controller 511 obtains control data from the digital control signal DS1 supplied from the transceiver 5 and supplies it to the analog control circuit 52, and further supplies a control signal CS22 to the switched capacitor circuit 20 to control the switched capacitor circuit 20.

[0119] The digital control signal DS1 is a serial data signal. For example, a source synchronous digital control signal is used as the serial data signal. Note that a clock-embedded digital control signal may also be used as the serial data signal.

[0120] In this embodiment, one clock signal (CLK) and one data signal (DATA) are used as the digital control signal DS1, but this is not limited to this. For example, one clock signal and multiple data signals may be used as the digital control signal DS1, or multiple clock signals and multiple data signals may be used. For example, the data signal containing control data for controlling the regulator circuit 2 may be different from the data signal containing control data for controlling the tracker circuit 1. In this case, the digital control signal DS1 for the regulator circuit 2 may be the same as the digital control signal for the power amplifier 8.

[0121] The second controller 512 processes the digital control signal DS2 supplied from the transceiver 5 and can supply a control signal CS30 for controlling the power supply modulation circuit 30 to the power supply modulation circuit 30.

[0122] The digital control signal DS2 is a parallel data signal. Examples of the parallel data signal include digital control level (DCL) signals (DCL1, DCL2). The DCL signals (DCL1, DCL2) are generated by the transceiver 5 based on the envelope signal of the high-frequency signal. The control signal CS30 is a signal that controls the opening and closing of switches S301, S302, S303, S304, S305, and S306 included in the power supply modulation circuit 30.

[0123] Each of the DCL signals (DCL1, DCL2) is a 1-bit signal. A plurality of discrete voltages V1, V2, V3, V4, V5, and V6 are represented by a combination of two 1-bit signals. For example, V3, V4, V5, and V6 are represented by "00," "01," "10," and "11," respectively. Gray code may be used to represent the voltage levels.

[0124] In this embodiment, two DCL signals are used to control the power supply modulation circuit 30, but the number of DCL signals is not limited to this. For example, any number of DCL signals, such as one, three, or four or more, may be used depending on the number of voltage levels selectable by the power supply modulation circuit 30. Furthermore, the parallel data signals used to control the power supply modulation circuit 30 are not limited to DCL signals.

[0125] Based on control data supplied from the first controller 511 of the digital control circuit 51, the analog control circuit 52 can supply a control signal CS10 for controlling the pre-regulator circuit 10 and a control signal CS21 for controlling the switched capacitor circuit 20 to the tracker circuit 1, and can supply a control signal CS40 for controlling the switch S40 of the regulator circuit 2 to the regulator circuit 2.

[0126] When the power amplifier 7 operates in the APT mode, the control signal CS30 that controls the power supply modulation circuit 30 may be generated by the first controller 511 and the analog control circuit 52 based on the digital control signal DS1.

[0127] 5 is an example, and is not intended to be limiting. For example, part or all of the control circuit 3 may not be included in the tracker circuit 1, and may instead be included in the transceiver 5, for example.

[0128] [1.5 Control Method of Regulator Circuit 2] Next, a control method of the regulator circuit 2 according to this embodiment will be described with reference to Fig. 6 to Fig. 9. Fig. 6 is a flowchart showing the control method of the regulator circuit 2 according to this embodiment.

[0129] <Step S1001> The control circuit 3 acquires the digital control signal DS1. Specifically, the first controller 511 of the digital control circuit 51 acquires the digital control signal DS1 from the transceiver 5. Note that the control circuit 3 may acquire, as the digital control signal DS1, a signal transmitted from the transceiver 5 to the power supply circuit 4, or a signal transmitted from the transceiver 5 to a high-frequency module including the power amplifier 8.

[0130] <Step S1002> The control circuit 3 determines whether the digital control signal DS1 includes control data related to an increase in the output current Iout2 of the regulator circuit 2. Specifically, the first controller 511 of the digital control circuit 51 obtains the control data from the digital control signal DS1 and supplies it to the analog control circuit 52. Then, the analog control circuit 52 determines whether the control data is data related to an increase in the output current Iout2.

[0131] The control data regarding the increase in output current Iout2 is data based on the control of the power amplifier 8 to increase the output current Iout2. For example, the control data may be data indicating switching the power amplifier 8 from an OFF state to an ON state. Also, for example, the control data may be data indicating an increase in the power supply voltage of the power amplifier 8.

[0132] Here, if it is determined that the digital control signal DS1 includes control data related to an increase in the output current Iout2 (Yes in S1002), the process proceeds to step S1003. On the other hand, if it is not determined that the digital control signal DS1 includes control data related to an increase in the output current Iout2 (No in S1002), steps S1003 and S1004 are skipped and the process ends. In other words, if the digital control signal DS1 does not include control data related to an increase in the output current Iout2, the switch S40 is not closed but remains open.

[0133] <Step S1003> The control circuit 3 supplies a control signal CS40 for closing the switch S40 to the regulator circuit 2. This causes the switch S40 to be closed before the output current Iout2 increases.

[0134] <Step S1004> The control circuit 3 supplies a control signal CS40 for opening the switch S40 to the regulator circuit 2. As a result, the switch S40 is opened after the output current Iout2 has increased. Step S1004 is executed, for example, after a predetermined time (for example, several tens of microseconds) has elapsed since step S1003.

[0135] [1.6 Operation of Regulator Circuit 2] The control state of switch S40 controlled in this manner will be described with reference to Fig. 7. Fig. 7 is a graph showing the control state of switch S40 of regulator circuit 2 according to this embodiment. In Fig. 7, the upper graph is a graph showing the time course of output current Iout2, and the lower graph is a graph showing the state of switch S40.

[0136] As shown in the lower graph, the state of switch S40 is off (open) from time t0 to t1. Just before time t1, a digital control signal DS1 including control data related to an increase in output current Iout2 is acquired, and a control signal CS40 that switches switch S40 on (closes) is supplied to regulator circuit 2. As a result, the state of switch S40 is switched on at time t1.

[0137] At time t2, the output current Iout2 increases. Thereafter, a control signal CS40 that turns off the switch S40 is supplied to the regulator circuit 2, and the switch S40 is switched off at time t3.

[0138] The change in output impedance of the output driver D40 due to switching of the switch S40 will be described with reference to Fig. 8. Fig. 8 is a graph showing the output impedance of the output driver D40 of the LDO circuit 40 according to this embodiment. In Fig. 8, the horizontal axis represents the output current, and the vertical axis represents the output impedance.

[0139] During the time t0 to t1 when the switch S40 is open and the output current Iout2 to the power amplifier 8 is approximately zero, the output impedance of the output driver D40 is relatively high (e.g., 600 ohms). During the time t1 to t2 from when the switch S40 is closed until the output current Iout2 increases, a current flows from the output driver D40 to ground via the resistor R40 and the switch S40, causing the output impedance to decrease (e.g., 10 ohms). After that, after the time t2 when the output current Iout2 increases, the output driver D40 supplies the output current Iout2 to the power amplifier 8, causing the output impedance to decrease further (e.g., 1 ohm).

[0140] By closing the switch S40 before the output current Iout2 of the regulator circuit 2 increases in this way, it is possible to reduce the output impedance of the output driver D40 at time t2 when the output current Iout2 increases suddenly.

[0141] Next, the relationship between the output impedance of the output driver D40 and the output voltage Vout2 at the timing when the output current Iout2 increases will be described with reference to Fig. 9. Fig. 9 is a graph showing the relationship between the output impedance of the output driver D40 of the LDO circuit 40 and the output voltage Vout2 of the regulator circuit 2 at the timing when the output current Iout2 of the regulator circuit 2 increases. In Fig. 9, the horizontal axis represents time, the left vertical axis represents the output voltage Vout2, and the right vertical axis represents the output current Iout2.

[0142] The line labeled Iout2 in the graph shows the output current Iout2 over time. The line labeled Vout2(1) in the graph shows the output voltage Vout2 over time when the output impedance of the output driver D40 is low. The line labeled Vout2(2) in the graph shows the output voltage Vout2 over time when the output impedance of the output driver D40 is high.

[0143] 9, if the output impedance of the output driver D40 is high at the timing (1.000 ms) when the output current Iout2 increases, the output voltage Vout2(2) temporarily drops significantly after the output current Iout2 increases. On the other hand, if the output impedance of the output driver D40 is low at the timing (1.000 ms) when the output current Iout2 increases, the output voltage Vout2(1) temporarily drops slightly after the output current Iout2 increases. In other words, the drop in the output voltage Vout2(1) is smaller than the drop in the output voltage Vout2(2).

[0144] That is, by closing the switch S40 before the output current Iout2 increases and reducing the output impedance of the output driver D40, it is possible to suppress a decrease in the output voltage Vout2 after the output current Iout2 increases. After the output current Iout2 increases, it is possible to reduce power consumption by opening the switch S40.

[0145] [1.7 Summary] As described above, the power supply circuit 4 according to this embodiment includes the control terminal 44 that receives the digital control signal DS1, the tracker circuit 1 that is configured to supply the output voltage Vout1 to the power amplifier 7 that operates in tracking mode, and the regulator circuit 2 that is configured to supply the output voltage Vout2 to a load (for example, the power amplifier 8), and the regulator circuit 2 includes the LDO circuit 40, and the resistor R40 and switch S40 that are connected in series between the output terminal T40b of the LDO circuit 40 and ground.

[0146] This allows the output impedance of the LDO circuit 40 to be controlled by opening and closing the switch S40. For example, by closing the switch S40 before the output current Iout2 to the load increases, the output impedance of the LDO circuit 40 can be reduced in advance. As a result, as shown in FIG. 9 , it is possible to suppress a voltage drop when the output current Iout2 to the load increases. Furthermore, by keeping the switch S40 open when the output current Iout2 to the load does not increase, it is possible to suppress power consumption.

[0147] Furthermore, for example, the power supply circuit 4 according to the present embodiment may further include a control circuit 3 configured to control the switch S40 based on the digital control signal DS1.

[0148] According to this, the switch S40 is controlled based on the digital control signal DS1. For example, if the digital control signal DS1 includes control data for a load, the control circuit 3 processes the digital control signal DS1 to detect control data for increasing the output current Iout2 to the load, thereby reducing the output impedance of the LDO circuit 40 before the output current Iout2 to the load increases. Furthermore, for example, if the digital control signal DS1 includes control data for the switch S40, the control circuit 3 processes the digital control signal DS1 to detect control data for the switch S40, thereby reducing the output impedance of the LDO circuit 40.

[0149] Furthermore, for example, in the power supply circuit 4 according to this embodiment, the control circuit 3 may be configured to close the switch S40 when the digital control signal DS1 includes control data relating to an increase in the output current Iout2 of the regulator circuit 2.

[0150] This allows the output impedance of the LDO circuit 40 to be reduced before the output current Iout2 to the load increases, thereby suppressing a voltage drop when the output current Iout2 to the load increases.

[0151] For example, in the power supply circuit 4 according to this embodiment, the control circuit 3 may include a digital control circuit 51 configured to acquire control data from the digital control signal DS1, and an analog control circuit 52 configured to generate a control signal CS40 that closes the switch S40 when the control data is data related to an increase in the output current Iout2 of the regulator circuit 2.

[0152] This allows the output impedance of the LDO circuit 40 to be controlled by the digital control circuit 51 and the analog control circuit 52 .

[0153] Also, for example, in the power supply circuit 4 according to this embodiment, the tracking mode may be the D-ET mode, and the tracker circuit 1 may include a multilevel conversion circuit 100 configured to generate a plurality of discrete voltages V1 to V6 from an input voltage Vin, and a power supply modulation circuit 30 configured to selectively output at least one of the plurality of discrete voltages V1 to V6 to the power amplifier 7 as an output voltage Vout1.

[0154] This makes it possible to suppress a decrease in the output voltage Vout2 that accompanies an increase in the output current Iout2 to the load in a power supply circuit 4 that can supply an output voltage Vout1 to a power amplifier 7 operating in D-ET mode.

[0155] Also, for example, in the power supply circuit 4 according to this embodiment, the multilevel conversion circuit 100 may include a pre-regulator circuit 10 configured to convert the input voltage Vin into a regulated voltage, and a switched capacitor circuit 20 configured to generate a plurality of discrete voltages V1 to V6 from the regulated voltage.

[0156] This allows the pre-regulator circuit 10 and the switched capacitor circuit 20 to generate a plurality of discrete voltages V1 to V6.

[0157] Also, for example, in the power supply circuit 4 according to this embodiment, the tracker circuit 1 may be configured to generate the output voltage Vout1 from the input voltage Vin, and the regulator circuit 2 may be configured to generate the output voltage Vout2 from the input voltage Vin.

[0158] This allows the regulator circuit 2 to generate the output voltage Vout2 using the same input voltage Vin as the tracker circuit 1.

[0159] Also, for example, in the power supply circuit 4 according to this embodiment, the power amplifier 7 may be configured to amplify a 5G NR signal or a 4G LTE signal, and the load may be a power amplifier 8 configured to amplify a 2G GSM signal.

[0160] This allows the power amplifier 7 capable of amplifying the 5G NR signal or the 4G LTE signal to operate in tracking mode, improving power efficiency. Furthermore, it is possible to suppress a voltage drop in the output voltage Vout2 supplied to the power amplifier 8 capable of amplifying the 2G GSM signal, thereby suppressing deterioration in the quality of the 2G GSM signal.

[0161] Also for example, in the power supply circuit 4 according to the present embodiment, the power amplifier 7 may be configured to amplify a cellular signal, and the load may be a power amplifier 8 configured to amplify a WLAN signal.

[0162] This allows the power amplifier 7 capable of amplifying cellular signals to operate in tracking mode, improving power efficiency. Furthermore, it is possible to suppress a voltage drop in the output voltage Vout2 supplied to the power amplifier 8 capable of amplifying WLAN signals, thereby suppressing deterioration in the quality of the WLAN signals.

[0163] Furthermore, the control method according to this embodiment is a control method for a regulator circuit 2 including an LDO circuit 40 and a resistor R40 and a switch S40 connected in series between an output terminal T40b of the LDO circuit 40 and ground, and includes the steps of acquiring a digital control signal DS1 (S1001), determining whether the acquired digital control signal DS1 includes control data related to an increase in the output current Iout2 of the regulator circuit 2 (S1002), and, if it is determined that the digital control signal DS1 includes the control data (Yes in S1002), (i) closing the switch S40 before the output current Iout2 increases (S1003), and (ii) opening the switch S40 after the output current Iout2 increases (S1004).

[0164] According to this, by closing switch S40 before the output current Iout2 increases, the output impedance of LDO circuit 40 can be reduced in advance. As a result, as shown in Fig. 9, it is possible to suppress a voltage drop when the output current Iout2 to the load increases. Furthermore, by opening switch S40 after the output current Iout2 has increased, it is possible to suppress power consumption.

[0165] (Embodiment 2) Next, embodiment 2 will be described. In this embodiment, one of a plurality of discrete voltages generated by a tracker circuit is used as the input voltage of the regulator circuit. This embodiment will be described below with reference to the drawings, focusing on the differences from embodiment 1.

[0166] [2.1 Configuration of the Communication System] First, an exemplary configuration of a communication system including a power supply circuit 4A according to this embodiment will be described with reference to FIG.

[0167] Fig. 10 is a block diagram showing the configuration of a communication system according to this embodiment. Note that Fig. 10 is an exemplary configuration, and the communication system is not limited to the configuration shown in Fig. 10. Therefore, the description of the communication system provided below should not be interpreted in a limiting manner.

[0168] The communication system includes a power supply circuit 4A, a transceiver 5, a DC power supply 6, and power amplifiers 7 and 8.

[0169] The power supply circuit 4A can supply a power supply voltage to the power amplifiers 7 and 8. The power supply circuit 4A includes a tracker circuit 1A, a regulator circuit 2A, a control circuit 3, an input terminal 41, output terminals 42 and 43, and control terminals 44 and 45.

[0170] The tracker circuit 1A can receive an input voltage Vin from a DC power supply 6 via an input terminal 41. Furthermore, the tracker circuit 1A can supply an output voltage Vout1 to a power amplifier 7 operating in D-ET mode via an output terminal 42. The tracker circuit 1A can also supply voltage V1 of a plurality of discrete voltages V1 to V6 to a regulator circuit 2A. Note that if the power amplifier 7 operates in APT mode in addition to D-ET mode, the tracker circuit 1A may be capable of switching between the D-ET mode and the APT mode. Furthermore, the tracker circuit 1A may supply the output voltage Vout1 to one or more other power amplifiers in addition to the power amplifier 7.

[0171] The regulator circuit 2A can receive the voltage V1 from the tracker circuit 1A. Furthermore, the regulator circuit 2A can supply an output voltage Vout2 to the power amplifier 8 operating in a fixed voltage mode via an output terminal 43. Note that the regulator circuit 2A may supply the output voltage Vout2 to one or more other power amplifiers in addition to the power amplifier 8. Furthermore, the regulator circuit 2A may supply the output voltage Vout2 to a device of a different type from the power amplifier instead of or in addition to the power amplifier 8.

[0172] [2.2 Circuit Configuration of Tracker Circuit 1A] Next, an exemplary circuit configuration of the tracker circuit 1A included in the power supply circuit 4A will be described with reference to FIG. 11. FIG. 11 is a circuit configuration diagram of the tracker circuit 1A according to this embodiment. Note that FIG. 11 is an exemplary circuit configuration, and the tracker circuit 1A can be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the tracker circuit 1A provided below should not be interpreted as limiting.

[0173] The tracker circuit 1A according to this embodiment includes a multilevel conversion circuit 100 including a pre-regulator circuit 10 and a switched-capacitor circuit 20, and a power supply modulation circuit 30, similar to the tracker circuit 1 according to the first embodiment.

[0174] The switched-capacitor circuit 20 according to this embodiment can supply the voltage V1 to the regulator circuit 2A in addition to the power supply modulation circuit 30. Specifically, the output terminal T201 of the switched-capacitor circuit 20 is connected to the regulator circuit 2A.

[0175] The switched capacitor circuit 20 may supply the regulator circuit 2A with the voltage V2, V3, V4, V5, or V6 instead of the voltage V1. In this case, the output terminal T202, T203, T204, T205, or T206 may be connected to the regulator circuit 2A instead of the output terminal T201.

[0176] The detailed circuit configurations of the pre-regulator circuit 10, the switched capacitor circuit 20, and the power supply modulation circuit 30 are the same as those in the first embodiment, and therefore will not be described again.

[0177] [2.3 Circuit Configuration of Regulator Circuit 2A] Next, an exemplary circuit configuration of the regulator circuit 2A included in the power supply circuit 4A will be described with reference to Fig. 4. In the regulator circuit 2A according to this embodiment, the input terminal T40a of the LDO circuit 40 is connected to the output terminal T201 of the switched capacitor circuit 20. The LDO circuit 40 can regulate the output voltage Vout2 from the voltage V1 by controlling the drain-source resistance of the output driver D40 using a feedback loop.

[0178] The other circuit configuration of the regulator circuit 2A is the same as that of the regulator circuit 2 according to the first embodiment, and therefore the description thereof will be omitted.

[0179] Furthermore, the control method for the regulator circuit 2A is similar to the control method for the regulator circuit 2 according to the first embodiment, and therefore the description thereof will be omitted.

[0180] [2.4 Summary] As described above, in the power supply circuit 4A according to this embodiment, the regulator circuit 2A may be configured to generate the output voltage Vout2 from one of the plurality of discrete voltages V1 to V6.

[0181] This allows the regulator circuit 2A to generate the output voltage Vout2 using any of the multiple discrete voltages V1 to V6 generated within the tracker circuit 1 A. This makes it possible to use a voltage suitable for generating the output voltage Vout2, thereby improving the power efficiency of the regulator circuit 2A.

[0182] Furthermore, for example, in the power supply circuit 4A according to this embodiment, the regulator circuit 2A may be configured to generate the output voltage Vout2 from the lowest voltage V1 of the plurality of discrete voltages V1 to V6.

[0183] This allows the output voltage Vout2 to be generated using the lowest voltage V1 among the plurality of discrete voltages V1 to V6, thereby further improving the power efficiency of the regulator circuit 2A.

[0184] (Other Embodiments) While the power supply circuit and control method according to the present invention have been described above based on the embodiments, the power supply circuit and control method according to the present invention are not limited to the above embodiments. The present invention also includes other embodiments realized by combining any of the components in the above embodiments, modifications obtained by applying various modifications to the above embodiments that would occur to those skilled in the art without departing from the spirit of the present invention, and various devices incorporating the above power supply circuit.

[0185] For example, in the circuit configurations of the various circuits according to the above embodiments, other circuit elements and wiring may be inserted between the paths connecting the circuit elements and signal paths disclosed in the drawings. For example, an inductor and / or a capacitor may be inserted between the tracker circuit and the power amplifier.

[0186] Furthermore, for example, by combining the first and second embodiments, a power supply circuit including the regulator circuits 2 and 2A may be realized.

[0187] In the above embodiments, the power supply circuits 4 and 4A include tracker circuits 1 and 1A for supplying voltage to the power amplifier 7 operating in D-ET mode, but this is not limiting. For example, the power supply circuits 4 and / or 4A may include tracker circuits 1 and / or 1A for supplying voltage to the power amplifier 7 operating in A-ET mode. In this case, the tracker circuits 1 and / or 1A may include a pre-regulator circuit and a linear amplifier circuit instead of the multi-level conversion circuit 100 and the power supply modulation circuit 30. Also, for example, the power supply circuits 4 and / or 4A may include tracker circuits 1 and / or 1A for supplying voltage to the power amplifier operating in SPT mode. In this case, the tracker circuits 1 and / or 1A may include multiple pre-regulator circuits as multi-level conversion circuits.

[0188] In the above-described embodiments, the power supply circuits 4 and 4A supply voltage to two power amplifiers 7 and 8 that amplify two different high-frequency signals (e.g., a 5G NR signal and a 2G GSM signal), but this is not limiting. For example, the power supply circuits 4 and / or 4A may supply voltage to two power amplifiers included in a multi-stage amplifier circuit that amplifies a single high-frequency signal. In this case, the tracker circuits 1 and 1A may supply an output voltage Vout1 to a power amplifier that constitutes the output stage of the multi-stage amplifier circuit, and the regulator circuits 2 and 2A may supply an output voltage Vout2 to a power amplifier that constitutes the input stage of the multi-stage amplifier circuit.

[0189] That is, in each of the above embodiments, the power amplifier 7 may constitute the output stage of a multistage amplifier circuit, and the power amplifier 8 may constitute the input stage of the multistage amplifier circuit.

[0190] This allows the output stage of the multi-stage amplifier circuit to operate in tracking mode. Therefore, the output stage, which consumes more power, can amplify high-frequency signals with high efficiency, improving power-added efficiency. Meanwhile, the input stage of the multi-stage amplifier circuit can operate in fixed voltage mode. Therefore, the input stage, which consumes less power, can be supplied with voltage with high efficiency, improving power efficiency in generating the power supply voltage.

[0191] The features of the power supply circuit and the control method described based on the above embodiments will be described below.

[0192] <1> A power supply circuit comprising: a control terminal for receiving a digital control signal; a tracker circuit configured to supply a first output voltage to a first power amplifier operating in a tracking mode; and a regulator circuit configured to supply a second output voltage to a load, wherein the regulator circuit comprises: an LDO (Low Drop Out) circuit; and a resistor and a switch connected in series between an output terminal of the LDO circuit and ground.

[0193] <2> The power supply circuit according to <1>, further comprising: a control circuit configured to control the switch based on the digital control signal.

[0194] <3> The power supply circuit according to <2>, wherein the control circuit is configured to close the switch when the digital control signal includes control data related to an increase in the output current of the regulator circuit.

[0195] <4> The power supply circuit according to <3>, wherein the control circuit comprises: a digital control circuit configured to obtain control data from the digital control signal; and an analog control circuit configured to generate a control signal that closes the switch when the control data is data related to an increase in the output current of the regulator circuit.

[0196] <5> The power supply circuit according to any one of <1> to <4>, wherein the tracking mode is a digital envelope tracking mode, and the tracker circuit comprises: a multilevel conversion circuit configured to generate a plurality of discrete voltages from an input voltage; and a power supply modulation circuit configured to selectively output at least one of the plurality of discrete voltages to the first power amplifier as the first output voltage.

[0197] <6> The power supply circuit according to <5>, wherein the multilevel conversion circuit comprises: a pre-regulator circuit configured to convert the input voltage into a regulated voltage; and a switched capacitor circuit configured to generate the plurality of discrete voltages from the regulated voltage.

[0198] <7> The power supply circuit according to <5> or <6>, wherein the regulator circuit is configured to generate the second output voltage from one of the plurality of discrete voltages.

[0199] <8> The power supply circuit according to <7>, wherein the regulator circuit is configured to generate the second output voltage from the lowest voltage of the plurality of discrete voltages.

[0200] <9> The power supply circuit according to any one of <1> to <6>, wherein the tracker circuit 1 is configured to generate the first output voltage from an input voltage, and the regulator circuit is configured to generate the second output voltage from the input voltage.

[0201] <10> The power supply circuit according to any one of <1> to <9>, wherein the first power amplifier is configured to amplify a 5GNR (5th Generation New Radio) signal or a 4GLTE (4th Generation Long Term Evolution) signal, and the load is a second power amplifier configured to amplify a 2G GSM (2nd Generation Global System for Mobile communications) signal.

[0202] <11> The power supply circuit according to any one of <1> to <9>, wherein the first power amplifier is configured to amplify a cellular signal, and the load is a second power amplifier configured to amplify a wireless local area network signal.

[0203] <12> The power supply circuit according to any one of <1> to <9>, wherein the first power amplifier constitutes an output stage of a multistage amplifier circuit, and the load is a second power amplifier that constitutes an input stage of the multistage amplifier circuit.

[0204] <13> A control method for a regulator circuit including an LDO circuit and a resistor and a switch connected in series between an output terminal of the LDO circuit and ground, the control method comprising: acquiring a digital control signal; determining whether the acquired digital control signal includes control data related to an increase in an output current of the regulator circuit; and, when it is determined that the digital control signal includes the control data, (i) closing the switch before the output current increases; and (ii) opening the switch after the output current increases.

[0205] The present invention can be widely used in communication devices such as mobile phones as a power supply circuit that supplies voltage to a power amplifier that amplifies high frequency signals.

[0206] 1, 1A Tracker circuit 2, 2A Regulator circuit 3 Control circuit 4, 4A Power supply circuit 5 Transceiver 6 DC power supply 7, 8 Power amplifier 10 Pre-regulator circuit 20 Switched capacitor circuit 30 Power supply modulation circuit 40 LDO circuit 41, T40a, T101, T200, T301, T302, T303, T304, T305, T306 Input terminal 42, 43, T40b, T102, T201, T202, T203, T204, T205, T206, T307 Output terminal 44, 45 Control terminal 51 Digital control circuit 52 Analog control circuit 100 Multi-level conversion circuit 511 First controller 512 Second controller A40 Error amplifier C101 Capacitor C200, C201, C202, C203, C204, C205, C206, C207, C208, C209 Flying capacitors C210, C211, C212, C213, C214, C215 Smoothing capacitors CS10, CS21, CS22, CS30, CS40 Control signal D40 Output driver DS1, DS2 Digital control signal Iout2 Output current L101 Power inductor N1, N2, N3, N4, N5, N6 Node R40 Resistor S40, S101, S102, S103, S104, S200, S201, S202, S203, S204, S205, S206, S207, S208, S209, S210, S211, S212, S213, S214, S215, S216, S217, S218, S219, S220, S221, S222, S223, S301, S302, S303, S304, S305, S306 Switches V1, V2, V3, V4, V5, V6 Voltage Vin Input voltage Vout1, Vout2 Output voltage Vref Reference voltage

Claims

1. A power supply circuit comprising: a control terminal for receiving a digital control signal; a tracker circuit configured to supply a first output voltage to a first power amplifier operating in a tracking mode; and a regulator circuit configured to supply a second output voltage to a load, the regulator circuit comprising: an LDO (Low Drop Out) circuit; and a resistor and a switch connected in series between an output terminal of the LDO circuit and ground.

2. The power supply circuit of claim 1, further comprising: a control circuit configured to control the switch based on the digital control signal.

3. The power supply circuit of claim 2, wherein the control circuit is configured to close the switch when the digital control signal includes control data for increasing an output current of the regulator circuit.

4. The power supply circuit of claim 3, wherein the control circuit comprises: a digital control circuit configured to obtain control data from the digital control signal; and an analog control circuit configured to generate a control signal for closing the switch when the control data is data relating to an increase in the output current of the regulator circuit.

5. A power supply circuit as claimed in any one of claims 1 to 4, wherein the tracking mode is a digital envelope tracking mode, and the tracker circuit comprises: a multi-level conversion circuit configured to generate a plurality of discrete voltages from an input voltage; and a power supply modulation circuit configured to selectively output at least one of the plurality of discrete voltages to the first power amplifier as the first output voltage.

6. The power supply circuit of claim 5, wherein the multi-level conversion circuit comprises: a pre-regulator circuit configured to convert the input voltage to a regulated voltage; and a switched capacitor circuit configured to generate the plurality of discrete voltages from the regulated voltage.

7. A power supply circuit as claimed in claim 5 or 6, wherein the regulator circuit is configured to generate the second output voltage from one of the plurality of discrete voltages.

8. The power supply circuit of claim 7, wherein the regulator circuit is configured to generate the second output voltage from a lowest voltage of the plurality of discrete voltages.

9. A power supply circuit as claimed in any one of claims 1 to 6, wherein the tracker circuit is configured to generate the first output voltage from an input voltage, and the regulator circuit is configured to generate the second output voltage from the input voltage.

10. The power supply circuit according to any one of claims 1 to 9, wherein the first power amplifier is configured to amplify a 5GNR (5th Generation New Radio) signal or a 4GLTE (4th Generation Long Term Evolution) signal, and the load is a second power amplifier configured to amplify a 2G GSM (2nd Generation Global System for Mobile communications) signal.

11. A power supply circuit as claimed in any one of claims 1 to 9, wherein the first power amplifier is configured to amplify a cellular signal, and the load is a second power amplifier configured to amplify a wireless local area network signal.

12. A power supply circuit according to any one of claims 1 to 9, wherein the first power amplifier constitutes an output stage of a multi-stage amplifier circuit, and the load is a second power amplifier that constitutes an input stage of the multi-stage amplifier circuit.

13. A control method for a regulator circuit having an LDO circuit and a resistor and a switch connected in series between an output terminal of the LDO circuit and ground, the control method comprising: acquiring a digital control signal; determining whether the acquired digital control signal includes control data related to an increase in an output current of the regulator circuit; and, if it is determined that the digital control signal includes the control data, (i) closing the switch before the output current increases; and (ii) opening the switch after the output current increases.

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