Semiconductor package

Abstract

This semiconductor package comprises a semiconductor substrate, at least two analog circuit regions, a digital circuit region, and a plurality of conductor parts. The digital circuit region is provided between the two analog circuit regions and is disposed so as to overlap the center line of the semiconductor substrate in plan view. The plurality of conductor parts are electrically connected to a digital circuit in the digital circuit region and are arranged so as to form a plurality of lines along the center line. The plurality of conductor parts include a plurality of control signal conductor parts for controlling a first analog circuit and a second analog circuit. The plurality of control signal conductor parts are arranged in a line along the center line.

Description

Semiconductor Package

[0001] This application claims priority from Japanese Patent Application No. 2023-215118, filed on December 20, 2023, the contents of which are incorporated herein by reference.

[0002] Conventionally, a semiconductor package having an analog circuit and a digital circuit has been known, as disclosed in Patent Document 1. In this semiconductor package, a plurality of analog circuits are arranged asymmetrically with respect to the digital circuit.

[0003] Japanese Patent Application Publication No. 2014-207462

[0004] However, in the conventional semiconductor package described above, there is a difference in the transmission time of a control signal transmitted from a digital circuit to multiple analog circuits. For example, a control signal is transmitted quickly to an analog circuit located near the digital circuit, while the control signal is transmitted with a delay to an analog circuit located farther from the digital circuit. As a result, if the semiconductor package is, for example, a beamforming integrated circuit (IC), the beam direction cannot be determined until the control signal reaches all of the multiple analog circuits. Furthermore, as a measure to determine the beam direction, circuit design is required, such as lengthening the wiring connecting the analog circuit located near the digital circuit to the digital circuit. However, this poses a problem in that the wiring occupies a large area in the circuit design of the semiconductor package.

[0005] Furthermore, the initial evaluation of a beam-forming IC is typically performed with a test probe in contact with multiple terminals arranged in the peripheral region of the beam-forming IC. In such evaluations, signals are often input and output to and from the multiple terminals arranged in the peripheral region. Specifically, the initial evaluation of a beam-forming IC is performed by changing the direction of the test probe relative to the beam-forming IC through procedures such as contacting the test probe with multiple terminals, releasing the contact, repositioning the test probe relative to the beam-forming IC, and then contacting another multiple terminals. The initial evaluation evaluates parameters obtained, such as reflection, transmission, and isolation. Known IC evaluation methods that do not use probes include methods using dedicated probe cards and methods that involve mounting probes on a substrate. However, probe cards are typically used for mass-produced IC testing and are expensive. Mounting probes on a substrate not only requires cost and time for designing and manufacturing the substrate, but also makes it difficult to extract the characteristics of the IC alone because the characteristics of electronic components other than the IC are measured during the evaluation of the substrate.

[0006] The present invention has been made in consideration of the above circumstances, and aims to provide a semiconductor package that can reduce the difference in path length for signals to be transmitted from a digital circuit to multiple analog circuits, thereby enabling simple testing using a single test probe.

[0007] In order to solve the above problem, a semiconductor package according to one aspect of the present invention comprises: a rectangular semiconductor substrate having a first side and a second side intersecting the first side; at least two analog circuit areas arranged on the semiconductor substrate so as to be symmetrical with respect to a center line passing through the center of the semiconductor substrate, and each having an analog circuit; a digital circuit area provided on the semiconductor substrate between the two analog circuit areas, arranged so as to overlap the center line in a planar view, and having a digital circuit that controls the analog circuit; and a plurality of conductors electrically connected to the digital circuit and arranged to form a plurality of rows along the center line, the plurality of conductors including a plurality of control signal conductors that control the analog circuit, and the plurality of control signal conductors being arranged in a row along the center line.

[0008] With this configuration, the path length for a signal to travel from a digital circuit to an analog circuit in one of the two analog circuit areas can be made substantially the same as the path length for a signal to travel from a digital circuit to an analog circuit in the other analog circuit area, thereby making it possible to make the propagation time for a signal output from a digital circuit to be transmitted to multiple analog circuits substantially the same.

[0009] Furthermore, the plurality of control signal conductors for controlling the analog circuit are arranged in a row along the center line. Therefore, the semiconductor package can be inspected by using only one inspection probe and simply contacting the inspection probe with the plurality of control signal conductors arranged in a row along the center line. This allows for quick and easy inspection of the semiconductor package.

[0010] In the semiconductor package according to one aspect of the present invention, the plurality of control signal conductor portions may be arranged on the center line.

[0011] With this configuration, the difference between the path length for a signal to travel from a digital circuit to an analog circuit in one analog circuit area and the path length for a signal to travel from a digital circuit to an analog circuit in the other analog circuit area can be further reduced.The semiconductor package can be inspected by using only one inspection probe and simply contacting the inspection probe with the plurality of control signal conductors arranged on the center line.

[0012] A semiconductor package according to one aspect of the present invention may have a sealing resin portion that covers the semiconductor substrate, and the plurality of conductor portions may penetrate the sealing resin portion to be exposed to the outside of the semiconductor substrate and electrically connected to the digital circuit.

[0013] According to this configuration, a semiconductor package having a sealing resin portion can be realized.

[0014] In a semiconductor package according to one aspect of the present invention, the analog circuit and the digital circuit may constitute a beamforming IC, and the analog circuit may control the phase and amplitude of a signal transmitted to and received from an antenna connected to the beamforming IC to operate the antenna.

[0015] With this configuration, a beamforming IC can be realized. Furthermore, the analog circuit can control the phase and amplitude of signals transmitted to and received from an antenna connected to the beamforming IC to operate the antenna.

[0016] According to the above aspect of the present invention, it is possible to reduce the difference in path length along which a signal travels from a digital circuit to a plurality of analog circuits, thereby enabling simple testing using a single test probe.

[0017] While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments and is not to be construed as limiting the invention.

[0018] A semiconductor package 100 according to an embodiment of the present invention will be described with reference to the drawings. In the description of the embodiment, components having the same or similar functions are designated by the same reference numerals. Duplicate descriptions of these components may be omitted. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. may not necessarily be the same as in reality.

[0019] In the description of the embodiments, ordinal numbers such as "first," "second," and "third" may be used. These ordinal numbers do not indicate the number of components described by the ordinal numbers. Ordinal numbers may be used to indicate that each of multiple components is a separate component. In the description of the semiconductor package 100, the terms "thickness direction," "vertical direction," and "horizontal direction" are used as directional terms. The thickness direction corresponds to the thickness direction of the semiconductor package 100. In the embodiments, the thickness direction corresponds to, for example, the Z direction. Note that the thickness direction and the Z direction may be referred to as "plan view." The vertical direction is one of the directions in which the semiconductor package 100 extends when viewed in a plan view of the semiconductor package 100. In the embodiments, the vertical direction corresponds to, for example, the Y direction. The horizontal direction is one of the directions in which the semiconductor package 100 extends when viewed in a plan view of the semiconductor package 100. The horizontal direction is a direction intersecting the vertical direction. In the embodiments, the horizontal direction corresponds to, for example, the X direction. The terms "thickness direction," "vertical direction," and "horizontal direction" are used to describe the relative positions of the multiple components that make up each semiconductor package 100, or the shape and structure of each of the multiple components, and do not define the posture of each component.

[0020] 1 to 3, the semiconductor package 100 includes a semiconductor substrate 10, a plurality of conductors 30, a sealing resin portion 50, a mold resin (not shown), and a plurality of rewirings (not shown). The semiconductor package 100 is a fan-out wafer level package (FOWLP) semiconductor device. The thickness of the semiconductor package 100, excluding the conductors 30, is 1 mm or less (e.g., approximately 500 μm).

[0021] A method for manufacturing a semiconductor package 100 having such a configuration will be described. One example of the manufacturing method is to arrange multiple semiconductor substrates 10 in a grid pattern, fill the gaps between adjacent semiconductor substrates 10 with molding resin, form rewiring or the like, and then cut the molding resin. This manufacturing method allows multiple semiconductor packages 100 to be efficiently manufactured in a single process. Note that, as with FOWLP, a similar package having a conductor portion 30 and molding resin, such as FC-BGA (Flip Chip-Ball Grid Array) technology, may also be used for the semiconductor package 100.

[0022] <Semiconductor Substrate 10> The semiconductor substrate 10 has two first sides 10X and two second sides 10Y. The second sides 10Y intersect the first sides 10X. In a plan view, the semiconductor substrate 10 has a rectangular shape. In the embodiment, the first sides 10X extend in the horizontal direction, i.e., the X direction. In the embodiment, the second sides 10Y extend in the vertical direction, i.e., the Y direction. In FIG. 2, the symbol CL denotes a center line passing through the center of the semiconductor substrate 10. The center of the semiconductor substrate 10 is the intersection point where the diagonals of the rectangular semiconductor substrate 10 intersect. In the embodiment, the center line CL is parallel to the second sides 10Y. The center line CL extends in the vertical direction, i.e., the Y direction. Note that the direction in which the center line CL extends is not limited to the Y direction. The center line CL may be parallel to the first sides 10X or may extend in the X direction.

[0023] The semiconductor substrate 10 has two surfaces located opposite each other in the thickness direction. One of the two surfaces of the semiconductor substrate 10 is a first surface 10F shown in FIG. 2. As shown in FIG. 2, an analog circuit region 11 and a digital circuit region 12 are provided on the first surface 10F. The other of the two surfaces of the semiconductor substrate 10 is a second surface 10S shown in FIG. 3. FIG. 3 shows a state in which a plurality of conductor portions 30 and a sealing resin portion 50 are provided on the second surface 10S.

[0024] <Analog Circuit Regions 11> In the embodiment, the number of analog circuit regions 11 is two. Therefore, two analog circuit regions 11 are arranged on the semiconductor substrate 10. The two analog circuit regions 11 may be referred to as a first analog circuit region 11F and a second analog circuit region 11S. In the embodiment, a case where the number of analog circuit regions 11 is two will be described, but the number of analog circuit regions 11 is not limited as long as it is an even number greater than or equal to two.

[0025] In this embodiment, the two analog circuit regions 11F and 11S are arranged symmetrically with respect to the center line CL on the semiconductor substrate 10. Each of the two analog circuit regions 11F and 11S has a first analog circuit 11A and a second analog circuit 11B arranged in an array.

[0026] The analog circuit area 11F has four first analog circuits 11A and two second analog circuits 11B. The second analog circuits 11B extend in the X direction. A first area A1 and a second area A2 are set on either side of the second analog circuit 11B in the Y direction. The first area A1 has two first analog circuits 11A lined up in the X direction. The second area A2 has two first analog circuits 11A lined up in the X direction. With this configuration, the analog circuit area 11F has four first analog circuits 11A.

[0027] The analog circuit area 11S has four first analog circuits 11A and two second analog circuits 11B. The second analog circuits 11B extend in the X direction. A first area A1 and a second area A2 are set on either side of the second analog circuit 11B in the Y direction. The first area A1 has two first analog circuits 11A lined up in the X direction. The second area A2 has two first analog circuits 11A lined up in the X direction. With this configuration, the analog circuit area 11S has four first analog circuits 11A.

[0028] In the example shown in Fig. 2, a total of eight first analog circuits 11A are arranged. In Fig. 2, the number of first analog circuits 11A is not limited to eight, and the number of first analog circuits 11A can be selected depending on the configuration of the beamforming IC. The configurations of the first analog circuits 11A and the second analog circuits 11B will be described later.

[0029] <Digital Circuit Area 12> The digital circuit area 12 is provided between the two analog circuit areas 11F and 11S on the semiconductor substrate 10. The digital circuit area 12 is arranged to overlap the center line CL in a plan view. The digital circuit area 12 has a digital circuit 12A that controls the first analog circuit 11A and the second analog circuit 11B.

[0030] <Conductor 30> In the semiconductor package 100, which is a FOWLP type semiconductor device, the multiple conductors 30 correspond to solder bumps. As shown in FIG. 3 , the multiple conductors 30 include multiple central conductors 30C and multiple peripheral conductors 30E. The multiple central conductors 30C are electrically connected to the digital circuit 12A. The multiple central conductors 30C are arranged to form multiple rows along the center line CL. Each of the multiple rows extends in the Y direction. The multiple rows are aligned in the X direction. In the example shown in FIG. 3 , the number of rows is two. The number of rows may be three or more.

[0031] The peripheral conductors 30E are not electrically connected to the digital circuit 12A. The peripheral conductors 30E are not terminals for controlling the digital circuit 12A. The peripheral conductors 30E include, for example, the following terminals (A) to (C): (A) a terminal for supplying power to the first analog circuit 11A and the second analog circuit 11B; (B) a terminal for inputting and outputting signals to and from the antenna; and (C) a GND terminal of the analog circuit.

[0032] The central conductors 30C are conductors located in the area surrounded by the dotted line in Fig. 3. The central conductors 30C further include control signal conductors 30S that control the first analog circuit 11A and the second analog circuit 11B. The control signal conductors 30S are arranged in a line along the center line CL. In other words, the control signal conductors 30S are arranged in a line in the Y direction.

[0033] The multiple central conductor portions 30C include the following terminals (1) to (5): (1) Data terminal (2) Address terminal (3) Clock terminal (4) GND terminal (5) Power supply terminal The data terminal is a signal terminal for controlling the analog circuit. The address terminal is a terminal for selecting or recognizing the eight analog circuits that make up the beamforming IC. The clock terminal is a terminal used when inputting a clock signal to the digital circuit 12A. The power supply terminal is a terminal used when supplying power to the digital circuit 12A. One of multiple voltages (1.2V, 1.8V, etc.) is supplied to the power supply terminal.

[0034] The plurality of control signal conductor sections 30S include, among the terminals (1) to (5) above, (1) a data terminal, (3) a clock terminal, (4) a GND terminal, and (5) a power supply terminal. Signals input to the plurality of control signal conductor sections 30S are input to the digital circuit 12A and control the digital circuit 12A. In response to signals input from the plurality of control signal conductor sections 30S, the digital circuit 12A can control the first analog circuit 11A and the second analog circuit 11B. The signals input to the plurality of control signal conductor sections 30S can control the phase and amplitude of signals transmitted from an antenna and signals received by an antenna.

[0035] <Sealing resin portion 50> The sealing resin portion 50 covers the second surface 10S of the semiconductor substrate 10. The plurality of central conductor portions 30C penetrate the sealing resin portion 50 and are exposed to the outside of the semiconductor substrate 10. The central conductor portions 30C that penetrate the sealing resin portion 50 are electrically connected to the digital circuit 12A.

[0036] 1, a horizontal polarization circuit unit 13H, a vertical polarization circuit unit 13V, and one digital circuit 12A are provided on the first surface 10F of the semiconductor substrate 10. The horizontal polarization circuit unit 13H has eight first analog circuits 11A for horizontal polarization and one second analog circuit 11B for horizontal polarization. The vertical polarization circuit unit 13V has eight first analog circuits 11A for vertical polarization and one second analog circuit 11B for vertical polarization (not shown). The horizontal polarization circuit unit 13H, the vertical polarization circuit unit 13V, and the digital circuit 12A constitute a beamforming IC.

[0037] The eight first analog circuits 11A and one second analog circuit 11B constituting each of the horizontal polarization circuit section 13H and the vertical polarization circuit section 13V are stacked, for example, in the thickness direction of the semiconductor substrate 10 shown in FIG. 2 with an interlayer insulating film interposed therebetween. A portion of the digital circuit 12A may be provided inside the semiconductor substrate 10 with an interlayer insulating film interposed therebetween. A portion of the digital circuit region 12 may be provided inside the semiconductor substrate 10.

[0038] In the following description, for simplicity, one of the eight first analog circuits 11A for horizontal polarization and one second analog circuit 11B for horizontal polarization will be described. The first analog circuit 11A and second analog circuit 11B and antenna 14 constituting the vertical polarization basically have the same configuration as the analog circuits and antennas for horizontal polarization. Therefore, a description of the eight analog circuits and antennas for vertical polarization will be omitted.

[0039] The first analog circuit 11A and the second analog circuit 11B control the phase and amplitude of signals transmitted to and received from the antenna 14 connected to the beamforming IC, thereby operating the antenna 14.

[0040] The first analog circuit 11A includes a phase shifter 21, switches 22A and 22B, a transmitting-side variable gain amplifier 23T, a receiving-side variable gain amplifier 23R, a low-noise amplifier 24R, and a power amplifier 24T. A first terminal of the phase shifter 21 is connected to a first terminal of the switch 22A. A second terminal of the phase shifter 21 is connected to a distributor / synthesizer 27 of the second analog circuit 11B. A first terminal of the switch 22A is connected to the first terminal of the phase shifter 21. A second terminal of the switch 22A is connected to a first terminal of the transmitting-side variable gain amplifier 23T. A third terminal of the switch 22A is connected to a first terminal of the receiving-side variable gain amplifier 23R. A first terminal of the transmitting-side variable gain amplifier 23T is connected to a second terminal of the switch 22A. A second terminal of the transmitting-side variable gain amplifier 23T is connected to a first terminal of the power amplifier 24T. A first terminal of the power amplifier 24T is connected to a second terminal of the transmitting-side variable gain amplifier 23T. The second terminal of the power amplifier 24T is connected to the second terminal of the switch 22B. The first terminal of the receiving-side variable gain amplifier 23R is connected to the third terminal of the switch 22A. The second terminal of the receiving-side variable gain amplifier 23R is connected to the first terminal of the low-noise amplifier 24R. The first terminal of the low-noise amplifier 24R is connected to the second terminal of the receiving-side variable gain amplifier 23R. The second terminal of the low-noise amplifier 24R is connected to the third terminal of the switch 22B. The first terminal of the switch 22B is connected to the antenna 14. The second terminal of the switch 22B is connected to the second terminal of the power amplifier 24T. The third terminal of the switch 22B is connected to the second terminal of the low-noise amplifier 24R. Each of the switches 22A and 22B can change the connection state in the first analog circuit 11A depending on whether the antenna 14 is used for signal transmission or whether the antenna 14 is used for signal reception.

[0041] The second analog circuit 11B includes switches 25A and 25B, a power amplifier 26T, a low-noise amplifier 26R, and a distributor / synthesizer 27. A first terminal of the switch 25A is connected to electronic components external to the semiconductor package 100. The first terminal of the switch 25A is connected to, for example, a frequency conversion integrated circuit (FCIC). A second terminal of the switch 25A is connected to a first terminal of the power amplifier 26T. A third terminal of the switch 25A is connected to a first terminal of the low-noise amplifier 26R. A first terminal of the power amplifier 26T is connected to a second terminal of the switch 25A. A second terminal of the power amplifier 26T is connected to a second terminal of the switch 25B. A first terminal of the low-noise amplifier 26R is connected to a third terminal of the switch 25A. A second terminal of the low-noise amplifier 26R is connected to a third terminal of the switch 25B. A first terminal of the switch 25B is connected to the distributor / synthesizer 27. A second terminal of the switch 25B is connected to the second terminal of the power amplifier 26T. A third terminal of the switch 25B is connected to the second terminal of the low-noise amplifier 26R. The distributor / synthesizer 27 is connected to each of the eight first analog circuits 11A and the switch 25B.

[0042] <Operation of Semiconductor Package 100> The operation of the semiconductor package 100 will be described. First, the operation when the semiconductor package 100 transmits a signal will be described. The signal output from the frequency conversion IC is input to the second analog circuit 11B. In the second analog circuit 11B, switches 25A and 25B switch the electrical connection. When the semiconductor package 100 transmits a signal, the input signal input to the second analog circuit 11B is amplified by the power amplifier 26T and input to the distributor / synthesizer 27. The distributor / synthesizer 27 outputs the signal to the eight first analog circuits 11A.

[0043] The output signal from the second analog circuit 11B is input to the phase shifter 21 of the first analog circuit 11A. The phase of the signal is adjusted in the phase shifter 21. The switches 22A and 22B switch the electrical connections, and the phase-adjusted signal is amplified by the transmitting-side variable gain amplifier 23T and the power amplifier 24T. The amplified signal is output from the first analog circuit 11A to the antenna 14.

[0044] Next, the operation of the semiconductor package 100 when receiving a signal will be described. The signal received by the antenna 14 is input to the first analog circuit 11A. In the first analog circuit 11A, the switches 22A and 22B switch the electrical connections, and the received signal is amplified by the low-noise amplifier 24R and the receiving-side variable gain amplifier 23R. The amplified signal is input to the phase shifter 21, and the phase of the signal is adjusted by the phase shifter 21. The phase shifter 21 outputs the signal to the second analog circuit 11B.

[0045] The output signal output from the first analog circuit 11A is input to the distributor / synthesizer 27 of the second analog circuit 11B. In the second analog circuit 11B, switches 25A and 25B switch the electrical connection. When the semiconductor package 100 receives a signal, the input signal input to the distributor / synthesizer 27 is amplified by the low-noise amplifier 26R and output from the second analog circuit 11B to the frequency conversion IC.

[0046] Such signal transmission and reception operations in the semiconductor package 100 are performed in the first analog circuit region 11F and the second analog circuit region 11S on the semiconductor substrate 10 shown in FIG.

[0047] <Effects> According to the semiconductor package 100 of the above-described embodiment, the path length (first path length) over which a signal is transmitted from the digital circuit 12A to the first analog circuit 11A in the first analog circuit area 11F can be made substantially equal to the path length (second path length) over which a signal is transmitted from the digital circuit 12A to the first analog circuit 11A in the second analog circuit area 11S. Furthermore, the path length (third path length) over which a signal is transmitted from the digital circuit 12A to the second analog circuit 11B in the first analog circuit area 11F can be made substantially equal to the path length (fourth path length) over which a signal is transmitted from the digital circuit 12A to the second analog circuit 11B in the second analog circuit area 11S. In other words, the difference between the multiple path lengths between the multiple analog circuits 11A, 11B and the digital circuit 12A can be reduced. This allows the transmission times of signals output from the digital circuit 12A to the multiple analog circuits 11A, 11B to be made substantially equal.

[0048] Furthermore, the plurality of control signal conductors 30S that control the first analog circuit 11A and the second analog circuit 11B are arranged in a row along the center line CL. Therefore, the semiconductor package 100 can be easily inspected by simply contacting a single inspection probe with the plurality of control signal conductors 30S arranged in a row along the center line CL. Inspection of such a semiconductor package 100 does not require the conventional procedures of contacting the inspection probe with multiple terminals, releasing the contact, repositioning the inspection probe relative to the semiconductor package 100, and then contacting another plurality of terminals. This significantly reduces the number of complicated inspection processes.

[0049] <Modification> In the above-described embodiment, the multiple control signal conductors 30S are arranged in a line along the center line CL. The multiple control signal conductors 30S may also be arranged on the center line CL. This configuration can further reduce the difference between the path length (first path length) over which a signal is transmitted from the digital circuit 12A to the first analog circuit 11A in the first analog circuit area 11F and the path length (second path length) over which a signal is transmitted from the digital circuit 12A to the first analog circuit 11A in the second analog circuit area 11S. Furthermore, the difference between the path length (third path length) over which a signal is transmitted from the digital circuit 12A to the second analog circuit 11B in the first analog circuit area 11F and the path length (fourth path length) over which a signal is transmitted from the digital circuit 12A to the second analog circuit 11B in the second analog circuit area 11S can further reduce. Therefore, the effects achieved by the above-described embodiment can be further enhanced. Furthermore, similar to the above-described embodiment, the semiconductor package can be inspected by using only one inspection probe to inspect the semiconductor package, and simply contacting the inspection probe with a plurality of control signal conductor portions arranged on the center line.

[0050] While preferred embodiments of the present invention have been described and illustrated above, it should be understood that these are illustrative of the present invention and should not be considered as limiting. Additions, omissions, substitutions, and other modifications can be made without departing from the scope of the present invention. Accordingly, the present invention should not be deemed limited by the foregoing description, but rather by the scope of the claims.

[0051] In the above-described embodiment, the semiconductor package 100 constitutes a beamforming IC. However, the present invention is not limited to the semiconductor package 100 being a beamforming IC. The present invention is applicable to semiconductor packages in general that have analog and digital circuits. In particular, in the present invention, multiple control signal conductors that control the analog circuit are arranged in a single row, making it possible to easily inspect the semiconductor package using an inspection probe. Therefore, the present invention is effective for inspecting semiconductor packages in general with respect to inspection using an inspection probe.

[0052] 10...semiconductor substrate, 10F...first surface, 10S...second surface, 10X...first side, 10Y...second side, 11...analog circuit area, 11A...first analog circuit (analog circuit), 11B...second analog circuit (analog circuit), 11F...first analog circuit area (analog circuit area), 11S...second analog circuit area (analog circuit area), 12...digital circuit area, 12A...digital circuit, 13H...horizontal polarization circuit section, 13V...vertical polarization circuit section, 14...antenna NA, 21...phase shifter, 22A...switch, 22B...switch, 23R...receiving side variable gain amplifier, 23T...transmitting side variable gain amplifier, 24R...low noise amplifier, 24T...power amplifier, 25A...switch, 25B...switch, 26R...low noise amplifier, 26T...power amplifier, 27...divider / combiner, 30...conductor portion, 30C...central conductor portion, 30E...peripheral conductor portion, 30S...control signal conductor portion, 50...encapsulating resin portion, 100...semiconductor package, CL...center line

Claims

1. A semiconductor package comprising: a rectangular semiconductor substrate having a first side and a second side intersecting the first side; at least two analog circuit regions arranged on the semiconductor substrate to be symmetrical with respect to a center line passing through the center of the semiconductor substrate, each having an analog circuit; a digital circuit region provided between the two analog circuit regions on the semiconductor substrate, arranged overlapping the center line in a plan view, and having a digital circuit controlling the analog circuit; and a plurality of conductor parts electrically connected to the digital circuit and arranged to form a plurality of rows along the center line, wherein the plurality of conductor parts include a plurality of control signal conductor parts which control the analog circuit, and the plurality of control signal conductor parts are arranged in a row along the center line.

2. The semiconductor package according to claim 1, wherein the plurality of control signal conductor portions are arranged on the center line.

3. The semiconductor package according to claim 1 or 2, further comprising a sealing resin portion covering the semiconductor substrate, wherein the plurality of conductor portions penetrate the sealing resin portion, are exposed to the outside of the semiconductor substrate, and are electrically connected to the digital circuit.

4. The semiconductor package according to claim 1 or 2, wherein the analog circuit and the digital circuit constitute a beamforming IC, and the analog circuit controls the phase and amplitude of a signal transmitted to and received from an antenna connected to the beamforming IC to operate the antenna.

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