Multilayer wiring board and method for producing same

Abstract

This multilayer wiring board includes a first resin layer, a second resin layer that overlaps with the first resin layer in a plan view, at least one intermediate resin layer that is positioned between the first resin layer and the second resin layer, and at least one conductive via that is provided in the at least one intermediate resin layer. The first resin layer forms the outermost layer on the first surface side, the second resin layer forms the outermost layer on the second surface side that is opposite to the first surface side, and the Young's modulus of the first resin layer and the second resin layer has a higher value than the Young's modulus of the intermediate resin layer.

Description

Multilayer wiring board and method for manufacturing the same

[0001] An embodiment of the present invention relates to a structure of a multilayer wiring board for achieving electrical continuity between circuits on the front and back sides and relaying between circuits, and a method for manufacturing the multilayer wiring board.

[0002] When electrically connecting a semiconductor element manufactured by a wafer process to a printed wiring board, an intermediate substrate for pitch conversion called an interposer (also called a multilayer wiring substrate or interposer) is used. For example, an interposer (glass interposer) having multiple wiring layers and multiple microbumps formed on a glass substrate is disclosed (see Patent Document 1). Also disclosed is an interposer having a first core having a first through-hole electrode formed thereon, a second core having a second through-hole electrode formed thereon, and wiring connecting the first through-hole electrode and the second through-hole electrode formed thereon (see Patent Document 2).

[0003] International Publication No. 2001 / 082666 Japanese Patent Application Laid-Open No. 2017-130571

[0004] The method of manufacturing an interposer involves forming an interlayer insulating layer and conductive vias on a silicon wafer to create multiple layers, but this method has problems in terms of productivity and manufacturing costs.In addition, there is also an interposer that uses a rewiring layer of a resin substrate (RDL interposer) instead of a silicon interposer, but with the improvement of mounting accuracy, there is a demand for it to be free of warping and have high flatness.

[0005] A multilayer wiring board according to one embodiment of the present invention includes a first resin layer, a second resin layer overlapping the first resin layer in a planar view, at least one intermediate resin layer between the first and second resin layers, and at least one conductive via provided in the at least one intermediate resin layer, wherein the first resin layer forms the outermost layer on a first surface side, and the second resin layer forms the outermost layer on a second surface side opposite the first surface, and the Young's moduli of the first and second resin layers are higher than the Young's modulus of the intermediate resin layer.

[0006] A method for manufacturing a multilayer wiring board according to one embodiment of the present invention is a method for manufacturing a multilayer wiring board having a first resin layer, a second resin layer overlapping the first resin layer in a planar view, at least one intermediate resin layer between the first resin layer and the second resin layer, and at least one conductive via provided in the at least one intermediate resin layer, and includes forming the first resin layer by applying a non-photosensitive resin composition onto a glass substrate and baking it, forming the second resin layer from a thermosetting organic-inorganic composite material, and forming at least one intermediate resin layer from a photosensitive resin material.

[0007] A multilayer wiring board according to one embodiment of the present invention includes a first resin layer formed of a non-photosensitive material or a photosensitive material, a second resin layer overlapping the first resin layer in a planar view and formed of a thermosetting organic-inorganic composite material, at least one intermediate resin layer formed of a photosensitive material between the first resin layer and the second resin layer, and at least one conductive via provided in the at least one intermediate resin layer, wherein the first resin layer forms the outermost layer on the first surface side, and the second resin layer forms the outermost layer on the second surface side opposite the first surface side.

[0008] FIG. 1 shows a cross-sectional view of a multilayer wiring board according to one embodiment of the present invention. FIG. 2 shows a cross-sectional view of a multilayer wiring board according to one embodiment of the present invention. FIG. 3 shows a cross-sectional view illustrating a method for manufacturing a multilayer wiring board according to one embodiment of the present invention. FIG. 4 shows a cross-sectional view illustrating a method for manufacturing a multilayer wiring board according to one embodiment of the present invention. FIG. 5 shows a cross-sectional view illustrating a method for manufacturing a multilayer wiring board according to one embodiment of the present invention. FIG. 6 shows a cross-sectional view illustrating a method for manufacturing a multilayer wiring board according to one embodiment of the present invention. FIG. 7 shows a cross-sectional view illustrating a method for manufacturing a multilayer wiring board according to one embodiment of the present invention. FIG. 8 shows a cross-sectional view of a multilayer wiring board according to one embodiment of the present invention. FIG. 9 shows a cross-sectional view of a multilayer wiring board according to one embodiment of the present invention. FIG. 10 shows a cross-sectional view of a multilayer wiring board according to one embodiment of the present invention.

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different forms, and should not be construed as being limited to the description of the following exemplary embodiments. For clarity of explanation, the drawings may show schematic representations of the width, thickness, shape, etc. of each part compared to the actual form. However, these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, elements similar to those previously described with reference to the preceding drawings are designated by the same reference numerals (or reference numerals with A, B, etc. suffixed thereto), and detailed descriptions may be omitted as appropriate. Furthermore, the letters "first" and "second" attached to each element are convenient labels used to distinguish each element and have no further meaning unless otherwise specified.

[0010] In this specification, when a component or region is referred to as being "on (or under)" another component or region, unless otherwise specified, this includes not only the case where it is directly above (or directly under) the other component or region, but also the case where it is above (or under) the other component or region, i.e., the case where another component is included between the component or region and above (or under) the other component or region.

[0011] [First Embodiment] This embodiment shows the configuration of a multilayer wiring board having an intermediate resin layer made of a photosensitive material between a first resin layer and a second resin layer made of a non-photosensitive resin material. The multilayer wiring board shown in this embodiment is a redistribution board that connects an integrated circuit (or circuit board) on an upper layer to an integrated circuit (or circuit board) on a lower layer, and is also called an RDL (Redistribution Layer) interposer.

[0012] 1 shows a cross-sectional view of a multilayer wiring board 100 according to one embodiment of the present invention. The multilayer wiring board 100 includes a first resin layer D10, a second resin layer BSR, at least one intermediate resin layer D20 sandwiched between the first resin layer D10 and the second resin layer BSR, and at least one conductive via.

[0013] In this embodiment, the intermediate resin layer D20 refers to a layer provided between the first resin layer D10 and the second resin layer BSR, and there is no limit to the number of layers that can be stacked. Furthermore, conductive vias and wiring are appropriately provided within the intermediate resin layer D20. Fig. 1 shows an embodiment in which at least one intermediate resin layer D20 is composed of a first intermediate resin layer D21 and a second intermediate resin layer D22, with first conductive vias V11 and V12 provided in the first resin layer D10, second conductive vias V21 and V22 provided in the first intermediate resin layer D21, and a third conductive via V31 provided in the second intermediate resin layer D22.

[0014] The second resin layer BSR is disposed so as to overlap the first resin layer D10 in a planar view. The first resin layer D10 is the outermost layer on one surface (first surface) of the multilayer wiring substrate 100, and the second resin layer BSR is the outermost layer on the other surface (second surface (the surface opposite to the first surface)) of the multilayer wiring substrate 100. The first intermediate resin layer D21 and the second intermediate resin layer D22 are disposed so as to be sandwiched between the first resin layer D10 and the second resin layer BSR. The number of layers of the intermediate resin layer D20 is not limited to two, and may be one layer, or may have a structure in which three or more layers are stacked.

[0015] The first conductive vias V11 and V12 are conductive members provided in first via holes TH11 and TH12 that penetrate the first resin layer D10. The second conductive vias V21 and V22 are conductive members provided in second via holes TH21 and TH22 that penetrate the first intermediate resin layer D21, and the third conductive via V31 is a conductive member that penetrates the second intermediate resin layer D22 and is provided so as to protrude into the second resin layer BSR. The first conductive vias V11 and V12, the second conductive vias V21 and V22, and the third conductive via V31 are formed of a metal material and are provided so as to fill each via hole.

[0016] Each conductive via may be arranged to form an electrical connection with a via on an upper or lower layer. For example, as shown in FIG. 1 , second conductive vias V21 and V22 may be arranged to be connected above first conductive vias V11 and V12, respectively, and a third conductive via V31 may be arranged to be connected above the second conductive via V22. Although not shown in FIG. 1 , wiring for forming rewiring may be appropriately connected to each via. The wiring is formed from the same conductive layer as the conductive layer forming each via.

[0017] The multilayer wiring substrate 100 is fabricated on a glass substrate 150, and is peeled off from the glass substrate 150 after each layer is formed. An alkali-free glass substrate is preferably used as the glass substrate 150. The glass substrate 150 can also be a large-area glass substrate (mother glass substrate) such as that used in the manufacture of liquid crystal displays. By using such a large-area glass substrate, multiple multilayer wiring substrates 100 can be fabricated on a single glass substrate, and productivity can be increased by singulating them in the final stage of the process.

[0018] Although the present embodiment uses a glass substrate 150 as an example, substrates that can be used to manufacture the multilayer wiring substrate 100 are not limited to glass substrates, and semiconductor substrates such as silicon wafers, ceramic substrates, quartz substrates, etc. can also be used.

[0019] After the multilayer wiring substrate 100 is peeled off from the glass substrate 150, the first conductive vias V11 and V12 are exposed on the outer surface on the side of the first resin layer D10. On the other hand, the third conductive via V31 is covered with the second resin layer BSR, but the first opening OP1 is provided, thereby forming a structure in which it is exposed to the outside.

[0020] 2 shows a structure in which first bumps BP11 and BP12 electrically connected to first conductive vias V11 and V12 are provided on the first resin layer D10 side, and a second bump BP21 electrically connected to a third conductive via V31 is provided on the second resin layer BSR side. The first bumps BP11 and BP12 are provided to form an electrical connection with a first integrated circuit (or a first circuit board) 202, and the second bump BP21 is provided to form an electrical connection with a second integrated circuit (or a second circuit board) 204. The first bumps BP11 and BP12 and the second bump BP21 can be formed using a metal material such as solder, gold (Au), or copper (Cu).

[0021] Referring again to FIG. 1 , the first resin layer D10, the second resin layer BSR, and the intermediate resin layer D20 (first intermediate resin layer D21, second intermediate resin layer D22) are layers formed of a resin material. The first resin layer D10 and the second resin layer BSR are formed of a material having a higher Young's modulus than the intermediate resin layer D20 (first intermediate resin layer D21, second intermediate resin layer D22). For example, the Young's modulus of the first resin layer D10 and the second resin layer BSR is 5 GPa or more, preferably 7 GPa or more. On the other hand, the Young's modulus of the intermediate resin layer D20 (first intermediate resin layer D21, second intermediate resin layer D22) may be less than 5 GPa.

[0022] When the first resin layer D10 and the second resin layer BSR have such Young's modulus, the rigidity of the multilayer wiring substrate 100 can be increased and flatness can be ensured. The resin layer is produced by applying a composition containing a precursor of a predetermined resin material (hereinafter also referred to as a "resin composition") to the substrate and curing it. Resin compositions are broadly classified into photocurable resin compositions and thermosetting resin compositions. Of these, it is considered preferable to use a thermosetting resin composition that does not contain a photosensitive group in order to obtain a high Young's modulus.

[0023] Therefore, it is preferable to form the first resin layer D10 using a non-photosensitive resin composition. In other words, it is preferable to form the first resin layer D10 using a thermosetting resin composition. For example, the first resin layer D10 can be formed using a non-photosensitive (thermosetting) polyimide. Such a first resin layer D10 is a resin layer containing imide ring bonds and not containing photosensitive groups. Since the first resin layer D10 does not contain photosensitive groups, the Young's modulus can be increased. That is, a resin layer formed using a non-photosensitive polyimide can have a Young's modulus of, for example, 7 GPa or more, e.g., 7.7 GPa. The Young's modulus varies depending on the preparation conditions (such as the baking temperature) of the non-photosensitive polyimide resin composition, but in this embodiment, the Young's modulus should be 5 GPa or more, preferably 7 GPa or more.

[0024] The first resin layer D10 formed from a non-photosensitive resin composition (thermosetting resin composition) has internal stress, and this internal layer stress is tensile stress. For example, if the first resin layer D10 is formed from a non-photosensitive polyimide resin composition, the tensile stress will be approximately 20 MPa. If the first resin layer D10 has tensile stress, this will cause the glass substrate 150 to warp during manufacturing, and will also cause the multilayer wiring substrate 100 to warp after manufacturing (after peeling it from the glass substrate 150).

[0025] 1, it is preferable to provide a first inorganic insulating layer D12 having a compressive stress on the first resin layer D10. That is, by providing the first inorganic insulating layer D12 having a compressive stress, the tensile stress of the first resin layer D10 can be offset, and warping of the glass substrate 150 during manufacturing and warping of the multilayer wiring substrate 100 after manufacturing can be prevented.

[0026] The first inorganic insulating layer D12 may be, for example, a silicon nitride layer. The silicon nitride layer may be fabricated by vapor deposition (plasma CVD), and the compressive stress may be retained by controlling the deposition conditions. For example, the compressive stress may be imparted by increasing the film density of the silicon nitride layer.

[0027] The first resin layer D10 is provided with first via holes TH11 and TH12. When the first resin layer D10 is made using a non-photosensitive resin composition, forming the first via holes TH11 and TH12 requires creating a mask by photolithography and forming openings by etching. When the first inorganic insulating layer D12 is provided, openings must also be formed in this layer. When the first inorganic insulating layer D12 is formed of a silicon nitride layer, openings can be formed relatively easily by dry etching using a fluorine-based etching gas. The first inorganic insulating layer D12 can then be used as a hard mask for the subsequent etching of the first resin layer D10. Because the hard mask has higher etching resistance than a mask made of a resist material, the sidewalls of the first via holes TH11 and TH12 can be formed nearly vertically.

[0028] Like the first resin layer D10, the second resin layer BSR is also made of a thermosetting resin material. The second resin layer BSR can be formed using an organic-inorganic hybrid material composed of an organic material and an inorganic material. For example, the second resin layer BSR can be formed using a coating-type thermosetting epoxy resin composition containing an epoxy resin, an active ester compound containing a naphthalene structure, and an inorganic filler.

[0029] The second resin layer BSR may be provided as a film- or sheet-like intermediate material called a prepreg (a prepreg that does not contain glass fiber) formed from the above-described thermosetting epoxy resin material, and may be formed by attaching it to the intermediate resin layer D20 and thermally curing it. Alternatively, the second resin layer BSR may be produced by applying the above-described thermosetting epoxy resin composition onto the intermediate resin layer D20 and thermally curing it. By forming the second resin layer BSR from such a material, the layer thickness is greater than that of the first resin layer D10.

[0030] By using such a thermosetting resin material, the second resin layer BSR can have a Young's modulus of 7 to 13 GPa.

[0031] The intermediate resin layer D20 (first intermediate resin layer D21, second intermediate resin layer D22) is formed of a photosensitive resin material. Phenol-based or polyimide-based resin materials can be used as the photosensitive resin material. The intermediate resin layer D20 (first intermediate resin layer D21, second intermediate resin layer D22) can be formed by applying a resin composition containing a precursor of the photosensitive resin material and a photosensitive group as described above, exposing it to light, developing it, and baking it. Both positive-type (exposed portions have increased solubility in a developer and are removed, while unexposed portions remain) and negative-type (exposed portions have decreased solubility in a developer and remain, while unexposed portions are removed) photosensitive resin compositions can be used.

[0032] The second via holes TH21 and TH22 are formed simultaneously in the process of exposing and developing the first intermediate resin layer D21, and the third via hole TH31 is formed simultaneously in the process of exposing and developing the second intermediate resin layer D22. For example, when a positive resin composition is used, the respective via holes can be formed by exposing using a photomask that exposes the portions of the second via holes TH21 and TH22 and the third via hole TH31, and then developing.

[0033] The first conductive vias V11 and V12, the second conductive vias V21 and V22, and the third conductive via V31 are formed of conductive materials such as copper (Cu), tungsten (W), polysilicon, etc. Among these, copper (Cu) is a preferred material from the viewpoint of reducing the resistance of the vias. Such conductive vias are formed, for example, by an electrolytic plating method. Although the details of the manufacturing process will be described later, the first conductive vias V11 and V12, the second conductive vias V21 and V22, and the third conductive via V31 can be formed by forming a seed layer by a sputtering method, then forming a mask pattern using a resist, and then forming a plating layer by electrolytic plating (semi-additive method) so as to fill the via holes in the corresponding regions.

[0034] In the multilayer wiring board 100 according to this embodiment, the Young's modulus of the first resin layer D10 and the second resin layer BSR located on the outermost layers is higher than that of the intermediate resin layer D20 formed of a photosensitive material, which prevents warping, provides excellent flatness when viewed as a whole, and also improves flatness when viewed microscopically (when viewed in terms of the size of the components to be mounted). This improves the mounting accuracy of the semiconductor integrated circuits (or circuit boards) mounted on the upper and lower sides of the multilayer wiring board 100.

[0035] Next, a method for manufacturing the multilayer wiring board 100 shown in Fig. 1 will be described. Here, an example is shown in which the first resin layer D10 and the second resin layer BSR are made of a non-photosensitive resin material, the intermediate resin layer D20 is made of a photosensitive resin material, and the first conductive vias V11 and V12, the second conductive vias V21 and V22, and the third conductive via V31 are made by a semi-additive method.

[0036] 3A shows a step of forming a sacrificial layer AL01 on a glass substrate 150, and then forming a first resin layer D10 and a first inorganic insulating layer D12 thereon. The sacrificial layer AL01 is provided to peel the multilayer wiring substrate 100 from the glass substrate 150 after the multilayer wiring substrate 100 is formed on the glass substrate 150. The sacrificial layer AL01 is made of, for example, a hydrogenated amorphous silicon film. The hydrogenated amorphous silicon can be produced by silane (SiH ４ ) and hydrogen (H ２ However, depending on the patterning, if peeling can be performed without using the sacrificial layer AL01, it may be omitted.

[0037] Alternatively, the sacrificial layer AL01 may be formed of a resin material. For example, the sacrificial layer AL01 may be formed by applying a polyimide varnish containing a soluble polyimide resin, a thermosetting crosslinking agent, and a solvent, and then performing a heat treatment at a temperature lower than the crosslinking initiation temperature of the crosslinking agent.

[0038] The first resin layer D10 is formed from a thermosetting (non-photosensitive) polyimide material to a thickness of 3 μm to 10 μm, for example, 5 μm. Specifically, the first resin layer D10 is formed by applying a composition containing a polyimide precursor (not containing photosensitive groups) onto the sacrificial layer AL01 and then baking it. The baking temperature is preferably in the range of 350°C to 450°C. While thermosetting polyimide compositions can be baked at temperatures above 500°C, temperatures above 450°C can significantly release hydrogen from the hydrogenated amorphous silicon layer formed as the sacrificial layer AL01, potentially preventing successful peeling during the peeling process. Therefore, baking within the above temperature range is preferred. As described above, the first resin layer D10 is formed from a material with a higher Young's modulus than the intermediate resin layer D20 (first intermediate resin layer D21, second intermediate resin layer D22) formed in a later process.

[0039] A silicon nitride film is formed as the first inorganic insulating layer D12 on the first resin layer D10. The silicon nitride film is formed by silane (SiH ４ ), ammonia (NH ３ ), nitrogen (N ２ The silicon nitride film may be formed by vapor deposition (plasma CVD) using a silicon nitride film. The silicon nitride film may also be formed by sputtering.

[0040] 3B shows the step of forming first via holes TH11 and TH12 in the first resin layer D10 and the first inorganic insulating layer D12, and then forming a seed layer 120. Because the first resin layer D10 is formed from a non-photosensitive resin composition, the first via holes TH11 and TH12 are formed by etching. Specifically, a resist mask is formed on the first inorganic insulating layer D12 by photolithography, and the first inorganic insulating layer D12 is then etched. If the first inorganic insulating layer D12 is formed from a silicon nitride film, dry etching can be performed using a fluorine-based etching gas. Then, the first resin layer D10 is etched using the first inorganic insulating layer D12 as a hard mask. If the first resin layer D10 is formed from polyimide, CF is used as the etching gas. ４ , S.F. ６ , N.F. ３ Fluorine-based gases such as oxygen (O ２) or oxygen (O ２ ) gas alone can be used for dry etching.

[0041] After the first via holes TH11 and TH12 are formed, a seed layer 120 is formed on the entire surface of the glass substrate 150. The seed layer 120 is formed by depositing a metal film such as copper (Cu) by a sputtering method. The seed layer 120 is formed to a thickness of about 10 nm to 100 nm.

[0042] 3C shows the step of forming a resist mask 130 on the seed layer 120 and forming first conductive vias V11 and V12. The first conductive vias V11 and V12 are formed by electrolytic plating. For example, copper (Cu) is grown as the first conductive vias V11 and V12 by electrolytic plating. By electrolytic plating, copper (Cu) grows on the surface of the seed layer 120 exposed from the resist mask 130, filling the first via holes TH11 and TH12, and further growing to a thickness of 4 μm to 6 μm on the first resin layer D10.

[0043] 3D shows a stage in which the resist mask 130 is removed after the electrolytic plating process is completed, and the remaining seed layer 120 is etched to form the first conductive vias V11 and V12. After the electrolytic plating process is completed, the seed layer 120 remains on the entire surface of the glass substrate 150, so etching is performed to remove the seed layer 120. Because the seed layer 120 is sufficiently thinner than the first conductive vias V11 and V12, etching the entire surface of the glass substrate 150 can remove the remaining seed layer 120 while leaving the first conductive vias V11 and V12.

[0044] 3E shows a state in which a first intermediate resin layer D21 is formed on top of the first conductive vias V11 and V12, followed by the formation of a seed layer 122 and a resist mask 132, and then the formation of the second conductive vias V21 and V22. The first intermediate resin layer D21 is formed using a photosensitive resin composition to a thickness of 5 μm to 10 μm, for example, 7 μm. The second via holes TH21 and TH22 are formed by exposing, developing, and baking the first intermediate resin layer D21. The formation of the seed layer 122, resist mask 132, and second conductive vias V21 and V22 is similar to the previous process, so detailed description will be omitted.

[0045] 3F shows the stage where a second intermediate resin layer D22 is formed on top of the second conductive vias V21 and V22, and a third conductive via V31 is formed by electrolytic plating through a similar process, thereby forming the second resin layer BSR. The second resin layer BSR is formed using a thermosetting resin material. The second resin layer BSR is formed by attaching a film called a prepreg (a prepreg that does not contain glass fiber) made of a thermosetting epoxy resin material onto the second intermediate resin layer D22 and curing it by heat treatment at a temperature of 150°C to 250°C.

[0046] The second resin layer BSR formed from such a material has a thickness of 30 μm to 40 μm and a Young's modulus of approximately 7 GPa to 13 GPa. That is, the second resin layer BSR has a higher Young's modulus than the intermediate resin layer D20 (first intermediate resin layer D21, second intermediate resin layer D22). The high Young's modulus of the second resin layer BSR, together with the first resin layer D10, ensures the rigidity of the surface region of the multilayer wiring substrate 100, provides excellent flatness when viewed as a whole, and also enhances flatness when viewed microscopically (when viewed in terms of the size of the components to be mounted).

[0047] The second resin layer BSR is provided with a first opening OP1 that exposes the third conductive via V31. The first opening OP1 is formed by, for example, laser processing.

[0048] Through the above steps, the multilayer wiring substrate 100 is formed on the glass substrate 150. After the multilayer wiring substrate 100 is formed on the glass substrate 150, a process of peeling it off from the glass substrate 150 is performed. FIG. 4 shows the step of peeling the multilayer wiring substrate 100 from the glass substrate 150. The peeling process is performed by irradiating the sacrificial layer AL01 with laser light from the glass substrate 150 side. The sacrificial layer AL01 irradiated with the laser light is instantaneously heated to 500° C. or higher. If the sacrificial layer AL01 is formed of a hydrogenated amorphous silicon film, the hydrogen in the film is explosively released by the irradiation of the laser light. This hydrogen release weakens the adhesive strength at the interface between the sacrificial layer AL01 and the first resin layer D10. As a result, the multilayer wiring substrate 100 can be peeled off from the glass substrate 150. This peeling method is also called laser ablation. When polyimide is used for the first resin layer D10, this laser ablation causes ablation at the interface between the glass substrate and the polyimide, allowing peeling at the interface, so depending on the pattern, the sacrificial layer AL01 may not be necessary.

[0049] Furthermore, when the sacrificial layer AL01 is formed by applying a polyimide varnish containing a soluble polyimide resin, a thermosetting crosslinking agent, and a solvent, and then performing a heat treatment at a temperature lower than the crosslinking initiation temperature of the crosslinking agent, as described above, the adhesive strength is reduced by heating the sacrificial layer AL01 so as to promote the crosslinking reaction of the crosslinking agent, and the sacrificial layer AL01 can be peeled off from the glass substrate 150 by applying an external force to one end of the sacrificial layer AL01. This peeling method is also called a mechanical peeling method.

[0050] Because the first resin layer D10 is made of a thermosetting polyimide material, ablation occurs when the first resin layer D10 is irradiated with laser light, weakening its adhesion to the glass substrate 150. On the other hand, because the first conductive vias V11 and V12 are formed by electrolytic plating, they have relatively strong adhesion to the underlying surface. However, by providing a sacrificial layer AL01 for peeling on the glass substrate, the multilayer wiring substrate 100 can be peeled off without damaging the first conductive vias V11 and V12.

[0051] By peeling the multilayer wiring substrate 100 from the glass substrate 150, the multilayer wiring substrate 100 as shown in Fig. 1 can be obtained. The multilayer wiring substrate 100 is further provided with first bumps BP11, BP12 and second bumps BP21 as shown in Fig. 2, and can connect semiconductor integrated circuits (or circuit boards) arranged on the first resin layer D10 side and the second resin layer BSR side.

[0052] The multilayer wiring board 100 according to this embodiment has high flatness due to the high Young's modulus of the first resin layer D10 and the second resin layer BSR, which form the outermost layers. That is, the multilayer wiring board 100 prevents warping when viewed as a whole, and further reduces warping (microscopic warping) when viewed at the component level. The multilayer wiring board 100 has such high flatness that it can improve mounting accuracy and prevent poor electrical connections.

[0053] Second Embodiment This embodiment differs from the multilayer wiring substrate shown in the first embodiment in the configuration of the glass substrate 150 in the manufacturing process. The following description will focus on the differences from the first embodiment, and a description of overlapping parts will be omitted.

[0054] 5 is a cross-sectional view showing the structure at a stage when the multilayer wiring substrate 100 is formed on a glass substrate 150. As shown in FIG.

[0055] As described in the first embodiment, a first resin layer D10, an intermediate resin layer D20, and a second resin layer BSR are laminated on a glass substrate 150, and plated layers for forming conductive vias and wiring are formed between each resin layer. When multiple layers are laminated in this manner, there is a concern that the glass substrate 150 may warp due to the influence of internal stress (residual stress) of each layer. A characteristic of this structure is that the first resin layer D10, which is formed from a thermosetting resin composition, has a strong tensile stress.

[0056] Therefore, warping of the glass substrate 150 during the manufacturing process can be prevented by providing a base insulating layer BL01 having a compressive stress on the glass substrate 150. That is, by providing the base insulating layer BL01 having a compressive stress on the glass substrate 150, even if a layer having a tensile stress, such as the first resin layer D10, is formed on the upper layer side, the stresses are offset, and warping of the glass substrate 150 can be suppressed.

[0057] The base insulating layer BL01 is preferably an insulating film formed of an inorganic material, and is preferably a silicon nitride film, an aluminum oxide film, an aluminum nitride film, or the like, which has compressive stress. For example, by using a silicon nitride film having a compressive stress of about 300 MPa as the base insulating layer BL01, warping of the glass substrate 150 due to the formation of a resin layer can be suppressed. The internal stress of the silicon nitride film depends on the film formation conditions, but the internal stress can be increased by having a film thickness of 300 nm or more.

[0058] The base insulating layer BL01 may have a structure in which a silicon oxide film and a silicon nitride film are stacked. When the base insulating layer BL01 has a structure in which a silicon oxide film and a silicon nitride film are stacked in this order from the glass substrate 150 side, adhesion can be improved and peeling can be prevented.

[0059] The sacrificial layer AL01 is provided on the base insulating layer BL01. The silicon nitride film used as the base insulating layer BL01 is sufficiently transparent to light in the visible to infrared bands, and therefore has no effect even when the sacrificial layer AL01 is irradiated with laser light to peel off the multilayer wiring substrate 100. After peeling, the base insulating layer BL01 remains on the glass substrate 150, and therefore the glass substrate 150 can be reused.

[0060] As shown in this embodiment, by providing a base insulating layer BL01 on the glass substrate 150, it is possible to prevent warping of the glass substrate 150 during the manufacturing process and to prevent unintended peeling of the resin layer. The configuration of the multilayer wiring substrate 100 according to this embodiment is the same as that of the first embodiment except for having the base insulating layer BL01, and similar effects can be obtained.

[0061] [Third Embodiment] This embodiment shows a mode in which the configuration of the intermediate resin layer is different from that of the multilayer wiring board shown in the first embodiment. In the following explanation, the differences from the first embodiment will be mainly explained, and explanation of overlapping parts will be omitted.

[0062] In the first embodiment, the intermediate resin layer D20 was formed from a photosensitive resin composition, but in this embodiment, the intermediate resin layer D20 is formed from a non-photosensitive resin composition. Fig. 6 shows an example in which the first intermediate resin layer D21 and the second intermediate resin layer D22 are formed from a non-photosensitive resin material. The first intermediate resin layer D21 and the second intermediate resin layer D22 are formed using the same non-photosensitive resin composition as the first resin layer D10. Because the first intermediate resin layer D21 and the second intermediate resin layer D22 are formed by baking the non-photosensitive resin composition, they have a high Young's modulus similar to that of the first resin layer D10.

[0063] A second inorganic insulating layer D212 is provided on the first intermediate resin layer D21, and a third inorganic insulating layer D222 is provided on the second intermediate resin layer D22. The second inorganic insulating layer D212 and the third inorganic insulating layer D222 are layers having compressive stress, similar to the first inorganic insulating layer D12, and are preferably formed of silicon nitride films.

[0064] The first intermediate resin layer D21 and the second intermediate resin layer D22 are formed from a non-photosensitive resin composition, and thus have tensile stress similar to the first resin layer. In contrast, the second inorganic insulating layer D212 and the third inorganic insulating layer D222, which have compressive stress, are provided, thereby offsetting the tensile stress and preventing warping of the multilayer wiring substrate 100. The second via holes TH21 and TH22 formed in the first intermediate resin layer D21 and the third via hole TH31 formed in the second intermediate resin layer D22 are formed by etching. At this time, the second inorganic insulating layer D212 and the third inorganic insulating layer D222 are used as hard masks for etching. When the first intermediate resin layer D21 and the second intermediate resin layer D22 are formed from polyimide, CF is used as the etching gas. ４ , S.F. ６ , N.F. ３ Fluorine-based gases such as oxygen (O ２) or oxygen (O ２ ) gas alone can be used for dry etching.

[0065] According to the configuration of the multilayer wiring board 100 of this embodiment, the Young's modulus of each resin layer can be increased and the internal stress (residual stress) of each resin layer can be offset, thereby providing a multilayer wiring board 100 that is excellent in flatness and suitable for high-density mounting. The configuration of the multilayer wiring board 100 of this embodiment is the same as that of the first embodiment except for the configuration of the intermediate resin layer D20, and similar effects can be obtained.

[0066] The configuration of this embodiment can be implemented in appropriate combination with the configuration of the base insulating layer BL01 shown in the second embodiment.

[0067] Fourth Embodiment This embodiment shows the configuration of a multilayer wiring board having a large via hole diameter. The following description will focus on differences from the first embodiment, and will omit a description of overlapping parts.

[0068] 7 shows a schematic cross-sectional structure of a multilayer wiring substrate 100 in which the via hole diameter is relatively large (for example, 20 μm or more). When the via hole diameter formed in each resin layer is large, the conductive via formed by electrolytic plating may not be able to fill the via hole sufficiently. In such a case, the conductive via has a concave shape in the area corresponding to the center of the via hole. In other words, the conductive via conforms to the concave shape formed by the via hole.

[0069] The intermediate resin layer D20 is formed by applying a photosensitive resin composition and exposing it to light. The intermediate resin layer D20 can fill the uneven surface of the base by utilizing the fluidity of the photosensitive resin composition when applied, thereby forming a flat surface. In this case, if the upper surface of the conductive via has a concave shape, the film thickness of the intermediate resin layer D20 will increase in the area overlapping this concave shape.

[0070] When the photosensitive resin composition forming the intermediate resin layer D20 is a positive type, the portion where the via hole is to be formed is exposed, but for example, if the portion where the resin layer has increased in thickness is exposed, it may not be sufficiently exposed, and there is a concern that residues may remain after development. On the other hand, if an attempt is made to sufficiently expose the portion where the thickness of the intermediate resin layer D20 has increased, the other portions (portions where the thickness has not increased) will be overexposed, which is not preferable.

[0071] In order to solve this problem, the intermediate resin layer D20 of the multilayer wiring board 100 of this embodiment is formed using a negative photosensitive resin composition. When a negative resin composition is used, the via hole region is an unexposed region, so there is no insufficient exposure even when the film thickness is increased. As a result, the cross-sectional shape of the via hole can be made nearly vertical, and peeling around the conductive via can also be prevented.

[0072] The configuration of the multilayer wiring board 100 according to this embodiment is the same as that of the first embodiment, except that the intermediate resin layer D20 is formed from a negative photosensitive resin composition, and similar effects can be obtained.

[0073] The configuration of this embodiment can be implemented in appropriate combination with the configuration of the base insulating layer BL01 shown in the second embodiment.

[0074] Fifth Embodiment This embodiment shows an aspect in which the configuration of the first resin layer is different from that of the first embodiment. In the following description, differences from the first embodiment will be mainly described, and a description of overlapping parts will be omitted.

[0075] 8 is a cross-sectional view showing the configuration of a multilayer wiring board 100 according to this embodiment. The multilayer wiring board 100 according to this embodiment differs from the multilayer wiring board shown in the first embodiment in that the first inorganic insulating layer is removed from above the first resin layer D10. The first inorganic insulating layer is removed after the first via holes TH11 and TH12 are formed.

[0076] 8, the toughness of the multilayer wiring board 100 can be improved. That is, even when the multilayer wiring board 100 is bent, the toughness against bending can be increased. Furthermore, even when thermal stress such as a temperature rise when current is applied to the multilayer wiring board 100 and a subsequent temperature drop acts, cracks can be prevented, thereby improving reliability.

[0077] Furthermore, in the cross-sectional view of FIG. 8 , if the Young's modulus of the first resin layer D10 can be made higher than that of the intermediate resin layer D20, a photosensitive resin can be used for the first resin layer D10. For example, if a photosensitive polyimide material is used for the first resin layer D10 and a photosensitive phenolic resin is used for the intermediate resin layer D20, the Young's modulus of the first resin layer D10 can be set relatively higher than that of the intermediate resin layer D20. When the first resin layer D10 is patterned using a photosensitive resin by a photolithography process, dry etch damage during processing can be reduced. Therefore, even if the material of the first resin layer D10 originally has a low Young's modulus, maintaining a high Young's modulus of the second resin layer BSR can ensure the flatness of the multilayer wiring substrate 100 after peeling. The photosensitivity of the polyimide material can be either negative or positive.

[0078] 9 shows a configuration of the multilayer wiring substrate 100 in which the first inorganic insulating layer has been similarly removed from above the first resin layer D10. The configuration shown in FIG. 9 shows a configuration in which the first inorganic insulating layer D12 has been removed after the first conductive vias V11 and V12 have been formed. In this configuration, the first inorganic insulating layer has been removed from most of the area, but the first inorganic insulating layer D12 remains below the first conductive via V11.

[0079] According to the configuration shown in Figure 9, the toughness of the multilayer wiring board 100 is increased, and by interposing the first inorganic insulating layer D12 made of an inorganic insulating material (e.g., silicon nitride) between the first conductive vias V11, V12 made of a metal (e.g., copper (Cu)) and the first resin layer D10 made of a resin material (e.g., polyimide), the adhesion of the first conductive vias V11, V12 to the first resin layer D10 can be increased, and peeling can be prevented.

[0080] The configuration of the multilayer wiring substrate 100 according to this embodiment is the same as that of the first embodiment except that the first inorganic insulating layer D12 is removed, and similar effects can be obtained.

[0081] The configuration of this embodiment can be implemented in appropriate combination with the configurations shown in the second to fourth embodiments.

[0082] Sixth Embodiment This embodiment illustrates an example in which the configuration of the conductive vias provided in the first resin layer is different from that of the multilayer wiring board shown in the first embodiment. In the following explanation, the differences from the first embodiment will be mainly explained, and explanations of overlapping parts will be omitted.

[0083] 10A shows a stage in which the multilayer wiring substrate 100 according to this embodiment is formed on a glass substrate 150. The multilayer wiring substrate 100 according to this embodiment has a structure in which no conductive vias are provided in the first resin layer D10, and wirings M11 and M12 are provided on the first resin layer D10. The wirings M11 and M12 are formed by electrolytic plating, similar to the first conductive vias. At this stage, the first resin layer D10 does not have through holes to form via holes.

[0084] 10B shows a state in which the multilayer wiring substrate 100 has been peeled off from the glass substrate 150. As described in the first embodiment, the peeling of the multilayer wiring substrate 100 is performed by laser ablation or mechanical peeling. Thereafter, a laser beam is irradiated from the second resin layer BSR side to form a first opening OP1, and a laser beam is irradiated from the first resin layer D10 side to form second openings OP21 and OP22 that expose the wirings M11 and M12.

[0085] According to this embodiment, the process is carried out with the first resin layer D10 in a solid state (without via holes) until the second resin layer BSR is formed, and the second openings OP21 and OP22 are formed in the final stage. This process allows the process to be carried out with the first resin layer D10 in a state where it has higher rigidity, thereby improving the dimensional accuracy of the multilayer wiring substrate 100.

[0086] The configuration of the multilayer wiring board 100 according to this embodiment is the same as that of the first embodiment except for the configuration related to the first conductive vias, and similar effects can be obtained.

[0087] This embodiment can be implemented by appropriately combining the configurations shown in the second to fifth embodiments.

[0088] The various configurations of the multilayer wiring board exemplified above as one embodiment of the present invention can be combined as appropriate as long as they are not mutually inconsistent. Furthermore, multilayer wiring boards that have been created by a person skilled in the art based on the multilayer wiring boards disclosed in this specification and drawings, with appropriate additions, deletions, or design changes to components, or with additions, omissions, or changes to conditions of processes, are also included within the scope of the present invention as long as they comply with the gist of the present invention.

[0089] Even if there are other effects and advantages different from those brought about by the aspects of the embodiments disclosed in this specification, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention.

[0090] 100: multilayer wiring substrate, 120: seed layer, 122: seed layer, 130: resist mask, 132: resist mask, 150: glass substrate, 202: first integrated circuit (or first circuit board), 204: second integrated circuit (or second circuit board), AL01: sacrificial layer A, BL01: base insulating layer, BP11, BP12: first bump, BP21: second bump, BSR: second resin layer, D10: first resin layer, D12: first inorganic insulating layer, D2 0: intermediate resin layer, D21: first intermediate resin layer, D212: second inorganic insulating layer, D22: second intermediate resin layer, D222: third inorganic insulating layer, M11, M12: wiring, OP1: first opening, OP21, OP22: second opening, TH11, TH12: first via hole, TH21, TH22: second via hole, TH31: third via hole, V11, V12: first conductive via, V21, V22: second conductive via, V31, B32: third conductive via

Claims

1. A multilayer wiring board comprising: a first resin layer; a second resin layer overlapping the first resin layer in a planar view; at least one intermediate resin layer between the first resin layer and the second resin layer; and at least one conductive via provided in the at least one intermediate resin layer, wherein the first resin layer forms the outermost layer on a first surface side and the second resin layer forms the outermost layer on a second surface side opposite the first surface side, and the Young's modulus of the first resin layer and the second resin layer is higher than the Young's modulus of the intermediate resin layer.

2. The multilayer wiring board according to claim 1, wherein the Young's modulus of the first resin layer and the second resin layer is 5 GPa or more.

3. The multilayer wiring board according to claim 2, wherein the first resin layer and the second resin layer are formed from a resin material that does not contain a photosensitive group.

4. The multilayer wiring board described in claim 1, wherein the at least one conductive via includes a first conductive via exposed from the first resin layer on the first surface side, a second conductive via exposed from the second resin layer, a first bump on the side of the first resin layer, and a second bump on the side of the second resin layer, the first bump being electrically connected to the first conductive via, and the second bump being electrically connected to the second conductive via.

5. The multilayer wiring board according to claim 1, wherein the at least one intermediate resin layer includes a first intermediate resin layer adjacent to the first resin layer, and a first inorganic insulating layer (D12) is provided between the first resin layer and the first intermediate resin layer.

6. The multilayer wiring board according to claim 5, wherein said first resin layer has a tensile stress, and said first inorganic insulating layer has a compressive stress.

7. The multilayer wiring board described in claim 1, wherein the at least one intermediate resin layer includes a first intermediate resin layer adjacent to the first resin layer and a second intermediate resin layer adjacent to the second resin layer, has a first inorganic insulating layer between the first resin layer and the first intermediate resin layer, has a second inorganic insulating layer between the first intermediate resin layer and the second intermediate resin layer, and has a third inorganic insulating layer between the second intermediate resin layer and the second resin layer.

8. The multilayer wiring board according to claim 7, wherein the first resin layer, the first intermediate resin layer and the second intermediate resin layer have tensile stress, and the first inorganic insulating layer, the second inorganic insulating layer and the third inorganic insulating layer have compressive stress.

9. The multilayer wiring board according to claim 1, wherein the second resin layer is thicker than the first resin layer.

10. A method for producing a multilayer wiring board having a first resin layer, a second resin layer overlapping the first resin layer in a planar view, at least one intermediate resin layer between the first resin layer and the second resin layer, and at least one conductive via provided in the at least one intermediate resin layer, the method comprising: forming the first resin layer by applying a non-photosensitive resin composition onto a glass substrate and baking the composition; forming the second resin layer from a thermosetting organic-inorganic composite material; and forming the at least one intermediate resin layer from a photosensitive resin material.

11. The method for producing a multilayer wiring board according to claim 10, wherein the first resin layer and the second resin layer are formed from a material having a higher Young's modulus than the at least one intermediate resin layer.

12. The method for producing a multilayer wiring board according to claim 10, further comprising forming a first inorganic insulating layer having a compressive stress on the surface of the first resin layer.

13. The method for producing a multilayer wiring board according to claim 12, further comprising forming a base inorganic insulating layer having a compressive stress on the glass substrate before forming the first resin layer.

14. The method for producing a multilayer wiring board according to claim 10, wherein the second resin layer is formed from a coating type or film type organic-inorganic composite material.

15. The method for producing a multilayer wiring board according to claim 10, wherein the first resin layer is formed by applying a non-photosensitive polyimide composition and baking it.

16. A method for producing a multilayer wiring board as described in claim 10, comprising: forming a sacrificial layer on the glass substrate; and forming the first resin layer on the sacrificial layer; and after forming the second resin layer, irradiating the sacrificial layer with laser light to peel off the first resin layer, the at least one intermediate resin layer, and the second resin layer from the glass substrate.

17. The method for producing a multilayer wiring board according to claim 16, wherein the sacrificial layer is formed of a silicon semiconductor containing hydrogen, and the baking temperature of the first resin layer is set to 450° C. or less.

18. A multilayer wiring board comprising: a first resin layer formed of a non-photosensitive material or a photosensitive resin material; a second resin layer overlapping the first resin layer in a planar view and formed of a thermosetting organic-inorganic composite material; at least one intermediate resin layer formed of a photosensitive material between the first resin layer and the second resin layer; and at least one conductive via provided in the at least one intermediate resin layer, wherein the first resin layer forms the outermost layer on a first surface side, and the second resin layer forms the outermost layer on a second surface side opposite the first surface side.

19. The multilayer wiring board according to claim 18, wherein the first resin layer is formed of a non-photosensitive polyimide, and the second resin layer is formed of a thermosetting epoxy resin material containing an epoxy resin, an active ester compound containing a naphthalene structure, and an inorganic filler.

20. The multilayer wiring board according to claim 18, wherein the Young's modulus of the first resin layer and the second resin layer is higher than the Young's modulus of the intermediate resin layer.

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