Intelligent power module and semiconductor module

Abstract

This intelligent power module is provided with: two semiconductor elements that are connected in parallel with each other; a drive element that outputs a drive signal common to the two semiconductor elements; one pair of rectifying elements that are connected in series via a first connection point; another pair of rectifying elements that are connected in series via a second connection point; a first resistor that is connected between the first connection point and the drive element; and a second resistor that is connected between the second connection point and the drive element. The one pair of rectifying elements are connected such that forward currents flow from the first connection point respectively to two electrodes. The other pair of rectifying elements are connected such that forward currents flow respectively from the two electrodes to the second connection point.

Description

Intelligent Power Modules and Semiconductor Modules

[0001] The present disclosure relates to intelligent power modules and semiconductor modules.

[0002] Conventionally, semiconductor modules including semiconductor elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) have been known. For example, Patent Document 1 discloses an example of a conventional semiconductor module. The semiconductor module described in Patent Document 1 includes a plurality of semiconductor elements. Each of the plurality of semiconductor elements is, for example, a MOSFET. The plurality of semiconductor elements are electrically connected in parallel and driven in parallel by a common drive signal.

[0003] Japanese Patent Application Laid-Open No. 2023-161017

[0004] [Summary] When multiple semiconductor elements are connected in parallel, a resonance phenomenon may occur when each semiconductor element is switched (on / off). This resonance phenomenon may cause the drive signals of the multiple semiconductor elements to oscillate, which may cause malfunction or destruction of each semiconductor element.

[0005] An object of the present disclosure is to provide an intelligent power module and a semiconductor module that are improved over conventional ones. In particular, in view of the above circumstances, an object of the present disclosure is to provide an intelligent power module and a semiconductor module that are capable of suppressing resonance of a drive signal.

[0006] A first aspect of the present disclosure provides an intelligent power module comprising: a first semiconductor element having a first electrode, a second electrode, and a third electrode, the first electrode and the second electrode being electrically connected in response to a drive signal input to the third electrode; a second semiconductor element having a fourth electrode, a fifth electrode, and a sixth electrode, the fourth electrode and the fifth electrode being electrically connected in response to a drive signal input to the sixth electrode; a drive element outputting a common drive signal to each of the third electrode and the sixth electrode; a pair of first rectifier elements connected in series between the third electrode and the sixth electrode via a first connection point; a pair of second rectifier elements connected in series between the third electrode and the sixth electrode via a second connection point; a first resistor connected between the first connection point and the drive element; and a second resistor connected between the second connection point and the drive element. The first electrode and the fourth electrode are electrically connected. The second electrode and the fifth electrode are electrically connected. Each of the pair of first rectifying elements is connected so that a forward current flows individually from the first connection point to the third electrode and the sixth electrode, and each of the pair of second rectifying elements is connected so that a forward current flows individually from the third electrode and the sixth electrode to the second connection point.

[0007] A second aspect of the present disclosure provides a semiconductor module comprising: a first semiconductor element having a first electrode, a second electrode, and a third electrode, the first electrode and the second electrode being electrically connected to each other in response to a drive signal input to the third electrode; a second semiconductor element having a fourth electrode, a fifth electrode, and a sixth electrode, the fourth electrode and the fifth electrode being electrically connected to each other in response to a drive signal input to the sixth electrode; a pair of first rectifying elements connected in series between the third electrode and the sixth electrode via a first connection point; and a pair of second rectifying elements connected in series between the third electrode and the sixth electrode via a second connection point. A common drive signal is input to each of the third electrode and the sixth electrode. The first electrode and the fourth electrode are electrically connected. The second electrode and the fifth electrode are electrically connected. Each of the pair of first rectifying elements is connected so that a forward current flows individually from the first connection point to the third electrode and the sixth electrode. Each of the pair of second rectifying elements is connected so that a forward current flows from the third electrode and the sixth electrode to the second connection point, respectively.

[0008] FIG. 1 is a diagram showing an example of a circuit configuration of an intelligent power module according to a first embodiment. FIG. 2 is a perspective view showing a power conversion unit including an intelligent power module according to the first embodiment. FIG. 3 is a diagram showing the perspective view of FIG. 2 , with a portion of a wiring board (a circuit board arranged above) and components mounted on that portion omitted. FIG. 4 is a diagram showing the perspective view of FIG. 3 , with the other portion of the wiring board (a circuit board arranged below) and components mounted on that portion omitted. FIG. 5 is a plan view showing a power conversion unit including an intelligent power module according to the first embodiment. FIG. 6 is a diagram showing the plan view of FIG. 5 , with a portion of the wiring board (a circuit board arranged above) and components mounted on that portion omitted. FIG. 7 is a diagram showing the plan view of FIG. 6 , with the other portion of the wiring board (a circuit board arranged below) and components mounted on that portion omitted. FIG. 8 is a front view showing a power conversion unit including an intelligent power module according to the first embodiment. FIG. 9 is a bottom view showing a power conversion unit including an intelligent power module according to the first embodiment. FIG. 10 is a left side view showing a power conversion unit including an intelligent power module according to the first embodiment. FIG. 11 is a right side view showing a power conversion unit including an intelligent power module according to the first embodiment. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 6. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 6. FIG. 14 is a partially enlarged cross-sectional view of a power conversion unit including an intelligent power module according to the first embodiment. FIG. 15 is a partially enlarged plan view showing a part of the plan view of FIG. 6. FIG. 16 is a partially enlarged view showing a part of the left side view of FIG. 10. FIG. 17 is a partially enlarged cross-sectional view of a power conversion unit including an intelligent power module according to the first embodiment. FIG. 18 is a plan view showing a module portion of an intelligent power module according to the first embodiment. FIG. 19 is a view showing the sealing resin in the plan view of FIG. 18 with imaginary lines. FIG. 20 is a view showing the plan view of FIG. 19 with the sealing resin and one of the two conductive members omitted.FIG. 21 is a partially enlarged view of the plan view of FIG. 20 . FIG. 22 is a front view showing a module portion of the intelligent power module according to the first embodiment. FIG. 23 is a bottom view showing the module portion of the intelligent power module according to the first embodiment. FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 19 . FIG. 25 is a partially enlarged cross-sectional view of FIG. 24 . FIG. 26 is a partially enlarged cross-sectional view of FIG. 24 . FIG. 27 is a cross-sectional view taken along line XXVII-XXVII in FIG. 19 . FIG. 28 is a cross-sectional view taken along line XXVIII-XXVIII in FIG. 19 . FIG. 29 is a cross-sectional view taken along line XXIX-XXIX in FIG. 19 . FIG. 30 is a plan view showing a semiconductor element (IGBT) of the intelligent power module according to the first embodiment. FIG. 31 is a cross-sectional view taken along line XXXI-XXXI in FIG. 30 . FIG. 32 is a cross-sectional view taken along line XXXII-XXXII in FIG. 30. FIG. 33 is a cross-sectional view showing a modified semiconductor element (IGBT) of the intelligent power module according to the first embodiment, corresponding to the cross section of FIG. 31. FIG. 34 is a plan view showing a semiconductor element (MOSFET) of the intelligent power module according to the first embodiment. FIG. 35 is a cross-sectional view taken along line XXXV-XXXV in FIG. 34. FIG. 36 is a partially enlarged cross-sectional view of a portion of FIG. 35. FIG. 37 is a cross-sectional view showing a modified semiconductor element (MOSFET) of the intelligent power module according to the first embodiment, corresponding to the cross section of FIG. 35. FIG. 38 is a partially enlarged cross-sectional view of a portion of FIG. 37. FIG. 39 is a schematic diagram of a vehicle equipped with a power conversion unit including an intelligent power module according to the first embodiment. FIG. 40 is an enlarged plan view of a main portion of a module according to a modified embodiment. FIG. 41 is a plan view showing a power conversion unit according to a modified embodiment. Fig. 42 is a diagram in which a part of the wiring board (a circuit board arranged above) and components mounted on that part of the wiring board are omitted from the plan view of Fig. 41. Fig. 43 is a diagram in which another part of the wiring board (a circuit board arranged below) and components mounted on that part of the wiring board are omitted from the plan view of Fig. 42. Fig. 44 is a plan view showing a power conversion unit according to a modified example.Fig. 45 is a diagram showing an example of a circuit configuration of an intelligent power module according to a second embodiment. Fig. 46 is a diagram showing an example of a circuit configuration of an intelligent power module according to a third embodiment. Fig. 47 is a diagram showing an example of a circuit configuration of an intelligent power module according to a fourth embodiment.

[0009] DETAILED DESCRIPTION Preferred embodiments of the intelligent power module and semiconductor module of the present disclosure will be described below with reference to the drawings. Hereinafter, identical or similar components will be designated by the same reference numerals, and redundant descriptions will be omitted. Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not intended to necessarily assign any order to their objects.

[0010] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an) object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an) object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on (an) object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an) object B" includes "a certain object A is in contact with a certain object B and is located on (an) object B" and "a certain object A is located on (an) object B with another object interposed between the certain object A and the certain object B." Furthermore, "object A overlaps object B when viewed in a certain direction" includes "object A overlaps the entire object B" and "object A overlaps a part of object B," unless otherwise specified. Furthermore, "object A (its material) contains material C" includes "object A (its material) is made of material C" and "object A (its material) is mainly composed of material C." Furthermore, "a surface A faces in a certain direction B (one side or the other side of a certain direction B)," unless otherwise specified, is not limited to the case where surface A is at a 90° angle with respect to direction B, but also includes the case where surface A is tilted with respect to direction B. Furthermore, "a surface A is perpendicular to a surface B," unless otherwise specified, is not limited to the case where surface A is at a 90° angle with respect to surface B, but also includes the case where surface A is tilted with respect to surface B.

[0011] Intelligent power module A10: Circuit configuration: Fig. 1 shows an example of the circuit configuration of the intelligent power module A10 according to the first embodiment. The application of the intelligent power module A10 is not limited in any way, but it is used, for example, for driving and controlling an inverter motor. The intelligent power module A10 includes a module unit PM1 and a drive circuit unit DR1 in its circuit configuration.

[0012] The module unit PM1 converts input power and outputs it. The module unit PM1 is controlled by the drive circuit unit DR1. The module unit PM1 is an example of a "semiconductor module" as defined in the claims. The module unit PM1 includes two switching units SW1 and SW2 and a plurality of rectifying elements D11, D12, D21, and D22.

[0013] The two switching units SW1 and SW2 are elements that fulfill the electrical functions of the module unit PM1. In this embodiment, the two switching units SW1 and SW2 are configured identically. Each of the two switching units SW1 and SW2 includes two semiconductor elements 21 and 22. Unless otherwise specified, the semiconductor elements 21 and 22 described below are common to both the switching units SW1 and SW2. For convenience of explanation, the two semiconductor elements 21 and 22 of the switching unit SW1 may be referred to as semiconductor element 21A and semiconductor element 22A, respectively, and the two semiconductor elements 21 and 22 of the switching unit SW2 may be referred to as semiconductor element 21B and semiconductor element 22B, respectively.

[0014] In the example shown in FIG. 1 , the semiconductor element 21 is an IGBT. The semiconductor element 21 has a first semiconductor substrate (semiconductor substrate G31 described below). The constituent material of the first semiconductor substrate includes, for example, Si (silicon). The constituent material of the first semiconductor substrate may include, instead of Si, any of SiC (silicon carbide), GaAs (gallium arsenide), GaN (gallium nitride), GaO (gallium oxide), etc. Unlike this example, the semiconductor element 21 may be a transistor other than an IGBT (for example, a MOSFET, a bipolar transistor, etc.). The semiconductor element 21 is an example of a "first semiconductor element" as defined in the claims.

[0015] The semiconductor element 21 has three electrodes 211, 212, and 213. In an example where the semiconductor element 21 is an IGBT, the electrode 211 is a collector electrode, the electrode 212 is an emitter electrode, and the electrode 213 is a gate electrode. A drive signal is input to the electrode 213. The semiconductor element 21 switches between an ON state and an OFF state depending on the drive signal input to the electrode 213. In the ON state, the electrodes 211 and 212 are conductive, and in the OFF state, the electrodes 211 and 212 are non-conductive. Thus, in the semiconductor element 21, the electrodes 211 and 212 are conductive in response to the drive signal input to the electrode 213. The multiple electrodes 211, 212, and 213 are each an example of a "first electrode," a "second electrode," and a "third electrode" as defined in the claims.

[0016] In the example shown in FIG. 1 , the semiconductor element 22 is a MOSFET. The semiconductor element 22 has a second semiconductor substrate (semiconductor substrate M102 described below). The material of the second semiconductor substrate has a wider band gap than the material of the first semiconductor substrate, and includes, for example, SiC. The material of the second semiconductor substrate may be Si, GaAs, GaN, Ga2O3, or the like, instead of SiC. Unlike this example, the semiconductor element 22 may be a transistor other than a MOSFET (for example, an IGBT, a bipolar transistor, or the like). The semiconductor element 22 is an example of a "second semiconductor element" as defined in the claims.

[0017] The semiconductor element 22 has three electrodes 221, 222, and 223. In an example where the semiconductor element 22 is a MOSFET, the electrode 221 is a drain electrode, the electrode 222 is a source electrode, and the electrode 223 is a gate electrode. A drive signal is input to the electrode 223. The semiconductor element 22 switches between an on state and an off state depending on the drive signal input to the electrode 223. In the on state, the electrodes 221 and 222 are conductive, and in the off state, the electrodes 221 and 222 are non-conductive. Thus, in the semiconductor element 22, the electrodes 221 and 222 are conductive in response to the drive signal input to the electrode 223. The multiple electrodes 221, 222, and 223 are each an example of a "fourth electrode," a "fifth electrode," and a "sixth electrode" as defined in the claims.

[0018] In each of the switching units SW1 and SW2, the two semiconductor elements 21 and 22 are electrically connected in parallel. Specifically, the electrode 211 (collector electrode) of the semiconductor element 21 is electrically connected to the electrode 221 (drain electrode) of the semiconductor element 22, and the electrode 212 (emitter electrode) of the semiconductor element 21 is electrically connected to the electrode 222 (source electrode) of the semiconductor element 22. In each of the switching units SW1 and SW2, a common drive signal is input to the two semiconductor elements 21 and 22. For convenience of explanation, the drive signal input to the semiconductor elements 21A and 22A of the switching unit SW1 may be referred to as a "first drive signal," and the drive signal input to the semiconductor elements 21B and 22B of the switching unit SW2 may be referred to as a "second drive signal."

[0019] The switching unit SW1 has two connection terminals T11 and T12 and two signal terminals T13 and T14. The connection terminal T11 is electrically connected to the electrode 211 of the semiconductor element 21A and the electrode 221 of the semiconductor element 22A. The connection terminal T12 is electrically connected to the electrode 212 of the semiconductor element 21A and the electrode 222 of the semiconductor element 22A. The signal terminal T13 is electrically connected to the electrode 213 of the semiconductor element 21A, and the signal terminal T14 is electrically connected to the electrode 223 of the semiconductor element 22A. If either one of the two semiconductor elements 21A and 22A is in the ON state, the two connection terminals T11 and T12 are electrically connected, and the switching unit SW1 is in the ON state. On the other hand, if both the two semiconductor elements 21A and 22A are in the OFF state, the two connection terminals T11 and T12 are electrically disconnected, and the switching unit SW1 is in the OFF state. The switching unit SW1 is an example of the "first switching unit" set forth in the claims.

[0020] The switching unit SW2 has two connection terminals T21, T22 and two signal terminals T23, T24. The connection terminal T21 is electrically connected to the electrode 211 of the semiconductor element 21B and the electrode 221 of the semiconductor element 22B. The connection terminal T22 is electrically connected to the electrode 212 of the semiconductor element 21B and the electrode 222 of the semiconductor element 22B. The signal terminal T23 is electrically connected to the electrode 213 of the semiconductor element 21B, and the signal terminal T24 is electrically connected to the electrode 223 of the semiconductor element 22B. In this embodiment, the connection terminal T21 is electrically connected to the connection terminal T12. As a result, the switching units SW1 and SW2 are electrically connected in series. If either one of the two semiconductor elements 21B, 22B is in the ON state, the two connection terminals T21, T22 are electrically connected, and the switching unit SW2 is in the ON state. On the other hand, when both of the two semiconductor elements 21B and 22B are in the OFF state, there is no conduction between the two connection ends T21 and T22, and the switching unit SW2 is in the OFF state. The switching unit SW2 is an example of the "second switching unit" set forth in the claims.

[0021] Each of the rectifying elements D11, D12, D21, and D22 is an electronic component that allows current to flow in only one direction. In the example shown in FIG. 1 , each of the rectifying elements D11, D12, D21, and D22 is a diode. Note that the rectifying elements D11, D12, D21, and D22 are not limited to diodes as long as they allow current to flow in only one direction. For example, each of the rectifying elements D11, D12, D21, and D22 may be a switching element that is turned on when current flows in one direction.

[0022] The pair of rectifying elements D11 are connected in series via a connection point C11. One of the pair of rectifying elements D11 is connected so that a forward current flows from the connection point C11 to the electrode 213 of the semiconductor element 21A, and the other of the pair of rectifying elements D11 is connected so that a forward current flows from the connection point C11 to the electrode 223 of the semiconductor element 22A. In the example shown in FIG. 1 , the anode electrodes of the pair of rectifying elements D11 are connected to the connection point C11. The rectifying element D11 is an example of a "first rectifying element" recited in the claims, and the connection point C11 is an example of a "first connection point" recited in the claims.

[0023] The pair of rectifying elements D12 are connected in series via a connection point C12. One of the pair of rectifying elements D12 is connected so that a forward current flows from the electrode 213 of the semiconductor element 21A to the connection point C12, and the other of the pair of rectifying elements D12 is connected so that a forward current flows from the electrode 223 of the semiconductor element 22A to the connection point C12. In the example shown in FIG. 1 , each cathode electrode of the pair of rectifying elements D12 is connected to the connection point C12. The rectifying element D12 is an example of a "second rectifying element" recited in the claims, and the connection point C12 is an example of a "second connection point" recited in the claims.

[0024] The pair of rectifying elements D21 are connected in series via a connection point C21. One of the pair of rectifying elements D21 is connected so that a forward current flows from the connection point C21 to the electrode 213 of the semiconductor element 21B, and the other of the pair of rectifying elements D21 is connected so that a forward current flows from the connection point C21 to the electrode 223 of the semiconductor element 22B. In the example shown in FIG. 1 , each anode electrode of the pair of rectifying elements D21 is connected to the connection point C21.

[0025] The pair of rectifying elements D22 are connected in series via a connection point C22. One of the pair of rectifying elements D22 is connected so that a forward current flows from the electrode 213 of the semiconductor element 21B to the connection point C22, and the other of the pair of rectifying elements D22 is connected so that a forward current flows from the electrode 223 of the semiconductor element 22B to the connection point C22. In the example shown in FIG. 1 , each cathode electrode of the pair of rectifying elements D22 is connected to the connection point C22.

[0026] The module unit PM1 has a plurality of power terminals Tp, Tn, and Tout and a plurality of signal terminals Ton1, Toff1, Ton2, Toff2, Tss1, and Tss2. The signal terminal Ton1 is an example of a "first signal terminal" set forth in the claims, and Toff1 is an example of a "second signal terminal" set forth in the claims.

[0027] The power terminal Tp is electrically connected to the connection end T11 of the switching unit SW1. Therefore, the power terminal Tp is electrically connected to the electrode 211 of the semiconductor element 21A and the electrode 221 of the semiconductor element 22A. The power terminal Tn is electrically connected to the connection end T22 of the switching unit SW2. Therefore, the power terminal Tn is electrically connected to the electrode 212 of the semiconductor element 21B and the electrode 222 of the semiconductor element 22B. The power terminal Tout is electrically connected to the connection end T12 of the switching unit SW1 and the connection end T21 of the switching unit SW2. Therefore, the power terminal Tout is electrically connected to the electrode 212 of the semiconductor element 21A, the electrode 222 of the semiconductor element 22A, the electrode 211 of the semiconductor element 21B, and the electrode 221 of the semiconductor element 22B. The power terminals Tp, Tn, and Tout are examples of the "first power terminal," "second power terminal," and "third power terminal" set forth in the claims.

[0028] The module unit PM1 converts a power supply voltage (e.g., DC) applied between two power terminals Tp and Tn into AC power by switching between the on and off states of the switching units SW1 and SW2 (i.e., by switching operations of the two semiconductor elements 21 and 22 in each of the switching units SW1 and SW2). The converted AC power is input from the power terminal Tout to a power supply target such as a motor.

[0029] The two signal terminals Ton1 and Toff1 are input terminals for the first drive signal. The signal terminal Ton1 is electrically connected to the connection point C11 and is connected to two signal ends T13 and T14 via a pair of rectifying elements D11. The signal terminal Ton1 is connected to the electrode 213 (gate electrode) of the semiconductor element 21A and the electrode 223 (gate electrode) of the semiconductor element 22A via a pair of rectifying elements D11. The signal terminal Toff1 is electrically connected to the connection point C12 and is connected to two signal ends T13 and T14 via a pair of rectifying elements D12. The signal terminal Toff1 is connected to the electrode 213 (gate electrode) of the semiconductor element 21A and the electrode 223 (gate electrode) of the semiconductor element 22A via a pair of rectifying elements D12.

[0030] The two signal terminals Ton2 and Toff2 are input terminals for the second drive signal. The signal terminal Ton2 is electrically connected to the connection point C21 and is connected to two signal ends T23 and T24 via a pair of rectifying elements D21. The signal terminal Ton2 is connected to the electrode 213 (gate electrode) of the semiconductor element 21B and the electrode 223 (gate electrode) of the semiconductor element 22B via a pair of rectifying elements D21. The signal terminal Toff2 is electrically connected to the connection point C22 and is connected to two signal ends T23 and T24 via a pair of rectifying elements D22. The signal terminal Toff2 is connected to the electrode 213 (gate electrode) of the semiconductor element 21B and the electrode 223 (gate electrode) of the semiconductor element 22B via a pair of rectifying elements D22.

[0031] The signal terminal Tss1 is electrically connected to the electrode 212 of the semiconductor element 21A and the electrode 222 of the semiconductor element 22A. A voltage signal corresponding to the current flowing through the electrode 212 (emitter electrode) of the semiconductor element 21A and the electrode 222 (source electrode) of the semiconductor element 22A is output from the signal terminal Tss1. This voltage signal is a signal for detecting the current flowing through the semiconductor elements 21A and 22A (switching unit SW1), and may hereinafter be referred to as a first sensing signal.

[0032] The signal terminal Tss2 is electrically connected to the electrode 212 of the semiconductor element 21B and the electrode 222 of the semiconductor element 22B. A voltage signal corresponding to the current flowing through the electrode 212 (emitter electrode) of the semiconductor element 21B and the electrode 222 (source electrode) of the semiconductor element 22A is output from the signal terminal Tss2. This voltage signal is a signal for detecting the current flowing through the semiconductor elements 21B and 22B (switching unit SW2), and may hereinafter be referred to as a second sensing signal.

[0033] The drive circuit unit DR1 controls the power conversion by the module unit PM1. The drive circuit unit DR1 generates a first drive signal and a second drive signal. The drive circuit unit DR1 controls the on / off switching of the switching unit SW1 by inputting the generated first drive signal to the switching unit SW1, and controls the on / off switching of the switching unit SW2 by inputting the generated second drive signal to the switching unit SW2. The drive circuit unit DR1 includes two drive elements 82A and 82B and multiple resistors R11, R12, R21, and R22.

[0034] The resistor R11 is electrically connected between the signal terminal Ton1 and the driving element 82A. The resistor R12 is electrically connected between the signal terminal Toff1 and the driving element 82A. The resistor R21 is electrically connected between the signal terminal Ton2 and the driving element 82B. The resistor R22 is electrically connected between the signal terminal Toff2 and the driving element 82B. The resistor R11 is an example of a "first resistor" as defined in the claims, and the resistor R12 is an example of a "second resistor" as defined in the claims.

[0035] The driving element 82A is, for example, a gate drive IC, and generates a first driving signal. The first driving signal generated by the driving element 82A includes a first turn-on signal and a first turn-off signal. The driving element 82A is connected to the signal terminal Tss1, and receives the first sensing signal. The driving element 82A generates the first driving signal based on the input first sensing signal and the like.

[0036] The first turn-on signal is a signal for turning on the two semiconductor elements 21A and 22A. The first turn-on signal increases the potential of the electrode 213 (gate electrode) of the semiconductor element 21A and the electrode 223 (gate electrode) of the semiconductor element 22A. As a result, the voltage between the two electrodes 212 and 213 (gate-emitter voltage) of the semiconductor element 21A exceeds the threshold voltage, turning the semiconductor element 21A into an ON state. The voltage between the two electrodes 222 and 223 (gate-source voltage) of the semiconductor element 22A exceeds the threshold voltage, turning the semiconductor element 21A into an ON state. The first turn-on signal causes charge to be supplied from the drive element 82A to the signal terminal Ton1 via the resistor R11. The charge supplied to the signal terminal Ton1 is then supplied to the electrode 213 of the semiconductor element 21A and the electrode 223 of the semiconductor element 22A via the pair of rectifier elements D11. As a result, the potential of the electrode 213 of the semiconductor element 21A and the potential of the electrode 223 of the semiconductor element 22A are each increased. The resistor R11 functions as a gate resistor when the switching unit SW1 (two semiconductor elements 21A and 22A) is turned on.

[0037] The first turn-off signal is a signal for turning off the two semiconductor elements 21A and 22A. The first turn-off signal lowers the potential of the electrode 213 (gate electrode) of the semiconductor element 21A and the electrode 223 (gate electrode) of the semiconductor element 22A. As a result, the voltage between the two electrodes 212 and 213 (gate-emitter voltage) of the semiconductor element 21A falls below the threshold voltage, turning the semiconductor element 21A into an off state. The voltage between the two electrodes 222 and 223 (gate-source voltage) of the semiconductor element 22A falls below the threshold voltage, turning the semiconductor element 22A into an off state. The first turn-off signal causes electric charge to flow from the electrode 213 of the semiconductor element 21A and the electrode 223 of the semiconductor element 22A to the signal terminal Toff1 via the pair of rectifier elements D12. Then, electric charge moves from the signal terminal Toff1 to the drive element 82A via the resistor R12. This lowers the potential of the electrode 213 of the semiconductor element 21A and the potential of the electrode 223 of the semiconductor element 22A. The resistor R12 functions as a gate resistor when the switching unit SW1 (the two semiconductor elements 21A and 22A) is turned off.

[0038] The driving element 82B is, for example, a gate drive IC, and generates a second driving signal. The second driving signal generated by the driving element 82B includes a second turn-on signal and a second turn-off signal. The driving element 82B is connected to the signal terminal Tss2, and receives the second sensing signal. The driving element 82B generates the second driving signal based on the input second sensing signal and the like.

[0039] The second turn-on signal is a signal for turning on the two semiconductor elements 21B and 22B. The second turn-on signal increases the potential of the electrode 213 (gate electrode) of the semiconductor element 21B and the electrode 223 (gate electrode) of the semiconductor element 22B. As a result, the voltage between the two electrodes 212 and 213 (gate-emitter voltage) of the semiconductor element 21B exceeds the threshold voltage, turning it into an ON state. The voltage between the two electrodes 222 and 223 (gate-source voltage) of the semiconductor element 22B exceeds the threshold voltage, turning it into an ON state. The second turn-on signal causes charge to be supplied from the drive element 82B to the signal terminal Ton2 via the resistor R21. The charge supplied to the signal terminal Ton2 is then supplied to the electrode 213 of the semiconductor element 21B and the electrode 223 of the semiconductor element 22B via the pair of rectifier elements D21. As a result, the potential of the electrode 213 of the semiconductor element 21B and the potential of the electrode 223 of the semiconductor element 22B are each increased. The resistor R21 functions as a gate resistor when the switching unit SW2 (two semiconductor elements 21B and 22B) is turned on.

[0040] The second turn-off signal is a signal for turning off the two semiconductor elements 21B and 22B. The second turn-off signal lowers the potential of the electrode 213 (gate electrode) of the semiconductor element 21B and the electrode 223 (gate electrode) of the semiconductor element 22B. As a result, the voltage between the two electrodes 212 and 213 (gate-emitter voltage) of the semiconductor element 21B falls below the threshold voltage, turning the semiconductor element 21B into an off state. The voltage between the two electrodes 222 and 223 (gate-source voltage) of the semiconductor element 22B falls below the threshold voltage, turning the semiconductor element 22B into an off state. The second turn-off signal causes charges to flow from the electrode 213 of the semiconductor element 21B and the electrode 223 of the semiconductor element 22B to the signal terminal Toff2 via the pair of rectifier elements D22. Charge then moves from the signal terminal Toff2 to the drive element 82B via the resistor R22. This lowers the potential of the electrode 213 of the semiconductor element 21B and the potential of the electrode 223 of the semiconductor element 22B. The resistor R22 functions as a gate resistor when the switching unit SW2 (the two semiconductor elements 21B and 22B) is turned off.

[0041] Power Conversion Unit B10 (Intelligent Power Module A10): Structural Example: FIGS. 2 to 17 show structural examples of a power conversion unit B10 including the above-described intelligent power module A10. The power conversion unit B10 includes a plurality of intelligent power modules A10 (a plurality of module units PM1 and a plurality of drive circuit units DR1), an attachment object C1, a mounting member D1, and a wiring board E1. In the illustrated example, the power conversion unit B10 includes three intelligent power modules A10 (three module units PM1 and three drive circuit units DR1), but the number of intelligent power modules A10 is not limited in any way. In other words, the power conversion unit B10 may be configured to include one intelligent power module A10, or two, four, or more intelligent power modules A10.

[0042] In the following description, reference will be made to a first direction z, a second direction x, and a third direction y, which are perpendicular to one another. The first direction z corresponds to the thickness direction of the power conversion unit B10. Furthermore, "plan view" refers to a view in the first direction z. The second direction x is perpendicular to the first direction z. The third direction y is perpendicular to the first direction z and the second direction x. One side of the second direction x will be referred to as the x1 side of the second direction x, and the other side of the second direction x will be referred to as the x2 side of the second direction x. Furthermore, one side of the third direction y will be referred to as the y1 side of the third direction y, and the other side of the third direction y will be referred to as the y2 side of the third direction y. Furthermore, one side of the first direction z will be referred to as the z1 side of the first direction z, and the other side of the first direction z will be referred to as the z2 side of the first direction z. Furthermore, the z1 side of the first direction z will sometimes be referred to as the upper side, and the z2 side of the first direction z will sometimes be referred to as the lower side. Note that terms such as "top," "bottom," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each part, etc. in the first direction z, and are not necessarily terms that define the relationship with the direction of gravity.

[0043] As shown in FIGS. 2 to 4, 7, and 9 to 13, the multiple module units PM1 are arranged along the third direction y. Each module unit PM1 includes multiple semiconductor elements 21 and 22 and has the circuit configuration shown in FIG. 1. Therefore, each module unit PM1 constitutes, for example, a half-bridge switching circuit. Each of the multiple module units PM1 includes multiple power terminals 13, multiple signal terminals 17, and a sealing resin 50. In each of the multiple module units PM1, the multiple semiconductor elements 21 and 22 are covered with the sealing resin 50. Each of the multiple power terminals 13 protrudes in the second direction x from a side surface of the sealing resin 50 (either a side surface 531 or a side surface 532, described below). Each of the multiple signal terminals 17 protrudes in the first direction z from an upper surface of the sealing resin 50 (a top surface 51, described below). A detailed configuration example of each module unit PM1 will be described later.

[0044] In the illustrated example, the power conversion unit B10 includes three module units PM1. In the following description, when distinguishing between the three module units PM1, they are referred to as a first module unit PM11, a second module unit PM12, and a third module unit PM13. The first module unit PM11 is located closest to the y1 side in the third direction y among the multiple module units PM1. The third module unit PM13 is located closest to the y2 side in the third direction y among the multiple module units PM1.

[0045] As shown in FIGS. 2 to 4 , the mounting object C1 supports multiple module units PM1. The mounting object C1 is, for example, a heat sink. Instead of a heat sink, the mounting object C1 may be a housing (frame, etc.) for an electronic device, an electric vehicle, or the like. The majority of the mounting object C1 is located below the multiple module units PM1 in the first direction z (on the z2 side). The mounting object C1 faces the lower surface (bottom surface 52, described below) of the sealing resin 50 of the multiple module units PM1. The material of the mounting object C1 includes, for example, aluminum. The material is not limited to aluminum, and may be other metal materials or resin materials (preferably those with good thermal conductivity). The mounting object C1 includes a main body 71, multiple base portions 72, and multiple positioning portions 73.

[0046] The main body portion 71 is a plate material. The multiple module units PM1 are mounted on the main body portion 71. Therefore, as shown in FIGS. 2 to 4, 7, and 10 to 13, the multiple module units PM1 are arranged on the main body portion 71 along the third direction y. The main body portion 71 faces the lower surface (bottom surface 52 described below) of each sealing resin 50 of the multiple module units PM1. The main body portion 71 is in contact with each module unit PM1. The main body portion 71 is, for example, rectangular in plan view.

[0047] 3, 4, 7, 8, and 10 to 13, the plurality of pedestals 72 protrude upward in the first direction z from the main body 71. In the illustrated example, the plurality of pedestals 72 are formed integrally with the main body 71, but may be attached to the main body 71 as separate bodies.

[0048] As shown in FIGS. 4 , 12 , and 13 , each of the multiple base portions 72 includes a first portion 721 and a second portion 722. The first portion 721 is interposed between the wiring substrate E1 (a circuit board 81 described below) and the main body portion 71 in the first direction z. The dimension of the first portion 721 in the first direction z is larger than the dimension of the sealing resin 50 of each module portion PM1 in the first direction z. The second portion 722 is disposed on the first portion 721. The wiring substrate E1 (a circuit board 81 described below) is sandwiched between the first portion 721 and the second portion 722. With this configuration, the wiring substrate E1 is disposed at a fixed distance from the upper surface of the main body portion 71.

[0049] In this embodiment, as shown in Fig. 12, the first part 721 has a recessed part machined with an internal thread, and the second part 722 has a protruding part machined with an external thread. The second part 722 is fastened to the first part 721 by inserting the externally threaded part (protruding part) of the second part 722 into the internally threaded part (recessed part) of the first part 721. Note that each pedestal part 72 may have a structure in which the first part 721 and the second part 722 are fitted together. For example, the pedestal part 72 may have a structure in which the second part 722 is press-fitted into the first part 721. Alternatively, the first part 721 may have a protruding part and the second part 722 may have a recessed part.

[0050] As shown in FIGS. 3 , 4 , 6 , and 7 , the positioning portions 73 each protrude upward in the first direction z from the main body portion 71. In this embodiment, the positioning portions 73 are attached to the main body portion 71 as separate bodies. Alternatively, each positioning portion 73 may be formed integrally with the main body portion 71. Each positioning portion 73 is press-fitted into a through-hole formed in the main body portion 71. Each positioning portion 73 is cylindrical and tapered toward the z1 side in the first direction z. In the illustrated example, the diameter of each positioning portion 73 in a plan view is smaller than the diameter of each base portion 72 in a plan view. As shown in FIG. 7 , some of the positioning portions 73 are arranged closer to the y1 side in the third direction y than the first module portion PM11, and some are arranged closer to the y2 side in the third direction y than the third module portion PM13.

[0051] The mounting member D1 holds the multiple module units PM1 on the mounting object C1. The mounting member D1 is, for example, a leaf spring. The elastic force of the mounting member D1 presses the multiple module units PM1 against the mounting object C1. The material of the mounting member D1 is not limited in any way, but may be, for example, copper, iron, titanium, or an alloy containing any of these (including, for example, stainless steel). As shown in FIGS. 4, 7, and 13, the mounting member D1 includes multiple pressing portions 75 and multiple fixing portions 76.

[0052] The pressing portions 75 are provided individually for the module portions PM1, respectively. Each of the pressing portions 75 contacts the sealing resin 50 (top surface 51) of the corresponding module portion PM1. Each pressing portion 75 presses the corresponding module portion PM1 against the main body portion 71 of the attachment target C1.

[0053] Each of the multiple fixing portions 76 is fixed to the attachment object C1, and in this embodiment, is fixed to the main body portion 71. Each of the multiple fixing portions 76 is, for example, in the shape of a flat plate parallel to the xy plane. A through hole is formed in each of the multiple fixing portions 76. A fastener 79 (a hexagonal bolt in the illustrated example) is inserted into the through hole. The fastener 79 fixes the fixing portion 76 to the main body portion 71.

[0054] The multiple fixed portions 76 include multiple double-ended portions 761 and multiple intermediate portions 762. In the power conversion unit B10, the multiple fixed portions 76 include a pair of double-ended portions 761 and two intermediate portions 762. As shown in FIGS. 7 and 13 , one of the pair of double-ended portions 761 is located on the y1 side of the first module unit PM11 in the third direction y, and the other of the pair of double-ended portions 761 is located on the y2 side of the third module unit PM13 in the third direction y. One of the two intermediate portions 762 is located between the first module unit PM11 and the second module unit PM12, and the other of the two intermediate portions 762 is located between the second module unit PM12 and the third module unit PM13.

[0055] In the example shown in FIG. 7 , the width (dimension in the second direction x) of each of the two-end arrangement portions 761 is smaller than the width (dimension in the second direction x) of each of the pressing portions 75 and the width (dimension in the second direction x) of each of the intermediate arrangement portions 762. This prevents interference between the mounting member D1 (each of the two-end arrangement portions 761) and each of the positioning portions 73. Unlike this example, the width of the pressing portion 75 and the width of each of the intermediate arrangement portions 762 may be the same (or approximately the same) as the width of each of the two-end arrangement portions 761. In this case, the mounting member D1 can be formed into a rectangular (strip-like) shape in a plan view. Alternatively, the width of each of the intermediate arrangement portions 762 may be the same (or approximately the same) as the width of each of the two-end arrangement portions 761.

[0056] The wiring board E1 is for mounting a plurality of drive circuit units DR1. In this embodiment, the wiring board E1 includes two circuit boards 81 and 82, a plurality of interconnecting wires 83, and a plurality of positioning pins 84. The circuit board 81 is an example of a "first circuit board" as defined in the claims, and the circuit board 82 is an example of a "second circuit board" as defined in the claims.

[0057] As shown in FIGS. 3, 6, and 10 to 13, the circuit board 81 is provided in common to the multiple module units PM1. Alternatively, multiple circuit boards 81 may be provided individually for the multiple module units PM1. The circuit board 81 faces the upper surfaces (top surfaces 51) of the sealing resin 50 of each of the multiple module units PM1. The circuit board 81 is located on the opposite side of the multiple module units PM1 from the main body 71 of the attachment target C1. In a plan view, the circuit board 81 overlaps the sealing resin 50 of each of the multiple module units PM1. The circuit board 81 is held by multiple pedestals 72 at a fixed distance in the first direction z. As can be seen from FIGS. 9 and 11, the signal terminals 17 of the multiple module units PM1 are inserted into the circuit board 81. The circuit board 81 is electrically connected to each of the signal terminals 17. In this embodiment, a plurality of resistors R11, R12, R21, and R22 are mounted on the circuit board 81. The plurality of resistors R11, R12, R21, and R22 are arranged on the upper surface of the circuit board 81 (the surface facing upward in the first direction z). In other words, they are arranged on the side of the circuit board 81 opposite the surface facing each module unit PM1. In addition, the circuit board 81 may also be mounted with an overheat protection circuit (a protection circuit that is conductive to a pair of thermistors TH of the plurality of module units PM1), a surge voltage protection circuit, an active mirror circuit, and the like. If these are mounted, they may be arranged on the upper surface of the circuit board 81, for example.

[0058] As shown in FIG. 14 , the circuit board 81 has a base material 811, main wiring 812, back wiring 813, and internal wiring 814. The base material 811 has a plurality of through holes 811a penetrating in the first direction z. The main wiring 812 is formed on the upper surface of the base material 811 (the surface facing the z1 side in the first direction z). The back wiring 813 is formed on the lower surface of the base material 811 (the surface facing the z2 side in the first direction z). The internal wiring 814 is disposed on the inner surfaces of the plurality of through holes 811a. The internal wiring 814 is connected to the main wiring 812 and the back wiring 813. The main wiring 812 forms a path for mutual conduction between the back wiring 813 and the internal wiring 814 and circuits (e.g., resistors R11, R12, R21, and R22) provided on the circuit board 81.

[0059] Each signal terminal 17 of the multiple module units PM1 is inserted into a corresponding one of the multiple through holes 811a of the circuit board 81. Fig. 14 shows a state in which any signal terminal 17 of the multiple module units PM1 is inserted into the through hole 811a of the base material 811. Note that all of the signal terminals 17 of the multiple module units PM1 are inserted into the through hole 811a of the base material 811, as shown in Fig. 14.

[0060] 14 , each signal terminal 17 has a base 170A and a bulge 170B. One side of the base 170A in the first direction z is press-fitted into one of the multiple sleeves 64 (described later) of the multiple module units PM1. The bulge 170B is provided on one side (z1 side) of the base 170A in the first direction z. The bulge 170B bulges in a direction perpendicular to the first direction z.

[0061] As shown in FIG. 14 , each signal terminal 17 is press-fitted into one of the through holes 811a of the circuit board 81. As a result, the internal wiring 814 arranged in one of the through holes 811a is pressed against the bulging portion 170B of the signal terminal 17 inserted into the corresponding through hole 811a. Therefore, each signal terminal 17 is press-fitted into the through hole 811a in the first direction z, thereby establishing electrical continuity with the circuit board 81. By press-fitting each signal terminal 17 into a corresponding one of the through holes 811a, the circuit board 81 is supported by each signal terminal 17. Alternatively, each signal terminal 17 may not include the bulging portion 170B and may be formed only by the base portion 170A. In other words, each signal terminal 17 may be a straight pin with no change in thickness. In this case, each signal terminal 17 is inserted into the through hole 811a and then soldered to the circuit board 81.

[0062] As shown in FIGS. 6 and 12, the circuit board 81 is formed with a plurality of mounting holes 851 and a plurality of positioning holes 852 .

[0063] As shown in FIGS. 6 and 12 , the multiple mounting holes 851 are individually inserted through the multiple base portions 72 (e.g., second portions 722). Each mounting hole 851 is formed, for example, as a perfect circle in plan view. The diameter of each mounting hole 851 in plan view is smaller than the diameter of each base portion 72 (particularly the first portion 721) in plan view. Therefore, the circuit board 81 is held above the first portion 721 in the first direction z (on the z1 side).

[0064] As shown in FIG. 6 , a plurality of positioning portions 73 are individually inserted into the plurality of positioning holes 852. In the illustrated example, two positioning holes 852 are formed in the circuit board 81. One of the two positioning holes 852 (the positioning hole 852 located on the y1 side in the third direction y) is formed as a perfect circle, and the other of the two positioning holes 852 (the positioning hole 852 located on the y2 side in the third direction y) is formed as an elongated hole. This facilitates positioning of the circuit board 81 relative to the attachment object C1. In this case, by forming one of the two positioning holes 852 as an elongated hole, slight misalignment between the attachment object C1 and the circuit board 81 due to manufacturing errors can be suppressed.

[0065] The circuit board 82 is electrically connected to the circuit board 81 via a plurality of interconnecting wires 83. As shown in FIGS. 2, 5, and 10 to 13, the circuit board 82 extends in the third direction y. The circuit board 82 is provided with circuits that drive and control the plurality of module units PM1 (i.e., the plurality of drive circuit units DR1), but are not provided on the circuit board 81. In this embodiment, the circuit board 82 is provided with two drive elements 82A, 82B (three drive elements 82A and three drive elements 82B in the illustrated example) for each module unit PM1. The circuit board 82 is located on the opposite side of the mounting object C1 (main body unit 71) in the first direction z, with the circuit board 81 sandwiched therebetween. The two circuit boards 81, 82 overlap each other when viewed in the first direction z.

[0066] As shown in FIG. 16 , the multiple interconnection wires 83 electrically connect the two circuit boards 81 and 82. In the power conversion unit B10, each of the multiple interconnection wires 83 has a pair of connection portions 831 and 832. As shown in FIGS. 15 and 16 , the connection portion 831 is electrically connected to the circuit board 81. As shown in FIGS. 15 and 16 , the connection portion 831 includes multiple connection pins 831A. The multiple connection pins 831A extend in the first direction z. As shown in FIG. 16 , the connection portion 832 is electrically connected to the circuit board 82 and faces the connection portion 831. As shown in FIG. 17 , the connection portion 832 has a housing portion 832A and multiple connection holes 832B. The multiple connection pins 831A are individually inserted into the multiple connection holes 832B. This electrically connects the connection portion 831 to the connection portion 832.

[0067] 17 , the housing portion 832A of the connection portion 832 can be displaced relative to the multiple connection pins 831A in a direction perpendicular to the first direction z. This allows the connection portion 832 to be displaced relative to the connection portion 831A in a direction perpendicular to the first direction z. Therefore, the multiple communication wires 83 are configured to be displaceable in a direction perpendicular to the first direction z. The configuration of such multiple communication wires 83 can be applied to the configuration of known connectors disclosed in Japanese Patent Application Laid-Open Nos. 2018-113163, 2018-63886, and 2017-139101, for example.

[0068] As shown in Figures 10, 11, 13, and 16, the multiple positioning pins 84 are located between the two circuit boards 81, 82 in the first direction z. The multiple positioning pins 84 are arranged to be spaced apart in the third direction y. Each of the multiple positioning pins 84 is located between two module units PM1 that are adjacent to each other in the third direction y among the multiple module units PM1. The multiple positioning pins 84 are used to determine the position of the circuit board 82 relative to the circuit board 81 and to support the circuit board 82.

[0069] Module unit PM1: structural example: Figures 18 to 29 show structural examples of multiple module units PM1. Figures 18 to 28 show enlarged views of one of the multiple module units PM1. All of the multiple module units PM1 have the same structure. Unless otherwise specified, the module unit PM1 described below is common to the first module unit PM11, second module unit PM12, and third module unit PM13.

[0070] 18 to 29 , each module unit PM1 (each of the first module unit PM11, the second module unit PM12, and the third module unit PM13) includes the above-mentioned plurality of power terminals 13, a plurality of signal terminals 17, a plurality of semiconductor elements 21, 22, and sealing resin 50, as well as a support substrate 11, a pair of thermistors TH, two conductive members 31, 32, a plurality of wires 41 to 45, and a pair of control wirings 601, 602. The plurality of power terminals 13 include a power terminal 14, two power terminals 15, and two power terminals 16, and the plurality of signal terminals 17 include a plurality of signal terminals 171A, 171B, 172A, 172B, 173A, 173B, 181A, 181B, 181C, 181D, 181E, 181F, 181G, 181H. In this embodiment, the plurality of semiconductor elements 21 and 22 include two semiconductor elements 21A and 21B and two semiconductor elements 22A and 22B, similar to the circuit configuration shown in FIG.

[0071] The power terminal 14 corresponds to the power terminal Tp in the above circuit configuration, each of the two power terminals 15 corresponds to the power terminal Tn in the above circuit configuration, and the two power terminals 16 correspond to the power terminal Tout in the above circuit configuration. Thus, each module unit PM1 converts a power supply voltage (e.g., DC) applied to the power terminal 14 and the two power terminals 15 into AC power using multiple semiconductor elements 21 and 22. The converted AC power is input from the two power terminals 16 to a power supply target such as a motor.

[0072] As shown in Figures 20, 24 to 26, 28, and 29, the support substrate 11 supports multiple semiconductor elements 21A, 21B, 22A, and 22B in the first direction z. The support substrate 11 is made of, for example, a DBC (Direct Bonded Copper) substrate. The support substrate 11 includes an insulating layer 111, a wiring layer 112, and a wiring layer 113. The support substrate 11 is covered with a sealing resin 50 except for a portion of the wiring layer 113.

[0073] 20 and 24 to 29, the insulating layer 111 includes a portion interposed between the wiring layer 112 and the wiring layer 113 in the first direction z. The insulating layer 111 is made of a material with relatively high thermal conductivity. The insulating layer 111 is made of ceramics containing aluminum nitride (AlN), for example. The insulating layer 111 may be made of an insulating resin sheet instead of ceramics.

[0074] As shown in FIGS. 20 and 24 to 29, the wiring layer 112 is located above (on the z1 side of) the insulating layer 111 in the first direction z. The wiring layer 112 contains copper (Cu). As shown in FIG. 20, the wiring layer 112 is surrounded by the periphery of the insulating layer 111 in a planar view. As shown in FIGS. 20 and 24 to 29, the wiring layer 112 includes two mounting portions 1121 and 1122. Each of the two mounting portions 1121 and 1122 is rectangular in a planar view. The two mounting portions 1121 and 1122 are spaced apart from each other in the second direction x. Each of the multiple semiconductor elements 21A, 21B, 22A, and 22B is bonded to one of the two mounting portions 1121 and 1122.

[0075] As shown in Figures 24 to 29, the wiring layer 113 is located below (on the z2 side of) the insulating layer 111 in the first direction z. As shown in Figure 23, the wiring layer 113 is exposed from the sealing resin 50. The wiring layer 113 contacts the upper surface (the surface facing the z1 side in the first direction z) of the main body 71 of the attachment target C1. The wiring layer 113 contains copper. The wiring layer 113 has a rectangular shape in a plan view. The wiring layer 113 is surrounded by the periphery of the insulating layer 111 in a plan view.

[0076] The two semiconductor elements 21A and 22A are each mounted on a mounting portion 1121. The two semiconductor elements 21A and 22A are arranged along the third direction y. The two semiconductor elements 21B and 22B are each mounted on a mounting portion 1122. The two semiconductor elements 21B and 22B are arranged along the third direction y.

[0077] As described above, each of the two semiconductor elements 21A and 21B has a plurality of electrodes 211, 212, and 213. In each of the semiconductor elements 21A and 21B, the electrode 211 (collector electrode) is disposed on a surface facing downward in the first direction z, and the electrode 212 (emitter electrode) and the electrode 213 (gate electrode) are disposed on a surface facing upward in the first direction z. The electrode 211 faces either the mounting portion 1121 or the mounting portion 1122. A current corresponding to the power before conversion by the semiconductor element 21 flows through the electrode 211. The electrode 212 is located on the opposite side of the electrode 211 in the first direction z. A current corresponding to the power after conversion by the semiconductor element 21 flows through the electrode 212. The electrode 213 is located on the same side as the electrode 212 in the first direction z. A drive signal (first drive signal or second drive signal) for driving the semiconductor element 21 is input to the electrode 213. As shown in FIG. 21, the area of ​​the electrode 213 is smaller than the area of ​​the electrode 212 in a plan view.

[0078] As described above, each of the two semiconductor elements 22A and 22B has a plurality of electrodes 221, 222, and 223. In each of the semiconductor elements 22A and 22B, the electrode 221 (drain electrode) is disposed on a surface facing downward in the first direction z, and the electrode 222 (source electrode) and the electrode 223 (gate electrode) are disposed on a surface facing upward in the first direction z. The electrode 221 faces either the mounting portion 1121 or the mounting portion 1122. A current corresponding to the power before conversion by the semiconductor element 22 flows through the electrode 221. The electrode 222 is located on the opposite side of the electrode 221 in the first direction z. A current corresponding to the power after conversion by the semiconductor element 22 flows through the electrode 222. The electrode 223 is located on the same side as the electrode 222 in the first direction z. A drive signal (first drive signal or second drive signal) for driving the semiconductor element 22 is input to the electrode 223. As shown in FIG. 21, the area of ​​the electrode 223 is smaller than the area of ​​the electrode 222 in a plan view.

[0079] The conductive bonding layer 23 electrically connects one of the two mounting portions 1121, 1122 to the electrode 211 of one of the two semiconductor elements 21A, 21B or the electrode 221 of one of the two semiconductor elements 22A, 22B. FIG. 25 illustrates an example in which the conductive bonding layer 23 is interposed between the mounting portion 1121 and the electrode 221 of the semiconductor element 22A, while FIG. 26 illustrates an example in which the conductive bonding layer 23 is interposed between the mounting portion 1122 and the electrode 211 of the semiconductor element 21B. The conductive bonding layer 23 is, for example, solder. Alternatively, the conductive bonding layer 23 may include a sintered body of metal particles. The electrode 211 of the semiconductor element 21A and the electrode 221 of the semiconductor element 22A are electrically connected to the mounting portion 1121 via the conductive bonding layer 23. The electrodes 211 of the semiconductor element 21B and the electrodes 221 of the semiconductor element 22B are electrically connected to the mounting portion 1122 via the conductive bonding layer 23 .

[0080] The multiple power terminals 13 are electrically connected to the multiple semiconductor elements 21, 22, respectively. A current corresponding to the power before being converted by the multiple semiconductor elements 21, 22 (two switching units SW1, SW2) or a current corresponding to the power after being converted by the multiple semiconductor elements 21, 22 (two switching units SW1, SW2) flows through the multiple power terminals 13. The multiple power terminals 13 include a power terminal 14, two power terminals 15, and two power terminals 16. The power terminal 14, together with the power terminal Tp, is an example of a "first power terminal" as defined in the claims, each power terminal 15, together with the power terminal Tn, is an example of a "second power terminal" as defined in the claims, and each power terminal 16, together with the power terminal Tout, is an example of a "third power terminal" as defined in the claims.

[0081] As shown in FIGS. 20 and 27 , the power terminal 14 is bonded to the mounting portion 1121. This bonding method is not limited to any particular method, and may be performed using a conductive bonding material (e.g., solder), laser welding, or crimping. The power terminal 14 is electrically connected to the electrode 211 of the semiconductor element 21A and the electrode 221 of the semiconductor element 22A (i.e., the connection end T11 of the switching unit SW1) via the mounting portion 1121. The power terminal 14 is a P terminal (positive electrode) to which a DC power supply voltage to be converted into power is applied. As shown in FIG. 20 , the power terminal 14 is located on the opposite side of the mounting portion 1122 in the second direction x, with the mounting portion 1121 sandwiched therebetween. The power terminal 14 extends from the mounting portion 1121 to one side (x1 side) in the second direction x and protrudes from the sealing resin 50 to one side (x1 side) in the second direction x. 19 and 27 , the power terminal 14 includes a portion covered with the sealing resin 50 and a portion exposed from the sealing resin 50. In the power terminal 14, the portion covered with the sealing resin 50 is joined to the mounting portion 1121. In addition, in the power terminal 14, the portion exposed from the sealing resin 50 is used as the aforementioned P terminal of each module unit PM1.

[0082] A conductive member 32 is joined to the two power terminals 15. The two power terminals 15 are electrically connected to the electrode 212 of the semiconductor element 21B and the electrode 222 of the semiconductor element 22B (i.e., the connection end T22 of the switching unit SW2) via the conductive member 32. The two power terminals 15 are N terminals (negative electrodes) to which the DC power supply voltage to be converted is applied. The two power terminals 15 are spaced apart from each other in the third direction y. The power terminal 14 is located between the two power terminals 15. As shown in FIG. 20 , the two power terminals 15 are located on the same side as the power terminal 14 with respect to the mounting portions 1121 and 1122 in the second direction x. The two power terminals 15 are spaced apart from the two mounting portions 1121 and 1122. The two power terminals 15 each extend in the second direction x and protrude from the sealing resin 50 to one side (x1 side) in the second direction x. 19 and 24 , each of the two power terminals 15 includes a portion covered with the sealing resin 50 and a portion exposed from the sealing resin 50. In each power terminal 15, a conductive member 32 is joined to the portion covered with the sealing resin 50. In addition, in each power terminal 15, the portion exposed from the sealing resin 50 is used as the aforementioned N terminal of each module unit PM1.

[0083] As shown in FIGS. 20 and 24 , the two power terminals 16 are each bonded to the mounting portion 1122. This bonding method is not limited to any particular method, and may be achieved by bonding using a conductive bonding material (e.g., solder) (not shown), laser welding, or crimping. The two power terminals 16 are electrically connected to the electrode 211 of the semiconductor element 21B and the electrode 221 of the semiconductor element 22B (i.e., the connection end T21 of the switching unit SW2) via the mounting portion 1122. The two power terminals 16 are also electrically connected to the electrode 212 of the semiconductor element 21A and the electrode 222 of the semiconductor element 22A (i.e., the connection end T12 of the switching unit SW1) via the mounting portion 1122 and the conductive member 31. AC power converted by the multiple semiconductor elements 21 and 22 is output from the two power terminals 16. In other words, the two power terminals 16 are output terminals for the AC power. The two power terminals 16 are spaced apart from each other in the third direction y. As shown in FIG. 20 , the two power terminals 16 are located on opposite sides of the mounting portion 1121 in the second direction x, with the mounting portion 1122 sandwiched between them. Each of the two power terminals 16 extends from the mounting portion 1122 toward the other side (x2 side) in the second direction x and protrudes from the sealing resin 50 toward the other side (x2 side) in the second direction x. As shown in FIGS. 19 and 24 , each of the two power terminals 16 includes a portion covered with the sealing resin 50 and a portion exposed from the sealing resin 50. In each power terminal 16, the portion covered with the sealing resin 50 is joined to the mounting portion 1122. In addition, in each power terminal 16, the portion exposed from the sealing resin 50 is used as the aforementioned output terminal of each module unit PM1.

[0084] The pair of control wirings 601, 602 constitute part of the conductive paths between the multiple signal terminals 17 and the multiple semiconductor elements 21, 22. The control wiring 601 is located between the semiconductor elements 21A and 22A and the power terminals 14 and two power terminals 15. The control wiring 601 is bonded to the mounting portion 1121 as shown in FIGS. 20 and 27. The control wiring 602 is located between the semiconductor elements 21B and 22B and the two power terminals 16 in the second direction x. The control wiring 602 is bonded to the mounting portion 1122 as shown in FIGS. 20 and 27. Each of the pair of control wirings 601, 602 has an insulating layer 61, multiple wiring layers 62, a metal layer 63, and multiple sleeves 64. Each of the pair of control wirings 601, 602 is covered with the sealing resin 50 except for a portion of each of the multiple sleeves 64. The insulating layer 61, the plurality of wiring layers 62, the metal layer 63, and the plurality of sleeves 64 described below are common to the control wirings 601 and 602 unless otherwise specified.

[0085] 27 , the insulating layer 61 includes a portion interposed between the wiring layer 62 and the metal layer 63 in the first direction z. The insulating layer 61 is made of, for example, ceramics. The insulating layer 61 may be made of an insulating resin sheet instead of ceramics.

[0086] 27, the wiring layer 62 is located above the insulating layer 61 in the first direction z (on the z1 side). The wiring layer 62 contains copper. In each of the control wirings 601, 602, the wiring layer 62 includes a plurality of wiring portions 621 to 627 that are spaced apart from one another, as shown in FIG. 21. The shapes and arrangement of the plurality of wiring portions 621 to 627 are not limited to the example shown in the figure.

[0087] 27 , the metal layer 63 is located on the opposite side of the wiring layers 62 in the first direction z, with the insulating layer 61 sandwiched therebetween. The metal layer 63 contains copper. The metal layer 63 of the control wiring 601 is bonded to the mounting portion 1121 by an adhesive layer (not shown). The metal layer 63 of the control wiring 602 is bonded to the mounting portion 1122 by an adhesive layer (not shown). These adhesive layers are made of a material that may or may not be conductive. For example, these adhesive layers are solder.

[0088] 27 , each of the multiple sleeves 64 is bonded to one of the multiple wiring portions 621 to 627 by a conductive bonding layer (e.g., solder) not shown. The multiple sleeves 64 are made of a conductive material such as metal. Each of the multiple sleeves 64 has a cylindrical shape extending along the first direction z. One end of each of the multiple sleeves 64 (the edge on the z2 side in the first direction z) is conductively bonded to one of the multiple wiring portions 621 to 627. As shown in FIG. 27 , the other end of each of the multiple sleeves 64 (the edge on the z1 side in the first direction z) is exposed from the sealing resin 50.

[0089] 21 , one of the pair of rectifying elements D11 is joined to a wiring portion 621 of the control wiring 601, and the other of the pair of rectifying elements D11 is joined to a wiring portion 622 of the control wiring 601. Each of the pair of rectifying elements D11 has two electrodes (not shown). In each rectifying element D11, the two electrodes are individually arranged on the upper surface and the lower surface in the first direction z. In an example where each rectifying element D11 is a diode, the electrode arranged on the upper surface (upper surface electrode) is an anode electrode, and the electrode arranged on the lower surface (lower surface electrode) is a cathode electrode. In this example, the wiring portions 621 and 622 of the control wiring 601 are each electrically connected to the lower surface electrodes (cathode electrodes) of the pair of rectifying elements D11.

[0090] 21 , each of the pair of rectifying elements D12 is joined to a wiring portion 624 of the control wiring 601. Each of the pair of rectifying elements D12 has two electrodes (not shown), and the two electrodes of each rectifying element D12 are individually arranged on the upper and lower surfaces in the first direction z. In an example where each D12 is a diode, the electrode arranged on the upper surface (upper electrode) is an anode electrode, and the electrode arranged on the lower surface (lower electrode) is a cathode electrode. In this example, the wiring portion 624 of the control wiring 601 is electrically connected to the lower electrodes (cathode electrodes) of the pair of rectifying elements D12.

[0091] 21 , one of the pair of rectifying elements D21 is joined to a wiring portion 621 of the control wiring 602, and the other of the pair of rectifying elements D21 is joined to a wiring portion 622 of the control wiring 602. Each of the pair of rectifying elements D21 has two electrodes (not shown). In each rectifying element D21, the two electrodes are individually arranged on the upper surface and the lower surface in the first direction z. In an example where each rectifying element D21 is a diode, the electrode arranged on the upper surface (upper surface electrode) is an anode electrode, and the electrode arranged on the lower surface (lower surface electrode) is a cathode electrode. In this example, the wiring portions 621 and 622 of the control wiring 602 are each electrically connected to the lower surface electrodes (cathode electrodes) of the pair of rectifying elements D21.

[0092] 21 , each of the pair of rectifying elements D22 is joined to a wiring portion 624 of the control wiring 602. Each of the pair of rectifying elements D22 has two electrodes (not shown), and in each rectifying element D22, the two electrodes are individually arranged on the upper and lower surfaces in the first direction z. In an example where each D22 is a diode, the electrode arranged on the upper surface (upper electrode) is an anode electrode, and the electrode arranged on the lower surface (lower electrode) is a cathode electrode. In this example, the wiring portion 624 of the control wiring 602 is electrically connected to the lower electrodes (cathode electrodes) of the pair of rectifying elements D22.

[0093] As shown in FIG. 21 , one of the pair of thermistors TH straddles and is conductively connected to a pair of wiring portions 626 of the control wiring 601. As shown in FIG. 21 , the other of the pair of thermistors TH straddles and is conductively connected to a pair of wiring portions 626 of the control wiring 602. Each of the pair of thermistors TH is, for example, an NTC (Negative Temperature Coefficient) thermistor. NTC thermistors have the characteristic of gradually decreasing resistance as temperature rises. Each of the pair of thermistors TH is used as a temperature detection sensor for the corresponding module unit PM1.

[0094] As shown in FIGS. 22 and 27 , each of the signal terminals 17 is a metal pin extending in the first direction z. The signal terminals 17 protrude from a top surface 51 (described later) of the sealing resin 50. The signal terminals 17 are individually press-fitted into the sleeves 64 of the pair of control wirings 601 and 602. As a result, each of the signal terminals 17 is supported by one of the sleeves 64 and is electrically connected to one of the wiring layers 62 of the pair of control wirings 601 and 602. The signal terminals 17 include a pair of signal terminals 171A and 172A, a pair of signal terminals 171B and 172B, a signal terminal 173A, a signal terminal 173B, a pair of signal terminals 181A, a pair of signal terminals 181B, and a signal terminal 19. A pair of signal terminals 171A, 172A, a pair of signal terminals 171B, 172B, a signal terminal 173A, a signal terminal 173B, a pair of signal terminals 181A, a pair of signal terminals 181B and a signal terminal 19 are inserted into a circuit board 81 and input or output each signal to the circuit board 81.

[0095] The signal terminal 171A is press-fitted into one of the multiple sleeves 64 that is joined to the wiring portion 623 of the control wiring 601. As a result, the signal terminal 171A is supported by the sleeve 64 and is electrically connected to the wiring portion 623 of the control wiring 601. Furthermore, the signal terminal 171A is electrically connected to the electrode 213 of the semiconductor element 21A and the electrode 223 of the semiconductor element 22A. The signal terminal 172A is press-fitted into one of the multiple sleeves 64 that is joined to the wiring portion 624 of the control wiring 601. As a result, the signal terminal 172A is supported by the sleeve 64 and is electrically connected to the wiring portion 624 of the control wiring 601. Furthermore, the signal terminal 172A is electrically connected to the electrode 213 of the semiconductor element 21A and the electrode 223 of the semiconductor element 22A.

[0096] A pair of signal terminals 171A, 172A receive drive signals (first drive signals) for driving the semiconductor elements 21A and 22A. A first turn-on signal is input to the signal terminal 171A, and a first turn-off signal is input to the signal terminal 172A. The pair of signal terminals 171A, 172A correspond to the signal terminals Ton1, Toff1, respectively, in the circuit configuration of the intelligent power module A10 (see FIG. 1).

[0097] The signal terminal 171B is press-fitted into one of the multiple sleeves 64 that is joined to the wiring portion 623 of the control wiring 602. As a result, the signal terminal 171B is supported by the sleeve 64 and is electrically connected to the wiring portion 623 of the control wiring 602. Furthermore, the signal terminal 171B is electrically connected to the electrode 213 of the semiconductor element 21B and the electrode 223 of the semiconductor element 22B. The signal terminal 172B is press-fitted into one of the multiple sleeves 64 that is joined to the wiring portion 624 of the control wiring 602. As a result, the signal terminal 172B is supported by the sleeve 64 and is electrically connected to the wiring portion 624 of the control wiring 602. Furthermore, the signal terminal 172B is electrically connected to the electrode 213 of the semiconductor element 21B and the electrode 223 of the semiconductor element 22B.

[0098] A drive signal (second drive signal) for driving the semiconductor elements 21B and 22B is input to the pair of signal terminals 171B and 172B. A second turn-on signal is input to the signal terminal 171B, and a second turn-off signal is input to the signal terminal 172B. The pair of signal terminals 171B and 172B correspond to the signal terminals Ton2 and Toff2, respectively, in the circuit configuration of the intelligent power module A10 (see FIG. 1).

[0099] As shown in FIG. 21 , the signal terminal 173A is positioned next to the signal terminal 171A in the third direction y. The signal terminal 173A is press-fitted into one of the multiple sleeves 64 that is joined to the wiring portion 625 of the control wiring 601. This allows the signal terminal 173A to be supported by the sleeve 64 and to be electrically connected to the wiring portion 625 of the control wiring 601. Furthermore, the signal terminal 173A is electrically connected to the electrode 212 of the semiconductor element 21A and the electrode 222 of the semiconductor element 22A. A voltage corresponding to the maximum current flowing through the electrode 212 of the semiconductor element 21A and the electrode 222 of the semiconductor element 22A is applied to the signal terminal 173A. The signal terminal 173A corresponds to the signal terminal Tss1 in the circuit configuration of the intelligent power module A10 (see FIG. 1 ).

[0100] As shown in FIG. 21 , the signal terminal 173B is located next to the signal terminal 171B in the third direction y. The signal terminal 173B is press-fitted into one of the multiple sleeves 64 that is joined to the wiring portion 625 of the control wiring 602. This allows the signal terminal 173B to be supported by the sleeve 64 and to be electrically connected to the wiring portion 625 of the control wiring 602. Furthermore, the signal terminal 173B is electrically connected to the electrode 212 of the semiconductor element 21B and the electrode 222 of the semiconductor element 22B. A voltage corresponding to the maximum current flowing through the electrode 212 of the semiconductor element 21B and the electrode 222 of the semiconductor element 22B is applied to the signal terminal 173B. The signal terminal 173B corresponds to the signal terminal Tss2 in the circuit configuration of the intelligent power module A10 (see FIG. 1 ).

[0101] As shown in FIG. 21 , the pair of signal terminals 181A are located on opposite sides of the signal terminal 172A from the signal terminal 171A in the third direction y. The pair of signal terminals 181A are adjacent to each other in the third direction y. The pair of signal terminals 181A are individually press-fitted into a pair of sleeves 64 that are respectively joined to a pair of wiring portions 626 of the control wiring 601. As a result, the pair of signal terminals 181A are individually supported by the pair of sleeves 64 and are individually electrically connected to the pair of wiring portions 626 of the control wiring 601. Furthermore, the pair of signal terminals 181A are electrically connected to the thermistor TH on the control wiring 601.

[0102] As shown in FIG. 21 , the pair of signal terminals 181B are located on opposite sides of the signal terminal 172B from the signal terminal 171B in the third direction y. The pair of signal terminals 181B are adjacent to each other in the third direction y. The pair of signal terminals 181B are individually press-fitted into a pair of sleeves 64 that are respectively joined to a pair of wiring portions 626 of the control wiring 602. As a result, the pair of signal terminals 181B are individually supported by the pair of sleeves 64 and are individually electrically connected to the pair of wiring portions 626 of the control wiring 602. Furthermore, the pair of signal terminals 181B are electrically connected to the thermistor TH on the control wiring 602.

[0103] 21 , the signal terminal 19 is located on the opposite side of the signal terminal 171A from the signal terminal 173A in the third direction y. The signal terminal 19 is press-fitted into a sleeve 64 joined to the wiring portion 627 of the control wiring 601. As a result, the signal terminal 19 is supported by the sleeve 64 and is electrically connected to the wiring portion 627 of the control wiring 601. Furthermore, the signal terminal 19 is electrically connected to the mounting portion 1121. A voltage equivalent to the DC power input to the power terminal 14 is applied to the signal terminal 19.

[0104] Each of the plurality of wires 41 to 45 electrically connects portions spaced apart from one another. Each of the plurality of wires 41 to 45 is a bonding wire. The composition of each of the plurality of wires 41 to 45 includes gold (Au). Alternatively, the composition of each of the plurality of wires 41 to 45 may include copper or aluminum. Note that the plurality of wires 41 to 45 are omitted as appropriate in FIGS. 24 and 27.

[0105] 21 , one of the wires 41 is joined to the electrode 213 of the semiconductor element 21A and the wiring portion 621 of the control wiring 601, electrically connecting them. One of the wires 43 is joined to the upper electrode (anode electrode) of one of the pair of rectifying elements D11 (the rectifying element D11 joined to the wiring portion 621 of the control wiring 601) and the wiring portion 623 of the control wiring 601, electrically connecting them. Thus, the electrode 213 of the semiconductor element 21A is electrically connected to the signal terminal 171A via one of the pair of rectifying elements D11. In this electrical connection, the electrode 213 of the semiconductor element 21A is electrically connected to the lower electrode (cathode electrode) of the rectifying element D11, and the signal terminal 171A is electrically connected to the upper electrode (anode electrode) of the rectifying element D11. That is, the rectifying element D11 is connected so that a forward current flows from the signal terminal 171A to the electrode 213 of the semiconductor element 21A. Furthermore, one of the wires 44 is joined to the wiring portion 621 of the control wiring 601 and one of the upper electrodes (anode electrodes) of the pair of rectifying elements D12, electrically connecting them. Therefore, the electrode 213 of the semiconductor element 21A is electrically connected to the signal terminal 172A via one of the pair of rectifying elements D12. In this electrical connection, the electrode 213 of the semiconductor element 21A is electrically connected to the upper electrode (anode electrode) of the rectifying element D12, and the signal terminal 172A is electrically connected to the lower electrode (cathode electrode) of the rectifying element D12. That is, the rectifying element D12 is connected so that a forward current flows from the electrode 213 of the semiconductor element 21A to the signal terminal 172A.

[0106] 21 , one of the wires 41 is joined to the electrode 223 of the semiconductor element 22A and the wiring portion 622 of the control wiring 601, electrically connecting them. One of the wires 43 is joined to the top electrode (anode electrode) of the other of the pair of rectifying elements D11 (the rectifying element D11 joined to the wiring portion 622 of the control wiring 601) and the wiring portion 623 of the control wiring 601, electrically connecting them. Thus, the electrode 223 of the semiconductor element 22A is electrically connected to the signal terminal 171A via the other of the pair of rectifying elements D11. In this electrical connection, the electrode 223 of the semiconductor element 22A is electrically connected to the bottom electrode (cathode electrode) of the rectifying element D11, and the signal terminal 171A is electrically connected to the top electrode (anode electrode) of the rectifying element D11. That is, the rectifying element D11 is connected so that a forward current flows from the signal terminal 171A to the electrode 223 of the semiconductor element 22A. Furthermore, one of the wires 44 is joined to the wiring portion 622 of the control wiring 601 and the top electrode (anode electrode) of the other of the pair of rectifying elements D12, electrically connecting them. Therefore, the electrode 223 of the semiconductor element 22A is electrically connected to the signal terminal 172A via the other of the pair of rectifying elements D12. In this electrical connection, the electrode 223 of the semiconductor element 22A is electrically connected to the top electrode (anode electrode) of the rectifying element D12, and the signal terminal 172A is electrically connected to the bottom electrode (cathode electrode) of the rectifying element D12. That is, the rectifying element D12 is connected so that a forward current flows from the electrode 223 of the semiconductor element 22A to the signal terminal 172A.

[0107] 21 , one of the wires 41 is joined to the electrode 213 of the semiconductor element 21B and the wiring portion 621 of the control wiring 602, electrically connecting them. One of the wires 43 is joined to the upper electrode (anode electrode) of one of the pair of rectifying elements D21 (the rectifying element D21 joined to the wiring portion 621 of the control wiring 602) and the wiring portion 623 of the control wiring 602, electrically connecting them. Thus, the electrode 213 of the semiconductor element 21B is electrically connected to the signal terminal 171B via one of the pair of rectifying elements D21. In this electrical connection, the electrode 213 of the semiconductor element 21B is electrically connected to the lower electrode (cathode electrode) of the rectifying element D21, and the signal terminal 171B is electrically connected to the upper electrode (anode electrode) of the rectifying element D21. That is, the rectifying element D21 is connected so that a forward current flows from the signal terminal 171B to the electrode 213 of the semiconductor element 21B. Furthermore, one of the wires 44 is joined to the wiring portion 621 of the control wiring 602 and one of the upper electrodes (anode electrodes) of the pair of rectifying elements D22, electrically connecting them. Therefore, the electrode 213 of the semiconductor element 21B is electrically connected to the signal terminal 172B via one of the pair of rectifying elements D22. In this electrical connection, the electrode 213 of the semiconductor element 21B is electrically connected to the upper electrode (anode electrode) of the rectifying element D22, and the signal terminal 172B is electrically connected to the lower electrode (cathode electrode) of the rectifying element D22. That is, the rectifying element D22 is connected so that a forward current flows from the electrode 213 of the semiconductor element 21B to the signal terminal 172B.

[0108] 21 , one of the wires 41 is joined to the electrode 223 of the semiconductor element 22B and the wiring portion 622 of the control wiring 602, electrically connecting them. One of the wires 43 is joined to the upper electrode (anode electrode) of the other of the pair of rectifying elements D21 (the rectifying element D21 joined to the wiring portion 622 of the control wiring 602) and the wiring portion 623 of the control wiring 602, electrically connecting them. Thus, the electrode 223 of the semiconductor element 22B is electrically connected to the signal terminal 171B via the other of the pair of rectifying elements D21. In this electrical connection, the electrode 223 of the semiconductor element 22B is electrically connected to the lower electrode (cathode electrode) of the rectifying element D21, and the signal terminal 171B is electrically connected to the upper electrode (anode electrode) of the rectifying element D21. That is, the rectifying element D21 is connected so that a forward current flows from the signal terminal 171B to the electrode 223 of the semiconductor element 22B. Furthermore, one of the wires 44 is joined to the wiring portion 622 of the control wiring 602 and the top electrode (anode electrode) of the other of the pair of rectifying elements D22, electrically connecting them. Therefore, the electrode 223 of the semiconductor element 22B is electrically connected to the signal terminal 172B via the other of the pair of rectifying elements D22. In this electrical connection, the electrode 223 of the semiconductor element 22B is electrically connected to the top electrode (anode electrode) of the rectifying element D22, and the signal terminal 172B is electrically connected to the bottom electrode (cathode electrode) of the rectifying element D22. That is, the rectifying element D22 is connected so that a forward current flows from the electrode 223 of the semiconductor element 22B to the signal terminal 172B.

[0109] One of the plurality of wires 42 is joined to and electrically connects the electrode 212 of the semiconductor element 21A and the wiring portion 625 of the control wiring 601. One of the plurality of wires 42 is joined to and electrically connects the electrode 222 of the semiconductor element 22A and the wiring portion 625 of the control wiring 601. Thus, the electrode 212 of the semiconductor element 21A and the electrode 222 of the semiconductor element 22A are each electrically connected to the signal terminal 173A.

[0110] One of the plurality of wires 42 is joined to and electrically connects the electrode 212 of the semiconductor element 21B and the wiring portion 625 of the control wiring 602. One of the plurality of wires 42 is joined to and electrically connects the electrode 222 of the semiconductor element 22B and the wiring portion 625 of the control wiring 602. Thus, the electrode 212 of the semiconductor element 21B and the electrode 222 of the semiconductor element 22B are each electrically connected to the signal terminal 173B.

[0111] The wire 45 is joined to and electrically connects the wiring portion 627 of the control wiring 601 and the mounting portion 1121. Thus, the signal terminal 19 is electrically connected to the electrode 211 of the semiconductor element 21A and the electrode 221 of the semiconductor element 22A.

[0112] As shown in Figures 20, 21, and 24, the conductive member 31 is conductively bonded to the electrodes 212 of the semiconductor element 21A and the electrodes 222 of the semiconductor element 22A and the mounting portion 1122. This allows the electrodes 212 of the semiconductor element 21A and the electrodes 222 of the semiconductor element 22A to be electrically connected to the mounting portion 1122. The conductive member 31 contains copper. The conductive member 31 is a so-called metal clip. The conductive member 31 has a main body 311, a plurality of joints 312, and a plurality of joints 313.

[0113] The main body portion 311 forms a main part of the conductive member 31. As shown in FIGS. 20 and 21 , the main body portion 311 extends in the second direction x. As shown in FIGS. 20 , 21 , and 24 , the main body portion 311 straddles the two mounting portions 1121 and 1122. In the example shown in FIGS. 20 and 21 , a plurality of through holes are formed in the main body portion 311. Each of the plurality of through holes penetrates the main body portion 311 in the first direction z. In a plan view, the plurality of through holes overlap between the two mounting portions 1121 and 1122. This allows the sealing resin 50 to flow smoothly downward in the first direction z (toward the z2 side of the first direction z) of the main body portion 311 during the formation of the sealing resin 50.

[0114] As shown in Figures 20, 21, 24, 25, and 28, each of the multiple joints 312 is individually bonded to the electrode 212 of the semiconductor element 21A or the electrode 222 of the semiconductor element 22A. Each of the multiple joints 312 faces either the electrode 212 of the semiconductor element 21A or the electrode 222 of the semiconductor element 22A. In a plan view, each joint 312 extends from the main body 311 toward the x1 side in the second direction x. In the illustrated example, the multiple joints 312 are bifurcated from the main body 311, but they do not have to be bifurcated. The base end of each joint 312 (the end connected to the main body 311) is bent downward in the first direction z (toward the z2 side in the first direction z). Therefore, the tip of each joint 312 (the end opposite to the side connected to the main body 311) is located below the main body 311 in the first direction z (on the z2 side in the first direction z).

[0115] 20 , 21 , and 24 , the multiple joints 313 are joined to the mounting portion 1122. Each of the multiple joints 313 faces the mounting portion 1122. In a plan view, each joint 313 extends from the main body 311 toward the x2 side in the second direction x. The base end of each joint 313 (the end connected to the main body 311) is bent downward in the first direction z (toward the z2 side in the first direction z). Therefore, the tip of each joint 313 (the end opposite to the end connected to the main body 311) is located below the main body 311 in the first direction z (toward the z2 side in the first direction z).

[0116] 25 , the module unit PM1 further includes a plurality of conductive bonding layers 33. The plurality of conductive bonding layers 33 are respectively interposed between the electrode 212 of the semiconductor element 21A and the bonding portion 312 facing the electrode 212, and between the electrode 222 of the semiconductor element 22A and the bonding portion 312 facing the electrode 222. The conductive bonding layers 33 conductively bond the electrode 212 of the semiconductor element 21A and the electrode 222 of the semiconductor element 22A to the plurality of bonding portions 312. Each of the plurality of conductive bonding layers 33 is, for example, solder. Alternatively, each of the plurality of conductive bonding layers 33 may include a sintered body of metal particles.

[0117] 24 , the module unit PM1 further includes a plurality of conductive bonding layers 34. Each of the plurality of conductive bonding layers 34 is interposed between one of the plurality of bonding portions 313 of the conductive member 31 and the mounting portion 1122. Each of the plurality of conductive bonding layers 34 individually conductively bonds one of the plurality of bonding portions 313 to the mounting portion 1122. Each of the plurality of conductive bonding layers 34 is, for example, solder. Alternatively, each of the plurality of conductive bonding layers 34 may include a sintered body of metal particles.

[0118] 19 , the conductive member 32 is conductively bonded to the electrode 212 of the semiconductor element 21B, the electrode 222 of the semiconductor element 22B, and the two power terminals 15. This allows the electrode 212 of the semiconductor element 21B and the electrode 222 of the semiconductor element 22B to be electrically connected to the two power terminals 15. The conductive member 32 contains copper. The conductive member 32 is a so-called metal clip. The conductive member 32 includes a main body 321, a plurality of joints 322, and a pair of joints 323.

[0119] The main body 321 forms a main part of the conductive member 32. As shown in Fig. 24 and Fig. 27 to Fig. 29, the main body 321 is disposed parallel to the upper surfaces of the mounting portions 1121 and 1122. The main body 321 is spaced apart from the main body 311 of the conductive member 31 and from each of the two mounting portions 1121 and 1122.

[0120] As shown in FIGS. 26 and 29 , the multiple joints 322 are individually bonded to the electrodes 212 of the semiconductor element 21B and the electrodes 222 of the semiconductor element 22B. Each of the multiple joints 322 faces either the electrode 212 of the semiconductor element 21B or the electrode 222 of the semiconductor element 22B. In a plan view, the multiple joints 322 extend from the main body 321 in the second direction x. The base end of each joint 322 (the end connected to the main body 321) is bent downward in the first direction z (toward the z2 side of the first direction z). Therefore, the tip of each joint 322 (the end opposite to the end connected to the main body 321) is located below the main body 321 in the first direction z (toward the z2 side of the first direction z).

[0121] 19 and 24 , the pair of joints 323 are individually joined to the two power terminals 15. Each of the pair of joints 323 faces a corresponding one of the two power terminals 15.

[0122] 26 , the module unit PM1 further includes a plurality of conductive bonding layers 35. The plurality of conductive bonding layers 35 are respectively interposed between the electrode 212 of the semiconductor element 21B and the bonding portion 322 facing the electrode 212, and between the electrode 222 of the semiconductor element 22B and the bonding portion 322 facing the electrode 222. The plurality of conductive bonding layers 35 conductively bond the electrode 212 of the semiconductor element 21B and the electrode 222 of the semiconductor element 22B to the plurality of bonding portions 322. Each of the plurality of conductive bonding layers 35 is, for example, solder. Alternatively, each of the plurality of conductive bonding layers 35 may include a sintered body of metal particles.

[0123] 24 , the module unit PM1 further includes a plurality of conductive bonding layers 36. The plurality of conductive bonding layers 36 are respectively interposed between the two power terminals 15 and the pair of bonding portions 323. The plurality of conductive bonding layers 36 conductively bond the two power terminals 15 and the pair of bonding portions 323. Each of the plurality of conductive bonding layers 36 is, for example, solder. Alternatively, each of the plurality of conductive bonding layers 36 may include a sintered body of metal particles.

[0124] As shown in Figures 18, 19, and 22 to 29, the sealing resin 50 covers the semiconductor elements 21 and 22, the two conductive members 31 and 32, and the wires 41 to 45. The sealing resin 50 also covers the support substrate 11, the power terminals 13, and a portion of each of the signal terminals 17. The sealing resin 50 has electrical insulation properties. The sealing resin 50 contains, for example, a black epoxy resin. The sealing resin 50 is formed, for example, by molding. The sealing resin 50 has a top surface 51, a bottom surface 52, a plurality of resin side surfaces 53, and a pair of recesses 55.

[0125] As shown in Figures 18, 22, 24, and 27 to 29, the top surface 51 faces the same direction as the upper surfaces of the mounting portions 1121 and 1122 in the first direction z. The top surface 51 of each module unit PM1 contacts the attachment member D1. As shown in Figures 22 to 24 and 27 to 29, the bottom surface 52 faces the opposite side from the top surface 51 in the first direction z. As shown in Figures 23, 24, and 27 to 29, the wiring layer 113 of the support substrate 11 is exposed from the bottom surface 52. The bottom surface 52 of each module unit PM1 contacts the main body portion 71 of the attachment object C1.

[0126] The plurality of resin side surfaces 53 are connected to the top surface 51. The plurality of resin side surfaces 53 include a pair of side surfaces 531, 532 and a pair of side surfaces 533.

[0127] As shown in Figures 18, 19, 22, 23, 24, and 27, the pair of side surfaces 531, 532 are spaced apart from each other in the second direction x. Each of the pair of side surfaces 531, 532 is connected to the top surface 51. The pair of side surfaces 531, 532 face opposite each other in the second direction x and extend in the third direction y. The side surface 531 faces the x1 side in the second direction x, and the side surface 532 faces the x2 side in the second direction x. A power terminal 14 and two power terminals 15 protrude from the side surface 531. Two power terminals 16 protrude from the side surface 532. The side surface 531 is an example of a "first resin side surface" as defined in the claims, and the side surface 532 is an example of a "second resin side surface" as defined in the claims.

[0128] 18 , 19 , 23 , 28 , and 29 , the pair of side surfaces 533 are spaced apart from each other in the third direction y. The pair of side surfaces 533 face opposite each other in the third direction y and extend in the second direction x. The pair of side surfaces 533 are connected to the top surface 51 and the bottom surface 52.

[0129] 18 , the pair of recesses 55 are recessed from the side surface 531 in the second direction x. The pair of recesses 55 extend from the top surface 51 to the bottom surface 52 in the first direction z. The pair of recesses 55 are located on both sides of the power terminal 14 in the third direction y.

[0130] The specific configuration of each module unit PM1 described above is merely an example and is not limited to the above example. For example, the number of signal terminals 17, the signals input / output to / from each signal terminal 17, the number of semiconductor elements 21 and 22, and the configuration of the pair of control wirings 601 and 602 may be changed as appropriate. Furthermore, the support substrate 11 may have a conductive plate-like member bonded to the wiring layer 112 (each of the two mounting portions 1121 and 1122). In this case, the semiconductor elements 21 and 22 and the pair of control wirings 601 and 602 are mounted on the conductive plate-like member.

[0131] Furthermore, in each module unit PM1, the semiconductor element 21 may have an additional electrode on its upper surface that has the same potential as the electrode 212. Furthermore, the semiconductor element 22 may have an additional electrode on its upper surface that has the same potential as the electrode 222. In this case, each wire 42 is connected to one of these additional electrodes instead of the electrodes 212 and 222. That is, in each module unit PM1, each semiconductor element 21 and 22 may have an electrode for current sensing.

[0132] Semiconductor element 21 (IGBT): Figures 30 to 32 show detailed configuration examples of the semiconductor element 21 configured as an IGBT. Note that the configuration examples shown in Figures 30 to 32 are merely examples and are not intended to be limiting.

[0133] First, the planar structure of the semiconductor element 21 will be described with reference to Fig. 30. Fig. 30 is a plan view showing the semiconductor element 21.

[0134] The semiconductor element 21 includes a semiconductor layer G2 formed on a chip having a rectangular shape in plan view. The semiconductor layer G2 has an element formation region G6, an outer region G7, a breakdown voltage holding region G8, and a scribe region G9 defined therein.

[0135] The element forming region G6 is set in the central region of the semiconductor layer G2 in a plan view seen from the normal direction of the first main surface G3 of the semiconductor layer G2 (hereinafter simply referred to as "plan view"). The outer region G7 is set in a region outside the element forming region G6. The breakdown voltage holding region G8 is set in a region outside the outer region G7. The scribe region G9 is set in a region outside the breakdown voltage holding region G8.

[0136] The element formation region G6 is a region in which an IGBT (Insulated Gate Bipolar Transistor) is formed. The element formation region G6 is set to have a rectangular shape in a plan view, with four sides parallel to the sides of the semiconductor layer G2. The IGBT formed in the element formation region G6 structurally includes an npn-type parasitic bipolar transistor. The outer region G7 is a region that separates the element formation region G6 from other regions (voltage-resistance holding region G8). The voltage-resistance holding region G8 is a region for improving the voltage-resistance of the semiconductor element 21. The scribe region G9 is a region through which a cutting member such as a dicing blade passes during manufacturing.

[0137] A surface electrode G10 is formed on the first main surface G3 of the semiconductor layer G2. The surface electrode G10 includes a gate electrode G11 (corresponding to the above-mentioned electrode 213), an emitter electrode G12 (corresponding to the above-mentioned electrode 212), a field plate electrode G13, and an equipotential potential electrode G14. The gate electrode G11, the emitter electrode G12, the field plate electrode G13, and the equipotential potential electrode G14 are electrically insulated from each other by an insulating region G15 that borders them.

[0138] The gate electrode G11 includes a gate pad G16 and a gate finger G17. In this embodiment, the gate pad G16 is formed in a rectangular shape in a plan view. The gate pad G16 is drawn out from the outer region G7 into the element forming region G6 and crosses the boundary region between the element forming region G6 and the outer region G7. The gate finger G17 is drawn out from the gate pad G16 in the outer region G7 and defines the element forming region G6 from three directions. The gate finger G17 has a pair of open ends G18, G19. The gate finger G17 extends in a strip shape in the region between the pair of open ends G18, G19 and the gate pad G16.

[0139] The emitter electrode G12 includes an emitter pad G22, an emitter routing portion G23, and an emitter connection portion G24. The emitter pad G22 is formed in a region that is concave in plan view and defined by the periphery of the gate pad G16 and the periphery of the gate finger G17. The periphery of the emitter pad G22 extends from the element formation region G6 into the outer region G7 and crosses the boundary region between the element formation region G6 and the outer region G7. The emitter routing portion G23 is formed in the outer region G7. In the illustrated example, the emitter routing portion G23 is formed in an endless shape (a square ring shape in plan view) surrounding the gate finger G17. The emitter routing portion G23 may also be formed in an ended shape surrounding the gate finger G17. The emitter connection portion G24 is led out from the emitter pad G22. The emitter connection portion G24 crosses the region between the pair of open ends G18, G19 of the gate finger G17 and is connected to the emitter routing portion G23. The emitter routing portion G23 is electrically connected to the emitter pad G22 via the emitter connection portion G24.

[0140] In this embodiment, the emitter electrode G12, which includes the emitter pad G22, the emitter routing portion G23, and the emitter connection portion G24, forms an avalanche current recovery structure G25. The avalanche current recovery structure G25 recovers the avalanche current generated in a region outside the element formation region G6. More specifically, the emitter routing portion G23 recovers the avalanche current generated in a region outside the element formation region G6. The recovered avalanche current is taken out from the emitter pad G22 via the emitter connection portion G24.

[0141] A plurality of field plate electrodes G13 (five in the example) are formed at intervals from the outer region G7 to the scribe region G9. Each field plate electrode G13 is routed in a strip shape along the emitter routing portion G23.

[0142] The equipotential potential electrode G14 is formed in the scribe region G9 and is routed in a strip shape along the field plate electrode G13.

[0143] Next, the internal structure of the semiconductor element 21 will be described with reference to Figures 31 and 32. Figure 31 is a cross-sectional view taken along line XXXI-XXXI in Figure 30. Figure 32 is a cross-sectional view taken along line XXXII-XXXII in Figure 30.

[0144] The semiconductor layer G2 has a single-layer structure including an n-type semiconductor substrate G31. In this embodiment, the n-type semiconductor substrate G31 is a silicon FZ (Floating Zone) substrate formed by the FZ method. A collector electrode G32 (corresponding to the electrode 211) serving as a back surface electrode is connected to the second main surface G4 of the semiconductor layer G2.

[0145] In the element formation region G6, a p-type channel region G33 is formed in a surface layer portion of the first main surface G3 of the semiconductor layer G2. The element formation region G6 can be defined by a region surrounded by the periphery of the p-type channel region G33 in a plan view.

[0146] In the element formation region G6, an n-type drift region G34 is formed in a region on the second main surface G4 side of the semiconductor layer G2 relative to the p-type channel region G33. The n-type drift region G34 is electrically connected to the p-type channel region G33. The n-type drift region G34 is formed by utilizing a partial region of the n-type semiconductor substrate G31. In addition to the element formation region G6, the n-type drift region G34 is also formed in the outer region G7, the breakdown voltage holding region G8, and the scribe region G9.

[0147] In the element forming region G6, a p+ type collector region G35 is formed in a surface layer portion of the second main surface G4 of the semiconductor layer G2. The p+ type collector region G35 is electrically connected to the collector electrode G32 outside the semiconductor layer G2. The p+ type collector region G35 is electrically connected to the n- type drift region G34 within the semiconductor layer G2. In addition to the element forming region G6, the p+ type collector region G35 is also formed in the outer region G7, the breakdown voltage holding region G8, and the scribe region G9. The p+ type collector region G35 is formed not only in an opposing region opposing the p-type channel region G33, but also in a non-opposing region not opposing the p-type channel region G33.

[0148] An n-type buffer region G36 is formed in the boundary region between the n- type drift region G34 and the p+ type collector region G35. The n-type buffer region G36 is a high-concentration, low-resistance region having an n-type impurity concentration higher than the n- type impurity concentration of the n- type drift region G34. In the illustrated example, the p+ type collector region G35 is electrically connected to the n- type drift region G34 via the n-type buffer region G36.

[0149] In the element formation region G6, a plurality of trench gate structures G37 are formed at intervals on the first main surface G3 of the semiconductor layer G2. In this embodiment, the plurality of trench gate structures G37 are formed in band shapes extending in the same direction in a plan view.

[0150] The trench gate structure G37 includes a gate trench G38, a gate insulating film G39, and a buried gate electrode G40. The gate trench G38 is formed to penetrate the p-type channel region G33 and has a bottom located in the n-type drift region G34. The gate insulating film G39 is formed along the inner wall surface of the gate trench G38. The buried gate electrode G40 is buried in the gate trench G38 with the gate insulating film G39 sandwiched therebetween. A surface insulating film G41 covering the first main surface G3 of the semiconductor layer G2 outside the gate trench G38 is formed on the first main surface G3. The gate insulating film G39 is continuous with the surface insulating film G41 outside the gate trench G38.

[0151] 32, the trench gate structure G37 includes an arbitrary trench gate structure G37 formed in the vicinity of the outer region G7. The embedded gate electrode G40 of the arbitrary trench gate structure G37 includes a gate lead-out portion G42 led out from within the gate trench G38 toward the outer region G7.

[0152] The gate lead-out portion G42 is led out from within the gate trench G38 to a region (not shown) directly below the gate pad G16 and / or a region directly below the gate finger G17. FIG. 32 shows an example in which the gate lead-out portion G42 is formed in a region directly below the gate finger G17. The gate lead-out portion G42 is electrically connected to the gate pad G16 and the gate finger G17. This electrically connects the trench gate structure G37 to the gate electrode G11.

[0153] On the side of each trench gate structure G37, an n+ type emitter region G43 is formed in a surface layer portion of the p-type channel region G33. On the side of each trench gate structure G37, an n+ type emitter region G43, a p-type channel region G33, and an n- type drift region G34 are formed in this order from the first main surface G3 toward the second main surface G4 of the semiconductor layer G2.

[0154] In the region between adjacent trench gate structures G37, a first contact recess G44 for the emitter pad G22 is formed in the surface layer of the p-type channel region G33. The first contact recess G44 is shallower than the gate trench G38 and has a bottom located within the p-type channel region G33. The p-type channel region G33 is exposed from the bottom of the first contact recess G44. The p-type channel region G33 and the n+ type emitter region G43 are exposed from the side portions of the first contact recess G44.

[0155] The p-type channel region G33 includes a p+-type contact region G45 having a higher p-type impurity concentration than other regions. The p+-type contact region G45 is formed in a region of the p-type channel region G33 along the bottom of the first contact recess G44.

[0156] The p-type channel region G33 is shared by adjacent trench gate structures G37. The buried gate electrode G40 faces the n+ type emitter region G43, the p-type channel region G33, and the n- type drift region G34, with a gate insulating film G39 sandwiched therebetween.

[0157] The trench gate structure G37, the n+ type emitter region G43, the p-type channel region G33, and the n- type drift region G34 form a channel structure G46 of the IGBT. The channel of the IGBT is formed in the p-type channel region G33 between the n+ type emitter region G43 and the n- type drift region G34, on the side of the trench gate structure G37.

[0158] 32, a dummy channel structure G47 is formed in the boundary region between the element formation region G6 and the outer region G7. The dummy channel structure G47 has the same structure as the channel structure G46, except that it does not include the n+ type emitter region G43. In the dummy channel structure G47 that does not include the n+ type emitter region G43, no IGBT channel is formed on the side of the trench gate structure G37.

[0159] In the boundary region between the element formation region G6 and the outer region G7, the current in the element formation region G6 and the current outside the element formation region G6 merge, so the current density tends to be relatively high. The IGBT channel structure G46, due to its structure, forms the aforementioned npn-type parasitic bipolar transistor. The dummy channel structure G47 does not include the n+-type emitter region G43, so due to its structure, no npn-type parasitic bipolar transistor is formed. Therefore, by forming the dummy channel structure G47 in the boundary region between the element formation region G6 and the outer region G7, latch-up caused by the parasitic bipolar transistor can be suppressed.

[0160] 32 , in the outer region G7, a p+ type termination region G51 is formed in a surface layer portion of the first main surface G3 of the semiconductor layer G2. The p+ type termination region G51 defines the outer region G7. The p+ type termination region G51 is a high-concentration, low-resistance region having a p-type impurity concentration higher than the p-type impurity concentration of the p-type channel region G33. The bottom of the p+ type termination region G51 is formed at a position closer to the second main surface G4 of the semiconductor layer G2 than the bottom of the gate trench G38 in the thickness direction of the semiconductor layer G2.

[0161] The inner edge region of the p+ type termination region G51 located on the p-type channel region G33 side overlaps the bottom of the trench gate structure G37 of the dummy channel structure G47. The inner edge region of the p+ type termination region G51 may overlap the bottom of the p-type channel region G33. The bottom of the p+ type termination region G51 is formed at a distance from the p+ type collector region G35 toward the first main surface G3 of the semiconductor layer G2. The p+ type termination region G51 faces the p+ type collector region G35 across a portion of the n- type drift region G34. The p+ type termination region G51 faces the gate pad G16 and / or the gate finger G17 across the surface insulating film G41. The p+ type termination region G51 faces the gate pull-out portion G42 across the surface insulating film G41.

[0162] 32 , in the breakdown voltage holding region G8, a p+ type field limit region G52 is formed in a surface layer portion of the first main surface G3 of the semiconductor layer G2. The p+ type field limit region G52 relieves the electric field in the breakdown voltage holding region G8. The p+ type field limit region G52 has a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the p+ type termination region G51. The p+ type field limit region G52 has a depth that is approximately equal to the depth of the p+ type termination region G51.

[0163] 32, in the scribe region G9, an n+ type channel stop region G53 is formed in a surface layer portion of the first main surface G3 of the semiconductor layer G2. The n+ type channel stop region G53 is a high-concentration, low-resistance region having an n-type impurity concentration higher than the n-type impurity concentration of the n- type drift region G34. The n+ type channel stop region G53 suppresses the spread of a depletion layer from a pn junction formed in an inner region of the semiconductor layer G2.

[0164] In the outer region G7, a second contact recess G54 for the emitter pad G22 and a third contact recess G55 for the emitter routing portion G23 are formed in a surface layer portion of the p+ type termination region G51. The second contact recess G54 is formed by digging down into the first main surface G3 of the semiconductor layer G2. The second contact recess G54 has a bottom located within the p+ type termination region G51. The second contact recess G54 is formed to a depth approximately equal to that of the first contact recess G44. The third contact recess G55 is formed by digging down into the first main surface G3 of the semiconductor layer G2. The third contact recess G55 has a bottom located within the p+ type termination region G51. The third contact recess G55 is formed to a depth approximately equal to that of the first contact recess G44.

[0165] The p+ type termination region G51 includes a p+ type contact region G56 formed in a region along the bottom of the second contact recess G54. The p+ type contact region G56 is a high-concentration region in the p+ type termination region G51 where the p-type impurity concentration is higher than in other regions. The p+ type termination region G51 includes a p+ type contact region G57 formed in a region along the bottom of the third contact recess G55. The p+ type contact region G57 is a high-concentration region in the p+ type termination region G51 where the p-type impurity concentration is higher than in other regions.

[0166] In the breakdown voltage holding region G8, a fourth contact recess G58 for the field plate electrode G13 is formed in a surface layer portion of the p+ type field limit region G52. The fourth contact recess G58 is formed by digging down into the first main surface G3 of the semiconductor layer G2. The fourth contact recess G58 has a bottom located within the p+ type field limit region G52. The fourth contact recess G58 is formed to a depth approximately equal to that of the first contact recess G44.

[0167] The p+ type field limit region G52 includes a p+ type contact region G59 formed in a region along the bottom of the fourth contact recess G58. The p+ type contact region G59 is a high-concentration region in the p+ type field limit region G52 where the p-type impurity concentration is higher than in other regions.

[0168] In the scribe region G9, a fifth contact recess G60 for the equipotential potential electrode G14 is formed in a surface layer portion of the first main surface G3 of the semiconductor layer G2. The fifth contact recess G60 is formed by digging down into the first main surface G3 of the semiconductor layer G2. The fifth contact recess G60 is formed to a depth approximately equal to that of the first contact recess G44. The n+ type channel stop region G53 is exposed from the fifth contact recess G60.

[0169] In the semiconductor layer G2, a p+ type contact region G61 is formed in a region along the bottom of the fifth contact recess G60.

[0170] 31 and 32, an insulating layer G64 is formed on the first main surface G3 of the semiconductor layer G2. The insulating layer G64 covers the element forming region G6, the outer region G7, the breakdown voltage holding region G8, and the scribe region G9.

[0171] The insulating layer G64 has a first contact hole G65, a second contact hole G67, and a third contact hole G68 for the emitter electrode G12 formed therein. The first contact hole G65, the second contact hole G67, and the third contact hole G68 are flush with and communicate with the first contact recess G44, the second contact recess G54, and the third contact recess G55 in a one-to-one correspondence, respectively. The insulating layer G64 has a fourth contact hole G69 for the field plate electrode G13 formed therein. The fourth contact hole G69 is flush with and communicates with the fourth contact recess G58. The insulating layer G64 has a fifth contact hole G70 for the equipotential potential electrode G14 formed therein. The fifth contact hole G70 is flush with and communicates with the fifth contact recess G60. The insulating layer G64 has a gate contact hole G71 for the gate electrode G11 formed therein. The gate contact hole G71 exposes the gate lead portion G42 in the region directly below the gate pad G16 and / or the region directly below the gate finger G17.

[0172] The aforementioned surface electrode G10 is formed on the insulating layer G64. The surface electrode G10 has a laminated structure including a first conductive layer G72 formed on the insulating layer G64 and a second conductive layer G73 formed on the first conductive layer G72. The first conductive layer G72 may have a single-layer structure consisting of a titanium nitride layer or a titanium layer, or may have a laminated structure including a titanium nitride layer and a titanium layer formed on the titanium nitride layer. The first conductive layer G72 functions as a barrier electrode layer by including the titanium nitride layer and / or the titanium layer. The second conductive layer G73 may include at least one conductor selected from the group consisting of copper, a copper-containing alloy, aluminum, and an aluminum-containing alloy.

[0173] The gate pad G16 and / or the gate finger G17 of the surface electrode G10 enters the gate contact hole G71 from above the insulating layer G64. The gate pad G16 and / or the gate finger G17 are electrically connected to the gate lead-out portion G42 within the gate contact hole G71.

[0174] The emitter pad G22 of the front surface electrode G10 extends from above the insulating layer G64 into the first contact hole G65 and the second contact hole G67. The emitter pad G22 is electrically connected to the p-type channel region G33 and the n+ type emitter region G43 in the first contact hole G65. The emitter pad G22 is electrically connected to the p+ type termination region G51 in the second contact hole G67.

[0175] The emitter routing portion G23 of the surface electrode G10 extends from above the insulating layer G64 into the third contact hole G68. The emitter routing portion G23 is electrically connected to the p+ type termination region G51 within the third contact hole G68.

[0176] In the semiconductor layer G2, the avalanche current flowing in a region outside the element formation region G6 is collected by the emitter electrode G12 via the p+ type termination region G51. Therefore, the avalanche current collection structure G25 described above includes, in addition to the emitter pad G22, the emitter routing portion G23, and the emitter connection portion G24, the p+ type termination region G51 electrically connected to these.

[0177] The field plate electrode G13 of the surface electrode G10 extends from above the insulating layer G64 into the fourth contact hole G69. The field plate electrode G13 is electrically connected to the p+ type field limit region G52 within the fourth contact hole G69.

[0178] The semiconductor element 21 included in the intelligent power module A10 (power conversion unit B10) may be, for example, an IGBT having the planar structure and internal structure shown in FIGS. 30 to 32 . Note that the planar structure and internal structure shown in FIGS. 30 to 32 are merely examples and are not limiting. For example, although FIGS. 30 to 32 show an example in which the semiconductor element 21 is a trench gate IGBT, the semiconductor element 21 may also be a planar gate IGBT. FIG. 33 shows a configuration example of the semiconductor element 21 when a planar gate IGBT is formed in the element formation region G6. FIG. 33 is a schematic cross-sectional view of the semiconductor element 21 employing a planar gate IGBT.

[0179] The semiconductor element 21 shown in FIG. 33 includes the semiconductor layer G2 described above. As shown in FIG. 33, the p-type channel region G33 described above is formed at an interval in a surface layer portion of the first main surface G3 of the semiconductor layer G2. The n+ type emitter region G43 and the p+ type contact region G45 described above are formed at an interval inward from the periphery of the p-type channel region G33 in a surface layer portion of the p-type channel region G33. The n-type buffer region G36 and the p+ type collector region G35 described above are formed in a surface layer portion of the second main surface G4 of the semiconductor layer G2. In the semiconductor layer G2, the region between the p-type channel region G33 and the n-type buffer region G36 is the n- type drift region G34 described above.

[0180] In the element forming region G6, a planar gate structure G102 is formed on the first main surface G3 of the semiconductor layer G2. The planar gate structure G102 includes a gate insulating film G103 and a gate electrode G104.

[0181] The gate electrode G104 faces the n+ type emitter region G43, the p-type channel region G33, and the n- type drift region G34, with the gate insulating film G103 sandwiched therebetween. The planar gate structure G102 is covered with the insulating layer G64 described above. In this modification, the element formation region G6 is defined by a region surrounded by the p+ type termination region G51.

[0182] A contact hole G105 is formed in the insulating layer G64 to expose the p-type channel region G33 and the n+ type emitter region G43. The emitter electrode G12 described above extends into the contact hole G105 from above the insulating layer G64 and is electrically connected to the p-type channel region G33 and the n+ type emitter region G43 within the contact hole G105. A collector electrode G32 is formed on the second main surface G4 side of the semiconductor layer G2 so as to be electrically connected to the p+ type collector region G35.

[0183] As described above, the semiconductor element 21 included in the intelligent power module A10 (power conversion unit B10) of the present disclosure is not limited in any way to whether it is a trench gate type (see FIGS. 30 to 32) or a planar gate type (see FIG. 33). Furthermore, the semiconductor element 21 included in the intelligent power module A10 (power conversion unit B10) of the present disclosure is not limited in any way to whether it is a p-channel type or an n-channel type.

[0184] Semiconductor element 22 (MOSFET): FIGS. 34 to 36 show a detailed configuration example of the semiconductor element 22 configured as a MOSFET. FIG. 34 is a schematic plan view of the semiconductor element 22. FIG. 35 is a schematic cross-sectional view taken along line XXXV-XXXV in FIG. 34. Note that in FIG. 35, only the portions made of conductors are hatched, and hatching of other portions is omitted. FIG. 36 is a schematic enlarged cross-sectional view of the vicinity of the first region of the source region and the channel region shown in FIG. 35. Note that the configuration examples shown in FIGS. 34 to 36 are merely examples and are not intended to be limiting.

[0185] As shown in Fig. 35, the semiconductor element 22 includes a semiconductor substrate M102. The semiconductor substrate M102 is made of SiC doped with N-type impurities (N-type SiC). A semiconductor layer M103 is formed on the semiconductor substrate M102 by epitaxial growth. That is, the semiconductor layer M103 is an epitaxial layer made of N-type SiC.

[0186] A plurality of P-type well regions M104 are formed in a surface layer portion of the semiconductor layer M103. The plurality of well regions M104 have a quadrangular shape (approximately square shape) in a plan view and are arranged in a matrix.

[0187] An N-type source region M105 is formed in the surface layer of each well region M104 at a distance from the periphery of the well region M104. As shown in Figure 34, in the source region M105, a first region M105A having a predetermined width (e.g., 0.2 μm) from the periphery in a plan view has an N-type impurity concentration that is one to three orders of magnitude lower than the N-type impurity concentration of the remaining second region M105B (the region inside the first region M105A). That is, the source region M105 has an N+ type second region M105B having a relatively high N-type impurity concentration and an N- type first region M105A having a ring shape surrounding the second region M105B and a relatively low N-type impurity concentration. A step MS is formed between the upper surfaces of the first region M105A and the second region M105B, such that the upper surface of the second region M105B is one step lower than the upper surface of the first region M105A (see FIG. 16). There is no large step between the upper surface of the first region M105A and the upper surface of the well region M104 (channel region C), and they are substantially flush with each other.

[0188] A P+ type contact region M106 is formed in the center of the second region M105B of each source region M105, and is doped with a higher concentration of P type impurities than the well region M104. Each contact region M106 is formed to penetrate the second region M105B in the depth direction, and its deepest portion reaches the well region M104 present below the source region M105.

[0189] A gate insulating film M107 is formed on the semiconductor layer M103. The gate insulating film M107 has an AlON / SiO2 stacked structure including a relatively thin SiO2 film M107A made of SiO2 (silicon oxide) containing N (nitrogen), and an AlON film M107B made of AlON (aluminum oxynitride) and formed on the SiO2 film M107A.

[0190] As shown in FIG. 35 , a gate electrode M108 is formed on the gate insulating film M107 (AlON film M107B). The gate electrode M108 faces the semiconductor layer M103 between the well regions M104, the channel region C between the periphery of each well region M104 and the periphery of the source region M105 located inside it, and a part of the first region M105A of the source region M105, across the gate insulating film M107. The gate electrode M108 is formed in a lattice shape in a planar view as shown in FIG. 34 . This gives the semiconductor element 22 a planar-gate MIS structure. The gate electrode M108 is made of polysilicon doped with N-type or P-type impurities, or a metal material containing Al (aluminum).

[0191] 35, an interlayer insulating film M109 is formed on the semiconductor layer M103. The upper surface of the semiconductor layer M103 as well as the gate electrode M108 is covered with the interlayer insulating film M109. The interlayer insulating film M109 is made of, for example, silicon oxide.

[0192] A contact hole M110 is formed in the interlayer insulating film M109 at a position facing each contact region M106. Each contact hole M110 penetrates the gate insulating film M107, and the entire contact region M106 and a portion of the source region M105 surrounding the contact region M106 are exposed within each contact hole M110.

[0193] A source metal M111 (corresponding to the electrode 222) is formed on the interlayer insulating film M109. The source metal M111 penetrates each contact hole M110 formed in the interlayer insulating film M109 and is connected to the source region M105 and the contact region M106. The source metal M111 is made of a metal material containing, for example, aluminum (Al) as a main component.

[0194] As shown in FIG. 34, an opening is formed at the center of a portion along one side edge of the semiconductor element 22 to expose a portion of the gate electrode M108 as a gate pad M112 (corresponding to the above-mentioned electrode 223) for connection to the outside.

[0195] As shown in Figure 35, on the entire back surface of the semiconductor substrate M102, an ohmic metal M113 made of nickel (Ni) or the like and a drain metal M114 (corresponding to the above-mentioned electrode 221) made of a metal material containing aluminum as its main component are formed in this order from the semiconductor substrate M102 side.

[0196] 36, in the semiconductor element 22, the N-type impurity concentration of the first region M105A adjacent to the channel region C in the source region M105 is reduced, so that no large step is formed between the upper surface of the first region M105A and the upper surface of the channel region C (well region M104). Therefore, electrons (e-) flowing between the source metal M111 and the drain metal M114 move from the source region M105 along the upper surface of the first region M105A to the channel region C, and then move through the channel region C along its upper surface. In other words, the path of the electrons in the channel region C is a straight path along the upper surface of the channel region C.

[0197] The semiconductor element 22 included in the intelligent power module A10 (power conversion unit B10) may be a MOSFET having the planar structure and internal structure shown in FIGS. 34 to 36 . The planar structure and internal structure shown in FIGS. 34 to 36 are merely examples and are not limiting. For example, while FIGS. 34 to 36 show examples in which the semiconductor element 22 is a planar-gate MOSFET, the semiconductor element 22 may also be a trench-gate MOSFET. FIGS. 37 and 38 show configuration examples of the semiconductor element 22 that is a trench-gate MOSFET. FIGS. 37 and 38 are schematic cross-sectional views of the semiconductor element 22 that employs a trench-gate MIS-structure MOSFET. Note that in FIG. 37 , only the conductor portions are hatched, and the other portions are not. FIG. 38 is a schematic enlarged cross-sectional view of the first region of the source region and the vicinity of the channel region shown in FIG. 37 .

[0198] The semiconductor element 22 shown in FIGS. 37 and 38 includes a semiconductor substrate M162. The semiconductor substrate M162 is made of SiC doped with N-type impurities (N-type SiC). A semiconductor layer M163 is formed on the semiconductor substrate M162 by epitaxial growth. That is, the semiconductor layer M163 is an epitaxial layer made of N-type SiC. A base layer portion of the semiconductor layer M163 remains in the state after epitaxial growth and forms an N-type drain region M164. A surface layer portion of the semiconductor layer M163 is doped with P-type impurities to form a P-type well region M165.

[0199] Gate trenches M166 are formed in the semiconductor layer M163 by digging down from the surface thereof. The gate trenches M166 are formed in a lattice shape in a plan view, similar to the gate electrode M108 shown in Fig. 34. The gate trenches M166 penetrate the well region M165, and their deepest portions reach the drain region M164.

[0200] A gate insulating film M167 is formed on the inner surface of the gate trench M166. The gate insulating film M167 has an AlON / SiO2 stacked structure including a relatively thin SiO2 film M167A made of SiO2 (silicon oxide) containing N (nitrogen) and an AlON film M167B made of AlON (aluminum oxynitride). The SiO2 film M167A is in contact with the inner surface of the gate trench M166, and the AlON film M167B is formed on the SiO2 film M167A.

[0201] The inside of the gate insulating film M167 is filled with polysilicon doped with N-type or P-type impurities, so that a gate electrode M168 made of the doped polysilicon is buried in the gate trench M166. Here, the gate electrode M168 may be made of a metal material containing Al (aluminum).

[0202] An N-type source region M169 is formed in a surface layer portion of the well region M165. In the source region M169, a first region M169A at a predetermined depth (for example, 0.2 μm) from the bottom thereof has an N-type impurity concentration that is one to three orders of magnitude lower than the N-type impurity concentration of the remaining second region M169B (the region above the first region M169A). In other words, the source region M169 has an N+ type second region M169B with a relatively high N-type impurity concentration, and an N- type first region M169A formed below the second region M169B and with a relatively low N-type impurity concentration. Due to the difference in N-type impurity concentration between the first region M169A and the second region M169B, a step MS is formed between the side surface of the first region M169A and the side surface of the second region M169B, in which the side surface of the second region M169B is farther away from the gate electrode M168 than the side surface of the first region M169A. No large step is formed between the side surface of the first region M169A and the side surface of the well region M165 (channel region C), and they are substantially flush with each other.

[0203] In the surface layer of the well region M165, within each region surrounded by the gate trench M166, a P+ type contact region M170 is formed at a position spaced apart from the gate trench M166, penetrating the source region M169 in the thickness direction.

[0204] An interlayer insulating film M171 is stacked on the semiconductor layer M163. The interlayer insulating film M171 is made of, for example, silicon oxide. Contact holes M172 are formed through the interlayer insulating film M171 at positions facing each contact region M170. The entire contact region M170 and a portion of the source region M169 surrounding the contact region M170 face into each contact hole M172. A source metal M173 is formed on the interlayer insulating film M171. The source metal M173 penetrates each contact hole M172 and is connected to the source region M169 and the contact region M170. The source metal M173 is made of, for example, a metallic material containing Al as a main component.

[0205] On the entire back surface of the semiconductor substrate M162, an ohmic metal M174 made of nickel (Ni) or the like and a drain metal M175 made of a metal material containing aluminum as a main component are formed in this order from the semiconductor substrate M162 side.

[0206] 38 , in the semiconductor element 22, the N-type impurity concentration of the first region M169A adjacent to the channel region C in the source region M169 is reduced, so that no large step is formed between the side surface of the first region M169A and the side surface of the channel region C (well region M165). Therefore, electrons (e−) flowing between the source metal M173 and the drain metal M175 move from the source region M169 along the side surface of the first region M169A (the inner surface of the gate trench M166) to the channel region C, and then move through the channel region C along that side surface. In other words, the path of the electrons in the channel region C is a straight path along the side surface of the channel region C.

[0207] Vehicle F1: Next, the vehicle F1 equipped with the intelligent power module A10 will be described with reference to Fig. 39. The vehicle F1 is, for example, an electric vehicle (EV).

[0208] As shown in Figure 39, the vehicle F1 includes an on-board charger 93, a storage battery 94, and a drive system 95. The on-board charger 93 is supplied with power wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to the on-board charger 93 via a wired connection. The on-board charger 93 is configured with a step-up DC-DC converter. The voltage of the power supplied to the on-board charger 93 is stepped up by the converter and then supplied to the storage battery 94. The stepped-up voltage is, for example, 600V.

[0209] The drive system 95 drives the vehicle F1. The drive system 95 includes an inverter 951 and a drive source 952. The power conversion unit B10 (intelligent power module A10, module unit PM1) constitutes part of the inverter 951. Power stored in the storage battery 94 is supplied to the inverter 951. The power supplied from the storage battery 94 to the inverter 951 is DC power. Alternatively, unlike the power system shown in FIG. 39 , a step-up DC-DC converter may be further provided between the storage battery 94 and the inverter 951. The inverter 951 converts DC power into AC power. The inverter 951, including the power conversion unit B10 (intelligent power module A10, module unit PM1), is electrically connected to a drive source 952. The drive source 952 includes an AC motor and a transmission. When AC power converted by the inverter 951 is supplied to the drive source 952, the AC motor rotates, and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotational speed transmitted from the AC motor and then rotates the drive shaft of the vehicle F1. This drives the vehicle F1. To drive the vehicle F1, it is necessary to freely control the rotational speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. Therefore, the power conversion unit B10 (intelligent power module A10, module part PM1) in the inverter 951 is necessary to output AC power whose frequency is appropriately changed to correspond to the required rotational speed of the AC motor.

[0210] The functions and effects of the intelligent power module A10 and the power conversion unit B10 according to the first embodiment are as follows.

[0211] The intelligent power module A10 includes two semiconductor elements 21A and 22A, a pair of rectifying elements D11, and a pair of rectifying elements D12. The semiconductor element 21A has a plurality of electrodes 211, 212, and 213, and the semiconductor element 22A has a plurality of electrodes 221, 222, and 223. The pair of rectifying elements D11 are connected in series between the electrodes 213 and 223 via a connection point C11, and the pair of rectifying elements D12 are connected in series between the electrodes 213 and 223 via a connection point C12. The intelligent power module A10 also includes a driving element 82A, a resistor R11, and a resistor R12. The resistor R11 is connected between the connection point C11 and the driving element 82A, and the resistor R12 is connected between the connection point C12 and the driving element 82A. Each of the pair of rectifying elements D11 is connected so that a forward current flows individually from connection point C11 to electrode 213 and electrode 223. Each of the pair of rectifying elements D12 is connected so that a forward current flows individually from electrode 213 and electrode 223 to connection point C12. With this configuration, for example, in switching unit SW1, electrode 213 of semiconductor element 21A is electrically connected to electrode 223 of semiconductor element 22A through one of the pair of rectifying elements D12, connection point C12, signal terminal Toff1, resistor R12, resistor R11, signal terminal Ton1, connection point C11, and one of the pair of rectifying elements D11. In other words, in the two semiconductor elements 21 and 22, the electrical connection path between electrode 213 and electrode 223 is lengthened by the pair of rectifying elements D11 and the pair of rectifying elements D12. This increases the parasitic impedance of the wiring between the electrode 213 of the semiconductor element 21A and the electrode 223 of the semiconductor element 22A. This increase in parasitic impedance is effective in suppressing resonance of the drive signal when the two semiconductor elements 21A and 22A are driven in parallel. Therefore, even when the two semiconductor elements 21 and 22 are switched by a common drive signal, it is possible to suppress resonance of the drive signal. This also applies to the relationship between the two semiconductor elements 21B and 22B (switching unit SW2), the pair of rectifying elements D21 and the pair of rectifying elements D22, the drive element 82B, and the two resistors R21 and R22.

[0212] The intelligent power module A10 includes a pair of rectifying elements D11. The pair of rectifying elements D11 are connected in series via a connection point C11, and are connected so that forward currents flow individually from the connection point C11 to the electrodes 213 and 223. A resistor R11 is connected between the drive element 82A and the connection point C11. In the intelligent power module A10, the resistor R11 functions as a gate resistor when the switching unit SW1 (semiconductor elements 21A and 22A) is turned on. The intelligent power module A10 also includes a pair of rectifying elements D12. The pair of rectifying elements D12 are connected in series via a connection point C12, and are connected so that forward currents flow individually from the electrodes 213 and 223 to the connection point C12. The resistor R12 is connected between the drive element 82A and the connection point C12. In the intelligent power module A10, the resistor R12 functions as a gate resistor when the switching unit SW1 (semiconductor elements 21A and 22A) is turned off. Normally, when separate gate resistors are configured for turn-on and turn-off, diodes are connected in series to these gate resistors. However, in the intelligent power module A10, the pair of rectifying elements D11 and the pair of rectifying elements D12 serve as the diodes, respectively. That is, in the intelligent power module A10, there is no need to provide a gate resistor (resistor R11) for turn-on and a gate resistor (resistor R12) for turn-off. The same applies to the pair of rectifying elements D21 and the pair of rectifying elements D22.

[0213] In the intelligent power module A10, the semiconductor element 21 is an IGBT, and the semiconductor element 22 is a MOSFET. It is generally known that MOSFETs and IGBTs exhibit the following electrical characteristics due to differences in their physical properties and structures. For example, MOSFETs have faster switching speeds and lower switching losses than IGBTs. Switching losses are losses that occur when each switching element switches (when turned on or off). On the other hand, IGBTs have lower on-resistance and lower steady-state losses than MOSFETs in the high-current range. Steady-state losses are losses that occur when each switching element is in a steady state (conducting state) and are losses due to the on-resistance of each switching element. Therefore, in the intelligent power module A10, the semiconductor element 21, which is an IGBT, and the semiconductor element 22, which is a MOSFET, are electrically connected in parallel. This allows the intelligent power module A10 to reduce both switching losses and steady-state losses, thereby reducing power loss. In other words, the intelligent power module A10 can improve conversion efficiency.

[0214] In the intelligent power module A10, the semiconductor element 21 has a first semiconductor substrate (semiconductor substrate G31). The material of the first semiconductor substrate includes, for example, silicon (Si). The semiconductor element 22 has a second semiconductor substrate (semiconductor substrate M102). The material of the second semiconductor substrate has a wider band gap than the material of the first semiconductor substrate, including, for example, SiC. SiC has a wider band gap than Si, and switching elements using SiC have the advantage of, for example, lower power loss than switching elements using Si. On the other hand, switching elements using SiC are more expensive than switching elements using Si. Therefore, in the intelligent power module A10, the first semiconductor substrate (semiconductor substrate G31) of the semiconductor element 21 is made of Si, and the second semiconductor substrate (semiconductor substrate M102) of the semiconductor element 22 is made of SiC, thereby achieving both reduced power loss and suppressed cost increases. Furthermore, switching elements using SiC have a faster switching speed than switching elements using Si. Therefore, forming the second semiconductor substrate (semiconductor substrate M102) from SiC is effective in suppressing power loss (switching loss) during switching (turning on and off).

[0215] In the power conversion unit B10, the wiring board E1 includes two circuit boards 81 and 82. The two circuit boards 81 and 82 are arranged along the first direction z. Each electronic component (a plurality of resistors R11, R12, R21, and R22 and two drive elements 82A and 82B) constituting the drive circuit unit DR1 is mounted on one of the two circuit boards 81 and 82. This configuration allows the mounting area of ​​each electronic component constituting the drive circuit unit DR1 to be increased even if the planar area of ​​the wiring board E1 (the two circuit boards 81 and 82) is small. Therefore, even if the planar size of each module unit PM1 is reduced, for example, the mounting area of ​​each electronic component constituting the drive circuit unit DR1 can be ensured.

[0216] In the power conversion unit B10, the circuit board 81 has electronic components (each of the multiple resistors R11, R12, R21, and R22) mounted on its upper surface, but no electronic components mounted on its lower surface. When each module unit PM1 is energized, the semiconductor elements 21 and 22 of each module unit PM1 generate heat, which may radiate heat from each module unit PM1. Furthermore, when each module unit PM1 is energized, electromagnetic noise may leak from each module unit PM1. Therefore, by mounting electronic components on the upper surface of the circuit board 81 but not on its lower surface, it is possible to prevent failure and malfunction of the drive circuit unit DR1 due to the aforementioned heat radiation and electromagnetic noise leakage.

[0217] Other embodiments and modifications of the intelligent power module A10 and power conversion unit B10 of the present disclosure will be described below. The configurations of the components in each embodiment and each modification can be combined with each other to the extent that no technical contradictions arise.

[0218] In the first embodiment, each of the switching units SW1 and SW2 includes one semiconductor element 21 and one semiconductor element 22. However, instead of this configuration, each of the switching units SW1 and SW2 may include multiple semiconductor elements 21 and multiple semiconductor elements 22. In this example, in each of the switching units SW1 and SW2, the multiple semiconductor elements 21 are connected in parallel, and the multiple semiconductor elements 22 are connected in parallel. FIG. 40 shows an example of the structure of the module unit PM1 according to such a modified example. FIG. 40 shows an example in which two semiconductor elements 21A and two semiconductor elements 22A are electrically connected in parallel, and two semiconductor elements 21B and two semiconductor elements 22B are electrically connected in parallel. In the example shown in FIG. 40, the two semiconductor elements 21A and two semiconductor elements 22A are each mounted on the mounting portion 1121. The two semiconductor elements 21B and two semiconductor elements 22B are each mounted on the mounting portion 1122.

[0219] As can be seen from the modified example shown in FIG. 40 , the intelligent power module A10 (power conversion unit B10) of the present disclosure is not limited to one in which one semiconductor element 21 and one semiconductor element 22 are electrically connected in parallel, but also includes one in which multiple semiconductor elements 21 and multiple semiconductor elements 22 are electrically connected in parallel.

[0220] In the first embodiment described above, an example was shown in which the wiring board E1 of the power conversion unit B10 includes one circuit board 81 and one circuit board 82 for multiple module units PM1, but instead, the wiring board E1 may include an individual circuit board 81 and circuit board 82 for each module unit PM1. Figures 41 to 43 show an example structure of a power conversion unit B11 according to such a modified example.

[0221] In the power conversion unit B11, the wiring board E1 includes three circuit boards 81 and three circuit boards 82 for the three module units PM1. One circuit board 81 and one circuit board 82 form a pair, and the pair of circuit boards 81, 82 are arranged in the shape of the corresponding module unit PM1.

[0222] As can be understood from the modified examples shown in Figures 41 to 43, the power conversion unit (configuration including multiple intelligent power modules) of the present disclosure is not limited to one in which common circuit boards 81, 82 are provided for multiple module units PM1, but also includes one in which circuit boards 81, 82 are provided individually for each of the multiple module units PM1.

[0223] In the first embodiment described above, an example was shown in which the wiring board E1 of the power conversion unit B10 includes two circuit boards 81 and 82. However, instead of this example, the wiring board E1 may be configured to include only the circuit board 81. Fig. 44 shows an example of the structure of a power conversion unit B12 according to such a modified example.

[0224] 44, the wiring board E1 does not include a circuit board 81, but includes a circuit board 82. In addition to a plurality of resistors R11, R12, R21, and R22, a plurality of driving elements 82A and 82B are mounted on the circuit board 81.

[0225] As can be seen from the modified example shown in FIG. 44 , the power conversion unit (intelligent power module) of the present disclosure is not limited to one in which the electronic components of the drive circuit section DR1 are mounted on two circuit boards 81, 82, but also includes one in which the electronic components are mounted on a single circuit board 81.

[0226] In the first embodiment, an example was shown in which electrodes were formed on the upper and lower surfaces of each of the rectifying elements D11, D12, D21, and D22. However, instead of this configuration, electrodes may be formed on a pair of side surfaces facing opposite each other. In this example, the arrangement and shape of the wiring portions of each of the wiring layers 62 of the two control wirings 601 and 602 are appropriately modified, and each of the rectifying elements D11, D12, D21, and D22 is joined across two of the modified wiring portions.

[0227] 45 shows an intelligent power module A20 according to the second embodiment. The intelligent power module A20 differs from the intelligent power module A10 in the following respects. First, a pair of rectifying elements D11 and a pair of rectifying elements D12 are each provided in the drive circuit unit DR1. Second, a pair of rectifying elements D21, D22 are each provided in the drive circuit unit DR1.

[0228] In the intelligent power module A20, as in the intelligent power module A10, even when two semiconductor elements 21, 22 are switched by a common drive signal, it is possible to suppress resonance of the drive signal. In addition, the intelligent power module A20 has a common configuration with the intelligent power module A10, and therefore achieves the same effects as the intelligent power module A10.

[0229] 46 shows an intelligent power module A30 according to the third embodiment. The intelligent power module A30 differs from the intelligent power module A10 in the following respect: the intelligent power module A20 further includes two Miller clamp circuits MR1 ​​and MR2.

[0230] The Miller clamp circuit MR1 is connected to the signal terminal Tss1 in the module unit PM1. It is also connected to the electrical connection point of two resistors R11 and R12 in the drive circuit unit DR1. The Miller clamp circuit MR1 includes a switching element (not shown), which is controlled by, for example, the drive element 82A. The Miller clamp circuit MR1 may be controlled by something other than the drive element 82A (e.g., a control IC). When the switching unit SW1 is off, the Miller clamp circuit MR1 turns on the switching element, forcing the potential difference between the two signal terminals T13 and T14 and the signal terminal Tss1 to approximately 0 V, thereby suppressing an increase in the gate potential of each semiconductor element 21A, 22A. This prevents erroneous turn-on of each semiconductor element 21A, 22A.

[0231] Similarly, the Miller clamp circuit MR2 is connected to the signal terminal Tss2 in the module unit PM1. It is also connected to the electrical connection point of the two resistors R21 and R22 in the drive circuit unit DR1. The Miller clamp circuit MR2 includes a switching element (not shown), which is controlled by, for example, the drive element 82B. The Miller clamp circuit MR2 may be controlled by something other than the drive element 82B (e.g., a control IC). When the switching unit SW2 is off, the Miller clamp circuit MR2 turns on the switching element, forcing the potential difference between the two signal terminals T23 and T24 and the signal terminal Tss2 to approximately 0 V, thereby suppressing an increase in the gate potential of each semiconductor element 21B, 22B. This prevents erroneous turn-on of each semiconductor element 21B, 22B.

[0232] In the intelligent power module A30, as in the intelligent power module A10, even when two semiconductor elements 21, 22 are switched by a common drive signal, it is possible to suppress resonance of the drive signal. In addition, the intelligent power module A30 has a common configuration with the intelligent power module A10, and therefore achieves the same effects as the intelligent power module A10.

[0233] In the intelligent power modules A10, A20, A30 according to the first to third embodiments, one of the two switching units SW1, SW2 may not include the two semiconductor elements 21, 22. In other words, one of the two switching units SW1, SW2 may include either of the two semiconductor elements 21, 22 alone, or may include a plurality of either of the two semiconductor elements 21, 22 arranged in parallel with each other.

[0234] 47 shows an intelligent power module A40 according to the fourth embodiment. The intelligent power module A40 differs from the intelligent power module A10 in the following respects. First, the module unit PM1 includes a switching unit SW1 and a plurality of rectifying elements D11 and D12, but does not include a switching unit SW2 and a plurality of rectifying elements D21 and D22. Second, the drive circuit unit DR1 includes a drive element 82A and two resistors R11 and R12, but does not include a drive element 82B and resistors R21 and R22.

[0235] In the intelligent power module A40, as in the intelligent power module A10, even when two semiconductor elements 21, 22 are switched by a common drive signal, it is possible to suppress resonance of the drive signal. In addition, the intelligent power module A40 has a common configuration with the intelligent power module A10, and therefore achieves the same effects as the intelligent power module A10.

[0236] The intelligent power module and semiconductor module according to the present disclosure are not limited to the above-described embodiments. The specific configurations of the components of the intelligent power module and semiconductor module according to the present disclosure can be freely modified in various ways. For example, the intelligent power module and semiconductor module according to the present disclosure include embodiments according to the following supplementary notes. Supplementary Note 1. a first semiconductor element having a first electrode, a second electrode, and a third electrode, the first electrode and the second electrode being electrically connected in response to a drive signal input to the third electrode; a second semiconductor element having a fourth electrode, a fifth electrode, and a sixth electrode, the fourth electrode and the fifth electrode being electrically connected in response to a drive signal input to the sixth electrode; a drive element outputting a common drive signal to each of the third electrode and the sixth electrode; a pair of first rectifier elements connected in series between the third electrode and the sixth electrode via a first connection point; a pair of second rectifier elements connected in series between the third electrode and the sixth electrode via a second connection point; a first resistor connected between the first connection point and the drive element; and a second resistor connected between the second connection point and the drive element; an intelligent power module, wherein each of the pair of first rectifier elements is connected so that a forward current flows individually from the first connection point to the third electrode and the sixth electrode, and each of the pair of second rectifier elements is connected so that a forward current flows individually from the third electrode and the sixth electrode to the second connection point.Supplementary Note 2. The intelligent power module according to Supplementary Note 1, further comprising: a module unit including a first switching unit including the first semiconductor element and the second semiconductor element, and the module unit including an insulating sealing resin that covers the first switching unit.Appendix 3. The intelligent power module of Appendix 2, wherein the module section includes a first signal terminal to which the first resistor is connected and a second signal terminal to which the second resistor is connected, the sealing resin covers the pair of first rectifying elements and the pair of second rectifying elements, and the first signal terminal and the second signal terminal protrude from the sealing resin. Appendix 4. The intelligent power module of Appendix 3, wherein the module section includes a drive circuit section including the drive element, the first resistor, and the second resistor. Appendix 5. The intelligent power module of Appendix 4, further including a wiring board on which the drive circuit section is mounted, the wiring board including a first circuit board on which the first resistor and the second resistor are mounted. Appendix 6. The intelligent power module of Appendix 5, wherein the sealing resin has a top surface and a bottom surface facing opposite to each other in a first direction, and the first signal terminal and the second signal terminal protrude from the top surface. Appendix 7. Appendix 6. The intelligent power module according to Appendix 6, wherein the first circuit board has a through hole penetrating in the first direction and faces the top surface in the first direction, and the first signal terminal and the second signal terminal are inserted into the through hole. Appendix 8. The intelligent power module according to Appendix 7, wherein the wiring board includes a second circuit board spaced apart from the first circuit board and an interconnection wiring that electrically connects the first circuit board and the second circuit board, and the drive element is mounted on the second circuit board. Appendix 9. The intelligent power module according to Appendix 8, wherein the second circuit board is located on the opposite side from the module unit with respect to the first circuit board in the first direction.Supplementary Note 10. The intelligent power module according to any one of Supplementary Note 6 to Supplementary Note 8, wherein the first switching unit includes, in a circuit configuration, a first connection end conducting between the first electrode and the fourth electrode and a second connection end conducting between the second electrode and the fifth electrode, and wherein the drive signal is a first drive signal and a conduction state and a cut-off state are switched between the first connection end and the second connection end in response to the first drive signal, and the module unit includes a second switching unit, and the second switching unit includes, in a circuit configuration, a third connection end and a fourth connection end, and wherein a conduction state and a cut-off state are switched between the third connection end and the fourth connection end in response to the second drive signal. Supplementary Note 11. The intelligent power module according to Supplementary Note 10, further comprising: a first power terminal conducting to the first connection end; a second power terminal conducting to the fourth connection end; and a third power terminal conducting to the second connection end and the third connection end. Supplementary Note 12. The intelligent power module according to claim 11, wherein the sealing resin has a first resin side surface and a second resin side surface facing opposite each other in a second direction orthogonal to the first direction, the first power terminal and the second power terminal protruding from the first resin side surface, and the third power terminal protruding from the second resin side surface. Supplementary note 13. The intelligent power module according to any of Supplementary note 1 to Supplementary note 12, wherein the first semiconductor element is an IGBT, and the second semiconductor element is a MOSFET. Supplementary note 14. The intelligent power module according to any of Supplementary note 13, wherein the first semiconductor element includes a first semiconductor substrate, the first semiconductor substrate including Si, and the second semiconductor element includes a second semiconductor substrate, the second semiconductor substrate including SiC. Supplementary note 15. The intelligent power module according to any of Supplementary note 1 to Supplementary note 14, wherein each of the pair of first rectifying elements is a diode, and each of the pair of second rectifying elements is a diode.Supplementary Note 16. A semiconductor device comprising: a first semiconductor element having a first electrode, a second electrode, and a third electrode, the first electrode and the second electrode being electrically connected to each other by a drive signal input to the third electrode; a second semiconductor element having a fourth electrode, a fifth electrode, and a sixth electrode, the fourth electrode and the fifth electrode being electrically connected to each other by a drive signal input to the sixth electrode; a pair of first rectifier elements connected in series between the third electrode and the sixth electrode via a first connection point; and a pair of second rectifier elements connected in series between the third electrode and the sixth electrode via a second connection point, wherein a common drive signal is input to each of the third electrode and the sixth electrode, the first electrode and the fourth electrode are electrically connected, and the second electrode and the fifth electrode are electrically connected, and each of the pair of first rectifier elements is connected so that a forward current flows individually from the first connection point to the third electrode and the sixth electrode, a semiconductor module in which each of the pair of second rectifying elements is connected so that a forward current flows individually from the third electrode and the sixth electrode to the second connection point.Supplementary Note 17. The intelligent power module according to Supplementary Note 7, wherein the drive element is mounted on the first circuit board.Supplementary Note 18. The intelligent power module according to Supplementary Note 1, comprising: a module unit including a first switching unit including the first semiconductor element and the second semiconductor element; and a drive circuit unit including the drive element, the first resistor, the second resistor, the pair of first rectifying elements, and the pair of second rectifying elements.Supplementary Note 19. The intelligent power module according to Supplementary Note 6, wherein the first circuit board has a first surface facing the top surface in the first direction and a second surface facing opposite to the facing surface in the first direction, and the first resistor and the second resistor are mounted on the second surface.Supplementary Note 20. An intelligent power module according to Supplementary Note 1 to Supplementary Note 15, comprising: a mounting portion on which the first semiconductor element and the second semiconductor element are mounted; and a control board mounted on the mounting portion, wherein the control board includes an insulating layer and a wiring layer arranged on the opposite side of the insulating layer from the mounting portion, wherein the wiring layer includes a plurality of wiring portions spaced apart from each other, and the pair of first rectifying elements and the pair of second rectifying elements are joined to any of the plurality of wiring portions. Supplementary Note 21. A vehicle comprising: a drive source; and the intelligent power module according to Supplementary Note 1 to Supplementary Note 15, wherein the intelligent power module is electrically connected to the drive source. Supplementary Note 22. the first semiconductor element comprises: a first conductivity type semiconductor layer having a first main surface and a second main surface opposite thereto, the semiconductor layer defining an element formation region and an outer region outside the element formation region; a second conductivity type channel region formed in a surface layer portion of the first main surface in the element formation region; a plurality of trench gate structures each including a trench formed in the first main surface so as to penetrate the channel region, a gate insulating film covering an inner wall of the trench, and a gate electrode embedded in the trench with the gate insulating film sandwiched therebetween, the plurality of trench gate structures formed at intervals in the element formation region; a plurality of first conductivity type emitter regions formed in a surface layer portion of the channel region so as to extend along each of the trench gate structures; a second conductivity type termination region formed deeper than the channel region in the surface layer portion of the first main surface in the outer region, the termination region being connected to the outermost trench gate structure of the plurality of trench gate structures; a second conductivity type collector region formed in a surface layer portion of the second main surface in the element formation region; and a first conductivity type inner cathode region formed in a surface layer portion of the second main surface in the element formation region. 16. The intelligent power module according to claim 1, further comprising: an outer cathode region of the first conductivity type formed in a surface layer portion of the second main surface of the outer region.Supplementary Note 23. The intelligent power module according to Supplementary Note 22, wherein a channel structure including the channel region, the emitter region, and the trench gate structure is formed in an inner portion of the channel region, a dummy channel structure including the channel region and the trench gate structure but not the emitter region is formed in a peripheral portion of the channel region, and the termination region is connected to the outermost trench gate structure that constitutes the dummy channel structure.Supplementary Note 24. The intelligent power module according to Supplementary Note 1 to Supplementary Note 15, wherein the second semiconductor element comprises: a semiconductor layer made of SiC of a first conductivity type; a well region of a second conductivity type formed in a surface layer portion of the semiconductor layer; a source region of the first conductivity type formed in a surface layer portion of the well region; a gate insulating film formed on the semiconductor layer; and a gate electrode formed on the gate insulating film and facing a channel region in which a channel is formed in the well region, with the gate insulating film sandwiched between them, and wherein the impurity concentration of a first region of a predetermined width adjacent to the channel region in the source region is lower than the impurity concentration of a second region other than the first region.

[0237] DESCRIPTION OF SYMBOLS 11: Support substrate 13 to 16: Power terminal 17: Signal terminal 19: Signal terminal 21, 21A, 21B, 22, 22A, 22B: Semiconductor element 23: Conductive bonding layer 31, 32: Conductive member 33 to 36: Conductive bonding layer 41 to 45: Wire 50: Sealing resin 51: Top surface 52: Bottom surface 53: Resin side surface 55: Recess 61: Insulating layer 62: Wiring layer 63: Metal layer 64: Sleeve 71: Main body 72: Base 73: Positioning portion 75: Pressing portion 76: Fixing portion 79: Fastener 81, 82: Circuit board 82A, 82B: Drive element 83: Connecting wiring 84: Positioning pin 93: On-board charger 94: Storage battery 95: Drive system 107A: SiO2 film 111: Insulating layer 112, 113: Wiring layer 170A: Base portion 170B: Bulging portion 171A, 171B, 172A, 172B: Signal terminal 173A, 173B: Signal terminal 181A, 181B: Signal terminal 211, 212, 213: Electrode 221, 222, 223: Electrode 311: Main body portion 312, 313: Joint portion 321: Main body portion 322, 323: Joint portion 531 to 533: Side surface 601, 602: Control wiring 621 to 627: Wiring portion 721: First portion 722: Second portion 761: End-arrangement portion 762: Intermediate arrangement portion 811: Base material 811a: Through hole 812: Main portion wiring 813: Back portion wiring 814: Internal wiring 831: Connection part 831A: Connection pin 832: Connection part 832A: Housing part 832B: Connection hole 851: Mounting hole 852: Positioning hole 951: Inverter 952: Drive source 1121, 1122: Mounting part A10, A20, A30, A40: Intelligent power module B10, B11, B12: Power conversion unit C: Channel region C1: Mounting object C11, C12, C21, C22: Connection point D1: Mounting member D11, D12, D21, D22: Rectifier element DR1: Drive circuit part E1: Wiring board F1: Vehicle G10: Surface electrode G102: Planar gate structure G103: Gate insulating film G104: Gate electrode G105: Contact hole G11: Gate electrode G12: Emitter electrodeG13: Field plate electrode G14: Equipotential electrode G15: Insulating region G16: Gate pad G17: Gate finger G18: Open end G19: Open end G2: Semiconductor layer G22: Emitter pad G23: Emitter routing portion G24: Emitter connection portion G25: Avalanche current recovery structure G3: First main surface G31: Type semiconductor substrate G31: Semiconductor substrate G32: Collector electrode G33: P-type channel region G34: Type drift region G35: Type collector region G36: N-type buffer region G37: Trench gate structure G38: Gate trench G39: Gate insulating film G4: Second main surface G40: Buried gate electrode G41: Surface insulating film G42: Gate lead-out portion G43: Type emitter region G44: First contact recess G45: Mold contact region G46: Channel structure G47: Dummy channel structure G51: Mold termination region G52: Mold field limit region G53: Mold channel stop region G54: Second contact recess G55: Third contact recess G56: Mold contact region G57: Mold contact region G58: Fourth contact recess G59: Mold contact region G6: Element formation region G60: Fifth contact recess G61: Mold contact region G64: Insulating layer G65: First contact hole G67: Second contact hole G68: Third contact hole G69: Fourth contact hole G7: Outer region G70: Fifth contact hole G71: Gate contact hole G72: First conductor layer G73: Second conductor layer G8: Breakdown voltage holding region G9: Scribe region M102: Semiconductor substrate M103: Semiconductor layer M104: Well region M105: Source region M105A: First region M105B: Second region M106: Contact region M107: Gate insulating film M107A: SiO2 film M107B: AlON film M108: Gate electrode M109: Interlayer insulating film M110: Contact hole M111: Source metal M112: Gate pad M113: Ohmic metal M114: Drain metal M162: Semiconductor substrate M163: Semiconductor layer M164: Drain regionM165: Well region M166: Gate trench M167: Gate insulating film M167A: SiO2 film M167B: AlON film M168: Gate electrode M169: Source region M169A: First region M169B: Second region M170: Contact region M171: Interlayer insulating film M172: Contact hole M173: Source metal M174: Ohmic metal M175: Drain metal MR1, MR2: Miller clamp circuit MS: Step PM1: Module section PM11: First module section PM12: Second module section PM13: Third module section R11, R12, R21, R22: Resistors SW1, SW2: Switching section T11, T12: Connection end T13, T14: Signal end T21, T22: Connection terminals T23, T24: Signal terminals TH: Thermistor Tp, Tn, Tout: Power terminals Ton1, Ton2, Toff1, Toff2: Signal terminals Tss1, Tss2: Signal terminals

Claims

1. A semiconductor device comprising: a first semiconductor element having a first electrode, a second electrode, and a third electrode, the first electrode and the second electrode being electrically connected in response to a drive signal input to the third electrode; a second semiconductor element having a fourth electrode, a fifth electrode, and a sixth electrode, the fourth electrode and the fifth electrode being electrically connected in response to a drive signal input to the sixth electrode; a drive element outputting a common drive signal to each of the third electrode and the sixth electrode; a pair of first rectifier elements connected in series between the third electrode and the sixth electrode via a first connection point; a pair of second rectifier elements connected in series between the third electrode and the sixth electrode via a second connection point; a first resistor connected between the first connection point and the drive element; and a second resistor connected between the second connection point and the drive element; An intelligent power module, wherein each of the pair of first rectifying elements is connected so that a forward current flows individually from the first connection point to the third electrode and the sixth electrode, and each of the pair of second rectifying elements is connected so that a forward current flows individually from the third electrode and the sixth electrode to the second connection point.

2. An intelligent power module as described in claim 1, comprising a module section having a first switching section including the first semiconductor element and the second semiconductor element, the module section comprising an insulating sealing resin covering the first switching section.

3. The intelligent power module described in claim 2, wherein the module portion includes a first signal terminal to which the first resistor is connected and a second signal terminal to which the second resistor is connected, the sealing resin covers the pair of first rectifying elements and the pair of second rectifying elements, and the first signal terminal and the second signal terminal protrude from the sealing resin.

4. The intelligent power module according to claim 3, further comprising a drive circuit section including said drive element, said first resistor, and said second resistor.

5. The intelligent power module according to claim 4, further comprising a wiring board on which the drive circuit section is mounted, the wiring board comprising a first circuit board on which the first resistor and the second resistor are mounted.

6. The intelligent power module according to claim 5, wherein the sealing resin has a top surface and a bottom surface facing opposite each other in a first direction, and the first signal terminal and the second signal terminal protrude from the top surface.

7. The intelligent power module described in claim 6, wherein the first circuit board has a through hole penetrating in the first direction and faces the top surface in the first direction, and the first signal terminal and the second signal terminal are inserted into the through hole.

8. An intelligent power module as described in claim 7, wherein the wiring board comprises a second circuit board spaced apart from the first circuit board and interconnection wiring electrically connecting the first circuit board and the second circuit board, and the drive element is mounted on the second circuit board.

9. The intelligent power module according to claim 8, wherein the second circuit board is located on the opposite side of the module unit from the first circuit board in the first direction.

10. An intelligent power module as described in any one of claims 6 to 8, wherein the first switching unit, in a circuit configuration, includes a first connection end conductive to the first electrode and the fourth electrode and a second connection end conductive to the second electrode and the fifth electrode, and the drive signal is a first drive signal, and a conductive state and a cut-off state are switched between the first connection end and the second connection end in response to the first drive signal, and the module unit includes a second switching unit, and the second switching unit, in a circuit configuration, includes a third connection end and a fourth connection end, and a conductive state and a cut-off state are switched between the third connection end and the fourth connection end in response to the second drive signal.

11. The intelligent power module of claim 10, further comprising: a first power terminal conductive to the first connection end; a second power terminal conductive to the fourth connection end; and a third power terminal conductive to the second connection end and the third connection end.

12. An intelligent power module as described in claim 11, wherein the sealing resin has a first resin side surface and a second resin side surface facing opposite each other in a second direction perpendicular to the first direction, the first power terminal and the second power terminal protruding from the first resin side surface, and the third power terminal protruding from the second resin side surface.

13. An intelligent power module according to any one of claims 1 to 12, wherein the first semiconductor element is an IGBT, and the second semiconductor element is a MOSFET.

14. The intelligent power module of claim 13, wherein the first semiconductor element includes a first semiconductor substrate, the first semiconductor substrate including Si; and the second semiconductor element includes a second semiconductor substrate, the second semiconductor substrate including SiC.

15. The intelligent power module according to any one of claims 1 to 14, wherein each of the pair of first rectifying elements is a diode, and each of the pair of second rectifying elements is a diode.

16. A semiconductor device comprising: a first semiconductor element having a first electrode, a second electrode, and a third electrode, the first electrode and the second electrode being electrically connected by a drive signal input to the third electrode; a second semiconductor element having a fourth electrode, a fifth electrode, and a sixth electrode, the fourth electrode and the fifth electrode being electrically connected by a drive signal input to the sixth electrode; a pair of first rectifying elements connected in series between the third electrode and the sixth electrode via a first connection point; and a pair of second rectifying elements connected in series between the third electrode and the sixth electrode via a second connection point, wherein a common drive signal is input to each of the third electrode and the sixth electrode, the first electrode and the fourth electrode are electrically connected, and the second electrode and the fifth electrode are electrically connected, and each of the pair of first rectifying elements is connected so that a forward current flows individually from the first connection point to the third electrode and the sixth electrode, a pair of second rectifying elements each connected such that a forward current flows individually from the third electrode and the sixth electrode to the second connection point, the pair of second rectifying elements being connected to the second connection point;

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