Electronic device

Abstract

Electronic devices (1-3) each have high-side chips (11-13) with built-in upper arm elements (111-113). Low-side chips (14-16) have built-in lower arm elements (114-116) and are connected to the paired high-side chips (11-13) inside a module. A control chip (18) has a built-in pre-driver IC (180) that outputs a drive signal. A sealing part (35) seals the high-side chips (11-13), the low-side chips (14-16), and the control chip (18). The high-side chips and the low-side chips are arranged on the side of one side of the control chip (18) with gate electrodes thereof facing the control chip (18) side. In the control chip (18), the connected portions of signal lines (19) connected to the high-side chips or the low-side chips are provided along the one side thereof on the side where the high-side chips and the low-side chips are disposed.

Description

electronic equipment CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Patent Application No. 2023-212724, filed December 18, 2023, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to electronic devices.

[0003] Conventionally, semiconductor devices in which semiconductor elements are encapsulated have been known. For example, in a semiconductor device disclosed in Patent Document 1, a semiconductor chip incorporating a power transistor for a high-side switch, a semiconductor chip incorporating a power transistor for a low-side switch, and a semiconductor chip incorporating a control circuit are encapsulated in a sealing portion.

[0004] JP 2019-57576 A

[0005] In Patent Document 1, semiconductor chips for high-side and low-side switches are arranged on both sides of a semiconductor chip incorporating a control circuit, so wiring connecting the high-side and low-side elements must be provided external to the semiconductor device. For example, when connecting the high-side and low-side elements on a substrate, power wiring, which carries a relatively large current, and control signal wiring are mixed, which increases noise and surges and can lead to malfunctions. Furthermore, providing wiring connecting the high-side and low-side elements on a substrate makes it difficult to miniaturize the device and to route the signal wiring. An object of the present disclosure is to provide an electronic device that can reduce noise and surges.

[0006] An electronic device according to a first aspect of the present disclosure includes a plurality of high-side chips, a plurality of low-side chips, a control chip, and a sealing portion.An electronic device according to a second aspect of the present disclosure includes a plurality of high-side chips, a plurality of low-side chips, a sealing portion, and a terminal.

[0007] The high-side chip contains upper arm elements connected to the high-potential side, while the low-side chip contains lower arm elements connected to the low-potential side of each upper arm element, and is connected to its counterpart high-side chip inside the module.

[0008] In a first aspect, the control chip has a built-in pre-driver IC that outputs drive signals for the upper arm elements and the lower arm elements. The sealing portion seals the high-side chip, the low-side chip, and the control chip. The high-side chip and the low-side chip are arranged on one side of the control chip with their gate electrodes facing the control chip. In the control chip, the connection points of the signal lines connected to the high-side chip or the low-side chip are provided along the side on which the high-side chip and the low-side chip are arranged.

[0009] In a second aspect, the sealing portion seals the high-side chip and the low-side chip. The terminals include a power supply terminal, a ground terminal, an output terminal, and an output terminal connected to the high-side chip and the low-side chip, and are provided along the outer edge of the sealing portion. The output terminal is provided on one side of the sealing portion, and the signal terminal is provided on the side opposite to the side on which the output terminal is provided. The power supply terminal and the ground terminal are provided on the side of the side on which the output terminal is provided. This allows for consolidating areas through which a relatively large current flows, thereby suppressing the generation of noise and surges.

[0010] The above and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which Fig. 1 is a plan view showing an electronic device according to a first embodiment, Fig. 2 is a cross-sectional view taken along line II-II of Fig. 1, Fig. 3 is a circuit diagram of the electronic device according to the first embodiment, Fig. 4 is an explanatory diagram illustrating a parasitic inductor, Fig. 5 is a plan view showing an electronic device according to a second embodiment, Fig. 6 is a plan view showing an electronic device according to a third embodiment, and Fig. 7 is a cross-sectional view showing an electronic device according to another embodiment.

[0011] Hereinafter, an electronic device according to the present disclosure will be described with reference to the drawings. In the following, substantially identical components in multiple embodiments will be designated by the same reference numerals, and descriptions thereof will be omitted.

[0012] (First Embodiment) The first embodiment is shown in Figures 1 to 3. As shown in Figures 1 and 2, the electronic device 1 includes high-side chips 11 to 13, low-side chips 14 to 16, a control chip 18, a lead frame 20, clips 31 to 34, and a sealing portion 35. The chips 11 to 16, 21, lead frame 20, and clips 31 to 34 are sealed together with the sealing portion 35, and are formed into a generally rectangular shape in a plan view as a whole, with the top surface provided to a heat dissipation portion 95 so as to be able to dissipate heat. For ease of explanation, the sealing portion 35 is omitted from Figure 1 and the like, and hatching is omitted from Figure 2.

[0013] Terminals 36 are provided on the outer edge of the sealing portion 35. The terminals 36 may be of a non-lead type or may have protruding leads. The terminals 36 include a power terminal 361, a ground terminal 362, an output terminal 363, and a signal terminal 364. In the drawing, the output terminal 363 is labeled with the corresponding phase, such as "363_U." The terminals on the sides within the control region Rc can be used as signal terminals 364, but among the terminals connected to the control land 21, those located on the boundary side with the power region Rp are assigned as power terminals or ground terminals related to the supply of power to the pre-driver IC 180.

[0014] The high-side chips 11 to 13 incorporate upper arm elements 111 to 113, and the low-side chips 14 to 16 incorporate lower arm elements 114 to 116 (see FIG. 3 ). In this embodiment, the upper arm elements 111 to 113 and the lower arm elements 114 to 116 are MOSFETs, but may also be IGBTs, bipolar transistors, or the like. The high-side chips 11 to 13 and the low-side chips 14 to 16 each have a source electrode on the top surface and a drain electrode on the back surface. The chips 11 to 16 are connected to a control chip 18 via signal lines 19. The signal lines 19 include signal lines for gate drive, current detection, temperature detection, and the like.

[0015] As shown in Figure 3, six switching elements, namely upper arm elements 111 to 113 and lower arm elements 114 to 116, are bridge-connected to form a driver circuit 10 that drives a load, namely a motor 800. The drains of the upper arm elements 111 to 113 are connected to a power supply, and the sources are connected to the drains of the corresponding lower arm elements 114 to 116. The sources of the lower arm elements 114 to 116 are connected to ground. The gates of the upper arm elements 111 to 113 and the lower arm elements 114 to 116 are connected to a pre-driver IC 180 built into the control chip 18.

[0016] The connection point between the paired U-phase upper arm element 111 and lower arm element 114 is connected to one end of the U-phase motor winding 801. The connection point between the paired V-phase upper arm element 112 and lower arm element 115 is connected to one end of the V-phase motor winding 802. The connection point between the paired W-phase upper arm element 113 and lower arm element 116 is connected to one end of the W-phase motor winding 803. The other ends of the motor windings 801 to 803 are connected. Note that the motor windings 801 to 803 are not limited to being Y-connected, but may also be Delta-connected.

[0017] 1 and 2, the lead frame 20 includes lands 21 to 26. The back side of the lead frame 20 is exposed from the sealing portion 35 and is electrically connected to the wiring pattern of the substrate 90 by soldering or the like. Note that not all lands need to be connected to the back side of the substrate 90. Each of the lands 21 to 26 is formed integrally with or connected to a terminal 36 on the outer peripheral edge of the sealing portion 35. The control chip 18 is mounted on the control land 21, and the high-side chips 11 to 13 are mounted on the power land 22.

[0018] The control chip 18 is formed in a generally rectangular shape in a plan view. Hereinafter, the direction parallel to the long sides of the control chip 18 will be referred to as the "first direction," and the direction perpendicular to the first direction will be referred to as the "second direction." Furthermore, within the mold, the lead frame 20 side will be referred to as the "lower side," and the top side will be referred to as the "upper side."

[0019] The lands 21 to 25 are arranged in the following order from one side in the second direction: control land 21, power land 22, and three output lands 23 to 25. The ground land 26 is provided adjacent to the power land 22 and the output land 25. The control land 21 is at ground potential, and terminals located on both sides of its short side and at the end opposite the power land 22 are used as signal terminals 364.

[0020] The power land 22 is provided adjacent to the long side of the control land 21. The back side of the power land 22 abuts against the power supply pattern of the substrate 90 and is at the power supply potential. The power land 22 uses a terminal located at the end opposite the ground land 26 in the first direction as a power supply terminal 361. The high-side chips 11 to 13 are arranged side by side on the power land 22 with the source on the upper side, the drain on the lower side, and the gate facing the long side of the control chip 18. The drain electrodes of the high-side chips 11 to 13 are connected to the power land 22.

[0021] The output lands 23 to 25 are arranged side by side adjacent to the power land 22 on the opposite side of the control land 21. An output terminal 363 is formed at the end of the output lands 23 to 25 opposite the power land 22. The output terminal 363 is connected to each phase of the motor winding via circuit board wiring or the like (not shown). A ground terminal 362 is formed on the ground land 26 at the end opposite the land 25.

[0022] Intermediate clips 31 to 33 are placed on the high-side chips 11 to 13, respectively. Intermediate clips 31 to 33 are conductive metal plates made of, for example, copper, formed into a plate shape wider than chips 11 to 16, with one end connected to high-side chips 11 to 13 and low-side chips 14 to 16 and the other end connected to output lands 23 to 25. One end of intermediate clips 31 to 33 is shifted relative to the end of high-side chips 11 to 13 on the control chip 18 side so as to be farther away from control chip 18 than the end of high-side chips 11 to 13 on the control chip 18 side, so that the gate electrodes of high-side chips 11 to 13 can be connected to control chip 18.

[0023] The low-side chips 14 to 16 are arranged above the intermediate clips 31 to 33. The low-side chips 14 to 16 are arranged so that the drain is on the lower side and the source is on the upper side, with the gate facing the long side of the control chip 18. This connects the sources of the high-side chips 11 to 13 and the drains of the low-side chips 14 to 16 via the intermediate clips 31 to 33. The other ends of the intermediate clips 31 to 33 are bent downward and connected to the output lands 23 to 25, respectively.

[0024] The ground clip 34 is a conductive plate made of, for example, copper, formed in a plate shape. The ground clip 34 covers the upper sides of the low-side chips 14 to 16, is bent downward on one side in the first direction, and is connected to the ground land 26. In FIG. 1, the ground land 26 is disposed to the right of the power land 22 in the drawing, but the ground land 26 may be disposed to the left of the power land 22 in the drawing, or may be disposed on both sides. When the ground lands 26 are disposed on both sides, the ground clip 34 is bent downward on both sides to connect to the ground lands 26. The same applies to the ground lands 46 in the embodiment described below.

[0025] In the electronic device 1, the drain electrodes of the high-side chips 11 to 13 are connected by a power land 22, which is a common metal plate, and the source electrodes of the low-side chips 14 to 16 are connected by a ground clip 34, which is a common metal plate.

[0026] The end of the ground clip 34 on the control chip 18 side is shifted so as to be farther away from the control chip 18 than the end of the low-side chips 14 to 16 on the control chip 18 side, so that the gates of the low-side chips 14 to 16 can be connected to the control chip 18.

[0027] The ground clip 34 is formed wide enough to cover the upper sides of the bent portions of the intermediate clips 31 to 33. By making the area of ​​the ground clip 34 as large as possible, heat dissipation efficiency can be improved. It is preferable in terms of heat dissipation to make the sealing portion 35 on the top surface side of the ground clip 34 thin.

[0028] In the electronic device 1, the control chip 18 is provided on one side in the second direction, and the chips 11 to 16 that make up the driver circuit 10 are provided on the other side, with a power region Rp through which a relatively large current flows and a control region Rc through which a relatively small current flows being arranged in a concentrated manner. In the power region Rp, from the bottom, the power land 22, the high-side chips 11 to 13, the intermediate clips 31 to 33, the low-side chips 14 to 16, and the ground clip 34 are layered in this order, forming a stack structure.

[0029] Furthermore, the gate electrodes of chips 11 to 16 face the control chip 18, and are stacked in a staggered, stepped pattern to ensure that the gate electrodes can be connected to the control chip 18, thereby ensuring a non-overlapping area that does not overlap with components provided above the chips 11 to 16. This allows the chips 11 to 16 and the control chip 18 to be connected by wire bonding using signal lines 19. Furthermore, the connection points of the control chip 18 with the gate electrodes of chips 11 to 16 are concentrated on one side facing the chips 11 to 16.

[0030] In the electronic device 1, in the power region Rp, a power terminal 361 is provided on one side in the first direction, a ground terminal 362 is provided on the other side in the first direction, and an output terminal 363 is provided at the end on the second direction side. When viewed as a whole, power and ground are input in the first direction, and power related to motor drive is output in the second direction. This allows the wiring connecting the power and ground in the power region to be separated from the signal line 19 of the control chip 18, reducing the effects of noise and surges. Furthermore, the power land 22 and the ground land 26, which are at the power supply potential, are arranged adjacent to each other. This reduces the loop in the power section, which is a noise source, thereby reducing noise.

[0031] 4 is a diagram illustrating the parasitic inductance (hereinafter referred to as "ESL") in the driver circuit 10, and here, a U-phase arm is shown as an example. When a large current flows through the electronic device 1, a magnetic field is generated around it, and the area circled by a dashed line becomes ESL, and the energy accumulated there is applied to the element, resulting in switching loss. For example, as a reference example, if an upper arm element is arranged on one side of the control chip and a lower arm element is arranged on the other side, and the source of the upper arm element and the drain of the lower arm element are connected by board wiring outside the module, the wiring length becomes long, and the ESL becomes large.

[0032] In this embodiment, the sources of the high-side chips 11 to 13 and the drains of the low-side chips 14 to 16 are connected on both sides of the intermediate clips 31 to 33. That is, the wiring length between the drain and source indicated by A1 in FIG. 4 is the thickness of the intermediate clips 31 to 33, which is shorter than when the connection is made via board wiring or the like outside the module. Therefore, the ESL can be reduced.

[0033] 4, the drains of the upper arm elements 111 to 113 are connected to the power land 22 common to all three phases, and the sources of the lower arm elements 114 to 116 are connected to the ground clip 34 common to all three phases, which eliminates the ESL difference between the phases, speeding up the return current switching and reducing switching loss.

[0034] By providing the control chip 18 that constitutes the pre-driver IC 180 within the module and wiring the gate signal lines within the module, there is no need to provide vias or the like, as compared to providing gate wiring on a printed circuit board, for example, and therefore ESL can be reduced.

[0035] As described above, the electronic device 1 includes a plurality of high-side chips 11 to 13, a plurality of low-side chips 14 to 16, a control chip 18, and a sealing portion 35. The high-side chips 11 to 13 incorporate upper arm elements 111 to 113 connected to their high-potential sides. The low-side chips 14 to 16 incorporate lower arm elements 114 to 116 connected to the low-potential sides of the respective upper arm elements 111 to 113, and are connected to their paired high-side chips 11 to 13 within the module. Specifically, the paired U-phase high-side chip 11 and low-side chip 14 are connected, the paired V-phase high-side chip 12 and low-side chip 15 are connected, and the paired W-phase high-side chip 13 and low-side chip 16 are connected.

[0036] The control chip 18 includes a built-in pre-driver IC 180 that outputs drive signals for the upper arm elements 111 to 113 and the lower arm elements 114 to 116. The pre-driver IC 180 has at least the function of a pre-driver. The sealing unit 35 seals the high-side chips 11 to 13, the low-side chips 14 to 16, and the control chip 18.

[0037] The high-side chips 11 to 13 and the low-side chips 14 to 16 are arranged on one long side of the control chip 18, with the gate electrodes to which drive signals are input facing the control chip 18. In the control chip 18, the connection points of the signal lines 19 connected to the high-side chips 11 to 13 or the low-side chips 14 to 16 are provided along one side on the side on which the high-side chips 11 to 13 and the low-side chips 14 to 16 are provided. Here, it is not necessary for all signal terminals to be arranged on a straight line parallel to the long side; for example, due to space constraints, some offset is allowed and is considered to be included in the concept of "arranged along one side." By arranging the signal line connection points between the chips 11 to 16 and the control chip 18 facing each other, it is possible to separate the control region Rc from the power region Rp, through which a relatively large current flows.

[0038] The electronic device 1 includes high-side chips 11 to 13, low-side chips 14 to 16, a sealing portion 35, and terminals 36. The terminals 36 include a power supply terminal 361, a ground terminal 362, a signal terminal 364, and an output terminal 363 connected to the high-side chips 11 to 13 and the low-side chips 14 to 16, and are provided along the outer edge of the sealing portion 35.

[0039] The sealing portion 35 is formed in a rectangular shape, and the output terminal 363 is provided on one side of the sealing portion 35. The signal terminal 364 is provided on the side of the sealing portion 35 opposite to the side on which the output terminal 363 is provided. The power supply terminal 361 and the ground terminal 362 are provided on sides to the side on which the output terminal 363 is provided. Note that it is not necessary for all terminals on each side to be assigned to their respective terminals; there may be unused terminals, or the signal terminal 364 may be provided, for example, on the control region Rc side of the side on which the power supply terminal 361 and the ground terminal 362 are provided. By providing the output terminal 363 on the side opposite to the signal terminal 364, the control region Rc and the power region Rp can be separated.

[0040] This makes it possible to suppress the generation of noise and surges in the electronic device 1. Also, since the power lines, through which a relatively large current flows, can be separated from the signal lines, it is possible to suppress malfunctions. Also, it makes it easier to perform wiring on the board.

[0041] The high-side chips 11 to 13 and the low-side chips 14 to 16 are provided on one side of the control chip 18. The output terminal 363 is provided on the side on which the high-side chips 11 to 13 and the low-side chips 14 to 16 are provided. The signal terminal is provided on the side on which the control chip 18 is provided. This allows the control region Rc and the power region Rp to be appropriately separated.

[0042] The paired high-side chips 11 to 13 and low-side chips 14 to 16 are stacked in a shifted state so that the low-side chips 14 to 16 are on the top surface side and a portion of the top surface side of the high-side chips 11 to 13 does not overlap with the low-side chips 14 to 16. This allows the size of the electronic device 1 to be reduced. Furthermore, by stacking the low-side chips 14 to 16 in a shifted state and ensuring a non-overlapping area on the top surface side of the high-side chips 11 to 13, signal lines 19 can be connected appropriately.

[0043] Second Embodiment A second embodiment is shown in Figure 5. An electronic device 2 of the second embodiment includes high-side chips 11 to 13, low-side chips 14 to 16, a control chip 18, a lead frame 40, clips 51 to 54, relay substrates 56 and 57, a sealing portion 35 (not shown in Figure 5), etc. In this embodiment, the high-side chips 11 to 13 and the low-side chips 14 to 16 are not stacked, but are placed flat on the lead frame 40.

[0044] The lead frame 40 includes lands 41 to 46, each of which is formed integrally with or connected to a terminal 36 on the outer peripheral edge of the sealing portion 35. The control land 41 is generally similar to the control land 21 of the first embodiment, and has the control chip 18 disposed thereon.

[0045] The power land 42, like the power land 22 in the first embodiment, is at the power supply potential and is provided adjacent to the control land 41 so as to face one of the long sides of the control chip 18. In addition, the high-side chips 11 to 13 are arranged on the power land 42 and are connected to the drain electrodes on the back surface.

[0046] The output lands 43 to 45 are arranged side by side along the long side of the power land 42, on the side opposite the control land 41 of the power land 42. The low-side chips 14 to 16 are arranged on the output lands 43 to 45 and connected to the drain electrodes on the back surface. The source electrodes provided on the upper side of the high-side chip 13 are connected to the output lands 43 to 45 by intermediate clips 51 to 53. The intermediate clips 51 to 53 are generally similar to the intermediate clips 31 to 33 of the first embodiment, except that the low-side chips 14 to 16 are not mounted on the upper surface.

[0047] The ground clip 54 covers the upper sides of the low-side chips 14 to 16, is bent downward on one side in the first direction, and is connected to the ground land 46. The ground land 46 is arranged side by side with the output land 45. The clips 51 to 54 are arranged such that their ends on the control chip 18 side are shifted away from the control chip 18 so that the gate terminals of the chips 11 to 16 can be connected to the control chip 18.

[0048] In this embodiment, the chips 11 to 16 are placed flat, and the high-side chips 11 to 13 are arranged between the low-side chips 14 to 16 and the control chip 18, making it difficult to directly connect the gate electrodes of the low-side chips 14 to 16 to the control chip 18.

[0049] Therefore, in this embodiment, relay substrates 56 and 57 are provided in the power land 42, and the gate electrodes of the low-side chips 14 to 16 are connected to the control chip 18 via the relay substrates 56 and 57. The relay substrates 56 and 57 are, for example, printed circuit boards or ceramic substrates, and have wiring patterns formed thereon to which wires that connect the gate electrodes to the control chip can be connected. In this embodiment, the high-side chip 11, relay substrate 56, high-side chips 12 and 13, and relay substrate 57 are arranged in this order from one side in the first direction.

[0050] Intermediate board 56 is provided between high-side chips 11 and 12, and relays the connection between the gate electrodes of low-side chips 14 and 15 and control chip 18. That is, intermediate board 56 is used in common to relay the connection of the gate electrodes of high-side chips 11 and 12. Intermediate board 57 is provided on the side of high-side chip 13 opposite high-side chip 12, and relays the connection between the gate electrodes of low-side chip 16 and control chip 18. Note that the number, shape, arrangement, etc. of intermediate boards may vary as long as they are able to relay the connection between the gate electrodes of low-side chips 14 to 16 and control chip 18.

[0051] In the electronic device 2 of this embodiment, the high-side chips 11 to 13 are arranged horizontally along one side of the control chip 18, and the low-side chips 14 to 16 are arranged horizontally on the opposite side of the high-side chips 11 to 13 from the control chip 18.

[0052] The electronic device 2 includes relay substrates 56 and 57 arranged between or to the sides of the high-side chips 11 to 13, which are arranged side by side. The gate electrodes of the low-side chips 14 to 16 are connected to the control chip 18 via the relay substrates. This allows the control region Rc and the power region Rp to be appropriately separated even when the chips 11 to 16 are arranged flat. Furthermore, the gate electrodes of the low-side chips 14 to 16, which are arranged apart from the control chip 18, can be appropriately connected to the control chip 18.

[0053] (Third Embodiment) A third embodiment is shown in Figure 6. An electronic device 3 of the third embodiment includes high-side chips 11 to 13, low-side chips 14 to 16, a control chip 18, a lead frame 60, clips 51 to 54, a sealing portion 35 (not shown in Figure 6), etc. The lead frame 60 includes lands 43 to 46 and 61. The land 61 is at a power supply potential, and the high-side chips 11 to 13 and the control chip 18 are disposed on the land 61.

[0054] In the control chip 18 of this embodiment, the back side of the element is insulated. Therefore, the potential of the lands on which the control chip 18 is mounted is not limited to ground potential, but may also be power supply potential. By using a control chip 18 with an insulated back side and sharing lands 61 between the high-side chips 11 to 13 and the control chip 18, it is possible to reduce the size of the electronic device 3. Note that in the first and second embodiments, the high-side chips 11 to 13 and the control chip 18 may share lands, or in this embodiment, the high-side chips 11 to 13 and the control chip 18 may share lands.

[0055] In this embodiment, because the chips 11 to 16 are arranged flat, similarly to the second embodiment, it is difficult to directly connect the gate electrodes of the low-side chips 14 to 16 to the control chip 18. In this embodiment, the gate electrodes of the low-side chips 14 to 16 are connected to the control chip 18 via unused terminals 365 to which no power supply potential, ground potential, or various signals are assigned.

[0056] Specifically, the gate electrode of low-side chip 14 is connected to control chip 18 via unused terminal 365 on the left side of the page. The gate electrode of low-side chip 16 is connected to control chip 18 via unused terminal 365 on the right side of the page. The gate electrode of low-side chip 15, which is disposed between low-side chips 14 and 16, is connected to control chip 18 via a relay pad formed on low-side chip 16 and unused terminal 365 on the right side of the page. Note that a relay pad may be provided on low-side chip 14, and the gate electrode of low-side chip 15 may be connected to control chip 18 via the unused terminal on the left side of the page.

[0057] In the electronic device 3 of this embodiment, the chips 11 to 16 are arranged flat, as in the second embodiment. The gate electrodes of the low-side chips 14 to 16 are connected to the control chip 18 via unused terminals 365 provided on the sides of the sealing portion 35. Even with this configuration, the gate electrodes of the low-side chips 14 to 16 arranged apart from the control chip 18 can be appropriately connected to the control chip 18.

[0058] (Other Embodiments) In the above embodiment, the low-side chip is connected by a ground clip, which is a plate-shaped metal plate. In other embodiments, the member connecting the source of the low-potential side element is not limited to a metal plate, and ribbon bonding or aluminum bonding may be used. The same applies to the member connecting the high-side chip.

[0059] In the above embodiment, the ground clip 34 is sealed in the sealing portion 35. In another embodiment, as shown in Fig. 7 , the ground clip 34 may be exposed from the top surface of the sealing portion 35, allowing heat to be dissipated directly to the heat dissipation portion. This improves heat dissipation efficiency. Note that Fig. 7 illustrates the electronic device 1 of the first embodiment, but in the second or third embodiment, the top surface of the ground clip may be exposed from the sealing portion.

[0060] In the above embodiment, the driver circuit is a three-phase inverter having three sets of upper and lower arm elements. In other embodiments, the number of arms may be two or four or more. As described above, the present disclosure is not limited to the above embodiment and can be implemented in various forms without departing from the spirit of the present disclosure.

[0061] The present disclosure has been described based on the embodiments. However, the present disclosure is not limited to the embodiments and structures. The present disclosure also encompasses various modifications and variations within the scope of equivalents. Furthermore, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

Claims

1. An electronic device comprising: a plurality of high-side chips (11-13) incorporating upper arm elements (111-113) connected to a high potential side; a plurality of low-side chips (14-16) incorporating lower arm elements (114-116) connected to a low potential side of each of the upper arm elements, and connected inside a module to a pair of the high-side chips; a control chip (18) incorporating a pre-driver IC (180) that outputs drive signals for the upper arm elements and the lower arm elements; and a sealing portion (35) that seals the high-side chip, the low-side chip, and the control chip; wherein the high-side chip and the low-side chip are arranged on one side of the control chip with gate electrodes to which the drive signals are input facing the control chip side, and a connection point of a signal line (19) connected to the high-side chip or the low-side chip in the control chip is provided along the side on which the high-side chip and the low-side chip are arranged.

2. An electronic device comprising: a plurality of high-side chips (11-13) incorporating upper arm elements (111-113) connected to a high potential side; a plurality of low-side chips (14-16) incorporating lower arm elements (114-116) provided on the low potential side of each of the upper arm elements and connected inside a module to a paired high-side chip; a sealing portion (35) that seals the high-side chip and the low-side chip; and a plurality of terminals (36) provided along an outer edge of the sealing portion, including a power supply terminal (361), a ground terminal (362), a signal terminal (363), and an output terminal (364) connected to the high-side chip and the low-side chip, wherein the output terminal is provided on one side of the sealing portion, the signal terminal is provided on a side of the sealing portion opposite to the side on which the output terminal is provided, and the power supply terminal and the ground terminal are provided on sides lateral to the side on which the output terminal is provided.

3. The electronic device of claim 2, further comprising a control chip (18) that incorporates a pre-driver IC (180) that outputs drive signals for the upper arm elements and the lower arm elements and is sealed integrally with the sealing portion, the high-side chip and the low-side chip are provided on one side of the control chip, the output terminal is provided on the edge on the side on which the high-side chip and the low-side chip are provided, and the signal terminal is provided on the edge on which the control chip is provided.

4. The electronic device according to any one of claims 1 to 3, wherein the paired high-side chip and low-side chip are stacked such that the low-side chip is on the top surface and a portion of the top surface of the high-side chip is shifted so as not to overlap with the low-side chip.

5. The electronic device according to claim 1 or 3, wherein the high-side chip and the low-side chip are arranged side by side, and arranged from one side in the order of the control chip, the high-side chip, and the low-side chip.

6. The electronic device according to claim 5, further comprising relay substrates (56, 57) arranged between or to the sides of the high-side chips arranged side by side, wherein a gate electrode to which the drive signal of the low-side chip is input is connected to the control chip via the relay substrate.

7. The electronic device according to claim 5, wherein a gate electrode of the low-side chip to which the drive signal is input is connected to the control chip via a vacant terminal (366) provided on the side of the sealing portion.

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