Electronic device

Abstract

High-side chips (11-13) of electronic devices (1-9) have built-in upper arm elements (111-113) connected to the high-potential side. Low-side chips (14-16) each have a built-in lower arm element (114-116) connected to the low-potential side of each of the upper arm elements (111-113), and are connected to the pair of high-side chips inside the module. Power supply wiring members (22, 41, 51, 61) connect the high-side chips (11-13) to the power supply potential. Ground wiring members (34, 81-85) connect the low-side chips (14-16) to the ground potential. A sealing part (35) integrally seals the high-side chips (11-13), the low-side chips (14-16), the power supply wiring members (22, 41, 51, 61), and the ground wiring members (34, 81-85). The ground wiring members (34, 81-85) are shared by the plurality of low-side chips (14-16).

Description

electronic equipment CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Patent Application No. 2023-212729, filed December 18, 2023, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to electronic devices.

[0003] 2. Description of the Related Art Conventionally, semiconductor devices in which semiconductor elements are sealed have been known. For example, in Patent Document 1, two semiconductor switch elements are sealed in a sealing resin member to form a half bridge.

[0004] Japanese Patent Application Laid-Open No. 2014-229763

[0005] When an arm is defined as a combination of an upper arm element, which is an element on the high potential side in a bridge circuit, and a lower arm element, which is an element on the low potential side, and multiple arms are integrated into a module, unless the wiring is shared, the difference in parasitic inductance between phases becomes large, resulting in increased switching loss and surge voltage. An object of the present disclosure is to provide an electronic device that can reduce the difference in parasitic inductance between phases.

[0006] The electronic device of the present disclosure includes multiple high-side chips, multiple low-side chips, a power wiring member, a ground wiring member, and a sealing portion. The high-side chips incorporate upper arm elements connected to the high-potential side. The low-side chips incorporate lower arm elements connected to the low-potential side of the upper arm elements, and are connected to their corresponding high-side chips inside the module.

[0007] The power supply wiring member connects the high-side chip to a power supply potential. The ground wiring member connects the low-side chip to a ground potential. The sealing portion seals the high-side chip, the low-side chip, the power supply wiring member, and the ground wiring member together. The ground wiring member is shared by multiple low-side chips. This makes it possible to reduce the phase difference of the parasitic inductance.

[0008] The above and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which Fig. 1 is a plan view showing an electronic device according to a first embodiment, Fig. 2 is a cross-sectional view taken along line II-II of Fig. 1, Fig. 3 is a circuit diagram of the electronic device according to the first embodiment, Fig. 4 is an explanatory diagram illustrating a parasitic inductor, Fig. 5 is a plan view showing an electronic device according to a second embodiment, Fig. 6 is a plan view showing an electronic device according to a third embodiment, Fig. 7 is a plan view showing an electronic device according to a fourth embodiment, Fig. 8 is a cross-sectional view taken along line VIII-VIII of Fig. 7, and Fig. 9 is a cross-sectional view of the electronic device according to the fourth embodiment. 10 is a plan view showing an electronic device according to a fifth embodiment, FIG. 11 is a plan view showing an electronic device according to a sixth embodiment, FIG. 12 is a cross-sectional view taken along line XII-XII of FIG. 11, FIG. 13 is a plan view showing an electronic device according to a seventh embodiment, FIG. 14 is a plan view showing an electronic device according to an eighth embodiment, FIG. 15 is a plan view showing an electronic device according to a ninth embodiment, and FIG. 16 is a cross-sectional view showing an electronic device according to another embodiment.

[0009] Hereinafter, an electronic device according to the present disclosure will be described with reference to the drawings. In the following, substantially identical components in multiple embodiments will be designated by the same reference numerals, and descriptions thereof will be omitted.

[0010] (First Embodiment) The first embodiment is shown in Figures 1 to 3. As shown in Figures 1 and 2, the electronic device 1 includes high-side chips 11 to 13, low-side chips 14 to 16, a control chip 18, a lead frame 20, clips 31 to 34, and a sealing portion 35. The chips 11 to 16, 21, lead frame 20, and clips 31 to 34 are sealed together with the sealing portion 35, and are formed into a generally rectangular shape in a plan view as a whole, with the top surface provided to a heat dissipation portion 95 so as to be able to dissipate heat. For ease of explanation, the sealing portion 35 is omitted from Figure 1 and the like, and hatching is omitted from Figure 2.

[0011] Terminals 36 are provided on the outer edge of the sealing portion 35. The terminals 36 may be of a non-lead type or may have protruding leads. The terminals 36 include a power terminal 361, a ground terminal 362, an output terminal 363, and a signal terminal 364. In the drawing, the output terminal 363 is labeled with the corresponding phase, such as "363_U." The terminals on the sides within the control region Rc can be used as signal terminals 364, but among the terminals connected to the control land 21, those located on the boundary side with the power region Rp are assigned as power terminals or ground terminals related to the supply of power to the pre-driver IC 180.

[0012] The high-side chips 11 to 13 incorporate upper arm elements 111 to 113, and the low-side chips 14 to 16 incorporate lower arm elements 114 to 116 (see FIG. 3 ). In this embodiment, the upper arm elements 111 to 113 and the lower arm elements 114 to 116 are MOSFETs, but may also be IGBTs, bipolar transistors, or the like. The high-side chips 11 to 13 and the low-side chips 14 to 16 each have a source electrode on the top surface and a drain electrode on the back surface. The chips 11 to 16 are connected to a control chip 18 via signal lines 19. The signal lines 19 include signal lines for gate drive, current detection, temperature detection, and the like.

[0013] As shown in Figure 3, six switching elements, namely upper arm elements 111 to 113 and lower arm elements 114 to 116, are bridge-connected to form a driver circuit 10 that drives a load, namely a motor 800. The drains of the upper arm elements 111 to 113 are connected to a power supply, and the sources are connected to the drains of the corresponding lower arm elements 114 to 116. The sources of the lower arm elements 114 to 116 are connected to ground. The gates of the upper arm elements 111 to 113 and the lower arm elements 114 to 116 are connected to a pre-driver IC 180 built into the control chip 18.

[0014] The connection point between the paired U-phase upper arm element 111 and lower arm element 114 is connected to one end of the U-phase motor winding 801. The connection point between the paired V-phase upper arm element 112 and lower arm element 115 is connected to one end of the V-phase motor winding 802. The connection point between the paired W-phase upper arm element 113 and lower arm element 116 is connected to one end of the W-phase motor winding 803. The other ends of the motor windings 801 to 803 are connected. Note that the motor windings 801 to 803 are not limited to being Y-connected, but may also be Delta-connected.

[0015] 1 and 2, the lead frame 20 includes lands 21 to 26. The back side of the lead frame 20 is exposed from the sealing portion 35 and is electrically connected to the wiring pattern of the substrate 90 by soldering or the like. Note that not all lands need to be connected to the back side of the substrate 90. Each of the lands 21 to 26 is formed integrally with or connected to a terminal 36 on the outer peripheral edge of the sealing portion 35. The control chip 18 is mounted on the control land 21, and the high-side chips 11 to 13 are mounted on the power land 22.

[0016] The control chip 18 is formed in a generally rectangular shape in a plan view. Hereinafter, the direction parallel to the long sides of the control chip 18 will be referred to as the "first direction," and the direction perpendicular to the first direction will be referred to as the "second direction." Furthermore, within the mold, the lead frame 20 side will be referred to as the "lower side," and the top side will be referred to as the "upper side."

[0017] The lands 21 to 25 are arranged in the following order from one side in the second direction: control land 21, power land 22, and three output lands 23 to 25. The ground land 26 is provided adjacent to the power land 22 and the output land 25. The control land 21 is at ground potential, and terminals located on both sides of its short side and at the end opposite the power land 22 are used as signal terminals 364.

[0018] The power land 22 is provided adjacent to the long side of the control land 21. The back side of the power land 22 abuts against the power supply pattern of the substrate 90 and is at the power supply potential. The power land 22 uses a terminal located at the end opposite the ground land 26 in the first direction as a power supply terminal 361. The high-side chips 11 to 13 are arranged side by side on the power land 22 with the source on the upper side, the drain on the lower side, and the gate facing the long side of the control chip 18. The drain electrodes of the high-side chips 11 to 13 are connected to the power land 22.

[0019] The output lands 23 to 25 are arranged side by side adjacent to the power land 22 on the opposite side of the control land 21. An output terminal 363 is formed at the end of the output lands 23 to 25 opposite the power land 22. The output terminal 363 is connected to each phase of the motor winding via circuit board wiring or the like (not shown). A ground terminal 362 is formed on the ground land 26 at the end opposite the land 25.

[0020] Intermediate clips 31 to 33 are placed on the high-side chips 11 to 13, respectively. Intermediate clips 31 to 33 are conductive metal plates made of, for example, copper, formed into a plate shape wider than chips 11 to 16, with one end connected to high-side chips 11 to 13 and low-side chips 14 to 16 and the other end connected to output lands 23 to 25. One end of intermediate clips 31 to 33 is shifted relative to the end of high-side chips 11 to 13 on the control chip 18 side so as to be farther away from control chip 18 than the end of high-side chips 11 to 13 on the control chip 18 side, so that the gate electrodes of high-side chips 11 to 13 can be connected to control chip 18.

[0021] The low-side chips 14 to 16 are arranged above the intermediate clips 31 to 33. The low-side chips 14 to 16 are arranged so that the drain is on the lower side and the source is on the upper side, with the gate facing the long side of the control chip 18. This connects the sources of the high-side chips 11 to 13 and the drains of the low-side chips 14 to 16 via the intermediate clips 31 to 33. The other ends of the intermediate clips 31 to 33 are bent downward and connected to the output lands 23 to 25, respectively.

[0022] The ground clip 34 is a plate-shaped conductive plate made of, for example, copper. The ground clip 34 covers the upper sides of the low-side chips 14 to 16, is bent downward on one side in the first direction, and is connected to the ground land 26. In the electronic device 1, the drain electrodes of the high-side chips 11 to 13 are connected by the power land 22, which is a common metal plate, and the source electrodes of the low-side chips 14 to 16 are connected by the ground clip 34, which is a common metal plate.

[0023] The end of the ground clip 34 on the control chip 18 side is shifted so as to be farther away from the control chip 18 than the end of the low-side chips 14 to 16 on the control chip 18 side, so that the gates of the low-side chips 14 to 16 can be connected to the control chip 18.

[0024] The ground clip 34 is formed wide enough to cover the upper sides of the bent portions of the intermediate clips 31 to 33. By making the area of ​​the ground clip 34 as large as possible, heat dissipation efficiency can be improved. It is preferable in terms of heat dissipation to make the sealing portion 35 on the top surface side of the ground clip 34 thin.

[0025] In the electronic device 1, the control chip 18 is provided on one side in the second direction, and the chips 11 to 16 that make up the driver circuit 10 are provided on the other side, with a power region Rp through which a relatively large current flows and a control region Rc through which a relatively small current flows being arranged in a concentrated manner. In the power region Rp, from the bottom, the power land 22, the high-side chips 11 to 13, the intermediate clips 31 to 33, the low-side chips 14 to 16, and the ground clip 34 are layered in this order, forming a stack structure.

[0026] Furthermore, the gate electrodes of chips 11 to 16 face the control chip 18, and are stacked in a staggered, stepped pattern to ensure that the gate electrodes can be connected to the control chip 18, thereby ensuring a non-overlapping area that does not overlap with components provided above the chips 11 to 16. This allows the chips 11 to 16 and the control chip 18 to be connected by wire bonding using signal lines 19. Furthermore, the connection points of the control chip 18 with the gate electrodes of chips 11 to 16 are concentrated on one side facing the chips 11 to 16.

[0027] In the electronic device 1, in the power region Rp, a power terminal 361 is provided on one side in the first direction, a ground terminal 362 is provided on the other side in the first direction, and an output terminal 363 is provided at the end on the second direction side. When viewed as a whole, power and ground are input in the first direction, and power related to motor drive is output in the second direction. This allows the wiring connecting the power and ground in the power region to be separated from the signal line 19 of the control chip 18, reducing the effects of noise and surges. Furthermore, the power land 22 and the ground land 26, which are at the power supply potential, are arranged adjacent to each other. This reduces the loop in the power section, which is a noise source, thereby reducing noise.

[0028] 4 is a diagram illustrating the parasitic inductance (hereinafter referred to as "ESL") in the driver circuit 10, and here, a U-phase arm is shown as an example. When a large current flows through the electronic device 1, a magnetic field is generated around it, and the area circled by a dashed line becomes ESL, and the energy accumulated there is applied to the element, resulting in switching loss. For example, as a reference example, if an upper arm element is arranged on one side of the control chip and a lower arm element is arranged on the other side, and the source of the upper arm element and the drain of the lower arm element are connected by board wiring outside the module, the wiring length becomes long, and the ESL becomes large.

[0029] In this embodiment, the sources of the high-side chips 11 to 13 and the drains of the low-side chips 14 to 16 are connected on both sides of the intermediate clips 31 to 33. That is, the wiring length between the drain and source indicated by A1 in FIG. 4 is the thickness of the intermediate clips 31 to 33, which is shorter than when the connection is made via board wiring or the like outside the module. Therefore, the ESL can be reduced.

[0030] 4, the drains of the upper arm elements 111 to 113 are connected to the power land 22 common to all three phases, and the sources of the lower arm elements 114 to 116 are connected to the ground clip 34 common to all three phases. This eliminates the ELS difference between the phases, making it possible to speed up the return current switching and reduce switching loss.

[0031] By providing the control chip 18 that constitutes the pre-driver IC 180 within the module and wiring the gate signal lines within the module, there is no need to provide vias or the like, as compared to providing gate wiring on a printed circuit board, for example, and therefore ESL can be reduced.

[0032] As described above, the electronic device 1 includes a plurality of high-side chips 11 to 13, a plurality of low-side chips 14 to 16, a power land 22, a ground clip 34, and a sealing portion 35. The high-side chips 11 to 13 incorporate upper arm elements 111 to 113 connected to their high-potential sides. The low-side chips 14 to 16 incorporate lower arm elements 114 to 116 connected to the low-potential sides of the respective upper arm elements 111 to 113, and are connected to their paired high-side chips within the module. Specifically, the paired U-phase high-side chip 11 and low-side chip 14 are connected, the paired V-phase high-side chip 12 and low-side chip 15 are connected, and the paired W-phase high-side chip 13 and low-side chip 16 are connected.

[0033] Power lands 22, which are power supply wiring members, connect the high-side chips 11 to 13 to a power supply potential. Ground clips 34, which are ground wiring members, connect the low-side chips 14 to 16 to a ground potential. Sealing section 35 seals the high-side chips 11 to 13, the low-side chips 14 to 16, the power lands 22, and the ground clips 34 together.

[0034] The ground clip 34 is shared by the plurality of low-side chips 14 to 16. The power land 22 is also shared by the plurality of high-side chips 11 to 13. This allows the ESL of each phase to be common, thereby reducing surge voltage differences and switching loss differences between arms.

[0035] The power supply wiring member of this embodiment is a power land 22 on which the high-side chips 11 to 13 are arranged, and the power land 22 is arranged adjacent to a ground land 26 connected to a ground clip 34. This shortens the wiring distance between the power supply and ground, thereby reducing ESL.

[0036] The intermediate connecting member connecting the paired high-side chips 11 to 13 and low-side chips 14 to 16 is composed of two or less members. In this embodiment, the high-side chip 11, intermediate clip 31, and low-side chip 14 paired with the high-side chip 11 are stacked in this order, with the high-side chip 11 and low-side chip 14 connected on both sides of the intermediate clip 31. The high-side chip 12, intermediate clip 32, and low-side chip 15 paired with the high-side chip 12 are stacked in this order, with the high-side chip 12 and low-side chip 15 connected on both sides of the intermediate clip 32. The high-side chip 13, intermediate clip 33, and low-side chip 16 paired with the high-side chip 13 are stacked in this order, with the high-side chip 13 and low-side chip 16 connected on both sides of the intermediate clip 33. That is, in this embodiment, the paired high-side chips 11 to 13 and low-side chips 14 to 16 are connected by one intermediate clip 31 to 33, respectively.

[0037] By minimizing the number of intermediate connectors, the wiring length can be shortened, and ESL can be reduced. In addition, by forming the high-side chips 11 to 13, the intermediate clips 31 to 33, and the low-side chips 14 to 16 in a stacked structure, the electronic device 1 can be made smaller.

[0038] The intermediate clips 31 to 33 and the low-side chips 14 to 16 are provided on the top surfaces of the high-side chips 11 to 13 and are stacked in a shifted state so as not to overlap portions of the high-side chips 11 to 13. By stacking the intermediate clips 31 to 33 and the low-side chips 14 to 16 in a shifted state and ensuring non-overlapping areas on the top surfaces of the high-side chips 11 to 13, the signal line 19 can be connected appropriately.

[0039] The electronic device 1 includes a control chip 18 that incorporates a pre-driver IC 180 that outputs drive signals for the upper arm elements 111 to 113 and the lower arm elements 114 to 116 and is sealed in a sealing portion 35. The high-side chips 11 to 13 and the low-side chips 14 to 16 are arranged on one side of the control chip 18 with their gate electrodes facing the control chip. By incorporating the control chip 18, the number of terminals can be reduced. Furthermore, by collectively arranging the high-side chips 11 to 13 and the low-side chips 14 to 16 on one side of the control chip 18, the control region Rc and the power region Rp can be separated.

[0040] Second Embodiment A second embodiment is shown in FIG. 5. The electronic device 2 is similar to the first embodiment in terms of the arrangement and connection of the chips 11 to 16. FIG. 5 is a simplified illustration, omitting terminals other than signal terminals, and focusing on gate signal lines as signal lines, with other signal lines omitted as appropriate. This also applies to the figures of the following embodiments. In this embodiment, the land 27, which is a ground land, is integrally formed with a control land 271 adjacent to the power land 22 on the second direction side and on which the control chip 18 is disposed, and a ground land 272 adjacent to the power land 22 on the first direction side and connected to the ground clip 34. This configuration also achieves the same effects as the above embodiment.

[0041] (Third Embodiment) A third embodiment is shown in Figure 6. The electronic device 3 has the same arrangement of chips 11 to 16 as in the first embodiment. The land 28, which is the ground land in this embodiment, is formed integrally with a control land 281 on which the control chip 18 is placed, and ground lands 282 and 283. The ground lands 282 and 283 are formed on both sides of the power land 22.

[0042] The ground clip 81 is provided above the low-side chips 14 to 16, is bent downward on both sides in the first direction, and is connected to the ground lands 282 and 283. By providing the ground lands 282 and 283 on both sides, connection to the ground pattern of the board from either side is possible, improving the flexibility of the board layout. In addition, the same effects as those of the above embodiment are achieved.

[0043] (Fourth Embodiment) A fourth embodiment is shown in FIGS. 7 to 9. In the cross-sectional view of FIG. 8, hatching of the capacitor 93 is omitted. Also, FIG. 9 is a schematic diagram of FIG. 7, turned upside down. The lead frame 40 of the electronic device 4 has a power land 41, output lands 42 to 44, and ground lands 45 to 47. In this embodiment, a control chip is not built in, but a control chip may be built in as in the above embodiments. The same applies to the sixth and seventh embodiments.

[0044] The power land 41 is generally similar to the power land 22 in the above embodiment, with the high-side chips 11 to 13 arranged side by side. Intermediate clips 31 to 33 are provided on the high-side chips 11 to 13, and the low-side chips 14 to 16 are stacked on the intermediate clips 31 to 33. The high-side chips 11 to 13 and the low-side chips 14 to 16 are connected to both sides of one end of the intermediate clips 31 to 33, and the other end is connected to the output lands 42 to 44. The stacked structure of the chips 11 to 16 is the same as in the above embodiment. Furthermore, the gate terminals GUH, GUL, GVH, GVL, GWH, and GWL are assigned to terminals on one side in the second direction.

[0045] The output lands 42 to 44 are arranged between the power land 41 and the ground lands 45 to 47 in the second direction. The output land 43, which is arranged in the middle in the first direction, is provided with a terminal connection portion 431 that extends on both sides in the first direction. The output lands 42 and 44 are provided on both sides of the output land 43 on the ground land side of the terminal connection portion 431. The output terminal 363 connected to the output lands 42 to 44 is provided on the first direction side.

[0046] The ground lands 45 to 47 are provided on the opposite side of the power land 41 across the output lands 42 to 44. That is, in this embodiment, the power land 41, the terminal connection portion 431 of the output land 43, the output lands 42 to 44, and the ground lands 45 to 47 are arranged in this order from one side in the second direction. The ground terminal 362 connected to the ground lands 45 to 47 is provided on the opposite side of the gate terminal in the second direction.

[0047] The ground clip 82 has a base 821 and protrusions 822 to 824. The base 821 is provided to cover the upper sides of the low-side chips 14 to 16, offset so as not to overlap with the gate electrodes of the low-side chips 14 to 16. The protrusions 822 to 824 are bent downward and connected to the ground lands 45 to 47. The ground clip 82 of this embodiment is provided to cover the upper sides of the intermediate clips 31 to 33.

[0048] 8, the power land 41, which is the power supply potential, and the ground lands 45 to 47 are exposed from the sealing portion 35 on the underside, and are electrically connected to the power supply pattern 901 and the ground pattern 902 of the substrate 90 by soldering or the like. In other words, the electronic device 4 is connected to the substrate 90 by a backside connection.

[0049] If the mounting surface of the substrate 90 on which the electronic device 4 is mounted is referred to as the first mounting surface B1 and the opposite mounting surface is referred to as the second mounting surface B2, the power supply pattern 901 and the ground pattern 902 are formed to extend to the second mounting surface B2 side via vias 903. A capacitor 93 is connected to the second mounting surface B2 side of the power supply pattern 91 and the ground pattern 92. That is, the capacitor 93 is provided on the back surface of the driver circuit 10 and is connected to the common power supply pattern 901 and the ground pattern 902. This shortens the wiring length between the driver circuit 10 and the capacitor 93, thereby efficiently reducing ESL. Note that in embodiments other than this embodiment, the capacitor may be connected to the second mounting surface side of the power supply pattern and the ground pattern to which the electronic device is connected on the back surface.

[0050] In this embodiment, the power land 41 and the ground lands 45 to 47 connected to the low-side chips 14 to 16 via the ground clip 82 have their surfaces that abut against the substrate 90 exposed from the sealing portion 35 and are connected to the power supply pattern and ground pattern of the substrate 90, respectively.

[0051] The power supply pattern 901 and the ground pattern 902 are formed to extend to the rear surface side through vias 903 that penetrate the substrate 90, and are connected to a capacitor 93. This makes it possible to reduce ESL with high efficiency.

[0052] 10 shows a fifth embodiment. In the following embodiments, the high-side chips 11 to 13 and the low-side chips 14 to 16 are not stacked but are arranged flat. The lead frame 50 of the electronic device 5 has a power land 51, output lands 52 to 54, and a ground land 55.

[0053] The high-side chips 11 to 13 are disposed on the power land 51, and are connected to drain electrodes provided on the back surfaces of the high-side chips 11 to 13. Source electrodes provided on the upper surfaces of the high-side chips 11 to 13 are connected to intermediate clips 71 to 73. The intermediate clips 71 to 73 are provided to cover the upper surfaces of the high-side chips 11 to 13 in a state in which the gate electrodes and gate terminals of the high-side chips 11 to 13 can be connected, and one end of the intermediate clips 71 to 73 on the second direction side is bent downward and connected to the output lands 52 to 54.

[0054] The output lands 52 to 54 are provided adjacent to the power land 51 on the second direction side, and the low-side chips 14 to 16 are arranged on the output lands 52 to 54. The drain electrodes provided on the back surfaces of the low-side chips 14 to 16 are connected to the output lands 52 to 54. That is, the source electrodes of the high-side chips 11 to 13 and the drain electrodes of the low-side chips 14 to 16 are connected via two members, the intermediate clips 71 to 73 and the output lands 52 to 54.

[0055] That is, in this embodiment, intermediate clips 71-73 and output lands 52-54 are "intermediate connecting members," and the number of intermediate connecting members connecting the paired U-phase high-side chip 11 and low-side chip 14 is two. Similarly, the number of intermediate connecting members connecting the paired V-phase high-side chip 12 and low-side chip 15 is two, and the number of intermediate connecting members connecting the paired W-phase high-side chip 13 and low-side chip 15 is two.

[0056] The ground land 55 is provided adjacent to the first direction side of the power land 51 and the output land 52. The ground clip 34 is generally similar to the first embodiment except that it is narrower than the first embodiment, covers the upper sides of the low-side chips 14 to 16, is bent downward on the ground land 55 side, and is connected to the ground land 55.

[0057] The gate electrodes of chips 11 to 16 are connected to the gate terminals at locations not covered by clips 71 to 73 and 34. In this embodiment, a control IC is not built into the module, and the gate terminals connected to the gate electrodes of high-side chips 11 to 13 are provided on one side in the second direction, and the gate terminals connected to the gate electrodes of low-side chips 14 to 16 are provided on the other side in the second direction. Even with this configuration, the same effects as those of the above embodiment can be achieved.

[0058] 11 and 12. The lead frame 56 of the electronic device 6 differs from the fifth embodiment in that the ground lands 571 to 573 are provided on the opposite side of the power land 51, sandwiching the output lands 52 to 54. That is, in this embodiment, the power land 51, the output lands 52 to 54, and the ground lands 571 to 573 are arranged in this order from one side in the second direction.

[0059] The intermediate clips 71 to 73 are provided with notches 711 to 713 for connecting the gate electrodes of the high-side chips 11 to 13 to the gate terminals. The notches 711 to 713 are provided at the corners on the end side opposite the output lands 52 to 54.

[0060] The ground clip 83 is provided above the low-side chips 14 to 16. Three protrusions formed on the ground clip 83 on the sides of the ground lands 571 to 573 are bent downward and connected to the ground lands 571 to 573, respectively. The ground clip 83 is provided with cutouts 831 and 832 so that gate electrodes provided on the sides of the ground lands 571 to 573 of the low-side chips 14 to 16 can be connected to the gate terminals. The cutout 831 is provided at a position corresponding to the gate electrode of the U-phase low-side chip 14. The cutout 832 is provided at a position corresponding to the gate electrodes of the adjacent V-phase and W-phase low-side chips 15 and 16.

[0061] 13 is a modification of the sixth embodiment, in which the intermediate clips 71 to 73 are narrower than the high-side chips 11 to 13. The gate electrodes of the high-side chips 11 to 13 are connected to gate terminals on the sides of the intermediate clips 71 to 73 in the first direction. In addition, the ground clip 83 is provided with notches 833 to 835 for connecting the gate electrodes and gate terminals of the low-side chips 14 to 16 for each phase.

[0062] In the sixth embodiment, the W-phase low-side chip 16 is positioned offset in the second direction from the U-phase and V-phase low-side chips 14 and 15, but an offset that allows the source electrodes to be connected to a common ground clip 83 is permitted, and the chips are considered to be "arranged side by side." A similar amount of offset is also permitted for the high-side chips 11 to 13. This configuration achieves the same effects as the above-described embodiments.

[0063] (Eighth and Ninth Embodiments) An eighth embodiment is shown in Fig. 14, and a ninth embodiment is shown in Fig. 15. In the eighth and ninth embodiments, chips 11 to 16 are placed flat, and a control chip 18 is built into the module.

[0064] A lead frame 60 of an electronic device 8 according to the eighth embodiment has a power land 61, output lands 62 to 64, and ground lands 65 to 67. The power land 61 has element mounting portions 611 to 613 and an IC mounting portion 615. The element mounting portions 611 and 613 are provided to protrude on both sides of the IC mounting portion 615 in a first direction, and high-side chips 11 and 13 are disposed thereon. The element mounting portion 612 is provided to protrude on the second direction side of the IC mounting portion 615, and high-side chip 12 is disposed thereon. The drain electrodes of the high-side chips 11 to 13 are connected to the power land 61.

[0065] The control chip 18 is provided on the IC mounting section 615. In the control chip 18 of this embodiment, the back side of the element is insulated, so it can be placed on a land of power supply potential as in this embodiment, not just a land of ground potential. In embodiments other than this embodiment, a control chip with an insulated back side may also be used.

[0066] The output land 62 is provided adjacent to the element mounting portion 611 on the second direction side. The output land 63 is provided on the second direction side of the IC mounting portion 615, between the output land 62 and the element mounting portion 612. The output land 63 is provided adjacent to the element mounting portion 613 on the second direction side. Therefore, the output lands 62 to 64 and the element mounting portion 612 are arranged in the following order from one side in the first direction: output land 62, output land 63, element mounting portion 612, output land 64.

[0067] The output lands 62-64 are provided with the low-side chips 14-16 and are connected to the drain electrodes of the low-side chips 14-16. The intermediate clips 71-73 connect the sources of the high-side chips 11-13 to the output lands 62-64. The ground clip 84 connects the sources of the low-side chips 14-16 to the ground lands 65-67. The ground clip 84 is formed in a substantially rectangular shape and has a notch 841 where the intermediate clip 72 is provided.

[0068] Chips 11 to 16 are arranged so as to surround three sides of control chip 18 as a whole. Clips 71 to 73 and 84 are provided on chips 11 to 16 so as to be offset from one another so that the control chip 18 sides of chips 11 to 16 do not overlap, so that various signal lines including gate signal lines that connect gate electrodes and control chip 18 can be connected.

[0069] The electronic device 9 of the ninth embodiment shown in FIG. 15 is generally similar to the eighth embodiment, except for the shape of the ground clip 85. The ground clip 85 has a ground connection portion 851 connected to the ground lands 65 to 67 and protrusions 852 to 854 protruding from the ground connection portion 851 in the second direction. The protrusions 852 to 853 are provided where the low-side chips 14 to 16 are disposed, and are connected to the source electrodes of the low-side chips 14 to 16 on their lower surfaces. Note that FIG. 14 omits the second direction side terminals, ground side terminals, and signal lines such as gate connections. Even with this configuration, the same effects as the above-described embodiments can be achieved.

[0070] In the embodiment, the power lands 22, 41, 51, and 61 correspond to the "power supply wiring member," the ground clips 34 and 81 to 85 correspond to the "ground wiring member," the intermediate clips 31 to 33 and 71 to 73, and the output lands 52 to 54 correspond to the "intermediate connecting member," and the capacitor 93 corresponds to the "noise prevention element."

[0071] (Other Embodiments) In the above embodiment, the low-side chip is connected by a ground clip, which is a plate-shaped metal plate. In other embodiments, the member connecting the source of the low-potential side element is not limited to a metal plate, and ribbon bonding or aluminum bonding may be used. The same applies to the member connecting the high-side chip.

[0072] In the above embodiment, the ground clip is sealed in the sealing portion 35. In other embodiments, as shown in FIG. 16 , the ground clip may be exposed from the top surface of the sealing portion, allowing heat to be dissipated directly to the heat dissipation housing. That is, the ground clip is a metal plate connected to the top surface of the low-side chip, and the surface opposite the low-side chip is exposed from the sealing portion. This improves heat dissipation efficiency. Note that FIG. 16 illustrates the electronic device 1 of the first embodiment, but in embodiments other than the first embodiment, the top surface of the ground clip may be exposed from the sealing portion.

[0073] In the above embodiment, the noise prevention element is a capacitor. In other embodiments, the noise prevention element may be an electronic component other than a capacitor, such as a snubber circuit, as long as it is capable of reducing noise.

[0074] (Disclosure of Technical Ideas) This specification discloses multiple technical ideas described in the following multiple clauses. Some clauses may be described in a multiple dependent form, with the subsequent clause alternatively referring to the preceding clause. Furthermore, some clauses may be described in a multiple dependent form, with the subsequent clause referring to another multiple dependent clause. These multiple dependent clauses define multiple technical ideas.

[0075] (Technical Idea 1) An electronic device comprising: a plurality of high-side chips (11-13) each incorporating upper arm elements (111-113) connected to a high potential side; a plurality of low-side chips (14-16) each incorporating lower arm elements (114-116) connected to a low potential side of each of the upper arm elements, and connected inside a module to a paired high-side chip; a power supply wiring member (22, 41, 51, 61) connecting the high-side chips to a power supply potential; ground wiring members (34, 81-85) connecting the low-side chips to a ground potential; and a sealing portion (35) that integrally seals the high-side chips, the low-side chips, the power supply wiring member, and the ground wiring member, wherein the ground wiring member is shared by a plurality of the low-side chips. (Technical Idea 2) The electronic device according to Technical Idea 1, in which the power supply wiring member is shared by a plurality of the high-side chips. (Technical Concept 3) The electronic device according to Technical Concept 1 or 2, wherein the power supply wiring member is a power land on which the high-side chip is disposed and is disposed adjacent to a ground land (26-28, 55) connected to the ground wiring member. (Technical Concept 4) The electronic device according to Technical Concept 1 or 2, wherein the power supply wiring member is a power land on which the high-side chip is disposed, and the power lands and ground lands (26-28, 45-47, 55, 571-573, 65-67) connected to the low-side chip via the ground wiring member have surfaces that abut against the substrate (90) exposed from the sealing portion and are connected to a power supply pattern (901) and a ground pattern (902) on the substrate, respectively. (Technical Concept 5) The electronic device according to Technical Concept 4, wherein the power supply pattern and the ground pattern are formed to extend to the back side via a via (903) that penetrates the substrate and are connected to a noise suppression element (93). (Technical Idea 6) The electronic device according to any one of Technical Ideas 1 to 5, wherein the intermediate connection members (31 to 33, 51 to 53, 71 to 73) connecting the paired high-side chip and low-side chip are composed of two or less members.(Technical Idea 7) The electronic device according to Technical Idea 6, wherein the high-side chip, the intermediate connection member, and the low-side chip paired with the high-side chip are stacked in this order, and the high-side chip and the low-side chip are connected on both sides of the intermediate connection member. (Technical Idea 8) The electronic device according to Technical Idea 7, wherein the intermediate connection member and the low-side chip are provided on the top surface of the high-side chip and are stacked in a shifted state so that portions of the top surfaces of the high-side chips do not overlap. (Technical Idea 9) The electronic device according to any one of Technical Ideas 1 to 8, wherein the ground wiring member is a metal plate connected to the top surface of the low-side chip, and wherein the surface opposite to the low-side chip is exposed from the sealing portion. (Technical Idea 10) An electronic device according to any one of Technical Ideas 1 to 9, further comprising a control chip (18) sealed in the sealing portion, the control chip having a built-in pre-driver IC (180) that outputs drive signals for the upper arm elements and the lower arm elements, wherein the high-side chip and the low-side chip are arranged on one side of the control chip with gate electrodes to which the drive signals are input facing the control chip side.

[0076] As described above, the present disclosure is not limited to the above-described embodiment, and can be implemented in various forms without departing from the spirit of the present disclosure.

[0077] The present disclosure has been described based on the embodiments. However, the present disclosure is not limited to the embodiments and structures. The present disclosure also encompasses various modifications and variations within the scope of equivalents. Furthermore, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

Claims

1. An electronic device comprising: a plurality of high-side chips (11-13) incorporating upper arm elements (111-113) connected to the high potential side; a plurality of low-side chips (14-16) incorporating lower arm elements (114-116) connected to the low potential side of each of the upper arm elements and connected inside a module to the paired high-side chip; power supply wiring members (22, 41, 51, 61) connecting the high-side chips to a power supply potential; ground wiring members (34, 81-85) connecting the low-side chips to a ground potential; and a sealing portion (35) that integrally seals the high-side chip, the low-side chip, the power supply wiring members and the ground wiring member, wherein the ground wiring member is shared by a plurality of the low-side chips.

2. The electronic device according to claim 1, wherein the power supply wiring member is shared by a plurality of the high-side chips.

3. An electronic device according to claim 1 or 2, wherein the power supply wiring member is a power land on which the high-side chip is disposed, and is disposed adjacent to a ground land (26-28, 55) connected to the ground wiring member.

4. The electronic device of claim 1 or 2, wherein the power supply wiring member is a power land on which the high-side chip is disposed, and the power lands and ground lands (26-28, 45-47, 55, 571-573, 65-67) connected to the low-side chip via the ground wiring member have surfaces that come into contact with a substrate (90) exposed from the sealing portion and are connected to a power supply pattern (901) and a ground pattern (902) of the substrate, respectively.

5. The electronic device according to claim 4, wherein the power supply pattern and the ground pattern are formed to extend to the rear surface side through vias (903) that penetrate the substrate, and are connected to a noise suppression element (93).

6. The electronic device according to claim 1 or 2, wherein the intermediate connection members (31 to 33, 51 to 53, 71 to 73) connecting the pair of high-side chip and low-side chip are composed of two or less members.

7. The electronic device according to claim 6, wherein the high-side chip, the intermediate connection member, and the low-side chip paired with the high-side chip are stacked in this order, and the high-side chip and the low-side chip are connected on both sides of the intermediate connection member.

8. The electronic device according to claim 7, wherein the intermediate connection member and the low-side chip are provided on the top surface side of the high-side chip, and are stacked in a shifted state so that portions of the top surface side of the high-side chip do not overlap.

9. The electronic device according to claim 1 or 2, wherein the ground wiring member is a metal plate connected to the top surface of the low-side chip, and the surface opposite the low-side chip is exposed from the sealing portion.

10. An electronic device as described in claim 1 or 2, further comprising a control chip (18) sealed in the sealing portion, the control chip having a built-in pre-driver IC (180) that outputs drive signals for the upper arm elements and the lower arm elements, the high-side chip and the low-side chip being arranged on one side of the control chip with gate electrodes to which the drive signals are input facing the control chip.

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