Semiconductor device, semiconductor package, and method for manufacturing semiconductor device

Abstract

This semiconductor device includes a semiconductor substrate. A reform part is formed inside the semiconductor substrate. The reform part is indicative of information relating to a process for manufacturing the semiconductor device.

Description

Semiconductor device, semiconductor package, and method of manufacturing the semiconductor device

[0001] The present disclosure relates to a semiconductor device, a semiconductor package, and a method for manufacturing a semiconductor device.

[0002] For example, Japanese Patent No. 7355970 (Patent Document 1) describes a semiconductor device. The semiconductor device described in Patent Document 1 has a semiconductor substrate. In the semiconductor device described in Patent Document 1, for example, markings are formed on the main surface of the semiconductor substrate. The markings are formed by irradiating the main surface of the semiconductor substrate with laser light.

[0003] Patent No. 7355970

[0004] [Summary] When marking is performed by irradiating a main surface of a semiconductor substrate with laser light, as in the semiconductor device described in Patent Document 1, the surface roughness of the main surface of the semiconductor substrate increases in the areas where marking is performed, which can result in the generation of particles in, for example, manufacturing processes performed after marking.

[0005] The semiconductor device according to the present disclosure includes a semiconductor substrate, and a modified portion is formed inside the semiconductor substrate. The modified portion indicates information related to a manufacturing process of the semiconductor device.

[0006] 1 is a plan view of the semiconductor device 100. FIG. 1 is a plan view of the semiconductor device 100 before singulation. FIG. 2 is a cross-sectional view taken along III-III in FIG. 1. FIG. 3 is an enlarged plan view showing a first example of a formation mode of the modified portion 14. FIG. 4 is an enlarged plan view showing a second example of a formation mode of the modified portion 14. FIG. 5 is an enlarged plan view showing a third example of a formation mode of the modified portion 14. FIG. 6 is an enlarged plan view showing a fourth example of a formation mode of the modified portion 14. FIG. 7 is a cross-sectional view of a semiconductor package 200. FIG. 8 is a plan view of the semiconductor package 200. FIG. 9 is a manufacturing process diagram of the semiconductor device 100. FIG. 10 is a cross-sectional view illustrating an element isolation film forming step S2. FIG. 11 is a cross-sectional view illustrating a first ion implantation step S3. FIG. 12 is a cross-sectional view illustrating a gate insulating film forming step S4. FIG. 13 is a cross-sectional view illustrating a gate electrode forming step S5. FIG. 14 is a cross-sectional view illustrating a second ion implantation step S6. FIG. 15 is a cross-sectional view illustrating a sidewall spacer forming step S7. FIG. 16 is a cross-sectional view illustrating a third ion implantation step S8. FIG. 17 is a cross-sectional view illustrating a first interlayer insulating film forming step S9. FIG. 18 is a cross-sectional view illustrating a contact plug forming step S10. FIG. 19 is a cross-sectional view illustrating a first wiring forming step S11. FIG. 19 is a cross-sectional view illustrating a second interlayer insulating film forming step S12. 29. A cross-sectional view illustrating a via plug forming step S13. A cross-sectional view illustrating a second wiring forming step S14. A cross-sectional view illustrating a protective film forming step S15. A cross-sectional view illustrating a first example of a marking step S17. A cross-sectional view illustrating a second example of a marking step S17. An enlarged plan view illustrating a first example of a formation mode of a modified portion 14 in the semiconductor device 100A. A schematic cross-sectional view taken along XXVII-XXVII in FIG. 26. An enlarged plan view illustrating a second example of a formation mode of a modified portion 14 in the semiconductor device 100A. An enlarged plan view illustrating a third example of a formation mode of a modified portion 14 in the semiconductor device 100A. A schematic plan view taken along XXX-XXX in FIG. 29. A plan view illustrating a first example of a semiconductor package 200A. A schematic cross-sectional view taken along XXXII-XXXII in FIG. 31. A plan view illustrating a second example of a semiconductor package 200A. A schematic cross-sectional view taken along XXXIV-XXXIV in FIG. 33. A plan view illustrating a third example of a semiconductor package 200A. 36 is a schematic cross-sectional view taken along the line XXXVI-XXXVI in FIG. 35. FIG. 36 is a cross-sectional view of the semiconductor device 100B.

[0007] DETAILED DESCRIPTION A semiconductor device according to an embodiment of the present disclosure will be described. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant description will not be repeated.

[0008] First Embodiment A semiconductor device according to a first embodiment will be described. The semiconductor device according to the first embodiment is designated as a semiconductor device 100.

[0009] <Configuration of Semiconductor Device 100> The configuration of the semiconductor device 100 will be described below.

[0010] Fig. 1 is a plan view of a semiconductor device 100. Fig. 2 is a plan view of the semiconductor device 100 before singulation. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1. As shown in Figs. 1 to 3, the semiconductor device 100 includes a semiconductor substrate 10, a gate insulating film 20, a gate electrode 30, a sidewall spacer 40, an interlayer insulating film 50, wiring 60, a contact plug 61, a via plug 62, and a protective film 70.

[0011] The semiconductor substrate 10 has a main surface 10a and a main surface 10b. The main surface 10b is the surface opposite to the main surface 10a. The main surface 10a and the main surface 10b are end surfaces in the thickness direction of the semiconductor substrate 10. The constituent material of the semiconductor substrate 10 is, for example, single crystal silicon. However, the constituent material of the semiconductor substrate 10 is not limited to this. The constituent material of the semiconductor substrate 10 may be, for example, silicon carbide or gallium nitride.

[0012] A planar view refers to a view along the normal direction of the main surface 10a. In a planar view, the semiconductor substrate 10 has a device region 11 and a marking region 12. The device region 11 is a region where circuit elements such as transistors are formed. The marking region 12 is a region where information related to the manufacturing process of the semiconductor device 100 is held. In a planar view, the device region 11 and the marking region 12 are located inside the outer periphery of the semiconductor substrate 10. More specifically, the device region 11 and the marking region 12 are located inside a scribe lane (not shown) of the semiconductor wafer. The semiconductor wafer is cut along the boundary region between two adjacent semiconductor devices 100 to be divided into multiple semiconductor devices 100, and this boundary region is the scribe lane.

[0013] In the device region 11, the semiconductor substrate 10 has a source region 11 a, a drain region 11 b, and a well region 11 c. The source region 11 a is formed on the main surface 10 a. The drain region 11 b is formed on the main surface 10 a so as to be spaced apart from the source region 11 a. The well region 11 c is formed on the main surface 10 a so as to surround the source region 11 a and the drain region 11 b in a cross-sectional view along the normal direction of the main surface 10 a.

[0014] The conductivity type of the source region 11a and the drain region 11b is opposite to that of the well region 11c. For example, if the conductivity type of the source region 11a and the drain region 11b is n-type, the conductivity type of the well region 11c is p-type. The portion of the well region 11c between the source region 11a and the drain region 11b is sometimes called a channel region.

[0015] The source region 11a has a first region 11aa and a second region 11ab. The drain region 11b has a first region 11ba and a second region 11bb. The first region 11aa is closer to the drain region 11b than the second region 11ab, and the first region 11ba is closer to the source region 11a than the second region 11bb. The dopant concentration in the first region 11aa is lower than that in the second region 11ab, and the dopant concentration in the first region 11ba is lower than that in the second region 11bb. In other words, the source region 11a and the drain region 11b have an LDD (Lightly Doped Diffusion) structure.

[0016] An element isolation film 13 is formed on the main surface 10a. The element isolation film 13 surrounds the well region 11c in a plan view. The element isolation film 13 is made of, for example, silicon oxide. The element isolation film 13 is embedded in, for example, a trench formed in the main surface 10a. That is, the element isolation film 13 is an STI (Shallow Trench Isolation) film. The element isolation film 13 may also be a LOCOS (Local Oxidation Of Silicon) film.

[0017] The gate insulating film 20 is disposed on the main surface 10a in the device region 11. More specifically, the gate insulating film 20 is disposed on the channel region. The gate insulating film 20 is formed of, for example, silicon oxide. The gate electrode 30 is disposed on the gate insulating film 20. That is, the gate electrode 30 is disposed opposite the channel region with the gate insulating film 20 interposed therebetween. The gate electrode 30 is formed of, for example, polycrystalline silicon containing a dopant. The source region 11a, the drain region 11b, the well region 11c, the gate insulating film 20, and the gate electrode 30 constitute a transistor, and two adjacent transistors are separated by an element isolation film 13.

[0018] The sidewall spacers 40 are arranged on the main surface 10a in the device region 11. More specifically, the sidewall spacers 40 are arranged on the first regions 11aa and 11ba so as to contact the side surfaces of the gate electrode 30. The sidewall spacers 40 are made of, for example, silicon oxide.

[0019] The lowermost interlayer insulating film 50 is disposed on the main surface 10a so as to cover the element isolation film 13, the gate electrode 30, and the sidewall spacers 40. The interconnection 60 is disposed on the interlayer insulating film 50. The lowermost interconnection 60 is electrically connected to the source region 11a (first region 11aa) and the drain region 11b (second region 11bb) by contact plugs 61. Although not shown, the lowermost interconnection 60 is also electrically connected to the gate electrode 30 by the contact plugs 61. The contact plugs 61 are embedded in contact holes formed in the lowermost interlayer insulating film 50.

[0020] The upper interlayer insulating film 50 is disposed on the lower interlayer insulating film 50 so as to cover the wiring 60 disposed on the lower interlayer insulating film 50. The wiring 60 of adjacent layers is electrically connected by via plugs 62. The via plugs 62 are embedded in via holes formed in the interlayer insulating films 50 other than the bottom layer. The protective film 70 is disposed on the uppermost interlayer insulating film 50 so as to cover the wiring 60 of the uppermost layer.

[0021] The interlayer insulating film 50 is made of, for example, silicon oxide. The wiring 60 is made of, for example, aluminum or an aluminum alloy. The contact plugs 61 and the via plugs 62 are made of, for example, tungsten. The protective film 70 is made of, for example, silicon nitride.

[0022] In the marking region 12, a modified portion 14 is formed inside the semiconductor substrate 10. The modified portion 14 is a portion of the semiconductor substrate 10 into which defects (such as dislocations) have been introduced. The modified portion 14 indicates information related to the manufacturing process of the semiconductor device 100. The information related to the manufacturing process of the semiconductor device 100 may include, for example, inspection results during the manufacturing of the semiconductor device 100, the lot number of the semiconductor wafer from which the semiconductor device 100 was obtained, and / or the position of the semiconductor device 100 on the semiconductor wafer. However, the information related to the manufacturing process of the semiconductor device 100 is not limited to this. A crack may or may not be introduced into the modified portion 14. The information related to the manufacturing process of the semiconductor device 100 may include, for example, a company code or a product code. The information related to the manufacturing process of the semiconductor device 100 may be different for each semiconductor device 100 to ensure traceability of each semiconductor device 100. The information related to the manufacturing process of the semiconductor device 100 may include, for example, an ID identifying the manufacturing equipment used in the manufacturing process of the semiconductor device 100 to ensure traceability of the cause of defects in the manufacturing process.

[0023] The wiring 60 is arranged so as not to overlap the marking region 12 in plan view. The arithmetic mean roughness (Ra) of the portion of the main surface 10a that overlaps the modified portion 14 in plan view is 1 nm or less. From another perspective, the calculated mean roughness of the portion of the main surface 10a that overlaps the modified portion 14 in plan view is approximately the same as the arithmetic mean roughness of the portion of the main surface 10a that does not overlap the modified portion 14 in plan view.

[0024] FIG. 4 is an enlarged plan view showing a first example of a formation mode of the modified portion 14. As shown in FIG. 4, the marking region 12 may be divided into a plurality of regions 12a (indicated by dotted lines in FIG. 4) arranged in a matrix. Information related to the manufacturing process of the semiconductor device 100 is indicated by whether or not the modified portion 14 is formed in each of the plurality of regions 12a. The marking region 12 may have a plurality of columns of regions 12a. One column of regions 12a and another column of regions 12a indicate information related to different manufacturing processes of the semiconductor device 100.

[0025] In the example of Figure 4, the column (first column) of the leftmost area 12a indicates the lot number of the semiconductor wafer, the column (second column) of the area 12a immediately to the right of the first column indicates the position of the semiconductor device 100 on the semiconductor wafer, and the column (third column) of the area 12a immediately to the right of the second column indicates the inspection results during the manufacturing of the semiconductor device 100.

[0026] 5 is an enlarged plan view showing a second example of the formation mode of the modified portions 14. As shown in Fig. 5, in the second example as well, information about the manufacturing process of the semiconductor device 100 is indicated by whether or not the modified portions 14 are formed in each of the multiple regions 12a, and the modified portions 14 arranged two-dimensionally in a plan view form a QR code (registered trademark).

[0027] 6 is an enlarged plan view showing a third example of the formation mode of the modified regions 14. In the third example, as shown in FIG. 6, the modified regions 14 extend along a first direction DR1 in a plan view and are arranged along a second direction DR2 in a plan view. The second direction DR2 is a direction perpendicular to the first direction DR1 in a plan view. In the third example, the spacing between two adjacent modified regions 14 in the second direction DR2 indicates information related to the manufacturing process of the semiconductor device 100. From another perspective, the arrangement of the modified regions 14 may form a barcode.

[0028] 7 is an enlarged plan view showing a fourth example of the formation mode of the modified portions 14. As shown in Fig. 7, the modified portions 14 may be arranged to form letters or numbers. In the fourth example, the letters or numbers indicate information related to the manufacturing process of the semiconductor device 100.

[0029] <Configuration of Semiconductor Package 200> The following describes the configuration of a semiconductor package using the semiconductor device 100. The semiconductor package using the semiconductor device 100 is referred to as a semiconductor package 200.

[0030] FIG. 8A is a cross-sectional view of the semiconductor package 200. FIG. 8B is a plan view of the semiconductor package 200. As shown in FIGS. 8A and 8B , the semiconductor package 200 includes a semiconductor device 100, a substrate 210, and a sealing member 220. The substrate 210 is, for example, a printed circuit board (PCB). The semiconductor device 100 is disposed on the substrate 210 and is electrically connected to the substrate 210. The sealing member 220 seals the semiconductor device 100 on the substrate 210. More specifically, the sealing member 220 is, for example, a molded resin, and is disposed on the substrate 210 so as to cover the semiconductor device 100. A portion of the semiconductor package 200 that overlaps the marking area 12 in a plan view, for example, a portion of the sealing member 220 that overlaps the marking area 12 in a plan view, is formed of a material that does not block X-rays, infrared rays, terahertz waves, visible light, or other electromagnetic waves used to read markings made in the marking area 12.

[0031] 9 is a manufacturing process diagram of the semiconductor device 100. As shown in FIG. 9, the manufacturing method of the semiconductor device 100 includes a preparation step S1, an element isolation film formation step S2, a first ion implantation step S3, a gate insulating film formation step S4, a gate electrode formation step S5, a second ion implantation step S6, a sidewall spacer formation step S7, a third ion implantation step S8, a first interlayer insulating film formation step S9, a contact plug formation step S10, a first wiring formation step S11, a second interlayer insulating film formation step S12, a via plug formation step S13, a second wiring formation step S14, a protective film formation step S15, and a singulation step S16.

[0032] In the preparation step S1, a semiconductor substrate 10 is prepared. FIG. 10 is a cross-sectional view illustrating the element isolation film formation step S2. As shown in FIG. 10, in the element isolation film formation step S2, an element isolation film 13 is formed. In the element isolation film formation step S2, first, a hard mask is formed on the main surface 10a. The hard mask is formed, for example, by stacking a silicon oxide film and a silicon nitride film using a CVD (Chemical Vapor Deposition) method. Second, a resist pattern is formed on the hard mask. The resist pattern is formed by applying a photoresist and exposing and developing the applied photoresist. Third, the hard mask and the semiconductor substrate 10 are etched using the resist pattern as a mask, thereby forming a groove in the main surface 10a.

[0033] Fourth, the trenches are filled with the isolation film 13 by, for example, CVD. Fifth, the isolation film 13 that protrudes from the trenches is removed by CMP (Chemical Mechanical Polishing). After the isolation film 13 is filled in the trenches, the hard mask is removed.

[0034] Fig. 11 is a cross-sectional view illustrating the first ion implantation step S3. As shown in Fig. 11, in the first ion implantation step, ion implantation is performed to form a well region 11c. Fig. 12 is a cross-sectional view illustrating the gate insulating film formation step S4. As shown in Fig. 12, in the gate insulating film formation step S4, for example, the main surface 10a is thermally oxidized to form a gate insulating film 20 on the main surface 10a.

[0035] 13 is a cross-sectional view illustrating the gate electrode formation step S5. As shown in FIG. 13, in the gate electrode formation step S5, the gate electrode 30 is formed. In the gate electrode formation step S5, first, the gate electrode 30 is formed on the gate insulating film 20 using, for example, a CVD method. Second, a resist pattern is formed on the gate electrode 30. The resist pattern is formed by applying a photoresist and exposing and developing the applied resist pattern. Third, the gate electrode 30 is patterned by etching using the resist pattern as a mask.

[0036] 14 is a cross-sectional view illustrating the second ion implantation step S6. As shown in FIG. 14, in the second ion implantation step S6, ion implantation is performed to form the first region 11aa and the first region 11ba.

[0037] 15 is a cross-sectional view illustrating the sidewall spacer formation step S7. As shown in FIG. 15, in the sidewall spacer formation step S7, sidewall spacers 40 are formed. In the sidewall spacer formation step S7, first, the sidewall spacers 40 are formed on the main surface 10a by, for example, CVD so as to cover the element isolation film 13, the gate insulating film 20, and the gate electrode 30. Second, the sidewall spacers 40 are removed except for positions adjacent to the gate electrode 30 by, for example, etch-back.

[0038] FIG. 16 is a cross-sectional view illustrating the third ion implantation step S8. As shown in FIG. 16, in the third ion implantation step S8, ion implantation is performed to form second regions 11ab and 11bb. FIG. 17 is a cross-sectional view illustrating the first interlayer insulating film formation step S9. As shown in FIG. 17, in the first interlayer insulating film formation step S9, the lowermost interlayer insulating film 50 is formed. In the first interlayer insulating film formation step S9, first, the interlayer insulating film 50 is formed on the main surface 10a so as to cover the element isolation film 13, the gate electrode 30, and the sidewall spacers 40. Second, the upper surface of the interlayer insulating film 50 is planarized using, for example, a CMP method.

[0039] 18 is a cross-sectional view illustrating the contact plug forming step S10. As shown in FIG. 18, in the contact plug forming step S10, a contact plug 61 is formed. In the contact plug forming step S10, first, a resist pattern is formed on the lowermost interlayer insulating film 50. The resist pattern is formed by applying a photoresist and exposing and developing the applied resist pattern. Second, the lowermost interlayer insulating film 50 is etched using the resist pattern as a mask, thereby forming a contact hole.

[0040] Third, a metal film is formed on the second region 11ab, the second region 11bb, and the upper surface of the gate electrode 30 exposed from the contact hole, on the inner wall surface of the contact hole, and on the lowermost interlayer insulating film 50, and then heat treatment is performed. As a result, the metal film reacts with the second region 11ab, the second region 11bb, and the gate electrode 30, resulting in silicidation. After silicidation, the unreacted metal film is removed. Fourth, a contact plug 61 is embedded in the contact hole by, for example, CVD. Fifth, the contact plug 61 protruding from the contact hole is removed by, for example, CMP.

[0041] 19 is a cross-sectional view illustrating the first wiring formation step S11. As shown in FIG. 19, in the first wiring formation step S11, the lowermost wiring 60 is formed. In the first wiring formation step S11, first, the lowermost wiring 60 is formed on the lowermost interlayer insulating film 50 by, for example, sputtering. Second, a resist pattern is formed on the lowermost wiring 60. The resist pattern is formed by applying a photoresist and exposing and developing the applied resist pattern. Third, the lowermost wiring 60 is patterned by etching the lowermost wiring 60 using the resist pattern as a mask.

[0042] 20 is a cross-sectional view illustrating the second interlayer insulating film forming step S12. As shown in Fig. 20, in the second interlayer insulating film forming step S12, another interlayer insulating film 50 is formed on one interlayer insulating film 50 so as to cover the wiring 60 arranged on the one interlayer insulating film 50 by a method similar to that in the first interlayer insulating film forming step S9.

[0043] 21 is a cross-sectional view illustrating the via plug forming step S13. As shown in FIG. 21, in the via plug forming step S13, a via plug 62 is formed. In the via plug forming step S13, first, a resist pattern is formed on the interlayer insulating film 50 other than the bottom layer. The resist pattern is formed by applying a photoresist and then exposing and developing the applied resist pattern. Second, the interlayer insulating film 50 other than the bottom layer is etched using the resist pattern as a mask, thereby forming a via hole. Third, the via plug 62 is embedded in the via hole by, for example, CVD. Fourth, the via plug 62 protruding from the via hole is removed by, for example, CMP.

[0044] 22 is a cross-sectional view illustrating the second wiring forming step S14. As shown in FIG. 22, in the second wiring forming step S14, wirings 60 other than the bottom layer are formed on one interlayer insulating film 50 by the same method as in the first wiring forming step S11. The second interlayer insulating film forming step S12, the via plug forming step S13, and the second wiring forming step S14 are repeated until the top layer wiring 60 is formed.

[0045] 23 is a cross-sectional view illustrating the protective film forming step S15. As shown in FIG. 23 , in the protective film forming step S15, a protective film 70 is formed. In the protective film forming step S15, first, the protective film 70 is formed on the uppermost interlayer insulating film 50 so as to cover the uppermost wiring 60 using, for example, a CVD method. Second, a resist pattern is formed on the protective film 70. The resist pattern is formed by applying a photoresist and then exposing and developing the applied resist pattern. Third, the protective film 70 is etched using the resist pattern as a mask, thereby forming openings (not shown) in the protective film 70 that expose pads of the uppermost wiring 60.

[0046] In the singulation step S16, the semiconductor wafer formed as described above is cut along the boundary regions (scribe lanes) between adjacent semiconductor devices 100, thereby being singulated into a plurality of semiconductor devices 100.

[0047] 9 , the method for manufacturing the semiconductor device 100 further includes a marking step S17. The marking step S17 is performed, for example, after the preparation step S1 and before the element isolation film forming step S2. The marking step S17 may be performed between each step of the method for manufacturing the semiconductor device 100.

[0048] 24 is a cross-sectional view showing a first example of the marking step S17. As shown in Fig. 24, in the marking step S17, laser light L is irradiated so as to be focused and absorbed inside the semiconductor substrate 10. As a result, defects are partially introduced into the portion of the semiconductor substrate 10 near the focused point of the laser light L, and a modified portion 14 is formed.

[0049] 25 is a cross-sectional view showing a second example of the marking step S17. This figure shows an example in which the marking step S17 is performed between the steps of the manufacturing method of the semiconductor device 100. As shown in this example, the laser light L is irradiated so as to be collected and absorbed inside the semiconductor substrate 10, thereby forming a modified portion 14 inside the semiconductor substrate 10. However, in this example, the laser light L passes through the interlayer insulating film 50 (and the protective film 70) while avoiding the wiring 60, and is collected and absorbed inside the semiconductor substrate 10.

[0050] The position where the modified portion 14 is formed in the marking step S17 is determined based on the map data. The map data includes the lot number of the semiconductor wafer, the position of the semiconductor device 100 on the semiconductor wafer, and the results of inspections of the semiconductor device 100 performed during the manufacturing process. In addition, a wavelength of the laser light L that has a low absorption rate for the semiconductor substrate 10 and the interlayer insulating film 50 is selected, and the focal position of the laser light L is adjusted so that the laser light L is focused and absorbed inside the semiconductor substrate 10.

[0051] <Effects of the Semiconductor Device 100> The effects of the semiconductor device 100 will be described below.

[0052] When marking the semiconductor substrate 10 by irradiating the main surface 10a with laser light, the surface roughness of the main surface 10a deteriorates in the vicinity of the area irradiated with the laser light L. As a result, unevenness in the application of photoresist occurs in subsequent processes, which may cause the generation of particles that adversely affect the manufacturing process.

[0053] On the other hand, in the semiconductor device 100, marking on the semiconductor substrate 10 is performed by forming the modified portion 14 inside the semiconductor substrate 10. Therefore, in the semiconductor device 100, the surface roughness of the main surface 10a is less likely to deteriorate due to marking (more specifically, the arithmetic mean roughness of the portion of the main surface 10a that overlaps with the modified portion 14 in a plan view can be set to 1 nm or less), and the generation of particles that adversely affect the manufacturing process is suppressed.

[0054] Furthermore, when marking the semiconductor substrate 10 by irradiating the main surface 10a with laser light, marking on the semiconductor substrate 10 can only be performed when the semiconductor substrate 10 is inserted. On the other hand, in the semiconductor device 100, marking is performed by forming the modified portion 14 inside the semiconductor substrate 10, so marking can be performed not only when the semiconductor substrate 10 is inserted but also during the manufacturing process. As a result, in the semiconductor device 100, information such as the results of inspections performed during the manufacturing of the semiconductor device can also be marked on the semiconductor substrate 10.

[0055] The traceability of the semiconductor device 100 is ensured by marking the inspection results during the manufacturing process of the semiconductor device 100, the lot number of the semiconductor wafer from which the semiconductor device 100 was obtained, and the position of the semiconductor device 100 on the semiconductor wafer. Even when the semiconductor device 100 is packaged (assembled in the semiconductor package 200), the markings made on the semiconductor substrate 10 (the formation mode of the modified portion 14) can be read by irradiating the semiconductor device 100 with, for example, X-rays, infrared rays, terahertz waves, visible light, or other electromagnetic waves. Therefore, the traceability of the semiconductor package 200 can be ensured without removing the sealing member 220.

[0056] Second Embodiment A semiconductor device according to a second embodiment will be described. The semiconductor device according to the second embodiment is designated as semiconductor device 100A. Here, differences from semiconductor device 100 will be mainly described, and overlapping descriptions will not be repeated.

[0057] Figure 26 is an enlarged plan view showing a first example of a formation mode of the modified regions 14 in the semiconductor device 100A. Figure 27 is a schematic cross-sectional view taken along line XXVII-XXVII in Figure 26. As shown in Figures 26 and 27, in the semiconductor device 100A, a plurality of modified regions 14 may be arranged three-dimensionally. More specifically, the plurality of modified regions 14 includes a plurality of modified regions 14a, a plurality of modified regions 14b, and a plurality of modified regions 14c.

[0058] The modified regions 14a are formed in a first plane, the modified regions 14b are formed in a second plane, and the modified regions 14c are formed in a third plane. The first, second, and third planes are, for example, planes parallel to the main surface 10a. The first plane is located closer to the main surface 10a than the second and third planes. The second plane is located closer to the main surface 10a than the third plane.

[0059] Each of the multiple modified regions 14a is arranged so as not to overlap with either the multiple modified regions 14b or the multiple modified regions 14c in a planar view. Each of the multiple modified regions 14b is arranged so as not to overlap with either the multiple modified regions 14a or the multiple modified regions 14c in a planar view. Each of the multiple modified regions 14c is arranged so as not to overlap with either the multiple modified regions 14a or the multiple modified regions 14b in a planar view.

[0060] In the semiconductor device 100, when reading markings made on the semiconductor substrate 10, by changing the depth of the observation focus, it is possible to distinguish and read each of the modified regions 14a, 14b, and 14c. For example, when the observation focus is set to a shallow first position, it is possible to read the modified region 14a, but it is not possible to read the modified regions 14b and 14c. When the observation focus is set to a third position deeper than the first position, it is possible to read the modified region 14c, but it is not possible to read the modified regions 14a and 14b. When the observation focus is set to a second position intermediate between the first and third positions, it is possible to read the modified region 14b, but it is not possible to read the modified regions 14a and 14c. In this way, by changing the observation focus when reading the markings, it is possible to distinguish and read the modified region 14 formed in one surface from the modified region 14 formed in another surface.

[0061] 28 is an enlarged plan view showing a second example of the formation mode of the modified portion 14 in the semiconductor device 100A. As shown in FIG. 28 , the modified portion 14a may partially overlap the modified portion 14b or the modified portion 14c in a plan view. The modified portion 14b may partially overlap the modified portion 14c in a plan view. In this case, when reading the marking, by detecting the positional deviation between the modified portion 14a and the modified portion 14b (the positional deviation between the modified portion 14a and the modified portion 14c, or the positional deviation between the modified portion 14b and the modified portion 14c), it is possible to distinguish and read the modified portion 14 formed in one surface from the modified portion 14 formed in another surface.

[0062] FIG. 29 is an enlarged plan view showing a third example of the formation of the modified regions 14 in the semiconductor device 100A. FIG. 30 is a schematic cross-sectional view taken along the line XXX-XXX in FIG. 29. As shown in FIGS. 29 and 30, the modified regions 14a may overlap with the modified regions 14b or 14c in a plan view. The modified regions 14b may overlap with the modified regions 14c in a plan view. In this case, images obtained by irradiating the semiconductor device 100A with X-rays or other electromagnetic waves while rotating the semiconductor device 100A are synthesized to obtain three-dimensional arrangement information of the modified regions 14. Based on such three-dimensional arrangement information of the modified regions 14, it is possible to read information related to the manufacturing process of the semiconductor device 100A.

[0063] Third Embodiment A semiconductor package according to a third embodiment will be described below. The semiconductor package according to the third embodiment is designated as a semiconductor package 200A.

[0064] Fig. 31 is a plan view showing a first example of a semiconductor package 200A. Fig. 32 is a schematic cross-sectional view taken along line XXXII-XXXII in Fig. 31. As shown in Figs. 31 and 32, in the semiconductor package 200A, the semiconductor device 100 is mounted on a substrate 210. In the semiconductor package 200A, a bonding pad 80 formed on the top surface of the semiconductor device 100 is connected to a conductor pattern 211 formed on the top surface of the substrate 210 by a bonding wire 230.

[0065] The bonding pad 80 is arranged so as not to overlap the marking area 12 in a planar view. The bonding wire 230 is arranged so as not to cross the marking area 12 in a planar view. The conductor pattern 211 is formed so as not to overlap the marking area 12 in a planar view. In this way, in the semiconductor package 200A, a structure formed above or below the semiconductor substrate 10 using a material that blocks electromagnetic waves used to read the marking made in the marking area 12, such as a metal material, does not overlap the marking area 12 in a planar view. Therefore, with the semiconductor package 200A, it is possible to more reliably read information related to the manufacturing process of the semiconductor device 100.

[0066] FIG. 33 is a plan view showing a second example of the semiconductor package 200A. FIG. 34 is a schematic cross-sectional view taken along line XXXIV-XXXIV in FIG. 33. FIG. 35 is a plan view showing a third example of the semiconductor package 200A. FIG. 36 is a schematic cross-sectional view taken along line XXXVI-XXXVI in FIG. 35. As shown in FIGS. 33 to 36, in the semiconductor package 200A, the semiconductor device 100 does not have to be an LSI (Large Scale Integrated circuit). As shown in FIGS. 33 and 34, the semiconductor device 100 may be a discrete semiconductor such as an LED (Light Emitting Diode), or as shown in FIGS. 35 and 36, the semiconductor device 100 may be a power semiconductor element such as a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). The power semiconductor element is not limited to a switching element, but may also be a rectifying element such as an SBD (Schottky Barrier Diode) or an FRD (Fast Recovery Diode). Even in these cases, structures formed above or below the semiconductor substrate 10 using materials that block electromagnetic waves used to read the markings made in the marking area 12 (mainly wiring materials such as lead frames, clips, and bonding wires made of metal materials such as aluminum and copper, and joining materials such as solder used to join semiconductor elements to the wiring materials) do not overlap the marking area 12 in a planar view. For example, a vertical power semiconductor element typically has a substrate with a high impurity concentration and an epitaxial layer with a low impurity concentration formed on the substrate by epitaxial growth, with element structures such as a MOSFET or an SBD formed in the epitaxial layer. In this case, the modified portion 14 constituting the marking may be formed in the epitaxial layer with a low impurity concentration or in the substrate with a high impurity concentration.

[0067] The above-described wiring material and bonding material need only be configured so as not to overlap the marking area 12 above or below the semiconductor substrate 10. For example, when electromagnetic waves used to read the marking are irradiated from above, there need not be any wiring material or bonding material above the marking area 12, and the wiring material or bonding material may overlap below the marking area 12. While FIGS. 33 to 36 show examples in which the wiring material or bonding material does not overlap the marking area 12 above and below the marking area 12, i.e., gaps 12b are provided in the wiring material or bonding material, gaps 12b may not be provided in the underlying wiring material or bonding material. The wiring material referred to here includes electrode materials provided on the back surface of a semiconductor element, lead frames on which semiconductor elements are mounted (see FIG. 34), and substrates on which semiconductor elements are mounted (insulating substrates with conductive wiring formed on both sides, as shown in FIG. 36). In this case, the marking may be read using reflected light rather than transmitted light, since the wiring material or bonding material below the marking area 12 overlaps with the marking area 12. The presence or absence of wiring material or bonding material overlapping with the marking area 12 is selected appropriately depending on the wavelength of the electromagnetic wave used for reading, the material of the semiconductor element (silicon, silicon carbide, gallium nitride, or other material), and the material, thickness, and shape of the wiring material or bonding material.

[0068] Fourth Embodiment A semiconductor device according to a fourth embodiment will be described below. The semiconductor device according to the fourth embodiment is designated as a semiconductor device 100B.

[0069] 37 is a cross-sectional view of the semiconductor device 100B. As shown in FIG. 37, the semiconductor substrate 10 has an impurity diffusion region 11d. The impurity diffusion region 11d is formed, for example, in the main surface 10a located in the device region 11. Both ends of the impurity diffusion region 11d form a diffusion resistor. The impurity diffusion region 11d is surrounded by an element isolation film 13 in a plan view. The impurity diffusion region 11d is electrically connected to an interconnect 60 by a contact plug 61. However, the interconnect 60 is arranged so as not to overlap the impurity diffusion region 11d in a plan view, except for both ends of the impurity diffusion region 11d.

[0070] In the semiconductor device 100B, the modified portion 14 does not indicate information related to the manufacturing process of the semiconductor device 100B and is not formed in the marking region 12. In the semiconductor device 100B, the modified portion 14 is formed so as to partially overlap the impurity diffusion region 11d. The impurity diffusion region 11d is formed by ion implantation in the first ion implantation step S3, the second ion implantation step S6, or the third ion implantation step S8. The modified portion 14 is formed, for example, by focusing and absorbing laser light L into the impurity diffusion region 11d through the protective film 70 and the interlayer insulating film 50 after the structure of the semiconductor device 100 other than the modified portion 14 has been formed.

[0071] Before forming the modified portion 14, the electrical resistance value of the diffused resistor (impurity diffusion region 10d) is measured. If the electrical resistance value of the diffused resistor deviates from the desired value, the modified portion 14 is formed to adjust the electrical resistance value of the diffused resistor. After forming the modified portion 14, the electrical resistance value of the diffused resistor is measured again. If the measured electrical resistance value is within the desired range, the formation of the modified portion 14 is terminated. On the other hand, if the measured electrical resistance value of the diffused resistor is not within the desired range, the formation of the modified portion 14 is continued. As described above, according to the semiconductor device 100B, trimming of the diffused resistor is possible by forming the modified portion 14 while measuring the electrical resistance value of the diffused resistor. Note that in the semiconductor device 100B, adjustment and trimming of the source region 11a and the drain region 11b may be performed by forming the modified portion 14. Note that, although the impurity diffusion region in the semiconductor substrate 10 is cited as an example of the target of trimming in this embodiment, the target of trimming is not limited thereto. For example, the target of trimming may be polysilicon and the electrical resistance value of the polysilicon may be adjusted, or the target of trimming may be a metal material and the electrical resistance value of the metal material may be adjusted.

[0072] (Additional Notes) The embodiments of the present disclosure include the following aspects.

[0073] <Supplementary Note 1> A semiconductor device comprising: a semiconductor substrate; a modified portion formed inside the semiconductor substrate; and the modified portion indicating information relating to a manufacturing process of the semiconductor device.

[0074] <Supplementary Note 2> The semiconductor device according to Supplementary Note 1, wherein the semiconductor substrate has a marking region in a planar view, the marking region has a plurality of regions arranged in a matrix in a planar view, and the information is indicated by whether or not the modified portion is formed in each of the plurality of regions.

[0075] <Supplementary Note 3> The semiconductor device according to Supplementary Note 1, wherein the modified portion extends along a first direction in a planar view, and the information is indicated by a distance between two of the modified portions that are aligned along a second direction perpendicular to the first direction in a planar view.

[0076] <Appendix 4> The semiconductor device according to Appendix 1, wherein the modified region includes a first modified region, a second modified region, and a third modified region, and the first modified region, the second modified region, and the third modified region are formed at different positions in the thickness direction of the semiconductor substrate and are arranged so as not to overlap each other in a planar view.

[0077] <Appendix 5> The semiconductor device according to Appendix 1, wherein the modified region includes a first modified region, a second modified region, and a third modified region, and the first modified region, the second modified region, and the third modified region are formed at different positions in the thickness direction of the semiconductor substrate and are arranged so as to partially overlap each other in a planar view.

[0078] <Appendix 6> The semiconductor device according to Appendix 1, wherein the modified region includes a first modified region, a second modified region, and a third modified region, and the first modified region, the second modified region, and the third modified region are formed at different positions in a thickness direction of the semiconductor substrate and are arranged so as to overlap in a planar view.

[0079] <Supplementary Note 7> The semiconductor device according to Supplementary Note 1, wherein the modified portion is formed to show a letter or a number corresponding to the information in a plan view.

[0080] <Supplementary Note 8> The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 7, further comprising a wiring that is arranged on the semiconductor substrate so as not to overlap the modified portion in a plan view.

[0081] <Supplementary Note 9> The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 8, wherein the semiconductor substrate has a main surface, and a portion of the main surface that overlaps with the modified portion in a plan view has an arithmetic mean roughness of 1 nm or less.

[0082] <Supplementary Note 10> The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 9, wherein the information indicates at least one of an inspection result during the manufacturing of the semiconductor device, a lot number of a wafer from which the semiconductor device was obtained, a position of the semiconductor device on the wafer, a code of a company that manufactured the semiconductor device, a code of the semiconductor device, and an ID indicating a manufacturing device used in the manufacturing process.

[0083] <Supplementary Note 11> The semiconductor device according to Supplementary Note 1, wherein the information is different for each of the semiconductor devices.

[0084] <Supplementary Note 12> A semiconductor package comprising: the semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 11; and a sealing member that seals the semiconductor device.

[0085] <Supplementary Note 13> The semiconductor package according to Supplementary Note 12, wherein a portion overlapping the modified portion in a planar view is formed of a material that does not block at least any of X-rays, infrared light, visible light, and terahertz waves.

[0086] <Appendix 14> A method for manufacturing a semiconductor device, comprising: a step of preparing a semiconductor substrate; and a step of forming a modified portion inside the semiconductor substrate by focusing and absorbing laser light inside the semiconductor substrate, wherein the modified portion indicates information related to the manufacturing process of the semiconductor device.

[0087] <Supplementary Note 15> The method for manufacturing a semiconductor device according to Supplementary Note 14, further comprising: forming an insulating film on the semiconductor substrate; and forming wiring on the insulating film, wherein the laser light passes through the insulating film to avoid the wiring, and is collected and absorbed inside the semiconductor substrate.

[0088] <Supplementary Note 16> A semiconductor device comprising: a semiconductor substrate, the semiconductor substrate having a main surface, an impurity diffusion region formed on the main surface, and a modified portion formed so as to partially overlap the impurity diffusion region.

[0089] Although the embodiments of the present disclosure have been described above, the above-described embodiments can be modified in various ways. Furthermore, the scope of the present invention is not limited to the above-described embodiments. The scope of the present invention is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0090] 100 semiconductor device, 100A semiconductor device, 100B semiconductor device, 200 semiconductor package, 200A semiconductor package, 10 semiconductor substrate, 10a main surface, 10b main surface, 11 device region, 11a source region, 11aa first region, 11ab second region, 11b drain region, 11ba first region, 11bb second region, 11c well region, 11d impurity diffusion region, 12 marking region, 12a region, 12b gap portion, 13 element isolation film, 14 modified portion, 14a, 14b, 14c modified portion, 20 gate insulating film, 30 gate electrode, 40 sidewall spacer, 50 interlayer insulating film, 60 wiring, 61 contact plug, 62 via plug, 70 protective film, 210 substrate, 220 sealing member, L laser light, S1 preparation step, S2 S10: contact plug formation step, S11: first wiring formation step, S12: second interlayer insulating film formation step, S13: via plug formation step, S14: second wiring formation step, S15: protective film formation step, S16: singulation step, S17: marking step, DR1: first direction, DR2: second direction.

Claims

1. A semiconductor device comprising: a semiconductor substrate; a modified portion formed inside the semiconductor substrate; and the modified portion indicating information relating to a manufacturing process of the semiconductor device.

2. The semiconductor device according to claim 1, wherein the semiconductor substrate has a marking region in a planar view, the marking region has a plurality of regions arranged in a matrix in a planar view, and the information is indicated by whether or not the modified portion is formed in each of the plurality of regions.

3. The semiconductor device according to claim 1, wherein the modified portion extends along a first direction in a planar view, and the information is indicated by the distance between two of the modified portions that are aligned along a second direction perpendicular to the first direction in a planar view.

4. The semiconductor device described in claim 1, wherein the modified area includes a first modified area, a second modified area, and a third modified area, and the first modified area, the second modified area, and the third modified area are formed at different positions in the thickness direction of the semiconductor substrate and are arranged so as not to overlap each other in a planar view.

5. The semiconductor device described in claim 1, wherein the modified area includes a first modified area, a second modified area, and a third modified area, and the first modified area, the second modified area, and the third modified area are formed at different positions in the thickness direction of the semiconductor substrate and are arranged so as to partially overlap each other in a planar view.

6. The semiconductor device according to claim 1, wherein the modified area includes a first modified area, a second modified area, and a third modified area, and the first modified area, the second modified area, and the third modified area are formed at different positions in the thickness direction of the semiconductor substrate and are arranged so as to overlap in a planar view.

7. The semiconductor device according to claim 1, wherein the modified portion is formed so as to show, in a plan view, a letter or a number corresponding to the information.

8. The semiconductor device according to claim 1, further comprising wiring arranged on the semiconductor substrate so as not to overlap the modified portion in a plan view.

9. The semiconductor device according to any one of claims 1 to 8, wherein the semiconductor substrate has a main surface, and a portion of the main surface that overlaps with the modified portion in a plan view has an arithmetic mean roughness of 1 nm or less.

10. A semiconductor device as claimed in any one of claims 1 to 9, wherein the information indicates at least any of the following: inspection results during the manufacture of the semiconductor device, the lot number of the wafer from which the semiconductor device was obtained, the position of the semiconductor device on the wafer, a code of the company that manufactured the semiconductor device, a code of the semiconductor device, and an ID indicating a manufacturing device used in the manufacturing process.

11. The semiconductor device according to claim 1, wherein the information is different for each of the semiconductor devices.

12. A semiconductor package comprising: the semiconductor device according to any one of claims 1 to 11; and a sealing member for sealing the semiconductor device.

13. The semiconductor package according to claim 12, wherein a portion overlapping the modified portion in a planar view is formed from a material that does not impede at least any of X-rays, infrared light, visible light, and terahertz waves.

14. A method for manufacturing a semiconductor device, comprising: a step of preparing a semiconductor substrate; and a step of forming a modified portion within the semiconductor substrate by focusing and absorbing laser light within the semiconductor substrate, wherein the modified portion indicates information relating to the manufacturing process of the semiconductor device.

15. The method for manufacturing a semiconductor device according to claim 14, further comprising the steps of: forming an insulating film on the semiconductor substrate; and forming wiring on the insulating film, wherein the laser light passes through the insulating film to avoid the wiring and is concentrated and absorbed inside the semiconductor substrate.

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