Circuit board and semiconductor package comprising same

Abstract

A circuit board according to an embodiment includes: a core layer; a first build-up layer arranged on the top surface of the core layer; and a second build-up layer arranged on the bottom surface of the core layer. The core layer includes a first via electrode having a first width in the horizontal direction and a second via electrode having a second width different from the first width in the horizontal direction. The side surface of the second via electrode includes a first portion having a curvature and a second portion having an inclination connected to the first portion.

Description

Circuit boards and semiconductor packages including the same

[0001] The embodiment relates to a circuit board and a semiconductor package including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on a limited-size semiconductor package substrate. However, conventional semiconductor packages typically consist of a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that utilize multiple substrates to arrange multiple semiconductor devices have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected to each other horizontally and / or vertically on the substrate. Accordingly, these semiconductor packages offer the advantages of efficiently utilizing the mounting area of ​​the semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between the semiconductor devices.

[0004] Furthermore, semiconductor packages used in products supporting the Internet of Things (IoT), autonomous vehicles, and high-performance servers are seeing increased integration, with the number of semiconductor devices and / or the size of each individual device increasing. Consequently, the area of ​​the circuit boards on which these devices are mounted is also increasing.

[0005] The circuit board described above has the problem of warping in a specific direction more significantly as its surface area increases. Therefore, the circuit board may include a core layer to improve rigidity. However, while increasing the vertical thickness of the circuit board can further improve the rigidity of the circuit board, this also increases the thickness of the semiconductor package and the length of the signal transmission line connected to the semiconductor device. Accordingly, the vertical thickness of the core layer of the circuit board described above is trending toward decreasing.

[0006] In addition, as the number of multiple semiconductor elements and / or semiconductor chiplets increases, heat generation becomes more severe, and accordingly, there is a problem that heat dissipation characteristics must be further improved. To this end, a heat dissipation via electrode for heat dissipation function may be provided in the core layer of the circuit board. The heat dissipation characteristics of the circuit board can be further improved as the area of ​​the heat dissipation via electrode increases. At this time, the vertical thickness of the core layer is decreasing, and accordingly, the horizontal width of the heat dissipation via electrode provided in the core layer is increasing to improve the heat dissipation characteristics. However, if the horizontal width of the heat dissipation via electrode exceeds a certain level compared to the vertical thickness of the heat dissipation via electrode, the flatness of the surface (upper surface and / or lower surface) of the heat dissipation via electrode may be deteriorated.

[0007] Furthermore, the core layer is provided with not only a heat-dissipating via electrode for heat dissipation, but also a signal via electrode for signal transmission. At this time, as the width of the signal via electrode increases in the horizontal direction, signal transmission loss may increase, and accordingly, the horizontal width of the signal via electrode may be provided to be smaller than the horizontal width of the heat-dissipating via electrode. The above-described via electrodes may be formed by filling a first via hole of the signal via electrode having a relatively small horizontal width, and a second via hole of the heat-dissipating via electrode having a relatively large horizontal width, with a metal material. However, when filling the first and second via holes with a metal material, the first via hole having a relatively small width may be filled before the second via hole. Accordingly, when the filling process is performed based on the first via hole, a problem may occur in which the second via hole is not completely filled.

[0008] Therefore, there is a need for a method that can improve the filling characteristics of multiple via holes having different widths provided in a core layer of a circuit board while improving the heat dissipation characteristics of the circuit board.

[0009] The embodiment provides a circuit board with significantly improved heat dissipation characteristics and a semiconductor package including the same.

[0010] Additionally, the embodiment provides a circuit board and a semiconductor package including the same capable of improving the flatness of via electrodes having different horizontal widths.

[0011] The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

[0012] A circuit board according to an embodiment includes a core layer; a first build-up layer disposed on an upper surface of the core layer; and a second build-up layer disposed on a lower surface of the core layer, wherein the core layer includes a first via electrode having a first width along a horizontal direction and a second via electrode having a second width different from the first width along the horizontal direction, and a side surface of the second via electrode includes a first portion having a curvature and a second portion having a slope connected to the first portion.

[0013] Additionally, the ratio of the horizontal width of each of the first and second via electrodes to the vertical length is at least 1.6 times.

[0014] Additionally, the horizontal width of each of the first and second via electrodes is less than three times the vertical length.

[0015] Additionally, the vertical lengths of each of the first and second via electrodes are equal to each other.

[0016] Additionally, the first build-up layer includes a first circuit layer disposed on an upper surface of the core layer, the first circuit layer including a first pad overlapping the first via electrode in a vertical direction; and a second pad overlapping the second via electrode in a vertical direction.

[0017] Additionally, the horizontal width of the first pad is smaller than the horizontal width of the second pad.

[0018] Additionally, the first pad includes a plurality of individual pads electrically connected to each of the plurality of first via electrodes and spaced apart from each other along the horizontal direction, and the second pad includes at least one integrated pad electrically connected in common with the plurality of second via electrodes.

[0019] Additionally, the vertical length has a range of 25 μm to 60 μm.

[0020] Additionally, the side surface of the first via electrode includes a third portion having a curvature and a fourth portion having a slope connected to the third portion, and a vertical length of the third portion of the first via electrode is different from a vertical length of the first portion of the second via electrode.

[0021] Additionally, the vertical length of the third portion of the first via electrode is smaller than the vertical length of the first portion of the second via electrode.

[0022] Additionally, the core layer includes a core insulating layer in which a reinforcing member is embedded, and the first portion of the first via electrode and the third portion of the via electrode overlap with the reinforcing member along the horizontal direction.

[0023] Additionally, the circuit board further includes a connecting member embedded in at least one of the core layer and the first build-up layer.

[0024] Additionally, the connecting member overlaps the second via electrode along at least one of the vertical and horizontal directions.

[0025] Meanwhile, a circuit board according to an embodiment includes a core layer; a first build-up layer disposed on an upper surface of the core layer; and a second build-up layer disposed on a lower surface of the core layer, wherein the core layer includes a first via electrode having a first width in a horizontal direction and a second via electrode having a second width different from the first width in the horizontal direction, and a horizontal width of each of the first and second via electrodes has a range of 1.6 times or more to 3 times or less of a vertical length.

[0026] Additionally, the ratio of the horizontal width and the vertical length of the first via electrode is smaller than the ratio of the horizontal width and the vertical length of the second via electrode.

[0027] Additionally, the side surface of the second via electrode includes a first portion having a curvature and a second portion having a slope connected to the first portion, and the side surface of the first via electrode includes a third portion having a curvature and a fourth portion having a slope connected to the third portion.

[0028] Additionally, the vertical length of the third portion of the first via electrode is different from the vertical length of the first portion of the second via electrode.

[0029] Meanwhile, a semiconductor package according to an embodiment includes a core layer; a first build-up layer disposed on an upper surface of the core layer; a second build-up layer disposed on a lower surface of the core layer; and a semiconductor element disposed on the first build-up layer, wherein the core layer includes a first via electrode having a first width along a horizontal direction and a second via electrode having a second width different from the first width along the horizontal direction, and a side surface of the second via electrode includes a first portion having a curvature and a second portion having a slope connected to the first portion.

[0030] Additionally, the semiconductor package further includes a connecting member embedded in at least one of the core layer and the first build-up layer, and the semiconductor element overlaps at least a portion of the connecting member along a vertical direction.

[0031] Additionally, the horizontal width of each of the first and second via electrodes is 1.6 times or more and 3 times or less in ratio to the vertical length.

[0032] The circuit board of the embodiment can densely fill a plurality of via holes having different horizontal widths provided in a core insulating layer with a metal material, thereby providing a core via electrode having excellent mechanical reliability and / or electrical reliability.

[0033] Specifically, the circuit board of the embodiment includes a core layer, a first build-up layer disposed on an upper surface of the core layer, and a second build-up layer disposed on a lower surface of the core layer, the core layer includes a first via electrode having a first width along a horizontal direction, and a second via electrode having a second width different from the first width along a horizontal direction, and a side surface of the second via electrode may include a first portion having a curvature and a second portion having a slope connected to the first portion.

[0034] Through this, in the process of filling a second via hole corresponding to a second via electrode with a conductive material, the embodiment can prevent rapid filling of the metal material on the inner wall of the second via hole, improve the filling property of the metal material on the inner side of the second via hole, and thereby enable the metal material to be densely filled in the second via hole.

[0035] Furthermore, the side surface of the first via electrode may include a third portion having a curvature and a fourth portion having a slope connected to the third portion. Through this, the embodiment may enable the first via electrode and the second via electrode to have vertical cross-sectional shapes corresponding to each other, and may solve a problem of warping of the circuit board that may occur due to different vertical cross-sectional shapes of the first and second via electrodes.

[0036] In addition, the vertical length of the third portion of the first via electrode may be different from the vertical length of the first portion of the second via electrode. Preferably, the vertical length of the third portion of the first via electrode may be greater than the vertical length of the first portion of the second via electrode. That is, the embodiment allows the vertical length of the third portion of the first via electrode having a relatively small width in the horizontal direction to be greater than the vertical length of the first portion of the second via electrode having a relatively large width in the horizontal direction, thereby allowing the times required for each of the first via hole and the second via hole having different widths in the horizontal direction to be completely filled with a metal material to be similarly matched, thereby improving the flatness of the first via electrode and the second via electrode while preventing the formation of dimples or voids.

[0037] In addition, the horizontal width of each of the first and second via electrodes is set to be at least 1.6 times the vertical length. If the horizontal width of the first via electrode is less than 1.6 times the vertical length of the first via electrode, the difference in process conditions in the process of filling the first via hole and the second via hole with a metal material may become large, and as a result, the first via hole may be excessively filled with the metal material, or the second via hole may not be densely filled with the metal material. Therefore, in the embodiment, the horizontal width of each of the first and second via electrodes is set to be at least 1.6 times the vertical length so as to improve the metal material filling processability according to the thickness of the core insulating layer while the signal transmission loss does not exceed a certain level. In addition, the horizontal width of each of the first and second via electrodes may be set to be at most 3 times the vertical length. Through this, the filling speeds of the first and second via holes having different widths in the horizontal direction can be maintained similarly, so that each of the first and second via holes can be densely filled with a metal material, and further, dimples and / or voids can be prevented from being formed in the first via electrode and the second via electrode.

[0038] Figure 1 is a cross-sectional view illustrating a circuit board according to the first embodiment.

[0039] Figure 2 is an electron microscope photograph showing a via electrode according to the prior art.

[0040] FIG. 3 is an enlarged view of the core layer of FIG. 1 according to one embodiment.

[0041] FIG. 4 is an enlarged view of the core layer of FIG. 1 according to another embodiment.

[0042] Figure 5 is a drawing illustrating a circuit board according to the second embodiment.

[0043] Figure 6 is a drawing illustrating a circuit board according to the third embodiment.

[0044] Figure 7 is a drawing illustrating a circuit board according to the fourth embodiment.

[0045] Figure 8 is a drawing illustrating a circuit board according to the fifth embodiment.

[0046] FIG. 9 is a drawing illustrating a semiconductor package according to an embodiment.

[0047] Figures 10 to 14 are drawings showing the process sequence for manufacturing the core layer of the circuit board illustrated in Figure 1.

[0048] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0049] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0050] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described, and commonly used terms, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0051] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0052] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0053] Additionally, when described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when expressed as "above" or "below", it may include the meaning of the downward direction as well as the upward direction based on one component.

[0054] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0055] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0056]

[0057] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing symbols, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0058]

[0059] Before describing the embodiment, an electronic device (not shown) to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the electronic device is not limited thereto, and it goes without saying that the electronic device may be any other electronic device that processes data.

[0060] An electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to a semiconductor package of the embodiment. Furthermore, the semiconductor package includes a circuit board, a semiconductor chip, a bonding portion for electrically connecting the semiconductor element and the circuit board, a resin portion for filling the space between the semiconductor element and the circuit board, and a molding portion for entirely enclosing the semiconductor element.

[0061] Semiconductor devices may include active and / or passive components and may have various functions. Active devices may be in the form of integrated circuits (ICs) in which hundreds to millions of transistors are integrated into a single semiconductor device, and may be, for example, logic chips, memory chips, etc. For example, the logic chip may be an application processor (AP) device including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a set of devices including a specific combination of the above. The memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0062] The semiconductor package of the embodiment may be any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package), but is not limited thereto.

[0063]

[0064] FIG. 1 is a cross-sectional view illustrating a circuit board according to a first embodiment, FIG. 2 is an electron microscope photograph showing a via electrode according to the prior art, FIG. 3 is an enlarged view of a core layer of FIG. 1 according to one embodiment, FIG. 4 is an enlarged view of a core layer of FIG. 1 according to another embodiment, FIG. 5 is a view illustrating a circuit board according to a second embodiment, FIG. 6 is a view illustrating a circuit board according to a third embodiment, FIG. 7 is a view illustrating a circuit board according to a fourth embodiment, FIG. 8 is a view illustrating a circuit board according to a fifth embodiment, and FIG. 9 is a view illustrating a semiconductor package according to an embodiment.

[0065]

[0066] Hereinafter, a circuit board and a semiconductor package including the same according to an embodiment will be specifically described with reference to FIGS. 1 to 9.

[0067] Referring to FIG. 1, the circuit board (100) includes a core layer (101), a first build-up layer (102) disposed on one surface of the core layer (101), and a second build-up layer (103) disposed on the other surface of the core layer (101). Here, the meaning of being disposed on one surface and the other surface should not be understood only as a configuration in direct contact with the one surface and the other surface, but should also be understood as having another configuration between the one surface and the first build-up layer (102), and between the other surface and the second build-up layer (103).

[0068] The core layer (101) may include a core insulating layer (120) and a core via electrode (121) penetrating the core insulating layer (120). The core insulating layer (120) is composed of a resin such as epoxy resin or BT (bismaleimide triazine) and a reinforcing member such as glass fiber, and has the function of improving the rigidity of the circuit board (100).

[0069] As the number of terminals of semiconductor devices arranged on a recent circuit board (100) increases, wiring becomes more complex, and accordingly, the number of layers and / or thickness of the first and second build-up layers (102, 103) tends to increase. Accordingly, the core layer (101) of the present embodiment includes a core insulating layer (120) having a reinforcing member such as glass fiber to improve the overall rigidity of the circuit board (100). In addition, the core insulating layer (120) may have a thickness in the range of 25 μm to 60 μm in the vertical direction to prevent excessive signal loss while improving the rigidity. When the thickness of the core insulation layer (120) in the vertical direction is less than 25 ㎛, the effect of improving the rigidity by the core insulation layer (120) may be insufficient, and mechanical reliability and / or electrical reliability problems may occur as the reinforcing member provided in the core insulation layer (120) comes into contact with the first build-up layer (102) and / or the second build-up layer (103).

[0070] A via hole penetrating one surface and the other surface may be formed in the core insulating layer (120). This may be formed using a CO2 laser or the like in the core layer (101). At this time, the via hole may be formed by a CO2 laser irradiated from one side of the core insulating layer (120). For example, the via hole provided in the core insulating layer (120) may be formed by penetrating the core insulating layer (120) using a CO2 laser irradiated to the upper surface of the core insulating layer (120). Accordingly, the width of the via hole provided in the core insulating layer (120) in the horizontal direction may be provided such that the width decreases or increases along the vertical direction. For example, the via hole provided in the core insulating layer (120) according to the prior art may be formed using a CO2 laser irradiated to the upper and lower surfaces of the core insulating layer (120), respectively, and may thus have an hourglass shape. In this case, it may be difficult for the horizontal central axis of the laser beam irradiated to the upper surface of the core insulating layer (120) and the horizontal central axis of the laser beam irradiated to the lower surface of the core insulating layer (120) to be precisely aligned along the vertical direction. Accordingly, in the conventional technology, it may be difficult to completely fill the via hole provided in the core insulating layer (120), and thus, multiple filling processes and / or polishing processes were performed to form the core via electrode. In contrast, the embodiment forms a via hole penetrating the core insulating layer (120) using a CO2 laser irradiated to one side of the core insulating layer (120), thereby improving the processability in the process of filling the via hole with a metal material, thereby significantly improving the product yield. Furthermore, the embodiment can improve the flatness of the upper and / or lower surfaces of the core via electrode (121), thereby improving the positional alignment of the first build-up layer (102) and / or the second build-up layer (103) disposed on the upper and / or lower surfaces thereof, and can significantly improve the mechanical reliability and / or physical reliability by improving the flatness.

[0071] A core via electrode (121) may be arranged within the via hole of the core insulating layer (120). The core via electrode (120) functions to electrically connect the first build-up layer (102) and the second build-up layer (103). Therefore, it is preferable that the core via electrode (121) densely fill the via hole for the purpose of resistance or heat dissipation. As described above, as the area of ​​the circuit board increases, the area of ​​the core via electrode (121) provided in the core insulating layer (120) may increase, and thus it may be difficult for the core via electrode (121) to densely fill the via hole. Furthermore, the core via electrode (121) provided in the core insulating layer (120) may include a first via electrode (121-1) having a first width in the horizontal direction and a second via electrode (121-2) having a second width different from the first width described above in the horizontal direction. At this time, the width of each of the first via electrode (121-1) and the second via electrode (121-2) may vary in the horizontal direction along the vertical direction. Accordingly, the width of the first via electrode (121-1) and the second via electrode (121-2) described below may mean the width in the horizontal direction in the area having the largest width among the entire areas in the vertical direction of each of the first via electrode (121-1) and the second via electrode (121-2). For example, the first width of the first via electrode (121-1) may mean the width on the top surface of the first via electrode (121), and the second width of the second via electrode (121-2) may mean the width on the top surface of the second via electrode (121-2).

[0072] The first via electrode (121-1) may be a via electrode performing a first function, and the second via electrode (121-2) may be a via electrode performing a second function different from the first function. For this purpose, the first via electrode (121-1) and the second via electrode (121-2) may be required to have different widths in the horizontal direction. For example, the first via electrode (121-1) may have a function of transmitting an electric signal between a semiconductor element and / or a main board, and may be required to have a relatively small width in the horizontal direction in order to prevent excessive signal transmission loss. In addition, the second via electrode (121-2) may have a heat dissipation function of transmitting heat generated in the semiconductor element, and thus may be required to have a relatively large width in the horizontal direction.

[0073] The first via electrode (121-1) and the second via electrode (121-2) have different widths in the horizontal direction, and thus, the processability may be reduced in the process of filling the first via hole corresponding to the first via electrode (121-1) and the second via hole corresponding to the second via electrode (121-2) with a conductive material. For example, when the first via hole and the second via hole are filled with a metal material, the first via hole having a relatively small width may be filled before the second via hole, and thus, since the second via hole is not completely filled, a dimple may be formed on the upper surface and / or lower surface of the second via electrode (121-2), or a void may be formed in the second via electrode (121). The above-described dimples may lower the processability in the process of laminating the first build-up layer (102) and / or the second build-up layer (103), may lower the flatness of the first build-up layer (102) and / or the second build-up layer (103), and may act as a factor causing a voltage drop. The above-described voids may lower the rigidity of the second via electrode (121-2), and may act as a factor causing cracks in the second via electrode (121-2) due to heat generated in the manufacturing process and / or operating environment of the circuit board and / or semiconductor package.

[0074] Accordingly, the embodiment improves the processability in the process of filling the first via hole of the first via electrode (121-1) and the second via hole of the second via electrode (121-2) with a metal material while making the horizontal widths of the first via electrode (121-1) and the second via electrode (121-2) different from each other according to the required characteristics of the first via electrode (121-1) and the second via electrode (121-2), thereby preventing the formation of dimples and / or voids in the first via electrode (121-1) and / or the second via electrode (121-2). By way of example, the embodiment can improve the heat dissipation characteristics by the second via electrode (121) while preventing the signal transmission characteristics by the first via electrode (121-1) from being deteriorated, and further prevent the formation of dimples and / or voids in the first via electrode (121-1) and / or the second via electrode (121-2). This can be achieved by controlling the ratio of the width in the horizontal direction and the length in the vertical direction of each of the first via electrode (121-1) and the second via electrode (121-2), and further control of the vertical cross-sectional shape of the first via electrode (121-1) and the second via electrode (121-2). This will be described later.

[0075] A first build-up layer (102) is arranged on one side of the core layer (101). The first build-up layer (102) includes a plurality of insulating layers (104, 105), a plurality of circuit layers (110, 111, 112), a plurality of upper via electrodes (116, 117), and a first protective layer (108).

[0076] The plurality of circuit layers (110, 111, 112) of the first build-up layer (102) may include a first circuit layer (110) that is most adjacent to the core layer (101) in the vertical direction, a second circuit layer (111) that is positioned further from the core layer (101) in the vertical direction than the first circuit layer (110), and a third circuit layer (112) that is positioned further from the core layer (101) in the vertical direction than the second circuit layer (111). The first to third circuit layers (110, 111, 112) may function to electrically connect to semiconductor elements arranged on the circuit board (100). Each of the first to third circuit layers (110, 111, 112) may be freely designed in consideration of impedance.

[0077] Additionally, upper via electrodes (116, 117) may be arranged to connect the first to third circuit layers (110, 111, 112), respectively. For example, the first upper via electrode (116) is arranged between the first circuit layer (122) and the second circuit layer (123), and the second upper via electrode (117) is arranged between the second circuit layer (123) and the third circuit layer (124), thereby electrically connecting the first to third circuit layers (110, 111, 112).

[0078] The first and second upper via electrodes (116, 117) can be formed simultaneously in the process of arranging the first to third circuit layers (110, 111, 112). For example, in the process of arranging the second circuit layer (111) on the first circuit layer (110), a through hole can be formed in the first insulating layer (104) to expose a portion of the first circuit layer (110), and through this, the second circuit layer (111) can be arranged together with the first upper via electrode (116) filling the through hole of the first insulating layer (104). Therefore, the first upper via electrode (116) can be distinguished as a protrusion of the second circuit layer (111). Likewise, each of the first and second upper via electrodes (116, 117) may be connected to another circuit layer disposed below each circuit layer by being separated by a protrusion of the second and third circuit layers (111, 112).

[0079] Each of the first and second upper via electrodes (116, 117) may include an upper via electrode (116-1, 117-1) connected to a first via electrode (121-1) of a core via electrode (121), and an upper via electrode (116-2, 117-2) connected to a second via electrode (121-2) of the core via electrode (121). The first upper via electrode (116) may include a first-first upper via electrode (116-1) corresponding to the first via electrode (121-1) and having a third width in a horizontal direction, and a first-second upper via electrode (116-2) corresponding to the second via electrode (121-2) and having a fourth width different from the third width in a horizontal direction. The first-first upper via electrode (116-1) may be a via electrode having a signal transmission function and may have a relatively small width in the horizontal direction. In addition, the first-second upper via electrode (116-2) may have a heat dissipation function and may have a relatively large width in the horizontal direction. In addition, the second upper via electrode (117) may include a second-first upper via electrode (117-1) corresponding to the first via electrode (121-1) and having a fifth width in the horizontal direction, and a second-second upper via electrode (117-2) corresponding to the second via electrode (121-2) and having a sixth width different from the fifth width in the horizontal direction. The second-first upper via electrode (117-1) may be a via electrode having a signal transmission function and may have a relatively small width in the horizontal direction. Additionally, the 2-2 upper via electrode (117-2) can have a heat dissipation function and can have a relatively large width in the horizontal direction.

[0080] The first circuit layer (110) may be in contact with one surface of the core layer (101). In this case, a part of the first circuit layer (110) may overlap with the core via electrode (121) described above in the vertical direction. For example, the first circuit layer (110) may have a pad that is in direct contact with the core via electrode (121). For example, the first circuit layer (110) may have a first pad (110-1) that is directly connected to the first via electrode (121-1) and a second pad (110-2) that is directly connected to the second via electrode (121-2). In addition, the first pad (110-1) may be connected to the first-first upper via electrode (116-1), and the second pad (110-2) may be connected to the first-second upper via electrode (116-2). The horizontal width of the first pad (110-1) may be different from the horizontal width of the second pad (110-2). The horizontal width of the first pad (110-1) may be smaller than the horizontal width of the second pad (110-2). A plurality of first pads (110-1) may be provided along the horizontal direction, and each of the plurality of first pads may be connected to a first via electrode (121-1) penetrating the core insulating layer (120). A plurality of second pads (110-2) may be provided along the horizontal direction, and at least one second pad among the plurality of second pads may be commonly connected to the plurality of second via electrodes (121-2).

[0081] The second circuit layer (111) may be disposed on the first insulating layer (104) of the first build-up layer (102). The second circuit layer (111) may include a third pad (111-1) connected to the first-first upper via electrode (116-1) and a fourth pad (111-2) connected to the first-second upper via electrode (116-2). The horizontal width of the third pad (111-1) may be smaller than the horizontal width of the fourth pad (111-2). A plurality of third pads (111-1) may be provided along the horizontal direction, and each of the plurality of third pads may be connected to the first-first upper via electrode (116-1) penetrating the first insulating layer (104). A plurality of fourth pads (111-2) may be provided along the horizontal direction, and at least one fourth pad among the plurality of fourth pads may be commonly connected to a plurality of first-second upper via electrodes (116-2).

[0082] The third circuit layer (112) may be disposed on the second insulating layer (105) of the first build-up layer (102). The third circuit layer (112) may include a fifth pad (112-1) connected to the 2-1 upper via electrode (117-1) and a sixth pad (112-2) connected to the 2-2 upper via electrode (117-2). The horizontal width of the fifth pad (112-1) may be smaller than the horizontal width of the sixth pad (112-2). A plurality of fifth pads (112-1) may be provided along the horizontal direction, and each of the plurality of fifth pads may be connected to the 2-1 upper via electrode (117-1) penetrating the second insulating layer (105). A plurality of sixth pads (112-2) may be provided along the horizontal direction, and at least one sixth pad among the plurality of sixth pads may be commonly connected to a plurality of second-second upper via electrodes (117-2).

[0083] The plurality of insulating layers (104, 105) of the first build-up layer (102) may include a first insulating layer (104) that is closest to the core layer (101) in a direction perpendicular to the core layer (101) and a second insulating layer (105) that is positioned further from the core layer (101) in a direction perpendicular to the first insulating layer (104). In this case, the first build-up layer (102) is illustrated as including the first and second insulating layers (104, 105), but is not limited thereto. For example, the first build-up layer (102) may include three or more insulating layers, thereby enabling a smoother electrical connection between the semiconductor element and the semiconductor package substrate.

[0084] The first and second insulating layers (104, 105) are arranged to vertically insulate between the first to third circuit layers (110, 111, 112) described above. For example, the first and second insulating layers (104, 105) may be formed using a thermosetting insulating material containing an inorganic filler in a resin, and Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Ltd. may be used. However, the embodiment is not limited thereto, and a photo-curable insulating material (Photo Imageable Dielectric, PID) for forming a fine pattern may be used. However, the embodiment is not limited thereto, and the core insulating layer (120) has a thickness smaller than that of a conventional core insulating layer, and accordingly, in order to further improve the rigidity of the circuit board, the first and second insulating layers (104, 105) may be formed using a prepreg having a reinforcing member such as glass fiber. When the first and second insulating layers (104, 105) include prepreg, each of the first and second insulating layers (104, 105) may have a thickness smaller than the thickness in the vertical direction of the core insulating layer (120).

[0085] The first protective layer (108) can protect the third circuit layer (112) from external moisture or contaminants. In addition, when semiconductor elements are arranged on the circuit board (100) using a material such as solder, the first protective layer (108) functions to prevent short circuits between solders due to its low wettability with the solder. The first protective layer (108) can be formed using a photocurable insulating material, and for example, a solder resist can be used.

[0086] A second build-up layer (103) is arranged on the other side of the core layer (101). The second build-up layer (103) includes a plurality of insulating layers (106, 107), a plurality of circuit layers (113, 114, 115), a plurality of via electrodes (118, 119), and a second protective layer (109).

[0087] The plurality of circuit layers (113, 114, 115) of the second build-up layer (103) may include a fourth circuit layer (113) that is most adjacent to the core layer (101) in the vertical direction, a fifth circuit layer (114) arranged under the fourth circuit layer (113), and a sixth circuit layer (115) arranged under the fifth circuit layer (114). The fourth to sixth circuit layers (113, 114, 115) may function to electrically connect a main board (not shown) of an electronic device and a semiconductor element arranged on a circuit board (100). Each of the fourth to sixth circuit layers (113, 114, 115) may be freely designed in consideration of impedance.

[0088] Additionally, lower via electrodes (118, 119) may be arranged to connect the fourth to sixth circuit layers (113, 114, 115), respectively. The first lower electrode (118) is arranged between the fourth circuit layer (113) and the fifth circuit layer (114), and the second lower via electrode (119) is arranged between the fifth circuit layer (114) and the sixth circuit layer (115), thereby electrically connecting the fourth to sixth circuit layers (113, 114, 115).

[0089] As described above with respect to the first and second upper electrodes (116, 117) of the first build-up layer (102), the arrangement of the first and second lower via electrodes (118, 119) can also be performed simultaneously in the process of arranging the fourth to sixth circuit layers (113, 114, 115). Therefore, as described above, the first lower via electrode (118) can be distinguished as a protrusion of the fourth circuit layer (114). However, since the fourth to sixth circuit layers (113, 114, 115) of the second build-up layer (103) are laminated in a different direction from the first build-up layer (102), the inclination direction of each upper via electrode (116, 117) of the first build-up layer (102) may have a direction opposite to the inclination direction of each lower via electrode (118, 119) of the second build-up layer (103). For example, each upper via electrode (116, 117) of the first build-up layer (102) may have a slope whose width becomes narrower as it approaches the core layer (101), and each lower via electrode (118, 119) of the second build-up layer (103) may also have a slope whose width becomes narrower as it approaches the core layer (101). For example, the slope of each upper via electrode (116, 117) of the first build-up layer (102) may be symmetrical with respect to the slope of each lower via electrode (118, 119) of the second build-up layer (103) with respect to the core layer (101).

[0090] Each of the first and second lower via electrodes (118, 119) may include a lower via electrode (118-1, 119-1) connected to the first via electrode (121-1) of the core via electrode (121), and a lower via electrode (118-2, 119-2) connected to the second via electrode (121-2) of the core via electrode (121). The first lower via electrode (118) may include a first-first lower via electrode (118-1) corresponding to the first via electrode (121-1) and having a third width in the horizontal direction, and a first-second lower via electrode (118-2) corresponding to the second via electrode (121-2) and having a fourth width different from the third width in the horizontal direction. The first-first lower via electrode (118-1) may be a via electrode having a signal transmission function and may have a relatively small width in the horizontal direction. In addition, the first-second lower via electrode (118-2) may have a heat dissipation function and may have a relatively large width in the horizontal direction. In addition, the second lower via electrode (119) may include a second-first lower via electrode (119-1) corresponding to the first via electrode (121-1) and having a fifth width in the horizontal direction, and a second-second lower via electrode (119-2) corresponding to the second via electrode (121-2) and having a sixth width different from the fifth width in the horizontal direction. The second-first lower via electrode (119-1) may be a via electrode having a signal transmission function and may have a relatively small width in the horizontal direction. Additionally, the 2-2 lower via electrode (119-2) can have a heat dissipation function and can have a relatively large width in the horizontal direction.

[0091] The fourth circuit layer (113) may be in contact with the other surface of the core layer (101). In this case, a part of the fourth circuit layer (113) may overlap with the core via electrode (121) described above in the vertical direction. For example, the fourth circuit layer (113) may have a pad that is in direct contact with the core via electrode (121). For example, the fourth circuit layer (113) may have a seventh pad (113-1) that is directly connected to the first via electrode (121-1) and an eighth pad (113-2) that is directly connected to the second via electrode (121-2). The horizontal width of the seventh pad (113-1) may be different from the horizontal width of the eighth pad (113-2). The horizontal width of the seventh pad (113-1) may be smaller than the horizontal width of the eighth pad (113-2). A plurality of seventh pads (113-1) may be provided along the horizontal direction, and each of the plurality of seventh pads may be connected to a first via electrode (121-1) penetrating the core insulating layer (120). A plurality of eighth pads (113-2) may be provided along the horizontal direction, and at least one of the plurality of eighth pads may be commonly connected to a plurality of second via electrodes (121-2).

[0092] The fifth circuit layer (114) may be disposed on the third insulating layer (106) of the second build-up layer (103). The fifth circuit layer (111) may include a ninth pad (114-1) connected to the first-first lower via electrode (118-1) and a tenth pad (114-2) connected to the first-second lower via electrode (118-2). The horizontal width of the ninth pad (114-1) may be smaller than the horizontal width of the tenth pad (114-2). A plurality of ninth pads (114-1) may be provided along the horizontal direction, and each of the plurality of ninth pads may be connected to the first-first lower via electrode (118-1) penetrating the third insulating layer (106). A plurality of 10th pads (114-2) may be provided along the horizontal direction, and at least one 10th pad among the plurality of 10th pads may be commonly connected to a plurality of 1-2nd lower via electrodes (118-2).

[0093] The sixth circuit layer (115) may be disposed on the third insulating layer (107) of the second build-up layer (103). The sixth circuit layer (115) may include an eleventh pad (115-1) connected to the second-first lower via electrode (119-1) and a twelfth pad (115-2) connected to the second-second lower via electrode (119-2). The horizontal width of the eleventh pad (115-1) may be smaller than the horizontal width of the twelfth pad (115-2). A plurality of eleventh pads (115-1) may be provided along the horizontal direction, and each of the plurality of eleventh pads may be connected to the second-first lower via electrode (119-1) penetrating the fourth insulating layer (107). A plurality of 12th pads (112-2) may be provided along the horizontal direction, and at least one 12th pad among the plurality of 12th pads may be commonly connected to a plurality of 2-2 lower via electrodes (119-2).

[0094] The plurality of insulating layers (106, 107) of the second build-up layer (103) may include a third insulating layer (106) that is most adjacent to the core layer (101) in the vertical direction, and a fourth insulating layer (107) that is arranged under the third insulating layer (106). The third and fourth insulating layers (106, 107) are arranged to insulate in the vertical direction between the fourth to sixth circuit layers (113, 114, 115) described above. In addition, as an example, the third and fourth insulating layers (106, 107) may use a thermosetting insulating material containing an inorganic filler in a resin, and Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Ltd. may be used. However, the embodiment is not limited thereto, and a photo-curable insulating material (Photo Imageable Dielectric, PID) for forming a fine pattern may be used. However, the embodiment is not limited thereto, and the core insulating layer (120) has a thickness smaller than that of a conventional core insulating layer, and accordingly, in order to further improve the rigidity of the circuit board, the third and fourth insulating layers (106, 107) may use a prepreg having a reinforcing member such as glass fiber. When the third and fourth insulating layers (106, 107) include a prepreg, each of the third and fourth insulating layers (106, 107) may have a thickness smaller than the thickness of the core insulating layer (120) in the vertical direction.

[0095] The second protective layer (109) can protect the sixth circuit layer (115) from external moisture or contaminants. In addition, when semiconductor elements are arranged on the circuit board (100) using a material such as solder, the second protective layer (109) functions to prevent short circuits between solders due to its low wettability with the solder. The second protective layer (109) can be formed using a photocurable insulating material, and for example, a solder resist can be used.

[0096] The structure of the circuit board (100) described above is only an example for explaining the present invention, and the technical idea of ​​the present invention is not limited to the laminated structure of the present embodiment.

[0097] A core via electrode (121) is provided in a core insulating layer (120) of a circuit board (100), and the core via electrode (121) provided in the core insulating layer (120) may be provided by filling an interstitial via hole (IVH) with a conductive material, unlike the upper via electrodes (116, 117) and the lower via electrodes (118, 119). At this time, when a plurality of interstitial via holes having different widths are simultaneously filled with a metal material, an interstitial via hole having a relatively small width is preferentially completely filled, and accordingly, as illustrated in FIG. 2, a dimple may be provided on the upper surface and / or lower surface of the via electrode filled in the interstitial via hole having a relatively large width. Accordingly, the embodiment controls the ratio of the width in the horizontal direction and the length in the vertical direction of each of the first via electrode (121-1) and the second via electrode (121-2), and further controls the vertical cross-sectional shape of the first via electrode (121-1) and the second via electrode (121-2), thereby preventing the signal transmission characteristics by the first via electrode (121-1) from being deteriorated while improving the heat dissipation characteristics by the second via electrode (121), and further preventing the formation of dimples and / or voids in the first via electrode (121-1) and / or the second via electrode (121-2).

[0098] Referring to FIG. 3, the core layer (101) includes a core insulating layer (120) and a core via electrode (121). The core via electrode (121) may include a first via electrode (121-1) having a first width (W1) in a horizontal direction and a second via electrode (121-2) having a second width (W2) greater than the first width (W1) in a horizontal direction. The first via electrode (121) may be used as a path for transmitting an electrical signal between the first build-up layer (102) and the second build-up layer (103), but is not limited thereto. The second via electrode (121-2) may be used as a path for transmitting heat between the first build-up layer (102) and the second build-up layer (103), but is not limited thereto.

[0099] The vertical length (H1) of the first via electrode (121-1) and the vertical length (H1) of the second via electrode (121-2) may be the same. That is, each of the first via electrode (121-1) and the second via electrode (121-2) is provided to penetrate the core insulating layer (120), and accordingly, the vertical length (H1) of each of the first via electrode (121-1) and the second via electrode (121-2) may correspond to the vertical thickness of the core insulating layer (120).

[0100] The first width (W1) in the horizontal direction of the first via electrode (121-1) can be designed under a condition that can minimize transmission loss of an electrical signal transmitted between the first build-up layer (102) and the second build-up layer (103). The second width (W2) in the horizontal direction of the second via electrode (121-2) can be designed under a condition that can maximize heat dissipation characteristics.

[0101] The larger the second width (W2) in the horizontal direction of the second via electrode (121-2) is, the better the heat dissipation characteristics can be. However, if the second width (W2) in the horizontal direction of the second via electrode (121-2) deviates from a certain level of the length (H1) in the vertical direction of the second via electrode (121-2), the processability in the process of filling the second via hole of the second via electrode (121-2) with a conductive material may deteriorate. For example, if the second width (W2) in the horizontal direction of the second via electrode (121-2) deviates from three times the length (H1) in the vertical direction of the second via electrode (121-2), the plating growth speed on the inner wall of the second via hole may rapidly increase, and thus, as illustrated in FIG. 2, a dimple may be formed on the upper surface and / or lower surface of the second via electrode (121-2). Accordingly, the second width (W2) in the horizontal direction of the second via electrode (121-2) is set to be less than three times the length (H1) in the vertical direction of the second via electrode (121-2).

[0102] The smaller the first width (W1) in the horizontal direction of the first via electrode (121-1), the higher the circuit integration and the lower the signal transmission loss. That is, the smaller the first width (W1) in the horizontal direction of the first via electrode (121-1), the better, and the larger the second via electrode (121-2) in the horizontal direction of the second via electrode (121-2), the better the trade-off relationship. At this time, if the difference between the first width (W1) in the horizontal direction of the first via electrode (121-1) and the second width (W2) in the horizontal direction of the second via electrode (121-2) exceeds a certain level, the difference between the time required to completely fill the first via hole and the time required to completely fill the second via hole increases, and thus voids and / or dimples may be formed in the first via electrode (121-1) and / or the second via electrode (121-2). Furthermore, if the first width (W1) in the horizontal direction of the first via electrode (121-1) is less than a certain level of the length (H1) in the vertical direction of the first via electrode (121-1), the plating growth speed on the inner wall of the first via hole corresponding to the first via electrode (121-1) rapidly increases, and thereby the difference in the time required to fill each of the first via hole and the second via hole may further increase.

[0103] The first width (W1) in the horizontal direction of the first via electrode (121-1) is set to be at least 1.6 times the length (H1) in the vertical direction of the first via electrode (121-1). If the first width (W1) in the horizontal direction of the first via electrode (121-1) is less than 1.6 times the length (H1) in the vertical direction of the first via electrode (121-1), the difference in process conditions in the process of filling the first via hole and the second via hole with a metal material may increase, and accordingly, the first via hole may be excessively filled with the metal material, or the second via hole may not be densely filled with the metal material. That is, the first width (W1) in the horizontal direction of the first via electrode (121-1) can be determined based on the condition that the metal material filling process can be improved according to the thickness of the core insulating layer (120) while the signal transmission loss does not exceed a certain level. In addition, when the first width (W1) in the horizontal direction of the first via electrode (121-1) exceeds three times the length (H1) in the vertical direction of the first via electrode (121-1), the signal transmission loss can increase rapidly, and further, the processability in the process of filling the first via hole can be deteriorated, so that the first via hole cannot be densely filled with the metal material.

[0104] Accordingly, the horizontal width (W1, W2) of each of the first via electrode (121-1) and the second via electrode (121-2) of the embodiment can be 1.6 times or more, and further, 3 times or less, of the vertical length (H1) of each of the first via electrode (121-1) and the second via electrode (121-2). Through this, the filling speeds of the first and second via holes having different widths in the horizontal direction can be maintained similarly, so that each of the first and second via holes can be densely filled with a metal material, and further, the formation of dimples and / or voids in the first via electrode (121-1) and the second via electrode (121-2) can be prevented.

[0105] In addition, the embodiment solves the problem that at least one via hole is not densely filled with a metal material in a process of simultaneously filling via holes having different widths with a metal material by changing the vertical cross-sectional shapes of the first via electrode (121-1) and the second via electrode (121-2).

[0106] Referring to FIG. 4, the circuit board may include a core insulating layer (210), a first upper pad (220), a second upper pad (230), a first lower pad (240), a second lower pad (250), a first via electrode (260), and a second via electrode (270). In the structure of the embodiment of FIG. 4, the remaining structure except for the shapes of the side surfaces of the first via electrode (260) and the second via electrode (270) may be substantially the same as the structure of the previous embodiment, and a detailed description of the structural features that are the same as the previous embodiment will be omitted.

[0107] The first via electrode (260) may have a first width (W1) along the horizontal direction, and the second via electrode (270) may have a second width (W2) greater than the first width (W1) along the horizontal direction. The first width (W1) and the second width (W2) may each correspond to the conditions described through FIG. 3, and a detailed description thereof will be omitted.

[0108] The side surface of the second via electrode (270) may include a first portion (271) having a curvature and a second portion (272) connected to the first portion (271) and having a slope. The first portion (271) of the second via electrode (270) may be curved and may have a specific curvature and may connect between the upper surface of the core insulating layer (210) and the upper end of the second portion (272) of the second via electrode (270). The first portion (271) of the second via electrode (270) may prevent rapid filling of the metal material on the inner wall of the second via hole in a process of filling the second via hole corresponding to the second via electrode (270) with a conductive material, and may improve the filling property of the metal material on the inner side of the second via hole, thereby allowing the metal material to be densely filled in the second via hole. In addition, if the side surface of the second via electrode (270) has an overall curvature, the time required to completely fill the second via hole may increase rapidly, or the adhesion between the second via electrode (270) and the core insulating layer (210) may decrease. Therefore, at least a portion of the side surface of the second via electrode (270) is configured to include a second portion (272) having a slope rather than a curvature.

[0109] The first via electrode (260) has a first width (W1) smaller than a second width (W2) in the horizontal direction of the second via electrode (270), and thus, unlike the second via electrode (270), a metal material can be densely filled in the first via hole even if the side surface does not have a curvature. However, when the side surface shapes of the first via electrode (260) and the second via electrode (270) are different, the difference in process conditions in the process of filling the first via hole and the second via hole may become larger, and accordingly, the degree to which the first via electrode (260) is excessively filled may increase, or a dimple and / or void may be formed in the second via electrode (270). Therefore, at least a part of the side surface of the first via electrode (260) may have a curvature.

[0110] That is, the first via electrode (260) may be provided with a third portion (261) having a curvature and a fourth portion (262) having a slope connected to the third portion (261).

[0111] At this time, the third part (261) of the first via electrode (260) and the first part (271) of the second via electrode (270) may overlap the reinforcing member (210GF) provided in the core insulating layer (210) along the horizontal direction, respectively. That is, the embodiment can use the reinforcing member (210GF) provided in the core insulating layer (210) to make at least a part of the inner wall of each of the first and second via holes have a curvature, thereby allowing each of the first and second via holes having different widths in the horizontal direction to be densely filled with a metal material.

[0112] The position between the third portion (261) and the fourth portion (262) of the first via electrode (260) may be misaligned with the position between the first portion (271) and the second portion (272) of the second via electrode (270) in the horizontal direction. For example, the vertical length (H2) of the third portion (261) of the first via electrode (260) may be different from the vertical length (H3) of the first portion (271) of the second via electrode (270). Preferably, the vertical length (H2) of the third portion (261) of the first via electrode (260) may be greater than the vertical length (H3) of the first portion (271) of the second via electrode (270). That is, the embodiment makes it so that the vertical length (H2) of the third portion (261) of the first via electrode (260) having a relatively small width in the horizontal direction is greater than the vertical length (H3) of the first portion (271) of the second via electrode (270) having a relatively large width in the horizontal direction, thereby making it possible to similarly match the times required for each of the first via hole and the second via hole having different widths in the horizontal direction to be completely filled with a metal material, thereby improving the flatness of the first via electrode (260) and the second via electrode (270) while preventing the formation of dimples or voids.

[0113] According to the embodiment of FIG. 5, the circuit board may include a core layer (310), a first build-up layer (320), and a second build-up layer (330). The first build-up layer (320) may have a pad portion (321) disposed at the uppermost portion, and may include a first protective layer (322) disposed on the pad portion (321). In addition, as the density of terminals of semiconductor devices increases, a problem of solder short-circuiting between adjacent pad portions may occur with conventional solder bonding. Therefore, in order to reduce the amount of solder used as the density of terminals of semiconductor devices increases, the semiconductor devices and the circuit board (100) may be bonded to each other through a thermal compression bonding method. When using thermal compression bonding, the circuit board (100) may further include a bump layer (340) protruding on the first protective layer (322). The bump layer (340) may have a protrusion (342) protruding on the upper surface of the first protective layer (322), and a penetration portion (341) penetrating the first protective layer (322) and contacting the pad portion (321). In addition, when the circuit board (100) and the semiconductor element are bonded by thermal compression bonding, a crack may occur in the penetration portion (341) of the bump layer (340) due to the load generated thereby. Therefore, the penetration portion (341) of the bump layer (340) may be prevented from cracking by disposing a material having an elastic modulus greater than the elastic modulus of the pad portion (321) in a portion adjacent to the pad portion (321). This material may be nickel (Ni), but a copper layer having a low grain density may be disposed by electroless plating.

[0114] The through-hole (341) of the bump layer (340) illustrated in FIG. 5 can be arranged in various ways. For example, a process may be performed in which the first protective layer (322) is exposed and developed to form an opening in the first protective layer (322), and then the through-hole (341) and the protrusion (342) of the bump layer (340) are arranged in the opening. In addition, a process may be performed in which a through-hole in the first protective layer (322) is formed using a laser, and then the through-hole (341) and the protrusion (342) of the bump layer (340) are arranged in the opening. In addition, by using DFR (Dry Film resist), DFR is first placed in the area where the penetration portion (341) is to be placed, and then the first protective layer (322) is placed so that the DFR is covered, and then a part of the first protective layer (322) is etched with a chemical solution to expose the DFR, and then the DFR is peeled off to form an opening in the first protective layer (322), and then the penetration portion (341) and the protrusion portion (342) of the bump layer (340) can be placed. Therefore, the penetration portion (341) can have various shapes depending on the process method. For example, when the opening of the first protective layer (322) is formed through an exposure process, the side surface of the through-hole (341) may have a structure in which the width gradually narrows toward the pad portion (321). When the opening of the first protective layer (322) is formed through a laser process, the side surface of the through-hole (341) may have a vertical side surface and a curved side surface adjacent to the pad portion (321). When the opening of the first protective layer (322) is formed using DFR, the side surface of the through-hole (341) may only have a vertical side surface. As described above, when the semiconductor element is bonded to the circuit board (100) through thermocompression bonding, a load may be applied to the through-hole (341). In this case, in the case of the through-hole (341) using DFR, the stress may be applied uniformly, so that the manufacturing yield may be increased.

[0115] According to the embodiment of FIG. 6, the circuit board may include a core layer (410), a first build-up layer (420), and a second build-up layer (430). In addition, the circuit board may further include at least one connecting member (440). Recently, as the number of signals that semiconductor devices must process increases, the size of semiconductor devices is trending toward larger areas, but this larger area of ​​semiconductor devices is causing a problem of lowering the yield of semiconductor devices. Therefore, there is a trend of dividing the pattern size or functional part of the semiconductor device, arranging chiplets on the circuit board, and embedding connecting members (440) that have the function of electrically connecting them within the circuit board. However, the connecting members (440) are not limited thereto, and may also connect semiconductor devices with other functions, such as memory. In addition, the connecting members (440) may be arranged on the core layer (410) of the circuit board. For example, the core layer (410) may have a through hole (not shown), and the connecting member (440) may be placed within the through hole of the core layer (410).

[0116] The connecting member (440) may overlap with the via electrodes provided in the core layer (410) in the horizontal direction. For example, the core layer (410) may include the via electrodes described with reference to FIG. 4, each side surface of the via electrodes provided in the core layer (410) may have a curved surface, and the connecting member (440) may overlap with the curved surface of each of the via electrodes provided in the core layer (410) in the horizontal direction. Through this, the embodiment can stably protect the connecting member (440) from horizontal stress due to expansion and / or contraction according to a heat cycle, thereby enabling the circuit board and / or semiconductor package to operate more stably.

[0117] In addition, the upper via electrode penetrating the first insulating layer (104) may have different widths depending on the location. For example, the upper via electrode may include a first upper via electrode (421, 422) having a signal transmission function and a second upper via electrode (423) having a heat transfer function. In addition, the first upper via electrode (421, 422) may include a first via portion (421) that vertically overlaps with the connecting member (440), and a second via portion (422) that horizontally overlaps with the first via portion (421) and does not vertically overlap with the connecting member (440). The above-described first via portion (421) may be directly connected to a pad portion provided on the upper surface of the connecting member (440). The horizontal width of the first via portion (421) may be smaller than the horizontal width of the second via portion (422). This embodiment can further improve circuit integration and provide more stable connection between the circuit board and the semiconductor device.

[0118] In addition, according to the embodiment of FIG. 7, the circuit board may include a core layer (510), a first build-up layer (520), and a second build-up layer (530). In addition, the circuit board may further include at least one connecting member (540). Unlike the embodiment of FIG. 6, the connecting member (540) may be embedded in the first build-up layer (520) rather than in the core layer (510). For example, when the connecting member (540) is embedded in the first build-up layer (520), the signal transmission distance with the semiconductor element can be reduced, which is advantageous in preventing signal loss. That is, the connecting member (540) electrically connects a plurality of semiconductor elements arranged on the circuit board, and thus, reducing the signal transmission distance while being adjacent to the plurality of semiconductor elements can be advantageous in reducing signal transmission loss. At this time, when the connecting member (540) is arranged on the first build-up layer (520), the first insulating layer (104) and the second insulating layer (105) of the first build-up layer (520) may have cavities. Conventionally, a cavity is provided only in one specific insulating layer to embed the connecting member (540), but in this case, the problem of deterioration of the flatness of the uppermost insulating layer may occur. In addition, when the thickness of the connecting member (540) is thicker than the thickness of the specific insulating layer of the first build-up layer (102), the problem of deterioration of the flatness may become more serious. Therefore, it is necessary to improve the flatness by reducing the difference between the thickness of the connecting member (540) and the depth of the cavity. At this time, when cavities are provided in the first insulating layer (104) and the second insulating layer (105), the cavity of the second insulating layer (105) can be formed to have a second inclination angle that is gentler than the first inclination angle of the inner wall forming the cavity of the first insulating layer (104). In this case, the positional alignment of the connecting member (540) can be increased, and the occurrence of voids can be prevented when the cavity is filled with another insulating layer.

[0119] Additionally, according to the embodiment of FIG. 8, the circuit board may include a core layer (610), a first build-up layer (620), and a second build-up layer (630). Additionally, the circuit board may further include at least one connecting member (640).

[0120] In addition, the core layer (610) of the circuit board may have via electrodes. At this time, the via electrodes provided in the core layer (610) may be as illustrated in FIGS. 6 and 7. In addition, the core layer (610) may further include a via electrode (650) that overlaps the connecting member (640) in a vertical direction. The via electrode (650) may have a curved portion as described above. In addition, the curved portion of the via electrode (650) may overlap the connecting member (640) in a vertical direction. Through this, the embodiment can stably protect the connecting member (640) from vertical stress due to expansion and / or contraction according to a heat cycle, thereby enabling the circuit board and / or semiconductor package to operate more stably.

[0121]

[0122] The circuit board (100) described above can be used as an interposer provided between the semiconductor package substrate and the semiconductor element of the semiconductor package.

[0123] According to the embodiment illustrated in FIG. 9, the semiconductor package includes an interposer (510). The interposer (510) may refer to the circuit board (100) described with reference to FIGS. 1 to 8. That is, as the terminal density of the semiconductor element increases, the wiring becomes more complex, and accordingly, the thickness of the circuit board increases. However, as the thickness increases, a problem may arise in that the yield of the circuit board decreases. Therefore, the circuit board may be divided into an interposer (710) and a semiconductor package board (770) and used, and the circuit board (100) described above may be used not only as the semiconductor package board (770) but also as the interposer (710).

[0124] Semiconductor elements (730, 740) are arranged on the interposer (710). The semiconductor elements (730, 740) may be provided in multiple numbers on the interposer (710) while being spaced apart from each other in the horizontal direction, but are not limited thereto. For example, the semiconductor elements (730, 740) may be arranged and stacked on the interposer (710) not only in the horizontal direction but also in the vertical direction.

[0125] A bonding member (750, 760) may be provided between the interposer (710) and the semiconductor elements (730, 740). In one embodiment, the bonding member (750, 760) may be placed on a bump layer (see FIG. 5) provided on the interposer (710), through which the semiconductor elements (730, 740) may be attached to the interposer (710) by a thermocompression bonding method. At this time, the semiconductor elements (730, 740) may be provided with terminals (731, 741), and the terminals (731, 741) may be electrically connected to the bump layer and the circuit layer of the interposer (710) through the bonding member (750, 760).

[0126] A connecting member (720) is embedded within the interposer (710). The connecting member (720) may function to electrically connect terminals (731, 741) of semiconductor elements (730, 740) disposed on the interposer (710). In this case, the connecting member (720) may be a bridge die. For example, the connecting member (720) partially vertically overlaps the semiconductor elements (730, 740) disposed on the interposer (710). In addition, the connecting member (720) electrically connects a portion of the terminal (731) of the first semiconductor element (730) and a portion of the terminal (741) of the second semiconductor element (740). The connecting member (720) may be formed of the same material as the semiconductor element, such as silicon, or may be formed of an organic material, such as a photosensitive resin or a thermosetting resin. A plurality of semiconductor devices having different functions, such as a CPU and GPU, a GPU and HBM, or a chiplet unit separated according to function and / or pitch, may be mounted on a circuit board, and a connecting member (720) may function to horizontally electrically connect them.

[0127] A semiconductor package substrate (770) is placed on the lower surface of the interposer (710). The semiconductor package substrate (770) can electrically connect the main board of an electronic device and the interposer (710).

[0128] At this time, a bonding member (780) may be placed between the interposer (710) and the semiconductor package substrate (770), through which the interposer (710) and the semiconductor package substrate (770) may be electrically bonded.

[0129] The circuit board of the embodiment can densely fill a plurality of via holes having different horizontal widths provided in a core insulating layer with a metal material, thereby providing a core via electrode having excellent mechanical reliability and / or electrical reliability.

[0130] Specifically, the circuit board of the embodiment includes a core layer, a first build-up layer disposed on an upper surface of the core layer, and a second build-up layer disposed on a lower surface of the core layer, the core layer includes a first via electrode having a first width along a horizontal direction, and a second via electrode having a second width different from the first width along a horizontal direction, and a side surface of the second via electrode may include a first portion having a curvature and a second portion having a slope connected to the first portion.

[0131] Through this, in the process of filling a second via hole corresponding to a second via electrode with a conductive material, the embodiment can prevent rapid filling of the metal material on the inner wall of the second via hole, improve the filling property of the metal material on the inner side of the second via hole, and thereby enable the metal material to be densely filled in the second via hole.

[0132] Furthermore, the side surface of the first via electrode may include a third portion having a curvature and a fourth portion having a slope connected to the third portion. Through this, the embodiment may enable the first via electrode and the second via electrode to have vertical cross-sectional shapes corresponding to each other, and may solve a problem of warping of the circuit board that may occur due to different vertical cross-sectional shapes of the first and second via electrodes.

[0133] In addition, the vertical length of the third portion of the first via electrode may be different from the vertical length of the first portion of the second via electrode. Preferably, the vertical length of the third portion of the first via electrode may be greater than the vertical length of the first portion of the second via electrode. That is, the embodiment allows the vertical length of the third portion of the first via electrode having a relatively small width in the horizontal direction to be greater than the vertical length of the first portion of the second via electrode having a relatively large width in the horizontal direction, thereby allowing the times required for each of the first via hole and the second via hole having different widths in the horizontal direction to be completely filled with a metal material to be similarly matched, thereby improving the flatness of the first via electrode and the second via electrode while preventing the formation of dimples or voids.

[0134] In addition, the horizontal width of each of the first and second via electrodes is set to be at least 1.6 times the vertical length. If the horizontal width of the first via electrode is less than 1.6 times the vertical length of the first via electrode, the difference in process conditions in the process of filling the first via hole and the second via hole with a metal material may become large, and as a result, the first via hole may be excessively filled with the metal material, or the second via hole may not be densely filled with the metal material. Therefore, in the embodiment, the horizontal width of each of the first and second via electrodes is set to be at least 1.6 times the vertical length so as to improve the metal material filling processability according to the thickness of the core insulating layer while the signal transmission loss does not exceed a certain level. In addition, the horizontal width of each of the first and second via electrodes may be set to be at most 3 times the vertical length. Through this, the filling speeds of the first and second via holes having different widths in the horizontal direction can be maintained similarly, so that each of the first and second via holes can be densely filled with a metal material, and further, dimples and / or voids can be prevented from being formed in the first via electrode and the second via electrode.

[0135] Meanwhile, the first via electrode and the second via electrode provided in the core layer of the embodiment can be manufactured by the manufacturing method described below, thereby enabling each of the first via hole and the second via hole to be filled with a metal material more stably, thereby improving the mechanical reliability and / or electrical reliability of the circuit board and the semiconductor package.

[0136]

[0137] Figures 10 to 14 are drawings showing the process sequence for manufacturing the core layer of the circuit board illustrated in Figure 1.

[0138] Referring to FIG. 10, an embodiment may prepare a base material for manufacturing a core layer (101). Here, the base material may be a CCL (Copper Clad Laminate). The base material may include a core insulating layer (120), upper and lower base metal layers (810, 820) provided on the upper and lower surfaces of the core insulating layer (120), respectively, an upper protective metal layer (830) disposed on the upper surface of the upper base metal layer (810), and a lower protective metal layer (840) provided on the lower base metal layer (820).

[0139] Next, referring to FIG. 11, the embodiment may proceed with a process of removing the upper protective metal layer (830) disposed on the upper base metal layer (810). At this time, the embodiment may leave the lower protective metal layer (840) without removing it.

[0140] Next, referring to FIG. 12, the embodiment may perform a process of forming a first via hole (VH1) and a second via hole (VH2) penetrating the core insulating layer (120). At this time, each of the first via hole (VH1) and the second via hole (VH2) may be formed by irradiating a laser beam onto the upper base metal layer (810). At this time, the irradiated laser beam may penetrate the upper base metal layer (810). At this time, a lower protective metal layer (840) is provided on the lower surface of the lower base metal layer (820), and accordingly, the laser beam may not penetrate the lower base metal layer (820) due to the lower protective metal layer (840).

[0141] Next, referring to FIG. 13, a process of removing the lower protective metal layer (840) provided on the lower surface of the lower base metal layer (820) may be performed. Thereafter, the embodiment may perform a process of laminating first and second dry films (DF1, DF2) having openings provided in areas where the first circuit layer (110), the second circuit layer (113), the first via electrode (113-1), and the second via electrode (113-2) are to be formed. Thereafter, the embodiment may perform a process of filling the first via hole (VH1), the second via hole (VH2) provided in the core insulating layer (120), and the openings of the first and second dry films (DF1, DF2) with a metal material to form the first circuit layer (110), the fourth circuit layer (113), the first via electrode (113-1), and the second via electrode (113-2). At this time, the via hole of the general core insulating layer is provided as an interstitial via hole (IVH). In contrast, the embodiment performs the process of forming the via hole and the process of forming the via electrode without removing the lower base metal layer (820) provided on the lower surface of the core insulating layer (120). Through this, the first via hole (VH1) and the second via hole (VH2) provided in the core insulating layer (120) of the embodiment can be provided as blind via holes (BVH). Accordingly, the embodiment can densely fill the first via hole (VH1) and the second via hole (VH2) having different widths in the horizontal direction with a metal material. Furthermore, the embodiment can control the ratio of the width in the horizontal direction and the length in the vertical direction of each of the via holes illustrated in FIGS. 3 and 4, and further can control the vertical cross-sectional shape of each of the first via hole (VH1) and the second via hole (VH2). Accordingly, the embodiment can more densely fill the first via hole (VH1) and the second via hole (VH2) with a metal material.

[0142] Next, referring to FIG. 14, the embodiment may proceed with a process of removing the first and second dry films (DF1, DF2), and then proceed with a process of removing a portion of the upper base metal layer (810) and a portion of the lower base metal layer (820) that do not vertically overlap with the first circuit layer (110), the fourth circuit layer (113), the first via electrode (113-1), and the second via electrode (113-2). Accordingly, at least a portion of the fourth circuit layer (113) of the embodiment may be provided with the lower base metal layer (820), and the lower surfaces of the first via electrode (113-1) and the second via electrode (113-2) may be in contact with the lower base metal layer (820) rather than the electroplating layer.

[0143]

[0144] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0145] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0146] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0147] Although the above has been described focusing on embodiments, these are merely examples and are not intended to limit the embodiments. Those skilled in the art to which the embodiments pertain will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. Core layer; A first build-up layer disposed on the upper surface of the core layer; and A second build-up layer is disposed on the lower surface of the core layer, The core layer includes a first via electrode having a first width along a horizontal direction, and a second via electrode having a second width different from the first width along the horizontal direction, The side surface of the second via electrode includes a first portion having a curvature, and a second portion having a slope connected to the first portion. Circuit board.

2. In paragraph 1, The horizontal width of each of the first and second via electrodes is at least 1.6 times the ratio of the vertical length to the horizontal width. Circuit board.

3. In paragraph 2, The horizontal width of each of the first and second via electrodes is less than three times the vertical length. Circuit board.

4. In any one of paragraphs 1 to 3, The vertical lengths of each of the first and second via electrodes are equal to each other. Circuit board.

5. In paragraph 4, The first build-up layer includes a first circuit layer disposed on an upper surface of the core layer, The above first circuit layer is, A first pad overlapping along the vertical direction with the first via electrode; and Including a second pad overlapping along the vertical direction with the second via electrode, Circuit board.

6. In paragraph 5, The horizontal width of the first pad is smaller than the horizontal width of the second pad. Circuit board.

7. In paragraph 5, The first pad includes a plurality of individual pads electrically connected to each of the plurality of first via electrodes and spaced apart from each other along the horizontal direction, The second pad comprises at least one integrated pad electrically connected in common with a plurality of second via electrodes. Circuit board.

8. In paragraph 2 or 3, The vertical length has a range of 25 μm to 60 μm, Circuit board.

9. In paragraph 4, The side surface of the first via electrode includes a third portion having a curvature, and a fourth portion having a slope connected to the third portion, The vertical length of the third portion of the first via electrode is different from the vertical length of the first portion of the second via electrode. Circuit board.

10. In paragraph 9, The vertical length of the third portion of the first via electrode is smaller than the vertical length of the first portion of the second via electrode. Circuit board.

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