Circuit board, and semiconductor package comprising same

Abstract

A circuit board according to an embodiment comprises: a first insulating layer; a second insulating layer which is disposed on the first insulating layer and includes a cavity; a protective layer disposed on the second insulating layer; and a via electrode which has the top surface located on the same plane as the top surface of the second insulating layer, and penetrates at least a partial region of the second insulating layer from the top surface of the via electrode toward the bottom surface of the second insulating layer, wherein the via electrode includes a through hole that penetrates at least a partial region of the via electrode from the top surface of the via electrode toward the bottom surface of the first insulating layer, and the through hole of the via electrode overlaps the cavity of the second insulating layer in a horizontal direction.

Description

Circuit boards and semiconductor packages including the same

[0001] The embodiment relates to a circuit board and a semiconductor package including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies for arranging a greater number of semiconductor devices on semiconductor package substrates are being proposed and researched. However, because conventional semiconductor packages are based on mounting a single semiconductor device, achieving desired performance is limited.

[0003] Accordingly, semiconductor packages that utilize multiple substrates to arrange multiple semiconductor devices have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected to each other horizontally and / or vertically on the substrate. Accordingly, these semiconductor packages have the advantage of efficiently utilizing the mounting area of ​​the semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between the semiconductor devices.

[0004] In addition, semiconductor packages applied to products that provide the Internet of Things (IoT), autonomous vehicles, and high-performance servers are expanding their concept to semiconductor chiplets as the number of semiconductor elements and / or the size of each semiconductor element increases in line with the trend toward high integration, or as the functional parts of semiconductor elements are divided.

[0005] Meanwhile, as the number of semiconductor devices and / or semiconductor chiplets mounted in a semiconductor package increases, the area of ​​the semiconductor package is increasing.

[0006] Accordingly, as the area of ​​a semiconductor package increases, the semiconductor package suffers from greater warpage. Furthermore, as the number of semiconductor devices and / or semiconductor chiplets increases, heat generation becomes more severe, necessitating further improvements in heat dissipation characteristics.

[0007] The embodiment provides a circuit board of a novel structure and a semiconductor package including the same.

[0008] Additionally, the embodiment provides a circuit board with improved heat dissipation characteristics and a semiconductor package including the same.

[0009] In addition, the embodiment provides a circuit board with improved bending characteristics and a semiconductor package including the same.

[0010] The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

[0011] A circuit board according to an embodiment comprises: a first insulating layer; a second insulating layer disposed on the first insulating layer and including a cavity; a protective layer disposed on the second insulating layer; and an upper surface positioned flush with an upper surface of the second insulating layer, and a via electrode penetrating at least a portion of the second insulating layer from the upper surface toward a lower surface of the second insulating layer, wherein the via electrode includes a through hole penetrating at least a portion of the via electrode from an upper surface of the via electrode toward a lower surface of the second insulating layer, and the through hole of the via electrode horizontally overlaps with the cavity provided in the second insulating layer.

[0012] Additionally, the second insulating layer includes a first portion disposed on the outside of the via electrode, and a second portion disposed within the through hole of the via electrode.

[0013] In addition, the through holes are provided in multiple numbers and spaced apart from the via electrode in a first horizontal direction and a second horizontal direction different from the first horizontal direction.

[0014] Additionally, the second insulating layer includes a via hole penetrating at least a portion of the second portion from the upper surface of the second portion toward the lower surface of the second portion, and further includes a sub-via electrode disposed within the via hole of the second insulating layer.

[0015] Additionally, the second portion of the second insulating layer surrounds the sub-via electrode and is provided between the inner surface of the through hole of the via electrode and the outer surface of the sub-via electrode.

[0016] Additionally, the through hole of the via electrode is spaced apart from the perimeter of the upper surface of the via electrode.

[0017] Additionally, the perimeter of the upper surface of the via electrode includes a plurality of curved portions and a plurality of straight portions provided between the plurality of curved portions, and the plurality of curved portions and the plurality of straight portions have a step along the horizontal direction.

[0018] Additionally, the perimeter of the upper surface of the via electrode includes a plurality of first straight sections and a plurality of second straight sections provided between the plurality of first straight sections, and the plurality of first straight sections and the plurality of second straight sections have steps along the horizontal direction.

[0019] In addition, the side wall of the cavity of the second insulating layer includes a first side wall connected to the upper surface of the second insulating layer and having a first slope, and a second side wall provided between the lower surface of the second insulating layer and the first side wall and having a second slope different from the first slope.

[0020] In addition, the second insulating layer includes a 2-1 insulating layer disposed on the first insulating layer and a 2-2 insulating layer disposed on the 2-1 insulating layer, and the cavity and the via electrode are provided in at least one of the 2-1 insulating layer and the 2-2 insulating layer.

[0021] In addition, the via electrode includes a first via electrode provided in the 2-1 insulating layer and having a plurality of through holes, and a second via electrode arranged to overlap the first via electrode in the 2-2 insulating layer in a vertical direction and having a plurality of through holes.

[0022] In addition, the 2-1 insulating layer has a via hole that overlaps the via electrode in a vertical direction, the 2-2 insulating layer has a protrusion positioned within the via hole of the 2-1 insulating layer, and the via electrode is provided to penetrate from the upper surface of the 2-2 insulating layer to the lower surface of the protrusion of the 2-2 insulating layer.

[0023] In addition, the cavity includes a first portion provided in the 2-1 insulating layer and a second portion provided in the 2-2 insulating layer, and a horizontal width of the first portion of the cavity is different from a horizontal width of the second portion of the cavity.

[0024] In addition, the circuit board further includes a lower pad connected to a lower surface of the via electrode; and an upper pad connected to an upper surface of the via electrode, wherein the lower surface of the upper pad includes a first lower surface in contact with the upper surface of the via electrode, a second lower surface in contact with the upper surface of the sub-via electrode, and a third lower surface provided between the first and second lower surfaces and in contact with the second portion of the second insulating layer.

[0025] Additionally, the lower pad vertically overlaps with the through hole of the via electrode and includes a through hole penetrating the lower pad.

[0026] In addition, the lower pads are provided in multiple numbers and are spaced apart horizontally, and the space between the multiple lower pads overlaps vertically with the through holes of the via electrodes.

[0027] In addition, the cavity further includes a third via electrode provided in the 2-2 insulating layer and vertically overlapping the cavity in the 2-1 insulating layer, and the third via electrode has a plurality of through holes spaced apart from each other in the horizontal direction and penetrating the third via electrode.

[0028] Meanwhile, a circuit board according to an embodiment includes a core layer; a first insulating layer disposed on the core layer; a second insulating layer disposed on the first insulating layer; and a via electrode penetrating the second insulating layer, wherein the via electrode has a plurality of through holes spaced apart in a first horizontal direction and a second horizontal direction different from the first horizontal direction, and a planar shape of the via electrode has a mesh shape in which positions where the plurality of through holes are provided are open.

[0029] In addition, the second insulating layer includes a 2-1 insulating layer disposed on the first insulating layer and a 2-2 insulating layer disposed on the 2-1 insulating layer, at least one of the 2-1 insulating layer and the 2-2 insulating layer has a cavity, and the via electrode includes at least one of a first via electrode disposed on the 2-2 insulating layer and horizontally overlapping the cavity, a second via electrode disposed on the 2-1 insulating layer and horizontally overlapping the cavity or vertically overlapping the first via electrode, and a third via electrode disposed on the 2-1 insulating layer and vertically overlapping the cavity or horizontally overlapping the second via electrode.

[0030] The circuit board of the embodiment may provide via electrodes having improved physical reliability and / or electrical reliability and improved heat dissipation characteristics and / or electrical characteristics.

[0031] That is, the circuit board may include a first insulating layer and a second insulating layer disposed on the first insulating layer. The second insulating layer may have a cavity, and the via electrode may penetrate at least a portion of the second insulating layer so as to horizontally overlap with the cavity of the second insulating layer. At this time, the via electrode may have a through hole. The through hole may penetrate the via electrode from a top surface of the via electrode toward a bottom surface of the via electrode. In addition, the through hole provided in the via electrode may be filled with the second insulating layer. The through hole provided in the via electrode may have a function of controlling a planar area of ​​the via electrode, thereby improving the processability in a process of filling a via hole corresponding to the via electrode with a conductive material, thereby preventing a void from being provided in the via electrode. For example, the inner surface of the through hole of the via electrode can function as a plating bridge in a process of filling the via hole provided in the second insulating layer with a conductive material, thereby ensuring that the via hole is uniformly filled with the conductive material throughout. Furthermore, the through hole provided in the via electrode can have the function of controlling the density of other via electrodes provided in the same layer by adjusting the planar area of ​​the via electrode, thereby solving a warpage problem of the circuit board that may occur due to a difference in density between via electrodes provided at symmetrical positions.

[0032] In addition, the number of through holes provided in the via electrode may be plural. Preferably, the through holes provided in the via electrode may include a plurality of through holes spaced apart in a first horizontal direction and a plurality of through holes spaced apart in a second horizontal direction different from the first horizontal direction. Therefore, compared to a plurality of circular via electrodes and / or bar-shaped via electrodes spaced apart in the first and second horizontal directions of the prior art, the planar area of ​​the via electrode can be maximized within a limited space, and thus the heat dissipation characteristics of the circuit board and / or semiconductor package by the via electrode can be further improved.

[0033] In addition, since the via electrode is provided with a plurality of through holes spaced apart in the first and second horizontal directions, a uniform filling process of a conductive material can be performed in all via holes provided in the circuit board, thereby further improving the mechanical reliability and / or electrical reliability of the via electrode.

[0034] Additionally, a semiconductor element may be placed on the via electrode. Accordingly, the via electrode may vertically overlap with the semiconductor element placed in the cavity, thereby further improving the heat dissipation characteristics of the semiconductor element, thereby enabling the semiconductor element to operate more stably.

[0035] Additionally, the perimeter of the upper surface of the via electrode may have a step, thereby significantly increasing the contact area between the first insulating layer and the via electrode. Accordingly, the embodiment can secure adhesion between the first insulating layer and the via electrode, thereby improving the mechanical reliability and / or electrical reliability of the circuit board and the semiconductor package including the same.

[0036] Additionally, the via electrode may include a first via electrode that overlaps the cavity in a horizontal direction, and a second via electrode that overlaps the cavity in a vertical direction. The first via electrode may be provided in the second insulating layer, and the second via electrode may be provided in the first insulating layer that includes the cavity. Through this, the embodiment can more efficiently dissipate heat generated in a semiconductor element placed within the cavity, thereby enabling the semiconductor element to operate more stably.

[0037] In addition, as an example, the first insulating layer may include a thermosetting material, and the second insulating layer may include a photocurable material. As another example, each of the first and second insulating layers may include a photocurable material. In this case, when the above-described via electrode is provided in the insulating layer including the photocurable material, the design freedom of the via electrode can be further improved. That is, a via hole can be formed in the insulating layer including the photocurable material through an exposure and development process, and the design freedom can be improved compared to a processing method such as a laser process. Furthermore, the embodiment can form the via electrode with a design that can implement optimal heat dissipation performance by taking into consideration the arrangement position of the semiconductor element disposed on the circuit board, etc., and thereby the heat dissipation characteristics of the circuit board and / or the semiconductor package can be further improved. This can enable the semiconductor element to operate more stably.

[0038] In addition, the via electrode is provided so as to penetrate at least a portion of the second insulating layer, thereby horizontally overlapping with a cavity provided in the second insulating layer. At this time, when the cavity is provided in the second insulating layer, the planar area of ​​the second insulating layer in the first build-up layer and the planar area of ​​the second insulating layer in the second build-up layer may be different from each other, and the circuit board may be significantly warped in a specific direction due to the difference in the planar areas therebetween. In this way, by providing a via electrode that horizontally overlaps with the cavity, the difference in the planar areas between the second insulating layer in the first build-up layer and the second insulating layer in the second build-up layer may be alleviated by the via electrode, thereby preventing the circuit board from being significantly warped in a specific direction. Furthermore, the via electrode may horizontally overlap with a semiconductor element disposed within the cavity, thereby improving the rigidity of the circuit board in an area horizontally overlapping with the semiconductor element, thereby enabling the semiconductor element to operate more stably.

[0039] In addition, the second insulating layer may be provided with a plurality of layers, and at least one via electrode may be provided so as to commonly penetrate the plurality of second insulating layers. For example, the second insulating layer may include a 2-1 and a 2-2 insulating layer. In addition, the 2-1 insulating layer may be provided with a via hole, and the 2-2 insulating layer may be provided with a protrusion filling the via hole of the 2-1 insulating layer. In addition, at least one of the via electrodes provided in the 2-2 insulating layer may be provided so as to penetrate from the upper surface of the 2-2 insulating layer to the lower surface of the protrusion of the 2-2 insulating layer. Through this, the embodiment can simplify the manufacturing process of the circuit board and improve the product yield. Furthermore, the embodiment can eliminate a pad that should be provided between the plurality of via electrodes, thereby improving the signal transmission characteristics accordingly.

[0040] In addition, the circuit board of the embodiment may include a core layer, a first insulating layer disposed on the core layer, and a second insulating layer disposed on the first insulating layer. In addition, the first insulating layer may be a thermosetting insulating layer, and the second insulating layer may be a photocurable insulating layer. That is, the circuit board of the embodiment includes a thermosetting insulating layer disposed between the core layer and the photocurable insulating layer. In addition, the thermosetting insulating layer disposed between the core layer and the photocurable insulating layer may function as a buffer layer that buffers stress applied to the circuit board. That is, the core layer improves the rigidity of the circuit board, and the photocurable insulating layer enables miniaturization of the via electrode and / or the circuit layer. In this case, the core layer may have a relatively low elastic modulus and / or thermal expansion coefficient, and the photocurable insulating layer may have a relatively high elastic modulus and / or thermal expansion coefficient. In addition, when a photocurable insulating layer is directly disposed on the core layer, the circuit board may warp significantly in a specific direction due to a difference in elastic modulus and / or thermal expansion coefficient between the core layer and the photocurable insulating layer, making it difficult to stably place semiconductor elements on the circuit board. Therefore, a thermosetting insulating layer having an elastic modulus and / or thermal expansion coefficient greater than those of the core layer and an elastic modulus and / or thermal expansion coefficient less than those of the photocurable insulating layer may be disposed between the core layer and the photocurable insulating layer. Therefore, by disposing the thermosetting insulating layer between the core layer and the photocurable insulating layer, it is possible to prevent the circuit board from warping significantly in a specific direction, enable semiconductor elements to be stably placed on the circuit board, and enable the semiconductor elements to operate stably. Through this, products such as servers to which the circuit board and semiconductor package of the embodiment are applied can be operated stably.In addition, adhesion between the core layer and the thermosetting insulating layer and adhesion between the thermosetting insulating layer and the photocurable insulating layer can be secured, thereby improving the mechanical reliability and / or electrical reliability of the circuit board and the semiconductor package including the same.

[0041] FIG. 1a is a cross-sectional view illustrating a circuit board according to the first embodiment.

[0042] Fig. 1b is an enlarged cross-sectional view of a cavity provided in the second insulating layer of Fig. 1a.

[0043] Figure 1c is a plan view of the via electrode of Figure 1a cut along line A-A'.

[0044] FIG. 2 is a plan view of the via electrode of FIG. 1a cut along line A-A' according to the second embodiment.

[0045] FIG. 3a is a cross-sectional view showing a via electrode of a circuit board according to a third embodiment.

[0046] Fig. 3b is a plan view of the via electrode of Fig. 3a cut along line B-B'.

[0047] FIG. 4a is a cross-sectional view showing a via electrode of a circuit board according to the fourth embodiment.

[0048] FIG. 4b is a drawing combining a plan view of the via electrode of FIG. 4a cut along line C-C' according to the first embodiment and a plan view of the lower pad cut along line D-D'.

[0049] Fig. 4c is a plan view of the lower pad of Fig. 4a cut along line D-D' according to the second embodiment.

[0050] Fig. 5 is a cross-sectional view showing a modified example of the circuit board illustrated in Fig. 1a.

[0051] Fig. 6a is a cross-sectional view showing a via electrode of a circuit board according to the fifth embodiment.

[0052] Figure 6b is a plan view of the lower pad of Figure 6a cut along line E-E'.

[0053] Fig. 7a is a cross-sectional view showing a via electrode of a circuit board according to the sixth embodiment.

[0054] Figure 7b is a plan view of the lower pad of Figure 7a cut along the line F-F'.

[0055] Figure 8 is a cross-sectional view showing a circuit board according to the seventh embodiment.

[0056] Figure 9 is a cross-sectional view showing a circuit board according to the eighth embodiment.

[0057] Fig. 10 is a cross-sectional view showing a circuit board according to the ninth embodiment.

[0058] Fig. 11a is a cross-sectional view showing a circuit board according to the 10th embodiment.

[0059] Figure 11b is a cross-sectional view showing a circuit board according to the 11th embodiment.

[0060] Fig. 11c is a cross-sectional view showing a circuit board according to the 12th embodiment.

[0061] FIG. 11d is a cross-sectional view showing a circuit board according to the 13th embodiment.

[0062] Fig. 12 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0063] Fig. 13 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0064] Fig. 14 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0065] Fig. 15 is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0066] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0067] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0068] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described, and commonly used terms, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0069] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0070] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0071] Additionally, when described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when expressed as "above" or "below", it may include the meaning of the downward direction as well as the upward direction based on one component.

[0072] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0073] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0074]

[0075] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing symbols, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0076]

[0077] Before describing the embodiment, an electronic device (not shown) to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the electronic device is not limited thereto, and it goes without saying that the electronic device may be any other electronic device that processes data.

[0078] An electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to a semiconductor package of the embodiment. Furthermore, the semiconductor package includes a circuit board, a semiconductor element, a bonding portion for electrically connecting the semiconductor element and the circuit board, a resin portion for filling the space between the semiconductor element and the circuit board, and a molding portion for entirely enclosing the semiconductor element.

[0079] Semiconductor devices may include active and / or passive components and may have various functions. Active devices may be in the form of integrated circuits (ICs) in which hundreds to millions of transistors are integrated into a single semiconductor device, and may be, for example, logic chips, memory chips, etc. For example, the logic chip may be an application processor (AP) device including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a set of devices including a specific combination of the above. The memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0080] The semiconductor package of the embodiment may be any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package), but is not limited thereto.

[0081]

[0082] FIG. 1A is a cross-sectional view showing a circuit board according to a first embodiment, FIG. 1B is an enlarged cross-sectional view of a cavity provided in a second insulating layer of FIG. 1A, FIG. 1C is a plan view of a via electrode of FIG. 1A cut along line A-A', FIG. 2 is a plan view of a via electrode of FIG. 1A cut along line A-A' according to a second embodiment, FIG. 3A is a cross-sectional view showing a via electrode of a circuit board according to a third embodiment, FIG. 3B is a plan view of a via electrode of FIG. 3A cut along line B-B', FIG. 4A is a cross-sectional view showing a via electrode of a circuit board according to a fourth embodiment, FIG. 4B is a drawing combining a plan view of a via electrode of FIG. 4A cut along line C-C' according to the first embodiment and a plan view of a lower pad cut along line D-D', and FIG. 4C is a drawing of a second embodiment. 4a is a plan view of the lower pad cut along the D-D' line, FIG. 5 is a cross-sectional view showing a modified example of the circuit board shown in FIG. 1a, FIG. 6a is a cross-sectional view showing a via electrode of a circuit board according to a fifth embodiment, FIG. 6b is a plan view of the lower pad of FIG. 6a cut along the E-E' line, FIG. 7a is a cross-sectional view showing a via electrode of a circuit board according to a sixth embodiment, FIG. 7b is a plan view of the lower pad of FIG. 7a cut along the F-F' line, FIG. 8 is a cross-sectional view showing a circuit board according to a seventh embodiment, FIG. 9 is a cross-sectional view showing a circuit board according to an eighth embodiment, FIG. 10 is a cross-sectional view showing a circuit board according to a ninth embodiment, FIG. 11a is a cross-sectional view showing a circuit board according to a tenth embodiment, FIG. 11b is a cross-sectional view showing a circuit board according to an eleventh embodiment, and FIG. 11c is a cross-sectional view showing a circuit board according to a twelfth embodiment. A cross-sectional view showing a circuit board according to an example, FIG. 11d is a cross-sectional view showing a circuit board according to the 13th embodiment, FIG. 12 is a cross-sectional view showing a semiconductor package according to the first embodiment, and FIG. 13 is a cross-sectional view showing a semiconductor package according to the second embodiment.Fig. 14 is a cross-sectional view showing a semiconductor package according to the third embodiment, and Fig. 15 is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0083]

[0084] Hereinafter, a circuit board and a semiconductor package including the same according to an embodiment will be specifically described with reference to FIGS. 1A to 15.

[0085] Referring to FIG. 1A, the circuit board (100) includes a core layer (101), a first build-up layer (102) disposed on one surface of the core layer (101), and a second build-up layer (103) disposed on the other surface of the core layer (101). Here, the meaning of being disposed on one surface and the other surface should not be understood only as a configuration in direct contact with the one surface and the other surface, but should also be understood as having another configuration between the one surface and the first build-up layer (102), and between the other surface and the second build-up layer (103).

[0086] The core layer (101) is composed of a resin such as epoxy resin or BT (bismaleimide triazine) and a reinforcing material such as glass fiber, and has the function of improving the rigidity of the circuit board (100).

[0087] As the number of terminals of semiconductor devices arranged on a recent circuit board (100) increases, wiring becomes more complex, and accordingly, the thickness of the first and second build-up layers (102, 103) is increasing. Accordingly, the core layer (101) of the present embodiment may have a thickness of 200 μm to 1200 μm in order to improve the overall rigidity of the circuit board (100) and prevent excessive signal loss. A via hole penetrating one surface and the other surface may be formed in the core layer (101). The via hole of the core layer (101) may be formed using a mechanical drilling process or a CO2 laser, etc. When a via hole of the core layer (101) is formed using a mechanical drill, the slope of the inner wall of the via hole may be perpendicular to one surface and / or the other surface of the core layer (101), and when a via hole of the core layer (101) is formed using a CO2 laser, the inner wall of the via hole may have a plurality of concave portions and / or convex portions alternately stacked along the vertical direction. Here, the concave portion may mean a concave area that is concave in a direction away from the horizontal center of the via hole provided in the core layer (101), and the convex portion may mean a protruding and / or convex area that is oriented toward the horizontal center of the via hole provided in the core layer (101). In the case of a via hole formed using a mechanical drilling process, the path for transmitting an electrical signal may be shortened, which may be advantageous for electrical characteristics, and the yield of forming a via hole in a thick core layer (101) may be high, but the process cost may increase. In addition, when forming concave and convex portions on the inner wall of a via hole using a CO2 laser, the thickness of the core via electrode (122) provided on the inner wall of the via hole can be increased in a subsequent process, which has the advantage of lowering the impedance and lowering the process cost. Accordingly, the processing method of the via hole provided in the core layer (101) can be freely and selectively used depending on the application field of the semiconductor package.

[0088] A core via electrode (122) may be arranged within the via hole of the core layer (101). The core via electrode (122) functions to electrically connect the first build-up layer (102) and the second build-up layer (103). Therefore, it is desirable for the core via electrode (122) to densely fill the via hole for resistance or heat dissipation. However, when the thickness of the core layer (101) becomes thick as described above, it may become difficult for the core via electrode (122) to densely fill the via hole. For example, when attempting to fill the via hole provided in the thick core layer (101) as described above according to the plating process, a void may occur within the core via electrode (122). The void expands due to heat generated during the operation of the semiconductor package, which becomes a factor that lowers the mechanical reliability of the circuit board. Accordingly, a core via electrode (122) having a predetermined thickness is arranged on the inner wall of the via hole of the core layer (101). The thickness of the core via electrode (122) refers to the thickness in the horizontal direction perpendicular thereto, not the thickness in the vertical direction in which the first build-up layer (102), the core layer (101), and the second build-up layer (103) are laminated. The thickness of the core via electrode (122) may be arranged to have a thickness of 5 μm to 20 μm in order to prevent a voltage drop that occurs as the thickness of the core layer (101) increases and to prevent the occurrence of voids. It is difficult to densely fill the inside of the core via electrode (122) with metal through a process such as plating, resulting in the creation of empty spaces. The empty spaces may cause a problem in that it is difficult to evenly arrange the first build-up layer (102) when laminating the first build-up layer (102).

[0089] Accordingly, the insulating member (123) can be arranged on the inner side of the core via electrode (122), thereby ensuring the flatness of the core layer (101). The upper surface of the insulating member (123) can be on the same plane as the upper surface of the core layer (101), or can be arranged closer to the first build-up layer (102) in the vertical direction than the upper surface of the core layer (101). The lower surface of the insulating member (123) can be on the same plane as the lower surface of the core layer (101), or can be arranged closer to the second build-up layer (103) in the vertical direction than the lower surface of the core layer (101). This can be freely designed to solve the flatness when laminating the first build-up layer (102) and the second build-up layer (103), or to ensure the flatness of the first circuit layer (110) and / or the fourth circuit layer (113) to be described later.

[0090] A first build-up layer (102) is arranged on one side of the core layer (101). The first build-up layer (102) includes a plurality of insulating layers (104, 105), a plurality of circuit layers (110, 111, 112), a plurality of via electrodes (1116, 117), and a first protective layer (108).

[0091] The plurality of circuit layers (110, 111, 112) of the first build-up layer (102) may include a first circuit layer (110) arranged closest to the core layer (101) in a vertical direction, a second circuit layer (111) arranged further apart from the core layer (101) in a vertical direction than the first circuit layer (110), and a third circuit layer (112) arranged further apart from the core layer (101) in a vertical direction than the second circuit layer (111).

[0092] The first to third circuit layers (110, 111, 112) may function to electrically connect with semiconductor elements arranged on a circuit board (100). Each of the first to third circuit layers (110, 111, 112) may be freely designed in consideration of impedance. Each of the first to third circuit layers (110, 111, 112) may include traces for transmitting signals and / or power, and pads for connecting the traces of each of the first to third circuit layers (110, 111, 112) to other components. For example, referring to FIG. 1A, the first circuit layer (110) and the second circuit layer (111) may be connected by a first via electrode (116). At this time, in order to connect the traces of the first via electrode (116) and the second circuit layer (111), the second circuit layer (111) may include a plurality of pads connected to the first via electrode (116), and the plurality of pads of the second circuit layer (111) may include a first pad (111P1) that vertically overlaps a cavity (105C) provided in the second insulating layer (105) to be described later. In addition, the second circuit layer (111) may include pads connected to the second via electrode (117). The second via electrode (117) may include a 2-1 via electrode (118) and a signal and / or 2-2 via electrode (119) depending on the size, function, and / or arrangement position. And, the second circuit layer (111) may include a second pad (111P2) that is connected to a pad of the third circuit layer (112) through a 2-1 via electrode (118) or that connects a trace of the second circuit layer (111) and the 2-1 via electrode (118). In addition, the second circuit layer (111) may include a third pad (111P3) that is connected to a pad of the third circuit layer (112) through a 2-2 via electrode (119) or that connects a trace of the second circuit layer (111) and the 2-2 via electrode (119).In addition, the third circuit layer (112) may include a fourth pad (112P1) that is connected to the second circuit layer (111) through the 2-1 via electrode (118) or that connects the trace of the 2-1 via electrode (118) and the third circuit layer (112). In addition, the third circuit layer (112) may include a fifth pad (112P2) that is connected to the second circuit layer (111) through the 2-2 via electrode (119) or that connects the trace of the 2-2 via electrode (119) and the third circuit layer (112). That is, although FIG. 1A illustrates only the pads of the first to third circuit layers (110, 111, 112), each of the first to third circuit layers (110, 111, 112) may further include traces that connect between a plurality of pads.

[0093] In addition, via electrodes (116, 117) may be arranged to connect the first to third circuit layers (110, 111, 112), respectively. For example, the first via electrode (116) is arranged between the first circuit layer (110) and the second circuit layer (111), and the second via electrode (117) is arranged between the second circuit layer (111) and the third circuit layer (112), thereby electrically connecting the first to third circuit layers (110, 111, 112). The first and second via electrodes (116, 117) may be arranged simultaneously in the process of arranging the second and third circuit layers (111, 112). For example, in the process of placing the second circuit layer (111) on the first circuit layer (110), a through hole may be formed in the first insulating layer (104) described later to expose a portion of the first circuit layer (110), and the second circuit layer (111) may be placed together with the first via electrode (116) filling the through hole of the first insulating layer (104). Accordingly, the first via electrode (116) may be distinguished by a protrusion of the second circuit layer (111). Similarly, the second via electrode (117) may be distinguished by a protrusion of the third circuit layer (112) and may be connected to the second circuit layer (111) placed under the third circuit layer (112). The second via electrodes (116, 117) may be divided into a 2-1 via electrode (118) and a 2-2 via electrode (119) depending on the size and / or function and / or arrangement position. The size of the 2-1 via electrode (118) may be larger than the size of the 2-2 via electrode (119). Here, the size may mean the width and / or area of ​​the upper surface and the width and / or area of ​​the lower surface of each of the 2-1 via electrode (118) and the 2-2 via electrode (119). The width and / or area of ​​the upper surface and / or lower surface of the 2-1 via electrode (118) may be larger than the width and / or area of ​​the upper surface and / or lower surface of the 2-2 via electrode (119).For example, the 2-1 via electrode (118) may have a function of transmitting heat, and the 2-2 via electrode (119) may have a function of transmitting signals and / or power, but the present invention is not limited thereto. Here, the 2-1 via electrode (118) and the 2-2 via electrode (119) may be distinguished by function as described above, or may be distinguished by configuration. For example, the 2-1 via electrode (118) may have a configuration having a plurality of through holes penetrating the upper and lower surfaces of the via electrode, and the 2-2 via electrode (119) may have a configuration in which a via electrode connected to one pad does not have a through hole. The detailed structures of the 2-1 via electrode (118) and the 2-2 via electrode (119) will be described later.

[0094] In addition, since the first to third circuit layers (110, 111, 112) are sequentially laminated along the vertical direction on the upper surface of the core layer (101), the slope directions of each of the first via electrode (116) and the second via electrode (117) may be the same. For example, each of the first via electrode (116) and the second via electrode (117) may have a slope in which the width in the horizontal direction gradually increases in the direction from the core layer (101) toward the first protective layer (108).

[0095] The first circuit layer (110) may be in contact with one surface of the core layer (101). In this case, a part of the first circuit layer (110) may be arranged to cover the insulating member (123) described above. The part of the first circuit layer (110) that covers the insulating member (123) may be thinner than the remaining parts that do not vertically overlap with the insulating member (123). Here, the thickness of the first circuit layer (110) refers to the thickness in the vertical direction. When designing the first circuit layer (110), the insulating member (123) may be covered or not covered depending on the degree of freedom of wiring, and thus the freedom of wiring connection may be increased. When the first circuit layer (110) does not cover the insulating member (123), the insulating member (123) may be in direct contact with the first insulating layer (104). When the first circuit layer (110) and the first insulating layer (104) are in direct contact with each other, the bonding strength may be better and heat dissipation may be advantageous compared to when the insulating member (123) and the first insulating layer (104) are in direct contact with each other. However, in order to reduce the process cost, the first circuit layer (110) may be arranged so as not to cover the insulating member (123).

[0096] The plurality of insulating layers (104, 105) of the first build-up layer (102) may include a first insulating layer (104) arranged most adjacent to the core layer (101) in a direction perpendicular to the core layer (101), and a second insulating layer (105) arranged further apart from the first insulating layer (104) in a direction perpendicular to the core layer (101).

[0097] The first insulating layer (104) and the second insulating layer (105) are arranged to vertically insulate between the first to third circuit layers (110, 111, 112) described above. In one embodiment, the first insulating layer (104) may be formed of a thermosetting insulating material containing an inorganic filler in a thermosetting resin, and as an example, Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Ltd. may be used. In another embodiment, the first insulating layer (104) may be formed of a thermosetting insulating material containing an inorganic filler and a reinforcing member (e.g., glass fiber) in a thermosetting resin, and as an example, prepreg (PPG) may be used. Although FIG. 1A illustrates that the first insulating layer (104) is implemented as a single layer, it is not limited thereto, and the first insulating layer (104) may be provided in two or more layers between the core layer (101) and the second insulating layer (105). In addition, when the first insulating layer (104) is provided in two or more layers, all of the two first insulating layers (104) may be implemented as a thermosetting insulating material that does not have a reinforcing member, or may be implemented as a thermosetting insulating material that does not have a reinforcing member, or may be implemented as a thermosetting insulating material that has a reinforcing member and a thermosetting insulating material that does not have a reinforcing member are laminated in a vertical direction.

[0098] The second insulating layer (105) may be disposed on the first insulating layer (104). The second insulating layer (105) may use a photocurable insulating material containing an inorganic filler in a photocurable insulating resin. For example, a PID (Photo Imageable Dielectric, PID) may be used as the second insulating layer (105). The second insulating layer (105) may include an epoxy resin, a photoinitiator, a silicon-based filler (Si filler), a curing agent, and the like. The second insulating layer (105) may be formed by laminating a photocurable resin film or applying a photocurable resin paste or liquid. At this time, in one example, the photocurable insulating material constituting the second insulating layer (105) may include at least one selected from photocurable polyhydroxystyrene (PHS), photocurable polybenzoxazole (PBO), photocurable polyimide (PI), photocurable benzocyclobutene (BCB), photocurable polysiloxane, photocurable epoxy, and novolac resin. Unlike the first insulating layer (104), the second insulating layer (105) can form a through hole through an exposure and development process, and thus, the width of the via electrode in the horizontal direction can be made finer, and further, the width and / or pitch of the circuit layer connected to the via electrode can be made finer. Furthermore, the second insulating layer (105) is an insulating layer positioned closest to a semiconductor element disposed on the circuit board among a plurality of insulating layers stacked along a vertical direction on the circuit board (100), and accordingly, miniaturization of the second via electrode (117) and / or the third circuit layer (112) provided in the second insulating layer (105) is required. For example, the third circuit layer (112) may have a pad connected to the semiconductor element, and the pad connected to the semiconductor element is required to be miniaturized. Therefore, by positioning the second insulating layer (105) closest to the semiconductor element, miniaturization of the second via electrode (117) and / or the third circuit layer (112) is possible.

[0099] The first insulating layer (104) provided between the core layer (101) and the second insulating layer (105) can function as a buffer layer that cushions the stress applied to the circuit board (100). That is, the core layer (101) improves the rigidity of the circuit board (100), and the second insulating layer (105) enables miniaturization of the via electrode and / or the circuit layer. At this time, the core layer (101) may have a relatively low elastic modulus and / or thermal expansion coefficient, and the second insulating layer (105) may have a relatively high elastic modulus and / or thermal expansion coefficient. In addition, when the second insulating layer (105) is directly disposed on the core layer (101), the circuit board (100) may be significantly warped in a specific direction due to the difference in elastic modulus and / or thermal expansion coefficient between the core layer (101) and the second insulating layer (105), making it difficult for the semiconductor element to be stably disposed on the circuit board (100). In addition, the circuit board (100) may cause each component to expand and / or contract due to heat generated during the manufacturing process and / or operating environment. If the second insulating layer (105) is placed directly on the core layer (101), stress may be concentrated at the interface between the core layer (101) and the second insulating layer (105) due to differences in elastic modulus and / or thermal expansion coefficient, which may cause mechanical reliability problems such as peeling.

[0100] The first insulating layer (104) may be disposed between the core layer (101) and the second insulating layer (105) and may function as a buffer layer that buffers the difference between the elastic coefficient and / or thermal expansion coefficient of the core layer (101) and the elastic coefficient and / or thermal expansion coefficient of the second insulating layer (105). Specifically, the elastic coefficient and / or thermal expansion coefficient of the first insulating layer (104) may have a value between the elastic coefficient and / or thermal expansion coefficient of the core layer (101) and the elastic coefficient and / or thermal expansion coefficient of the second insulating layer (105). By disposing the first insulating layer (104) between the core layer (101) and the second insulating layer (105), it is possible to prevent the circuit board (100) from being significantly warped in a specific direction, to allow the semiconductor element to be stably disposed on the circuit board (100), and to allow the semiconductor element to operate stably. Through this, products such as servers to which the circuit board and semiconductor package of the embodiment are applied can be ensured to operate stably. In addition, adhesion between the core layer (101) and the first insulating layer (104) and adhesion between the first insulating layer (104) and the second insulating layer (105) can be secured, thereby improving the mechanical reliability and / or electrical reliability of the circuit board and the semiconductor package including the same.

[0101] In addition, recently, as the functions provided by semiconductor devices increase and the performance of semiconductor devices improves, the number of I / O terminals provided in semiconductor devices is also increasing. Accordingly, more heat may be generated in the semiconductor devices, and higher heat dissipation characteristics of the circuit board on which the semiconductor devices are placed are required. Accordingly, the circuit board is provided with a via electrode that functions as a heat dissipation function, and the above-described via electrode can be provided by filling a via hole formed through a laser process with a conductive material. However, there are restrictions on the design of the via hole that can be formed in the insulating layer depending on the laser process capability, and forming the via hole may take a lot of time and / or cost, or the product yield or heat dissipation characteristics may be reduced. Therefore, the embodiment includes a second insulating layer (105) and forms a via hole for placing the via electrode in the second insulating layer (105). At this time, a via hole is formed in the second insulating layer (105) through an exposure and development process, and accordingly, the via hole is formed in a design that can implement optimal heat dissipation performance depending on the arrangement position of the semiconductor element placed on the circuit board, thereby improving the heat dissipation characteristics of the circuit board and / or semiconductor package. This allows the semiconductor element to operate more stably.

[0102] In addition, the second insulating layer (105) may have a cavity (105C). The cavity (105C) may penetrate the upper and lower surfaces of the second insulating layer (105). The cavity (105C) may be formed together with the through hole in a process of forming a through hole corresponding to the second via electrode (117) in the second insulating layer (105). In addition, the cavity (105C) may be formed by exposing and developing the second insulating layer (105), thereby removing a metal member, such as a laser stopper, which must be provided on the bottom surface of the cavity in order to form the cavity (105C) through a laser process. At this time, the metal member is provided in a closed loop shape along the circumferential direction of the bottom surface of the cavity (105C), and accordingly, when the metal member is provided, it is difficult to arrange a trace that directly connects between the first pad (111P1) that vertically overlaps the cavity (105C) and the second pad (111P2) and / or the third pad (111P3) that do not vertically overlap the cavity (105C) due to the electrical short circuit problem with the metal member described above. In contrast, it is possible to form a cavity (105C) in the second insulating layer (105) to remove the metal member, and through this, it is possible to arrange a trace that directly connects between the second pad (111P2) and / or the third pad (111P3) together with the first pad (111P1). Therefore, the circuit integration can be improved, and the signal transmission distance between a plurality of pads can be reduced to minimize signal transmission loss.

[0103] The cavity (105C) provides a space in which a connecting member and / or a semiconductor element is mounted. Recently, as the number of signals that a semiconductor element must process increases, the size of the semiconductor element is trending toward a larger area, but this larger area of ​​the semiconductor element is causing a problem of lowering the yield of the semiconductor element. Therefore, there is a trend of dividing the pattern size or functional part of the semiconductor element, arranging chiplets on a circuit board (100), and embedding a connecting member that has the function of electrically connecting them within the circuit board (100). In addition, the connecting member may be arranged within the cavity (105C). However, the embodiment is not limited thereto, and the connecting member arranged within the cavity (105C) may also connect the semiconductor element with a semiconductor element having another function, such as a memory. In addition, a semiconductor element may also be arranged within the cavity (105C). The connecting member and / or semiconductor element may be arranged in the cavity (105C) provided in the second insulating layer (105), so that the vertical thickness of the circuit board (100) can be reduced by the depth of the cavity (105C) compared to when the connecting member and / or semiconductor element is arranged on the circuit board (100). In addition, a plurality of connecting members and / or semiconductor elements may be arranged on the circuit board (100). At this time, among the plurality of connecting members and / or semiconductor elements, a connecting member and / or semiconductor element having a relatively large vertical thickness may be arranged in the cavity (105C) provided in the second insulating layer (105), thereby reducing the vertical thickness of the circuit board (100).

[0104] According to the embodiment of FIG. 1B, the cavity (105C) provided in the second insulating layer (105) may include a side wall (105C1) and a bottom surface (105). The cavity (105C) is provided so as to penetrate the second insulating layer (105), and accordingly, the bottom surface (105) of the cavity (105C) may be formed as the upper surface of the first insulating layer (104). The side wall (105C1) of the cavity (105C) may be provided with a slope such that the width in the horizontal direction changes from the upper surface of the second insulating layer (105) toward the lower surface of the second insulating layer (105). The side wall (105C1) of the cavity (105C) may include a first side wall (105C11) connected to the upper surface of the second insulating layer (105) and a second side wall (105C12) provided between the first side wall (105C11) and the lower surface of the second insulating layer (105). The first side wall (105C11) may be inclined so that the horizontal width of the cavity (105C) gradually decreases along a direction from the upper surface of the second insulating layer (105) toward the second insulating layer (105). The second side wall (105C12) may be connected to the first side wall (105C11) and may have an inclination angle different from the inclination angle of the first side wall (105C11). The second side wall (105C12) may have an inclination angle such that there is little change in the width in the horizontal direction of the cavity (105C) along the direction from the upper surface of the second insulating layer (105) toward the lower surface of the second insulating layer (105). The inclination angle of the second side wall (105C12) may be closer to 90° than the inclination angle of the first side wall (105C11). In addition, the second side wall (105C12) may be provided closer to the first pad (111P1) that vertically overlaps the cavity (105C) than the first side wall (105C11). This allows the connecting member and / or semiconductor element to be placed at an accurate position during the process of placing the connecting member and / or semiconductor element within the cavity (105C), and allows the connecting member and / or semiconductor element to be stably coupled to the first pad (111P1).If the positions of the first side wall (105C11) and the second side wall (105C12) are switched, the semiconductor element may come into contact with the first side wall (105C11) having a relatively gentle inclination angle during the process of arranging the connecting member and / or the semiconductor element, and as a result, the semiconductor element may not be stably arranged. In addition, if the width of the cavity (105C) is increased to solve this problem, the circuit integration may be reduced because the third circuit layer (112) may not be arranged in an area vertically overlapping with the cavity (105C). Through this, the embodiment can ensure that the connecting member and / or the semiconductor element are arranged at an accurate position without increasing the width of the cavity (105C).

[0105] The first protective layer (108) can protect the third circuit layer (118) from external moisture or contaminants. In addition, when a semiconductor element is arranged on a circuit board (100) using a material such as solder, the first protective layer (108) functions to prevent short circuits between adjacent solders due to low wettability with the solder. The first protective layer (108) may be formed using a photocurable insulating material, and for example, a solder resist may be used. Referring to FIG. 1B, the first protective layer (108) may have a through hole (108T) that vertically overlaps the cavity (105C). The through hole (108T) may have a width in a horizontal direction that is different from the width in the horizontal direction of the cavity (105C). For example, the width of the through hole (108T) of the first protective layer (108) in the horizontal direction may be greater than the width of the cavity (105C) on the upper surface of the second insulating layer (105) in the horizontal direction. For example, the side wall of the through hole (108T) of the first protective layer (108) may have a step with the first side wall (105C11) and the second side wall (105C12) of the cavity (105C). Through this, the adhesion between the molding member and the second insulating layer (105) and the first protective layer (108) can be improved during the process of filling the cavity (105C) with the molding member.

[0106] A second build-up layer (103) is arranged on the other side of the core layer (101). The second build-up layer (103) includes a plurality of insulating layers (106, 107), a plurality of circuit layers (113, 114, 115), and a second protective layer (109).

[0107] The plurality of circuit layers (113, 114, 115) of the second build-up layer (103) may include a fourth circuit layer (113) arranged closest to the core layer (101) in the vertical direction, a fifth circuit layer (114) arranged further apart from the core layer (101) in the vertical direction than the fourth circuit layer (113), and a sixth circuit layer (115) arranged further apart from the core layer (101) in the vertical direction than the fifth circuit layer (114).

[0108] The fourth to sixth circuit layers (113, 114, 115) may function to electrically connect with a semiconductor package substrate and / or a main board of an electronic device that is coupled to the circuit board (100). Each of the fourth to sixth circuit layers (113, 114, 115) may be freely designed in consideration of impedance. Each of the fourth to sixth circuit layers (113, 114, 115) may include traces for transmitting signals and / or power, etc., and pads for connecting the traces of each of the fourth to sixth circuit layers (113, 114, 115) to other components.

[0109] In addition, via electrodes (120, 121) may be arranged to connect the fourth to sixth circuit layers (113, 114, 115), respectively. For example, the third via electrode (120) is arranged between the fourth circuit layer (113) and the fifth circuit layer (114), and the fourth via electrode (121) is arranged between the fifth circuit layer (114) and the sixth circuit layer (115), thereby electrically connecting the fourth to sixth circuit layers (113, 114, 115). The third and fourth via electrodes (120, 121) may be arranged simultaneously in the process of arranging the fifth and sixth circuit layers (114, 115). For example, in the process of arranging the fifth circuit layer (114) under the fourth circuit layer (113), a through hole may be formed in the first insulating layer (106) of the second build-up layer (103) described later to expose a portion of the fourth circuit layer (113), and the fifth circuit layer (114) may be arranged together with a third via electrode (120) filling the through hole of the first insulating layer (106). Accordingly, the third via electrode (120) may be distinguished by a protrusion of the fifth circuit layer (114). Similarly, the fourth via electrode (121) may be distinguished by a protrusion of the sixth circuit layer (115) and may be connected to the fifth circuit layer (114) arranged on the sixth circuit layer (115).

[0110] In addition, since the fourth to sixth circuit layers (113, 114, 115) are sequentially laminated along the vertical direction on the lower surface of the core layer (101), the inclination directions of each of the third via electrode (120) and the fourth via electrode (121) may be the same. For example, each of the third via electrode (120) and the fourth via electrode (121) may have an inclination in which the width in the horizontal direction gradually increases in the direction from the core layer (101) toward the second protective layer (109).

[0111] The fourth circuit layer (113) may be in contact with one surface of the core layer (101). In this case, a part of the fourth circuit layer (113) may be arranged to cover the insulating member (123) described above. The part of the fourth circuit layer (113) that covers the insulating member (123) may be thinner than the remaining parts that do not vertically overlap with the insulating member (123). Here, the thickness of the fourth circuit layer (113) refers to the thickness in the vertical direction. When designing the fourth circuit layer (113), the insulating member (123) may be covered or not covered depending on the degree of freedom of wiring, and thus the freedom of wiring connection may be increased. When the fourth circuit layer (113) does not cover the insulating member (123), the insulating member (123) may be in direct contact with the first insulating layer (106). Compared to the case where the insulating member (123) and the first insulating layer (106) are in direct contact, the case where the fourth circuit layer (113) and the first insulating layer (106) are in contact with each other may have better bonding strength and may be advantageous for heat dissipation. However, in order to reduce the process cost, the fourth circuit layer (113) may be arranged so as not to cover the insulating member (123).

[0112] The plurality of insulating layers (106, 107) of the second build-up layer (103) may include a third insulating layer (106) arranged most adjacent to the core layer (101) in a direction perpendicular to the core layer (101), and a fourth insulating layer (107) arranged further apart from the third insulating layer (106) in a direction perpendicular to the core layer (101).

[0113] The third insulating layer (106) and the fourth insulating layer (107) of the second build-up layer (103) are arranged to vertically insulate between the fourth to sixth circuit layers (113, 114, 115) described above. In one embodiment, the third insulating layer (106) may be formed using a thermosetting insulating material containing an inorganic filler in a thermosetting resin, and for example, Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Ltd. may be used. In another embodiment, the third insulating layer (104) may be formed using a thermosetting insulating material containing an inorganic filler and a reinforcing member (e.g., glass fiber) in a thermosetting resin, and for example, prepreg (PPG) may be used. Although FIG. 1A illustrates that the third insulating layer (106) is implemented as a single layer, it is not limited thereto, and the third insulating layer (106) may be provided in two or more layers between the core layer (101) and the fourth insulating layer (107) of the second build-up layer (103). In addition, when the third insulating layer (106) is provided in two or more layers, all of the third insulating layers (106) of the two layers may be implemented as a thermosetting insulating material that does not have a reinforcing member, or may be implemented as a thermosetting insulating material that does not have a reinforcing member, or may be implemented as a thermosetting insulating material that has a reinforcing member and a thermosetting insulating material that does not have a reinforcing member are laminated in a vertical direction. The fourth insulating layer (107) of the second build-up layer (103) may be disposed on the lower surface of the third insulating layer (106) of the second build-up layer (103). The fourth insulating layer (107) may be formed using a photocurable insulating material containing an inorganic filler in a photocurable insulating resin. For example, a PID (Photo Imageable Dielectric) may be used as the photocurable insulating layer (107). The fourth insulating layer (107) may include an epoxy resin, a photoinitiator, a silicon-based filler (Si filler), a curing agent, and the like. The fourth insulating layer (105) may be formed by laminating a photocurable resin film or applying a photocurable resin paste or liquid.At this time, in one example, the photocurable insulating material constituting the fourth insulating layer (105) may include at least one selected from photocurable polyhydroxystyrene (PHS), photocurable polybenzoxazole (PBO), photocurable polyimide (PI), photocurable benzocyclobutene (BCB), photocurable polysiloxane, photocurable epoxy, and novolac resin. The plurality of insulating layers (106, 107) of the second build-up layer (103) may have a symmetrical structure with respect to the plurality of insulating layers (104, 105) of the first build-up layer (102) with respect to the core layer (101). Accordingly, the third insulating layer (106) of the second build-up layer (103) may be provided at a position symmetrical to the first insulating layer (104) of the first build-up layer (102) with respect to the core layer (101), and the fourth insulating layer (107) of the second build-up layer (103) may be provided at a position corresponding to the second insulating layer (105) of the first build-up layer (102) with respect to the core layer (101). Through this, the problem of warping of the circuit board that may occur due to the asymmetrical structure of the multiple insulating layers (104, 105) of the first build-up layer (102) and the multiple insulating layers (106, 107) of the second build-up layer (103) with respect to the core layer (101) can be solved by the problem of stress being concentrated in a specific area, but the embodiment is not limited thereto. For example, based on the core layer (101), the plurality of insulating layers (104, 105) of the first build-up layer (102) and the plurality of insulating layers (106, 107) of the second build-up layer (103) may have an asymmetrical structure, and the problem of warping of the circuit board or stress concentration in a specific area can be solved through design changes such as the thickness of each insulating layer provided on the circuit board, the thickness of each circuit layer and / or the wiring density, the thickness of the first protective layer (108), and the thickness of the second protective layer (109).

[0114] The second protective layer (109) can protect the third circuit layer (118) from external moisture or contaminants. In addition, when semiconductor elements are arranged on the circuit board (100) using a material such as solder, the second protective layer (109) functions to prevent short circuits between adjacent solders due to low wettability with the solder. The second protective layer (109) can be formed using a photocurable insulating material, and for example, a solder resist can be used.

[0115] The structure of the circuit board (100) described above is only an example for explaining the present invention, and the technical idea of ​​the present invention is not limited to the laminated structure of the present embodiment.

[0116] Recently, as the functions provided by semiconductor devices increase and their performance improves, the number of I / O terminals provided in semiconductor devices is increasing and the size of semiconductor devices is also increasing. Accordingly, the heat generation of semiconductor devices is increasing, and the heat dissipation characteristics of circuit boards are required to have higher heat dissipation characteristics. However, as described above, via electrodes formed by filling via holes formed through a laser process with a metal material have limitations in improving heat dissipation characteristics. Specifically, after forming multiple via holes using a laser process, each via hole can be filled with a conductive material so that multiple via electrodes connected to a single pad are interconnected. However, due to the nature of the laser process, the number of laser processes must be adjusted to match the number of via holes, which can increase manufacturing time and lower product yield. Furthermore, the shape of the via hole formed through the laser process is dependent on the waveform of the laser beam, which can reduce the design freedom of the via hole. In contrast, the embodiment forms a via hole in the second insulating layer (105), and then fills the via hole with a conductive material to form a via electrode (118). At this time, the via hole can be formed by performing an exposure process and a development process on the second insulating layer (105), thereby reducing the process time for forming the via hole and the via electrode (118), improving the product yield, and enabling the via hole and the via electrode (118) to be designed to have optimal heat dissipation performance according to the product design, thereby maximizing the heat dissipation characteristics while improving the design freedom.However, the embodiment is not limited to forming the via electrode (118) described above only in the second insulating layer (105), and if it is possible to form a via electrode corresponding to the structure of the via electrode (118) described below in the first insulating layer (114) depending on the laser process capability, the via electrode (118) described below may also be formed in the first insulating layer (105), and in this case, the via electrode provided in the first insulating layer (105) may be provided to overlap with the cavity provided in the second insulating layer (106) in the vertical direction.

[0117] The heat dissipation performance may increase in proportion to the planar area of ​​the via electrode (118). For example, as the planar area of ​​the via electrode (118) increases, the heat dissipation characteristics may be improved, and as the planar area of ​​the via electrode (118) decreases, the heat dissipation characteristics may be deteriorated. Accordingly, the planar area of ​​the via electrode (118) may be increased to improve the heat dissipation characteristics. However, if the planar area of ​​the via electrode (118) is simply increased, the planar area of ​​the via hole may also increase correspondingly, making it difficult to densely fill the via hole with a metal material, and thus, an empty space such as a void may be formed in the via electrode (118). In addition, the empty space formed in the via electrode (118) may act as a factor that deteriorates the heat dissipation characteristics, and warpage of the semiconductor package substrate may occur as a part where the electrode density is locally high is formed. When the planar area of ​​the via hole is increased to increase the planar area of ​​the via electrode (118), the heat dissipation characteristics may be improved, but as the planar area of ​​the via hole increases, it may be difficult to densely fill the inside of the via hole with a conductive material. In addition, the circuit board may be significantly warped in a specific direction depending on the difference in the wiring density of the via electrodes and circuit layers provided in each layer. For example, the circuit board may be significantly warped in a specific direction depending on the difference in wiring density between the first circuit layer (110) and the fourth circuit layer (113), the difference in wiring density between the second circuit layer (111) and the fifth circuit layer (114), the difference in wiring density between the third circuit layer (112) and the sixth circuit layer (115), the difference in wiring density between the first via electrode (116) and the third via electrode (120), and the difference in wiring density between the second via electrode (117) and the fourth via electrode (121).And, when a via electrode (118) is provided in the second insulating layer (105) of the first build-up layer (102), the wiring density of the second via electrode (117) may be greater than the wiring density of the fourth via electrode (121), which may cause the circuit board to be convexly bent upward or concavely bent downward. Therefore, when the planar area of ​​the via electrode (118) is simply increased, the circuit board (100) may be significantly bent in a specific direction, along with the problem of a void being provided in the above-described via electrode (118). Therefore, the embodiment provides a via electrode (118) having a structure that can significantly improve heat dissipation characteristics, prevent a void from being provided in the via electrode (118), and prevent the circuit board from being significantly bent in a specific direction.

[0118] Referring to FIG. 1C, a via electrode (118) may be provided from the upper surface of the second insulating layer (105) toward the lower surface, penetrating at least a portion of the via electrode (118). The upper surface of the via electrode (118) may be connected to the fourth pad (112P1) of the third circuit layer (112). The upper surface of the via electrode (118) may be located on the same plane as the upper surface of the second insulating layer (105). That is, a via hole corresponding to the via electrode (118) may be provided from the upper surface of the second insulating layer (105) to penetrate a portion of the second insulating layer (105). Through this, when the second insulating layer (105) is used as a photocurable material, an exposure process and a development process for forming a via hole can be performed on the upper surface of the second insulating layer (105), thereby avoiding a laser process for forming a cavity and a via hole, thereby preventing the problem of the inorganic filler and / or glass fiber of the lower insulating layer being exposed, and improving the electrical reliability that occurs when the via electrode (118) comes into contact with the inorganic filler and / or glass fiber later.

[0119] The via electrode (118) is provided to penetrate at least a portion of the second insulating layer (105), and thereby overlaps horizontally with the cavity (105C) provided in the second insulating layer (105). At this time, when the cavity (105C) is provided in the second insulating layer (105), the planar area of ​​the second insulating layer (105) in the first build-up layer (102) and the planar area of ​​the fourth insulating layer (107) in the second build-up layer (103) may be different from each other, and the circuit board may be greatly warped in a specific direction due to the difference in the planar areas therebetween. Through this, by providing a via electrode (118) that is horizontally overlapped with the cavity (105C), the difference in planar area between the second insulating layer (105) in the first build-up layer (102) and the fourth insulating layer (107) in the second build-up layer (103) can be alleviated by the difference in wiring density between the second via electrode (117) having the via electrode (118) and the fourth via electrode (121), thereby preventing the circuit board from being significantly bent in a specific direction. Furthermore, the via electrode (118) can also function as a reinforcing member that improves the rigidity of the circuit board (100). At this time, a connecting member and / or a semiconductor element may be arranged in the cavity (105C), and the via electrode (118) can improve the rigidity of the circuit board in an area that horizontally overlaps with the connecting member and / or the semiconductor element, thereby allowing the connecting member and / or the semiconductor element to operate more stably.

[0120] The via electrode (118) has a through hole (118T). The through hole (118T) can penetrate the via electrode (118) from the upper surface of the via electrode (118) toward the lower surface of the via electrode (118). In addition, the through hole (118T) provided in the via electrode (118) can be filled with a second insulating layer (105). That is, the through hole (118T) provided in the via electrode (118) can mean a portion in the second insulating layer (105) where a via hole is not formed. The through hole (118T) provided in the via electrode (118) can have a function of controlling the planar area of ​​the via electrode (118), and thereby, by filling the via hole with a conductive material, the processability can be improved, and voids can be prevented from being formed in the via electrode (118). For example, the inner surface of the through hole (118T) can function as a plating bridge in the process of filling the via hole with a conductive material, thereby ensuring that the via hole is uniformly filled with the conductive material throughout. Furthermore, the through hole (118T) provided in the via electrode (118) can have the function of controlling the wiring density of the second via electrode (117) by adjusting the planar area of ​​the via electrode (118), thereby solving the problem of warping of the circuit board that may occur due to the difference in wiring density between the second via electrode (117) and the fourth via electrode (118).

[0121] The number of through holes (118T) provided in the via electrode (118) may be plural. Preferably, the through holes (118T) provided in the via electrode (118) may include a plurality of through holes spaced apart in a first horizontal direction and a plurality of through holes spaced apart in a second horizontal direction different from the first horizontal direction. Accordingly, the via electrode (118) may have an overall plate-like planar shape, and may have a structure in which a plurality of through holes (118T) spaced apart in the first and second horizontal directions are formed. That is, the planar shape of the via electrode (118) may have a mesh shape including the through holes (118T). Therefore, compared to the thermal via electrode having a plurality of circular thermal vias and / or bar-shaped thermal vias spaced apart in the first and second horizontal directions of the prior art, the via electrode (118) can maximize the plane area within a limited space, and thus the heat dissipation characteristics of the circuit board and / or semiconductor package by the via electrode (118) can be further improved. In addition, since the via electrode (118) is provided in a plurality of through holes (118T) spaced apart in the first and second horizontal directions, a uniform filling process of a conductive material can be performed in the entire area of ​​the via hole, thereby further improving the mechanical reliability and / or electrical reliability of the via electrode (118).

[0122] The perimeter of the upper surface of the via electrode (118) may have a plurality of curved portions (118OS1) and a straight portion (118OS2) connecting the plurality of curved portions. For example, the via electrode (118) may have a structure in which a plurality of first thermal via parts having a circular planar shape and a plurality of second thermal via parts having a square planar shape are connected to each other, and through this, the perimeter of the upper surface of the via electrode (118) may have a curved portion (118OS1) corresponding to the first thermal via part and a straight portion (118OS2) corresponding to the second thermal via part. As the perimeter of the upper surface of the via electrode (118) has the curved portion (118OS1) and the straight portion (118OS2), the outer surface of the via electrode (118) may have a step along the perimeter direction of the outer surface of the via electrode (118). For example, the outer surface of the via electrode (118) may have a convex portion that is convex toward the outside (corresponding to the curved portion described above) and / or a concave portion that is concave toward the inside (corresponding to the straight portion described above). Through this, the embodiment can increase the contact area between the via electrode (118) and the second insulating layer (105). Therefore, the embodiment can solve the reliability problem of the via electrode (118) being peeled off from the second insulating layer (105), thereby improving the mechanical reliability and / or electrical reliability of the circuit board and / or the semiconductor package.

[0123] At this time, the lower surface of the via electrode (118) may be connected to the second pad (111P2) of the second circuit layer (111), and the upper surface of the via electrode (118) may be connected to the fourth pad (112P1) of the third circuit layer (112). In one embodiment, the second pad (111P2) and the fourth pad (112P) may be ground pads, and the via electrode (118) may be connected to the ground pad. In this case, heat dissipation characteristics may be further improved by allowing heat to be transferred through the ground. In addition, when the second pad (111P2) and the fourth pad (112P) are ground pads, at least one of them may be arranged to overlap the cavity (105C) in a horizontal direction, so as to function as a reinforcing member that improves the rigidity of the circuit board, thereby allowing the connecting member and / or semiconductor element arranged in the cavity (105C) to operate smoothly. However, the embodiment is not limited thereto, and the second pad (111P2) and the fourth pad (112P) may be pads having a function other than a ground function. The upper surface of the second pad (111P2) includes a first portion in contact with the lower surface of the via electrode (118) and a second portion in contact with the second insulating layer (105) provided in the through hole (118T) of the via electrode (118). In addition, the fourth pad (112P) includes a first portion in contact with the upper surface of the via electrode (118) and a second portion in contact with the second insulating layer (105) provided in the through hole (118T) of the via electrode (118). At this time, the second pad (111P2) and the fourth pad (112P1) may have a higher bonding strength when they contact both the upper surface of the via electrode (118) and the upper surface of the second insulating layer (105) compared to when they only contact the upper surface and / or lower surface of the via electrode (118), and through this, the problem of the fourth pad (112P) being peeled off from the via electrode (118) and / or the second insulating layer (105) can be solved.At this time, as illustrated in FIG. 1C, the perimeter of the upper surface of the via electrode (118) may be positioned closer to the upper surface of the circuit board and / or the perimeter of the upper surface of the second insulating layer (105) than the perimeter of the upper surface of the fourth pad (112P). For example, the planar area of ​​the upper surface of the via electrode (118) including the through hole (118T) may be smaller than the planar area of ​​the upper surface of the fourth pad (112P). Through this, the problem of the heat dissipation characteristic of the via electrode (118) being deteriorated due to the fact that at least a portion of the via electrode (118) does not vertically overlap with the fourth pad (112P) can be solved, and the semiconductor element can be stably placed on the fourth pad (112P) as the fourth pad (112P) secures the planar area. However, the embodiment is not limited thereto, and at least a portion of the perimeter of the upper surface of the via electrode (118) may be positioned on the same vertical line as at least a portion of the perimeter of the upper surface of the fourth pad (112P), thereby further increasing the planar area of ​​the via electrode (118) and further improving the heat dissipation characteristics.

[0124] According to the embodiment of FIG. 2, the circuit board has a second insulating layer (201), a via electrode (205) penetrating at least a portion of the second insulating layer (201). In addition, a fourth pad (202) connected to the via electrode (205) is arranged on an upper surface of the second insulating layer (201).

[0125] The via electrode (205) has a through hole (204) penetrating the upper surface of the via electrode (205) and the lower surface of the via electrode (205). In addition, a plurality of through holes (204) may be provided penetrating the via electrode (205) at positions spaced apart in the first horizontal direction and the second horizontal direction. The perimeter of the upper surface of the via electrode (205) may have a step. The perimeter of the upper surface of the via electrode (205) may have a first portion (205) and a second portion (206) having mutual steps. Specifically, the first portion (205) and the second portion (206) may be provided in the form of a straight line having mutual steps. The first portion (205) of the via electrode (205) may be a convex portion that is convex toward the outside with respect to the second portion (206), and the second portion (206) of the via electrode (205) may be a concave portion that is concave toward the inside with respect to the first portion (205). That is, the via electrode (205) may include a plurality of first via parts having a rectangular planar shape and a plurality of second via parts having a rectangular planar shape and connecting the plurality of first via parts, and accordingly, the perimeter of the upper surface of the via electrode (205) may include the first portion (205) and the second portion (206) of the straight portion. That is, in the embodiment, when the second insulating layer (201) is made of a photocurable material, a via hole can be formed in the second insulating layer (201) through an exposure and development process, thereby improving the degree of freedom in designing the planar shape of the via hole and the corresponding via electrode (205). In addition, according to the embodiment of FIG. 2, a via electrode (205) having a planar area larger than the planar area of ​​the via electrode (118) according to the embodiment of FIG. 1c can be provided, thereby further improving the heat dissipation characteristics.

[0126] According to the embodiments of FIGS. 3A and 3B, the circuit board has a second insulating layer (301), and a via electrode (304) penetrating at least a portion of the second insulating layer (201). In addition, a lower pad (302) connected to a lower surface of the via electrode (304) may be provided on a lower surface of the second insulating layer (301), and an upper pad (303) connected to a upper surface of the via electrode (304) may be provided on an upper surface of the second insulating layer (301). In addition, a first protective layer (306) may be disposed on an upper surface of the second insulating layer (301). Here, the lower pad (302) may correspond to the second pad (111P2) in the circuit board of the previous embodiment, and the upper pad (303) may correspond to the fourth pad (112P1) in the circuit board of the previous embodiment.

[0127] The via electrode (304) has a through hole (305) that penetrates the upper surface of the via electrode (304) and the lower surface of the thermal via electrode (305). In addition, a plurality of through holes (305) may be provided to penetrate the via electrode (304) at positions spaced apart in the first horizontal direction and the second horizontal direction. The perimeter (304S) of the upper surface of the via electrode (304) may not have a step. For example, the perimeter (304S) of the upper surface of the via electrode (304) may have a rectangular shape with the step removed. In this case, the shape and / or position of the perimeter (304S) of the upper surface of the via electrode (304) may correspond to the shape and / or position of the perimeter (303S) of the upper surface of the upper pad (303). The perimeter (304S) of the upper surface of the via electrode (304) may be positioned on the same vertical line as the perimeter (303S) of the upper surface of the upper pad (303). The embodiments of FIGS. 3A and 3B can provide a via electrode (304) having a larger planar area than the planar area of ​​the via electrode (118, 205) according to the embodiments of FIGS. 1C and 2, thereby further improving heat dissipation characteristics.

[0128] According to the embodiment of FIG. 4A, the circuit board may have a first insulating layer (401) and a second insulating layer (404) disposed on the first insulating layer (401). In addition, a lower pad (402) may be disposed between an upper surface of the first insulating layer (401) and a lower surface of the second insulating layer (404), and an upper pad (405) may be disposed on an upper surface of the second insulating layer (404). In addition, a first via electrode (403) may be connected to the lower pad (402) and may be disposed to penetrate at least a portion of the first insulating layer (401). In addition, a via electrode (406) may be connected to the lower pad (302) and the upper pad (405) and may be disposed to penetrate at least a portion of the second insulating layer (404). In addition, a first protective layer (407) may be disposed on the second insulating layer (404). At this time, the first insulating layer (401), the second insulating layer (404), the via electrodes (403, 406), the upper pad (405), and the first protective layer (407) in the circuit board according to the embodiment of FIG. 4a have substantially the same functions as the components with the same names described in the circuit board of the previous embodiment, and a duplicate description thereof is omitted.

[0129] The lower pad (402) is connected to the lower surface of the via electrode (406) and may have an open portion (409) that is vertically overlapping with a through hole (408) provided in the via electrode (406). In this case, the open portion (409) may mean a through hole provided in the lower pad (402), or may mean a separation area between a plurality of pads.

[0130] That is, according to the embodiment of FIG. 4B, a via electrode (406) is arranged on the lower pad (402). At this time, the via electrode (406) may have a through hole (408), and the lower pad (402) may include an open portion (409) that vertically overlaps the through hole (408) of the via electrode (406). The open portion (409) of the lower pad (402) may penetrate between the upper surface of the lower pad (402) and the lower surface of the lower pad (402) corresponding to the through hole (408) of the via electrode (406). At this time, the open portion (409) provided in the lower pad (402) may function as a gas exhaust hole through which gas generated in the process of manufacturing the circuit board is exhausted. For example, a manufacturing process of a circuit board includes a process of curing a first insulating layer (401) after laminating it, and gas may be generated during curing of the first insulating layer (401). At this time, if a lower pad (402) without an open portion (409) is provided on the upper surface of the first insulating layer (401), it may be difficult for the above-described gas to smoothly discharge to the upper side of the first insulating layer (401). In addition, if the above-described gas is not smoothly discharged, a problem may occur in which the interface between the first insulating layer (401) and the second insulating layer (404) and / or the interface between the first insulating layer (401) and the lower pad (402) swells, and a peeling problem may occur due to this. The open portion (409) provided in the lower pad (402) of the embodiment can function as a gas exhaust port through which gas generated during curing of the first insulating layer (401) is exhausted, thereby enabling the aforementioned gas to be smoothly exhausted, thereby further improving the mechanical reliability and / or electrical reliability of the circuit board and / or semiconductor package.

[0131] Additionally, the diameter and / or planar area of ​​the open portion (409) of the lower pad (402) may be smaller than the diameter and / or planar area of ​​the through hole (408) of the via electrode (406). Accordingly, at least a portion of the through hole (408) may vertically overlap with the upper surface of the lower pad (402), and the remaining portion of the through hole (408) may vertically overlap with the open portion (409) of the lower pad (402). Accordingly, the embodiment may allow the entire lower surface of the via electrode (406) to be in contact with the lower pad (402), thereby further improving the heat dissipation characteristics.

[0132] According to the embodiment of FIG. 4c, the lower pads (402) may be provided in multiple numbers and spaced apart from each other, and the open portion (409) may be a spaced area between the multiple lower pads. Through this, the embodiment can branch the heat transfer path into multiple paths by allowing heat to dissipate through the multiple lower pads (402), and can further improve the heat dissipation characteristics by allowing heat to be transferred through the multiple branched paths.

[0133] The circuit board (100A) according to the embodiment of FIG. 5 may be provided with a via electrode (116A) having the same structure as the via electrode (117, 203, 304, 406) having the through hole described with reference to FIGS. 1A to 4C in the first insulating layer (104). For example, the first insulating layer (104) can be formed with a laser process, and accordingly, if a via hole having a design corresponding to the via electrode (117, 203, 304, 406) can be formed in the first insulating layer (104) depending on the laser process capability, a via electrode (116A) having a structure corresponding to the via electrode (117, 203, 304, 406) can also be formed in the first insulating layer (104).

[0134] Accordingly, in one embodiment, the circuit board may have a structure in which the via electrodes (117, 203, 304, 406) described above are arranged only on the second insulating layer (105), and in this case, the via electrodes (117, 203, 304, 406) may have a structure in which they overlap horizontally with the cavity. In another embodiment, the circuit board may have a structure in which the via electrodes (117, 203, 304, 406, 116A) are arranged on each of the first insulating layer (104) and the second insulating layer (105), and in this case, some of the via electrodes (117, 203, 304, 406, 116A) may overlap horizontally with the cavity, and the remaining some may overlap vertically with the cavity. In another embodiment, the circuit board may have a structure in which a via electrode (116A) is arranged on the first insulating layer (104), and in this case, the via electrode (116A) may have a structure that overlaps the cavity in a vertical direction.

[0135] According to the embodiments of FIGS. 6A and 6B, the circuit board includes a second insulating layer (501), an upper pad (504) disposed on the second insulating layer (501), a protective layer (508) disposed on the upper pad (504), and a via electrode (505) penetrating at least a portion of the second insulating layer (501). The via electrode (505) may correspond to any one of the via electrodes illustrated in FIGS. 1C, 2, and 3. Although the via electrode (505) in FIG. 6 is illustrated as having a shape corresponding to the via electrode (203) of FIG. 2, it is not limited thereto, and may have a shape corresponding to the thermal via electrode illustrated in FIG. 1C or FIG. 3. The via electrode (505) may have a plurality of through holes (506) spaced apart in first and second horizontal directions. The second insulating layer (501) may be divided into a plurality of parts. The second insulating layer (501) may include a first portion (502) disposed within a through hole (506) provided in a via electrode (505), and a second portion (503) other than the first portion (502). At this time, the second insulating layer (501) may include a via hole penetrating the upper and lower surfaces of the second portion (503). The via hole provided in the second portion (503) of the second insulating layer (501) may correspond to the via electrode (505), and the via hole provided in the second portion (503) of the second insulating layer (501) may be filled with a conductive material to form the via electrode (505). In addition, the second insulating layer (501) may further include a sub-via hole penetrating the upper and lower surfaces of the first portion (502) but not connected to the above-described via hole. In addition, the sub-via electrode (507) can be formed by filling a sub-via hole formed in the first part (502) of the second insulating layer (501) with a conductive material. That is, the sub-via electrode (507) can be placed in a through hole (506) provided in the via electrode (505) and / or a via hole provided in the first part (502) of the second insulating layer (501), and may not be connected to the via electrode (505).That is, the first part (502) of the second insulating layer (501) may be provided between the inner surface of the through hole (506) of the via electrode (505) and the outer surface of the sub-via electrode (507), and thus may be provided to surround the outer surface of the sub-via electrode (507) so that the via electrode (505) and the sub-via electrode (507) do not directly contact each other. At this time, the through hole (506) provided in the via electrode (505) may be provided to improve the processability in the process of filling the via hole provided in the second insulating layer (501) with a conductive material. However, the planar area of ​​the via electrode (505) is reduced by the planar area of ​​the through hole (506) provided in the via electrode (505), and the heat dissipation characteristics may be deteriorated correspondingly. Accordingly, in the embodiment, a sub-via electrode (507) may be further arranged within the through hole (506) of the via electrode (505). The sub-via electrode (507) is not connected to the via electrode (505), and thus may not affect the processability in the filling process of a conductive material for forming the via electrode (505). Furthermore, the planar area of ​​the via electrode can be increased by the planar area of ​​the sub-via electrode (507), and thus the heat dissipation characteristics of the circuit board and the semiconductor package can be further improved.

[0136] According to the embodiment of FIGS. 7a and 7b, the circuit board includes a second insulating layer (501), an upper pad (504) disposed on the second insulating layer (501), a protective layer (508) disposed on the upper pad (504), and a via electrode (505) penetrating at least a portion of the second insulating layer (501).

[0137] In addition, the second insulating layer (501) can be divided into a plurality of parts. The second insulating layer (501) can include a first part (502) arranged in a through hole (506) provided in a via electrode (505), and a second part (503) other than the first part (502). At this time, the second insulating layer (501) can have a via hole that penetrates the upper and lower surfaces of the second part (503). The via hole provided in the second part (503) of the second insulating layer (501) can correspond to the via electrode (505), and the via electrode (505) can be formed by filling the via hole provided in the second part (503) of the second insulating layer (501) with a conductive material. In addition, the second insulating layer (501) may further include a sub-via hole that penetrates the upper and lower surfaces of the first portion (502) and is not connected to the above-described via hole. In addition, the sub-via electrode (509) may be formed by filling the sub-via hole formed in the first portion (502) of the second insulating layer (501) with a conductive material.

[0138] At this time, in the circuit board according to the embodiment of FIGS. 6A and 6B, the horizontal central axis of the through hole (506) provided in the via electrode (505) and the horizontal central axis of the sub-via electrode (507) arranged in the above-described through hole (506) may coincide with each other.

[0139] In contrast, in the circuit board according to the embodiments of FIGS. 7A and 7B, the horizontal center axis (X1) of the through hole (506) provided in the via electrode (505) and the horizontal center axis (X2) of the sub-via electrode (509) arranged within the above-described through hole (506) may be misaligned with each other. For example, the horizontal distance (W1) between the outer surface of the sub-via electrode (509) and the inner surface of the via electrode (505) on one side of the sub-via electrode (509) and the horizontal distance (W2) between the outer surface of the sub-via electrode (509) and the inner surface of the via electrode (505) on the other side of the sub-via electrode (509) may be different from each other. For example, the horizontal distance between the inner surface of the via electrode (505) and the inner surface of the sub-via electrode (509) may have a first horizontal distance and a second horizontal distance (W1, W2) that are different from each other along the circumferential direction of the outer surface of the sub-via electrode (509). Through this, the embodiment can provide the sub-via electrode (509) to be provided in a specific horizontal direction within the through hole (506) of the via electrode (505), thereby further improving the fairness of the circuit board accordingly. Furthermore, the embodiment can further improve the circuit board from being greatly bent in a specific direction by providing the sub-via electrode (509) to be provided in a specific horizontal direction within the through hole (506) of the via electrode (505). For example, the via electrode (505) has a plurality of through holes (506) and sub-via electrodes (509), and the misaligned directions of the horizontal central axes of each of the plurality of through holes (506) and each of the plurality of sub-via electrodes (509) may be different from each other.For example, the horizontal central axis of the sub-via electrode (509) positioned adjacent to the left side of the via electrode (505) may be shifted to the right with respect to the horizontal central axis of the through hole (506), and the horizontal central axis of the sub-via electrode (509) positioned adjacent to the right side of the via electrode (505) may be shifted to the left with respect to the horizontal central axis of the through hole (506). Through this, the embodiment can prevent the circuit board from being bent in a specific direction by adjusting the misalignment direction between the horizontal central axis of the sub-via electrode (509) and the horizontal central axis of the through hole (506), and further improve the mechanical reliability and / or electrical reliability of the circuit board and the semiconductor package. According to the embodiment of FIG. 8, the circuit board includes a core layer (601), a core via electrode (610) penetrating the core layer (601), an insulating member (611) disposed on the inner side of the core via electrode (610), and a first build-up layer disposed on the core layer (601). The first build-up layer includes a plurality of insulating layers (602, 603, 604), a first protective layer (605), a plurality of circuit layers (606, 607, 608, 609), a plurality of via electrodes (612, 613, 614), and a bonding portion (615). Each component of the circuit board according to the embodiment of Fig. 8 has substantially the same function as the component with the same name described in the circuit board of the previous embodiment, and a duplicate description thereof is omitted.

[0140] The plurality of insulating layers (602, 603, 604) may include a first insulating layer (602) disposed on the core layer (601), a first insulating layer (603) disposed on the first insulating layer (602), and a second insulating layer (604) disposed on the first insulating layer (603). Here, although two first insulating layers are depicted as being disposed between the core layer (601) and the second insulating layer (604), this is to explain the difference in width, inclination angle, and thickness of the via electrode provided in each insulating layer, and the structure of the present embodiment is not limited thereto.

[0141] The first-first insulation layer (602) may be provided as a thermosetting insulation material disposed on the core layer (601) and provided with a reinforcing member, and may be, for example, a prepreg. The first-second insulation layer (603) may be provided as a thermosetting insulation material disposed on the first-first insulation layer (602) and not provided with a reinforcing member, and may be, for example, ABF. In this case, only one of the first-first insulation layer (602) and the first-second insulation layer (603) may be provided as a single layer or multiple layers on the core layer (601). And, when the first-first insulation layer (602) and the first-second insulation layer (603) are respectively disposed between the core layer (601) and the second insulation layer (604), the first-first insulation layer (602) having the reinforcing member may be disposed closer to the core layer (601) than the first-second insulation layer (603). That is, the elastic modulus and / or thermal expansion coefficient of the first-first insulation layer (602) having the reinforcing member may be smaller than the elastic modulus and / or thermal expansion coefficient of the first-second insulation layer (603) not having the reinforcing member. Accordingly, the first-first insulating layer (602) having a relatively small elastic modulus and / or thermal expansion coefficient is arranged closer to the core layer (601) than the first-second insulating layer (603), so that the stress applied to the circuit board due to the difference in elastic modulus and / or thermal expansion coefficient between the core layer (601) and the second insulating layer (604) described above can be further cushioned.

[0142] The first via electrode (612) may penetrate at least a portion of the first-first insulating layer (602). The second via electrode (613) may penetrate at least a portion of the first-second insulating layer (603). The third via electrode (614) may penetrate at least a portion of the second insulating layer (604). The third via electrode (614) may include a via electrode having a heat dissipation function as described above and a via electrode having a signal and / or power transmission function, and FIG. 8 may illustrate only the via electrode having a signal and / or power transmission function among these. The inclination angle, the vertical thickness, and / or the horizontal width of at least one of the first via electrode (612), the second via electrode (613), and the third via electrode (614) may be different from the inclination angle, the vertical thickness, and / or the horizontal width of at least one other via electrode.

[0143] At this time, the vertical thickness (H1) of the first via electrode (612) may be different from the vertical thickness (H2) of the second via electrode (613) and the vertical thickness (H3) of the third via electrode (614). The vertical thickness (H1) of the first via electrode (612) may be greater than or equal to the vertical thickness (H2) of the second via electrode (613) and the vertical thickness (H3) of the third via electrode (614). For example, the vertical thickness (H1) of the first via electrode (612) may be greater than or equal to 15 μm, and the vertical thickness (H2) of the second via electrode (613) and the vertical thickness (H3) of the third via electrode (614) may each be greater than or equal to 10 μm. That is, the 1-1 insulating layer (602) has a reinforcing member, and thus there is a limit to reducing the vertical thickness of the 1-1 insulating layer (602). This is because, when the vertical thickness of the 1-1 insulating layer (602) is reduced, the reinforcing member provided in the 1-1 insulating layer (602) may be exposed and come into contact with the circuit layer, which may result in a deterioration of electrical characteristics. In addition, the first via electrode (612) may have a vertical thickness (H2) greater than or equal to the second via electrode (613) provided in the 1-2 insulating layer (603) that does not have a reinforcing member and a vertical thickness (H3) greater than or equal to the third via electrode (614) provided in the second insulating layer (604) as it penetrates at least a portion of the 1-1 insulating layer (602). Accordingly, by ensuring that the first via electrode (612) that can have a relatively large thickness is positioned closest to the core via electrode (610) provided in the core layer (601), signal transmission loss that may occur due to the difference in vertical thickness of each of the via electrodes stacked along the vertical direction can be minimized.

[0144] In addition, the horizontal width (W3) of the third via electrode (614) may be different from the horizontal width (W1) of the first via electrode (612) and the horizontal width (W2) of the second via electrode (613). For example, the horizontal width (W3) of the third via electrode (614) may be less than or equal to the horizontal width (W1) of the first via electrode (612) and the horizontal width (W2) of the second via electrode (613). That is, the third via electrode (614) is formed by filling a conductive material into a via hole formed through an exposure and development process, and thus may have a horizontal width (W3) that is smaller than the horizontal width (W1) of the first via electrode (612) and the horizontal width (W2) of the second via electrode (613), which are formed by filling a conductive material into a via hole formed through a laser process. Accordingly, the embodiment can provide a third via electrode (614) having a relatively small horizontal width (W3) at a position furthest from the core layer (601), thereby minimizing the horizontal width and / or pitch of the circuit layer (609) disposed on the third via electrode (614).

[0145] Additionally, each of the first via electrode (612), the second via electrode (613), and the third via electrode (614) may have a slope in which the horizontal width gradually decreases along the direction from the upper surface to the lower surface. And, the inclination angle (θ) of the third via electrode (614) may be different from the inclination angle (θ) of the first via electrode (612) and the inclination angle (θ) of the second via electrode (613). The inclination angle (θ) of the third via electrode (614) may be less than or equal to the inclination angle (θ) of the first via electrode (612) and the inclination angle (θ) of the second via electrode (613). For example, the inclination angle (θ) of the first via electrode (612) and the inclination angle (θ) of the second via electrode (613) may have a range of 75° to 85°. And, the inclination angle (θ) of the third via electrode (614) may have a range of 70° to 80°. This is performed by performing a desmear process after forming a via hole in the second insulating layer (604), and through the desmear process, the third via electrode (614) This is because the inclination angle (θ) has a different range from the inclination angle (θ) of the first via electrode (612) and the inclination angle (θ) of the second via electrode (613). Therefore, the embodiment can make the third via electrode (614) have a relatively gentle inclination angle, and thereby can further improve the adhesion between the second insulating layer (604) and the third via electrode (614). The second insulating layer (604) can have a greater elastic coefficient and / or thermal expansion coefficient than the elastic coefficient and / or thermal expansion coefficient of each of the core layer (601), the first-first insulating layer (602), and the first-second insulating layer (603), and thus, a greater stress can be applied due to expansion and / or contraction according to the heat cycle. Therefore, by making the third via electrode (614) have a relatively gentle inclination, the contact area between the second insulating layer (604) and the third via electrode (614) can be increased, thereby improving the adhesion between them. Can be secured.

[0146] In addition, a part of the circuit layer (609) disposed on the second insulating layer (604) may include a pad portion exposed from the first protective layer (605). In addition, as the density of terminals of the semiconductor element increases, a solder short circuit problem may occur between adjacent pad portions with conventional solder bonding. Therefore, in order to reduce the amount of solder used as the density of terminals of the semiconductor element increases, the semiconductor element and the circuit board (100) may be bonded to each other through a thermal compression bonding (TC bonding) method. When TC bonding is used, the circuit board (100) may further include a bonding portion (615) protruding on the first protective layer (605). The bonding portion (615) may have a protrusion (616) protruding on the upper surface of the first protective layer (605) and a penetration portion (617) penetrating through the first protective layer (605) to be in contact with the circuit layer (609). In addition, when the circuit board (100) and the semiconductor element are bonded by TC bonding, a crack may occur in the penetration portion (617) of the bonding portion (615) due to the load generated thereby. Therefore, cracks can be prevented by placing a material having a higher elastic modulus than the elastic modulus of the circuit layer (609) in the penetration portion (617) of the bonding portion (615) adjacent to the circuit layer (609). This material may be nickel (Ni), but a copper layer having a low grain density can be placed by electroless plating.

[0147] The protrusion (616) and the penetration (617) of the bonding portion (615) illustrated in FIG. 8 can be arranged in various ways. For example, a process may be performed in which the first protective layer (605) is exposed and developed to form an opening in the first protective layer (605), and then the protrusion (616) and the penetration (617) of the bonding portion (615) are arranged in the opening. Alternatively, a process may be performed in which a penetration hole in the first protective layer (605) is formed using a laser, and then the bonding portion (615) and the penetration (617) are arranged in the opening. In addition, by using DFR (Dry Film resist), DFR is first placed in the area where the penetration portion (617) is to be placed, and then the first protective layer (605) is placed so that the DFR is covered, and then a part of the first protective layer (605) is etched with a chemical solution to expose the DFR, and then the DFR is peeled off to form an opening in the first protective layer (605), and then the protrusion portion (616) of the bonding portion (615) and the penetration portion (617) can be placed. Therefore, the penetration portion (617) can have various shapes depending on the process method. For example, when the opening of the first protective layer (605) is formed through an exposure process, the side surface of the through-hole (617) may have a structure in which the width gradually narrows toward the circuit layer (609). When the opening of the first protective layer (605) is formed through a laser process, the side surface of the through-hole (617) may have a vertical side surface and a curved side surface in which the portion adjacent to the circuit layer (609) is recessed inward. When the opening of the first protective layer (605) is formed using DFR, the side surface of the through-hole (617) may only have a vertical side surface. As described above, when the semiconductor element is bonded to the circuit board (100) through TC bonding, a load may be applied to the through-hole (617). In this case, in the case of the through-hole (617) using DFR, the stress may be applied uniformly, so that the manufacturing yield may be increased.

[0148] According to the embodiment of FIG. 9, the circuit board may have a plurality of second insulating layers arranged on one side of the core layer, and in this case, the structure of the via electrodes and cavities provided in the plurality of second insulating layers may be different from that described in the previous embodiment.

[0149] Referring to FIG. 9, the circuit board includes a core layer (701), a first insulating layer (702) disposed on the core layer (701), a second insulating layer (703) disposed on the first insulating layer (702), and a first protective layer (706) disposed on the second insulating layer (703). In addition, the circuit board includes a plurality of circuit layers (707, 708, 709, 710) disposed on the core layer (701), the first insulating layer (702), and the second insulating layer (703), respectively, and via electrodes (713, 714, 715) connecting the plurality of circuit layers (707, 708, 709, 710). In addition, a core via electrode (711) is provided on the core layer (701), and an insulating member (712) is provided on the inner side of the core via electrode (711). Each component of the circuit board according to the embodiment of FIG. 9 has substantially the same function as the component with the same name described in the circuit board of the previous embodiment, and any overlapping description will be omitted.

[0150] The core layer (701), the first insulating layer (702), and the second insulating layer (703) may be sequentially laminated in the vertical direction. At this time, the second insulating layer (703) may be provided in multiple layers. That is, the second insulating layer (703) may include a 2-1 insulating layer (704) disposed on the first insulating layer (702), and a 2-2 insulating layer (705) disposed on the 2-1 insulating layer (704). When the second insulating layer (703) is provided in one layer, fine patterns may be concentratedly disposed on the second insulating layer of the first layer, and thus the planar area of ​​the circuit board may increase, or the length of the signal transmission line may increase, which may increase signal transmission loss. This is because the signal transmission line is connected only by a trace in one layer without a via electrode. Accordingly, the 2-1 insulating layer (704) and the 2-2 insulating layer (705) are sequentially arranged on the 1st insulating layer (702), and the circuit layers (709, 710) arranged on each of the 2-1 insulating layer (704) and the 2-2 insulating layer (705) are made miniaturized. Accordingly, the embodiment can further improve the circuit integration of the circuit board, and can reduce the length of the signal transmission line, thereby significantly improving the signal transmission characteristics.

[0151] A cavity (705C) may be provided in the second insulating layer (703). In particular, among the second insulating layers (703) in the embodiment of FIG. 9, the cavity (705C) may not be provided in the 2-1 insulating layer (704), and only the cavity (705C) may be provided in the 2-2 insulating layer (705). In addition, the side wall of the cavity (705C) provided in the 2-2 insulating layer (705) may correspond to the side wall (105C1) of the cavity (105C) in FIG. 1B. In this case, a portion of the circuit layer (709) disposed on the 2-1 insulating layer (704) may vertically overlap with the cavity (705C), thereby functioning as a mounting pad for mounting a connecting member and / or a semiconductor element. At this time, as the mounting pad is placed on the 2-1 insulating layer (704), the horizontal width and / or pitch of the mounting pad described above can be refined.

[0152] In addition, a plurality of via electrodes (714, 715) may be arranged on each of the second insulating layers (703), and at least one of the plurality of via electrodes (714, 715) may be provided with a via electrode (716) having the above-described through hole. For example, the cavity (705C) may be provided on the 2-2 insulating layer (705), and the via electrode (716) may be arranged on the 2-2 insulating layer (705) that horizontally overlaps the cavity (705C). At this time, the via electrode (715) provided on the 2-2 insulating layer (705) may further include a via electrode (717) that transmits signals and / or power and is spaced apart from the via electrode (716) in the horizontal direction, or that does not have a through hole.

[0153] According to the embodiment of FIG. 10, the circuit board may include a first insulating layer (801), a second-first insulating layer (802) disposed on the first insulating layer (801), and a second-second insulating layer (803) disposed on the second-first insulating layer (802). In addition, a first protective layer (804) may be disposed on the second-second insulating layer (803). In addition, a first circuit layer (805) may be disposed on an upper surface of the first insulating layer (801), a second circuit layer (806) may be disposed on an upper surface of the second-first insulating layer (802), and a third circuit layer (807) may be disposed on an upper surface of the second-second insulating layer (803). Additionally, a first via electrode (807) may be disposed through at least a portion of the 2-1 insulating layer (802), and a second via electrode (808) may be disposed through at least a portion of the 2-2 insulating layer (803).

[0154] Each of the first via electrodes (807) and the second via electrodes (808) may be provided in a plurality of pieces and may be spaced apart from each other in the horizontal direction. In addition, at least one of the plurality of first via electrodes (807) may vertically overlap with at least one of the plurality of second via electrodes (808) depending on the wiring design. In addition, at least another of the plurality of first via electrodes (807) may not vertically overlap with the plurality of second via electrodes (808), and at least another of the plurality of second via electrodes (808) may not vertically overlap with the plurality of first via electrodes (807).

[0155] At this time, the first via electrode (807) and the second via electrode (808) that do not overlap each other along the vertical direction can be formed separately in the manufacturing process of the circuit board. For example, the first via electrode (807) and the second via electrode (808) that do not overlap each other along the vertical direction can have a structure in which the first circuit layer (805), the first via electrode (807), the second circuit layer (806), the second via electrode (808), and the third circuit layer (807) are stacked along the vertical direction, thereby allowing electrical connection therebetween.

[0156] Furthermore, even in the case of the first via electrode (807) and the second via electrode (808) that are overlapped with each other along the vertical direction in the past, individual manufacturing processes were performed, and through this, a structure was formed in which a second circuit layer (806) connecting the first via electrode (807) and the second via electrode (808) was arranged between them. In this case, since the manufacturing process for forming the first via electrode (807) and the second via electrode (808) individually must be performed, the manufacturing time may increase and the product yield may decrease.

[0157] Accordingly, the circuit board of the embodiment may further include a third via electrode (809) that horizontally overlaps with each of the first via electrode (807) and the second via electrode (808). The third circuit layer (807) may be provided to horizontally overlap with the first via electrode (807), the second via electrode (808), and the second circuit layer (806). Specifically, the 2-1 insulating layer (802) may be provided with a plurality of via holes. The plurality of via holes may include a first via hole that does not vertically overlap with the second via electrode (808) and a second via hole (802T) that vertically overlaps with the second via electrode (808). In addition, during the manufacturing process of the circuit board, the above-described first via hole may be filled with a conductive material, thereby forming the first via electrode (807). Alternatively, during the manufacturing process of the circuit board, the second via hole (802T) described above may not be filled with a conductive material. This can be achieved by covering the second via hole (802T) while opening the first via hole through a dry film. Thereafter, the second via hole (802T) not filled with a conductive material can be filled with a second-second insulating layer (803) laminated on the second-first insulating layer (802). Accordingly, the second-second insulating layer (803) may have a protrusion (803P) that fills the second via hole (802T) provided in the second-first insulating layer (802). In addition, the 2-2 insulating layer (803) may be provided with a plurality of via holes, and at least one of the plurality of via holes is provided to penetrate from the upper surface of the 2-2 insulating layer (803) to the lower surface of the protrusion (803P) of the 2-2 insulating layer (803), thereby exposing the first circuit layer (805) disposed on the first insulating layer (801). In addition, the via hole that penetrates from the upper surface of the 2-2 insulating layer (803) to the lower surface of the protrusion (803P) of the 2-2 insulating layer (803) may be filled with a conductive material to form a third via electrode (809).Accordingly, the third via electrode (807) can directly connect the first circuit layer (805) and the third circuit layer (807) while having a slope in which the width in the horizontal direction gradually decreases from the upper surface of the third via electrode (809) toward the lower surface of the third via electrode (809). Therefore, the embodiment can simplify the manufacturing process of the circuit board and improve the product yield. Furthermore, the embodiment can directly connect the first circuit layer (805) and the third circuit layer (807) using the third via electrode (809), thereby further improving the signal transmission characteristics.

[0158] According to the embodiment of FIG. 11A, the circuit board includes a core layer (901), a first insulating layer (902) disposed on the core layer (901), a second insulating layer (903) disposed on the first insulating layer (902), and a first protective layer (906) disposed on the second insulating layer (903). In addition, the circuit board includes a plurality of circuit layers (907, 908, 909, 910) disposed on the core layer (901), the first insulating layer (902), and the second insulating layer (903), respectively, and via electrodes (913, 914, 917) connecting the plurality of circuit layers (907, 908, 909, 910). In addition, a core via electrode (911) is provided on the core layer (901), and an insulating member (912) is provided on the inner side of the core via electrode (911). The second insulating layer (903) may include a second-first insulating layer (904) disposed on the first insulating layer (902) and a second-second insulating layer (905) disposed on the second-first insulating layer (904).

[0159] At this time, via electrodes (914, 917) may be arranged on each of the 2-1 insulating layer (904) and the 2-2 insulating layer (905). The first via electrode (917) arranged on the 2-2 insulating layer (905) may overlap horizontally with the cavity (905C) provided in the 2-2 insulating layer (905) and may further include a via electrode (918) provided with the above-described through hole and a via electrode (919) not provided with the through hole or having a signal and / or power transmission function. In addition, the second via electrode (914) provided on the 2-1 insulating layer (904) may also include via electrodes (915, 916). Specifically, the first via electrode (914) provided in the 2-1 insulating layer (904) may further include a via electrode (915) that is vertically overlapped with the via electrode (918) provided in the 2-2 insulating layer (905). Specifically, the circuit board may include a plurality of via electrodes (915, 918) that are stacked along the vertical direction. Accordingly, the heat dissipation characteristics of the circuit board and the semiconductor package can be further improved, and the semiconductor element can be operated more stably.

[0160] According to the embodiment of Fig. 11b, the circuit board may have a different arrangement structure of the via electrodes (915, 918) from the structure of the embodiment of Fig. 11a. The embodiment of Fig. 11a may have a structure in which the via electrodes (915, 918) are provided in the 2-1 insulating layer (904) and the 2-2 insulating layer (905), respectively, and are interconnected through pads of the circuit layer (909) provided between the 2-1 insulating layer (904) and the 2-2 insulating layer (905).

[0161] In contrast, the embodiment of FIG. 11b may include a via hole (904T) in the 2-1 insulating layer (904), and the 2-2 insulating layer (905) may be formed by filling the via hole (904T) of the 2-1 insulating layer (904). That is, the 2-2 insulating layer (905) may include a protrusion positioned within the via hole (904T) of the 2-1 insulating layer (904). In addition, the via electrode (918) formed in the 2-2 insulating layer (905) may be formed to penetrate from the upper surface of the 2-2 insulating layer (905) to the lower surface of the protrusion of the 2-2 insulating layer (905). That is, the via electrode (918) can be provided to directly connect the circuit layer (908) disposed on the upper surface of the first insulating layer (902) and the circuit layer (910) disposed on the upper surface of the 2-2 insulating layer (905). Furthermore, a via electrode (919) that does not have a through hole disposed in the 2-2 insulating layer (905) can also have a structure corresponding to the via electrode (918) having a through hole and can penetrate from the upper surface of the 2-2 insulating layer (905) to the lower surface of the protrusion of the 2-2 insulating layer (905).

[0162] According to the embodiment of FIG. 11C, the first via electrode (914) provided in the 2-1 insulating layer (904) may include a via electrode (915) having a through hole and a via electrode (916) not having a through hole, and the via electrodes (915) having a through hole may be provided in plural and spaced apart from each other in the horizontal direction. Specifically, the via electrode (915) having a through hole may further include a first via electrode portion (915a) that is vertically overlapped while being connected to a via electrode (918) provided in the 2-2 insulating layer (905), and a second via electrode portion (915b) that is horizontally overlapped with the first via electrode portion (915a). The second via electrode portion (915b) may be spaced apart from the first via electrode portion (915a) in the horizontal direction and may vertically overlap with the cavity (905C). And the second via electrode portion (915b) may be provided for heat dissipation of a semiconductor element to be placed within the cavity (905C). Therefore, the embodiment can further facilitate heat dissipation of a plurality of semiconductor elements by providing a plurality of via electrodes at different locations on the circuit board, thereby further improving the heat dissipation characteristics of the circuit board and the semiconductor package including the circuit board.

[0163] According to the embodiment of FIG. 11d, a cavity (903C) may be provided in the 2-1 insulating layer (904) and the 2-2 insulating layer (905). The cavity (903C) may be provided in the 2-1 insulating layer (904) and the 2-2 insulating layer (905), respectively. That is, the cavity (903C) may include a first portion (904C) provided in the 2-1 insulating layer (904) and a second portion (905C) provided in the 2-2 insulating layer (905). Accordingly, the embodiment allows the cavity (903C) to include a first portion (904C) and a second portion (905C) provided in different second insulating layers, so that the depth of the cavity (903C) can be easily adjusted to correspond to the thickness of the connecting member and / or semiconductor element to be placed within the cavity (903C), thereby allowing the connecting member and / or semiconductor element to be placed more stably within the cavity (903C). In addition, each of the first portion (904C) and the second portion (905C) of the cavity (903C) may have a sidewall inclination angle as illustrated in FIG. 1B. However, the sidewall inclination angle of the first portion (904C) and the sidewall inclination angle of the second portion (905C) may be different from each other. For example, the slope angle of the side wall of the first portion (904C) may be provided more gently than the slope angle of the side wall of the second portion (905C), and conversely, the slope angle of the side wall of the second portion (905C) may be provided more gently than the slope angle of the side wall of the first portion (904C), and this may be designed in various ways depending on the type of semiconductor element to be placed within the cavity (903C).

[0164] In addition, the horizontal width of the first portion (904C) of the cavity (903C) may be different from the horizontal width of the second portion (905C). That is, each of the first portion (904C) and the second portion (905C) of the cavity (903C) may have a slope such that the width in the horizontal direction changes along the vertical direction. At this time, the horizontal width of the first portion (904C) on the upper surface of the 2-1 insulating layer (904) may be different from the horizontal width of the second portion (905C) on the lower surface of the 2-2 insulating layer (905). For example, the horizontal width of the first portion (904C) on the upper surface of the 2-1 insulating layer (904) may be greater than the horizontal width of the second portion (905C) on the lower surface of the 2-2 insulating layer (905). That is, the side walls of the first portion (904C) and the second portion (905C) of the cavity (903C) may have a step. Through this, the embodiment can further improve the adhesion with the molding member that molds the cavity (903C), thereby enabling the connecting member and / or semiconductor element placed within the cavity (903C) to be more stably protected.

[0165] The above-described circuit board may be provided as a semiconductor package by mounting a semiconductor element thereon.

[0166] According to the embodiment of FIG. 12, the semiconductor package may include a circuit board (1000) and semiconductor elements (1002, 1004) mounted on the circuit board (1000). The circuit board (1000) may be any one of the circuit boards described with reference to FIGS. 1A to 11, and may be, for example, the circuit board illustrated in FIG. 1A, but is not limited thereto.

[0167] A plurality of circuit layers provided on a circuit board (1000) may overlap a cavity in a vertical direction and have a first mounting portion provided within the cavity, and a first bonding member (1001) may be arranged on the first mounting portion. Here, the first mounting portion is a pad for mounting a first semiconductor element (1002), and may be, for example, the first pad (111P1) illustrated in FIG. 1A. In addition, the first semiconductor element (1002) may be attached to the first bonding member (1001). In the embodiment, the first semiconductor element (1002) may be arranged within a cavity provided on the circuit board, thereby reducing the vertical thickness of the circuit board (1000) by the depth of the cavity.

[0168] In addition, the plurality of circuit layers provided on the circuit board may include a second mounting portion arranged on a via electrode having a through hole, and a second bonding member (1003) may be arranged on the second mounting portion. In addition, a second semiconductor element (1004) may be attached on the second bonding member (1003). At this time, the second mounting portion may be a pad connected to the via electrode having a through hole, and may be, for example, the fourth pad (112P1) illustrated in FIG. 1A, but is not limited thereto. When the second mounting portion is the fourth pad (112P1), the size of the via electrode having a through hole may correspond to the size of the second semiconductor element (1004). Here, the size of the via electrode having a through hole may mean the entire planar area of ​​the via electrode including the planar area of ​​the above-described through hole. The via electrode may be connected to the second semiconductor element (1004) and may have a heat dissipation function to transfer heat generated from the second semiconductor element (1004). In addition, the via electrode may have a function to improve the rigidity of the circuit board so that the first semiconductor element (1002) can be stably attached by overlapping the cavity in a horizontal direction. Accordingly, the embodiment may enable the first and second semiconductor elements (1002, 1004) to be stably attached, and thus the first and second semiconductor elements (1002, 1004) to operate stably.

[0169] In addition, the semiconductor package further includes a molding member (1005) for molding the first and second semiconductor elements (1002, 1004). The molding member (1005) can mold the first and second semiconductor elements (1002, 1004) as a whole at once, but is not limited thereto. For example, the molding member (1005) may be provided in multiple pieces spaced apart from each other in the horizontal direction, thereby individually molding the first and second semiconductor elements (1002, 1004). Through this, the first and second semiconductor elements (1002, 1004) can be stably protected from external moisture, etc., thereby enabling the first and second semiconductor elements (1002, 1004) to operate more stably.

[0170] According to the embodiment of FIG. 13, the semiconductor package may include a circuit board (1100) and semiconductor elements (1102, 1105) mounted on the circuit board (1100). The circuit board (1100) may be any one of the circuit boards described with reference to FIGS. 1A to 9, and may be, for example, the circuit board illustrated in FIG. 1A, but is not limited thereto.

[0171] A plurality of circuit layers provided on a circuit board (1100) may overlap a cavity in a vertical direction and have a first mounting portion provided within the cavity, and a first connecting member (1101) may be arranged on the first mounting portion. Here, the first mounting portion is a pad for mounting a first semiconductor element (1102), and may be, for example, the first pad (111P1) illustrated in FIG. 1A. In addition, the first semiconductor element (1102) may be attached to the first connecting member (1101). In the embodiment, the first semiconductor element (1102) may be arranged within a cavity provided on the circuit board, thereby reducing the vertical thickness of the circuit board (1100) by the depth of the cavity.

[0172] In addition, the plurality of circuit layers provided on the circuit board may include a second mounting portion arranged on a via electrode, and a second bonding member (1103, 1104) may be arranged on the second mounting portion. In addition, a second semiconductor element (1105) may be attached on the second bonding member (1104). At this time, the second mounting portion may be a bonding portion respectively provided on a via electrode having a through hole and a via electrode not having a through hole, but is not limited thereto. In this case, the size of the via electrode may be smaller than the size of the second semiconductor element (1105).

[0173] In addition, the semiconductor package further includes a molding member (1106) for molding the first and second semiconductor elements (1102, 1105), thereby stably protecting the first and second semiconductor elements (1002, 1105) from external moisture, etc., and thereby enabling the first and second semiconductor elements (1002, 1105) to operate more stably.

[0174] According to the embodiment of FIG. 14, the semiconductor package may include a circuit board (1200) and semiconductor elements (1204, 1206, 1208) mounted on the circuit board (1200).

[0175] The circuit board (1200) has a cavity, and a first semiconductor element (1204) can be attached to the cavity through a first bonding member (1203).

[0176] In addition, second and third semiconductor elements (1206, 1207) may be mounted on the circuit board (1200) while being spaced apart horizontally from the first semiconductor element (1204). The second and third semiconductor elements (1206, 1207) may be provided on the circuit board (1200) while being spaced apart horizontally, but are not limited thereto. For example, the second and third semiconductor elements (1206, 1207) may be vertically stacked and arranged on the circuit board (1200). To this end, the circuit board (1200) may be provided with circuit layers (1201, 1202) that electrically connect the second and third semiconductor elements (1206, 1207) to each other. At this time, the circuit board (1200) may have a structure in which a plurality of insulating layers are stacked along a vertical direction, and among the plurality of insulating layers, at least one insulating layer arranged closest to the second and third semiconductor elements (1206, 1207) may be provided as a second insulating layer. Through this, a fine circuit layer can be arranged on the second insulating layer, and accordingly, the second and third semiconductor elements (1206, 1207) can be electrically connected to each other without a separate connecting member. Specifically, in order to electrically connect the second and third semiconductor elements (1206, 1207), a connecting member such as a bridge die must be provided within the circuit board (1200), and the connecting member may include a redistribution layer that connects the second and third semiconductor elements (1206, 1207). At this time, the embodiment can form a circuit layer corresponding to a rewiring layer provided in a connecting member on the second insulating layer, and thus the second and third semiconductor elements (1206, 1207) can be electrically connected without a separate connecting member. At this time, at least one of the circuit layers (1201, 1202) provided in the circuit board (1200) includes a ground pattern, and the ground pattern can be connected to a ground terminal provided in the second and third semiconductor elements (1206, 1207).At this time, the ground pattern can improve the rigidity of the circuit board while performing a ground function. For example, the ground pattern can overlap the first semiconductor element (1204) in a horizontal direction, thereby improving the rigidity of the circuit board in the area where the first semiconductor element (1204) is arranged.

[0177] In addition, a second bonding member (1205, 1207) may be arranged on the circuit board (1200), and second and third semiconductor elements (1206, 1207) may be attached on the second bonding member (1205, 1207). The second and third semiconductor elements (1206, 1207) may be electrically connected to each other through a circuit layer provided on the first insulating layer of the circuit board (1200). In addition, the circuit board (1200) may be provided with a via electrode having a through hole, and the via electrode may vertically overlap with each of the second and third semiconductor elements (1206, 1207). For example, the via electrode may have a first via electrode vertically overlapping with the second semiconductor element (1206) and a second via electrode vertically overlapping with the third semiconductor element (1207), thereby further improving the heat dissipation characteristics of the circuit board and the semiconductor package for heat generated from the second and third semiconductor elements (1206, 1207).

[0178] In addition, referring to FIG. 15, the circuit board of the embodiment can be used as an interposer provided between a semiconductor package substrate and a semiconductor element. For example, the semiconductor package includes a circuit board (1300), and a plurality of semiconductor elements can be attached to the circuit board (1300). In this case, the circuit board (1300) can be an interposer provided between the semiconductor package substrate (1302) and the plurality of semiconductor elements.

[0179] A semiconductor package substrate (1302) is arranged on a lower surface of a circuit board (1300). The circuit board (1300) may have a pad portion connected to the semiconductor package substrate (1302), and a third connecting member (1301) may be arranged on a lower surface of the pad portion. In addition, the semiconductor package substrate (1302) may be electrically connected to the circuit board (1300) through the third connecting member (1301). The semiconductor package substrate (1302) may electrically connect a main board of an electronic device and the circuit board (1300).

[0180]

[0181] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0182] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0183] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0184] Although the above has been described with reference to embodiments, these are merely examples and are not intended to limit the embodiments. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. First insulation layer; A second insulating layer disposed on the first insulating layer and including a cavity; A protective layer disposed on the second insulating layer; and It includes an upper surface positioned on the same plane as the upper surface of the second insulating layer, and a via electrode penetrating at least a portion of the second insulating layer from the upper surface toward the lower surface of the second insulating layer, The above via electrode includes a through hole penetrating at least a portion of the area of ​​the via electrode from the upper surface of the via electrode toward the lower surface of the second insulating layer, A circuit board in which the through hole of the above via electrode overlaps horizontally with the cavity provided in the second insulating layer.

2. In paragraph 1, A circuit board, wherein the second insulating layer includes a first portion disposed on the outside of the via electrode and a second portion disposed within the through hole of the via electrode.

3. In paragraph 1, A circuit board, wherein the above through holes are provided in plurality and spaced apart from the via electrode in a first horizontal direction and a second horizontal direction different from the first horizontal direction.

4. In paragraph 2, The second insulating layer includes a via hole penetrating at least a portion of the second portion from the upper surface of the second portion toward the lower surface of the second portion, A circuit board further comprising a sub-via electrode disposed within the via hole of the second insulating layer.

5. In paragraph 4, A circuit board, wherein the second part of the second insulating layer surrounds the sub-via electrode and is provided between the inner surface of the through hole of the via electrode and the outer surface of the sub-via electrode.

6. In paragraph 1, A circuit board, wherein the through hole of the above via electrode is spaced apart from the periphery of the upper surface of the above via electrode.

7. In paragraph 6, The perimeter of the upper surface of the above via electrode includes a plurality of curved portions and a plurality of straight portions provided between the plurality of curved portions, A circuit board, wherein the plurality of curved portions and the plurality of straight portions have steps along a horizontal direction.

8. In paragraph 6, The perimeter of the upper surface of the above via electrode includes a plurality of first straight sections and a plurality of second straight sections provided between the plurality of first straight sections, A circuit board, wherein the plurality of first straight sections and the plurality of second straight sections have steps along a horizontal direction.

9. In paragraph 1, A circuit board, wherein the sidewall of the cavity of the second insulating layer includes a first sidewall connected to the upper surface of the second insulating layer and having a first slope, and a second sidewall provided between the lower surface of the second insulating layer and the first sidewall and having a second slope different from the first slope.

10. In paragraph 1, The second insulating layer includes a 2-1 insulating layer disposed on the first insulating layer, and a 2-2 insulating layer disposed on the 2-1 insulating layer. A circuit board, wherein the cavity and the via electrode are provided in at least one of the 2-1 insulating layer and the 2-2 insulating layer.

Images