Multi-output buck-boost converter using single inductor and control method thereof

Abstract

One embodiment provides a buck-boost converter comprising: a power stage which includes an inductor disposed between a first node and a second node, a first switch that controls connection between the first node and a node at which an input voltage is formed, a second switch that controls connection between the second node and a node at which a first output voltage is formed, a third switch that controls connection between the first node and a node at which a second output voltage is formed, and a fourth switch that controls connection between the second node and a reference potential node; and a controller that determines an on-time of the first switch on the basis of the second output voltage, determines an on-time of the second switch on the basis of the current of the inductor, determines an on-time of the third switch on the basis of the first output voltage, and controls on / off operations of the switches such that the on-times of the first switch and the third switch do not overlap and the on-times of the second switch and the fourth switch do not overlap.

Description

A multi-output buck-boost converter using a single inductor and its control method

[0001] The present embodiment relates to a converter and a control method thereof.

[0002] A converter is a power conversion device that can receive a single input voltage and produce a single output voltage. However, depending on the application, more than one voltage output may be required. For example, in electronic systems, each component often requires different voltages. Microprocessors, memory, analog circuits, and other components may have different optimal operating voltages. To supply appropriate power to these components, a converter can provide multiple output voltages.

[0003] A multi-output voltage converter has the ability to simultaneously generate multiple different voltages based on a single input voltage. This can be implemented in the form of a switching mode power supply (SMPS), with each output voltage designed to meet different power requirements. For example, it can be used to power complex electronic devices that require various voltages from the main power supply.

[0004] Multiple-output voltage converters can convert power using inductors and switches. These converters can be structured to generate multiple output voltages by adjusting the input voltage to an appropriate level. Inductors can be used to convert voltages by storing energy through current and releasing it as needed, while switching elements can regulate the flow of energy during this process.

[0005] Switches (typically MOSFETs, Metal-Oxide-Semiconductor Field-Effect Transistors) can generate a desired output voltage by rapidly turning on and off the inductor current. The on / off timing of the switching element can be determined by a control circuit, thereby controlling the output voltage to maintain a target value. The switching frequency and duty cycle can act as factors that affect the output voltage and inductor current, allowing each output voltage to be individually adjusted.

[0006] Converters that provide multiple output voltages can use separate inductors for each output voltage. Using separate inductors for each output minimizes electrical interference between outputs, ensuring output voltage independence. Since each output voltage is controlled by a separate inductor, each output can respond independently to different voltage demands or load changes. However, this approach requires a separate inductor for each output, which increases the number of components required in the circuit and complicates the overall circuit structure. This can increase design and manufacturing costs, and the circuit size can increase due to the space occupied by the inductor.

[0007] Against this backdrop, the purpose of the present embodiment is, in one aspect, to provide a technique for a converter that generates multiple output voltages using a single inductor. In another aspect, the purpose of the present embodiment is to provide a technique for controlling a converter that generates multiple output voltages using a single inductor.

[0008] In order to achieve the above-described object, one embodiment provides a buck-boost converter, comprising: a power stage including an inductor disposed between a first node and a second node, a first switch controlling a connection between the first node and a node where an input voltage is formed, a second switch controlling a connection between the second node and a node where a first output voltage is formed, a third switch controlling a connection between the first node and the node where a second output voltage is formed, and a fourth switch controlling a connection between the second node and a reference potential node; and a controller determining an on-time of the first switch according to the second output voltage, determining an on-time of the second switch according to a current of the inductor, determining an on-time of the third switch according to the first output voltage, and controlling on-off of the switches such that the on-periods of the first switch and the third switch do not overlap and the on-periods of the second switch and the fourth switch do not overlap.

[0009] The above controller can determine the off-time of the third switch and the off-time of the fourth switch according to a ZCD (zero current detection) signal for the current of the inductor.

[0010] The potential of the first output voltage may be higher than the potential of the second output voltage.

[0011] The potential of the first output voltage may be higher than the potential of the reference potential node, and the potential of the second output voltage may be lower than the potential of the reference potential node.

[0012] Only one inductor and four switches can be placed in the above power stage.

[0013] The above controller can compare an error signal generated by a difference between the second output voltage and the second output reference voltage with a triangle wave to form a first clock, and turn on the first switch according to an edge signal of the first clock.

[0014] The above controller can turn on the second switch when the current level of the inductor reaches a certain value.

[0015] The above controller can compare an error signal generated by a difference between the first output voltage and the first output reference voltage with a triangle wave to form a third clock, and turn on the third switch according to an edge signal of the third clock.

[0016] The controller may form a first signal by comparing an error signal generated by a difference between the first output voltage and the first output reference voltage with a triangle wave, form a second signal when the current level of the inductor reaches a certain value, form a third clock by performing an OR operation on the first signal and the second signal, and turn on the third switch according to an edge signal of the third clock.

[0017] In one switching cycle, the first switch, the second switch, and the third switch can be turned on in that order.

[0018] Another embodiment is a power stage including an inductor disposed between a first node and a second node, a first switch controlling a connection between the first node and an input terminal, a second switch controlling a connection between the second node and a first output terminal, a third switch controlling a connection between the first node and a second output terminal, and a fourth switch controlling a connection between the second node and a reference potential node, wherein a first load is disposed between the first output terminal and the second output terminal, and a second load is disposed between the first output terminal and the reference potential node; And in one mode, the on-time of the first switch and the second switch is determined according to the voltage of the second load, the on-time of the third switch and the fourth switch is determined according to the voltage of the first load or the current of the inductor, and a controller is provided for controlling the on-off of the switches such that the on-periods of the first switch and the third switch do not overlap and the on-periods of the second switch and the fourth switch do not overlap.

[0019] The above controller can determine the off-time of the third switch and the off-time of the fourth switch according to a ZCD (zero current detection) signal for the current of the inductor.

[0020] The above controller can operate in the above mode when the current of the second load is N times or more (N is a natural number greater than or equal to 2) times the current of the first load.

[0021] The potential of the first output terminal may be higher than the potential of the reference potential node, and the potential of the second output terminal may be lower than the potential of the reference potential node.

[0022] The controller can compare an error signal generated by a difference between the voltage of the second load and the second load reference voltage with a triangle wave to form a fourth clock, and turn on the first switch and the second switch according to an edge signal of the fourth clock.

[0023] The controller may form a first signal by comparing an error signal generated by a difference between the voltage of the first load and the first load reference voltage with a triangle wave, form a second signal when the current level of the inductor reaches a certain value, form a third clock by performing an OR operation on the first signal and the second signal, and turn on the third switch and the fourth switch according to an edge signal of the third clock.

[0024] The controller, in another mode, determines the on-time of the first switch according to the voltage of the second output terminal, determines the on-time of the second switch according to the current of the inductor, and determines the on-time of the third switch according to the voltage of the first output terminal, and can control the on-off of the switches such that the on-periods of the first switch and the third switch do not overlap and the on-periods of the second switch and the fourth switch do not overlap.

[0025] The above controller can determine the switching between the one mode and the other mode based on the difference in current consumption or power consumption between the first load and the second load.

[0026] In the above mode, the first switch and the second switch can operate in synchronization, and the third switch and the fourth switch can operate in synchronization.

[0027] Another embodiment provides a method for controlling a converter comprising an inductor disposed between a first node and a second node, a first switch controlling a connection between the first node and a node where an input voltage is formed, a second switch controlling a connection between the second node and a node where a first output voltage is formed, a third switch controlling a connection between the first node and the node where a second output voltage is formed, and a fourth switch controlling a connection between the second node and a reference potential node, the method comprising: determining an on-time of the first switch according to the second output voltage; determining an on-time of the second switch according to a current of the inductor; determining an on-time of the third switch according to the first output voltage; and controlling on-off of the switches such that the on-periods of the first switch and the third switch do not overlap and the on-periods of the second switch and the fourth switch do not overlap.

[0028] As described above, according to this embodiment, a converter that generates multiple output voltages using a single inductor can be configured. Furthermore, according to this embodiment, the size of a solution including the converter can be reduced, and its price competitiveness can be improved.

[0029] Figure 1 is a configuration diagram of a power device according to one embodiment.

[0030] Figure 2 is a circuit diagram of a power stage according to one embodiment.

[0031] Figure 3 is a configuration diagram of a controller according to one embodiment.

[0032] FIG. 4 is a waveform diagram of clocks, switches, and inductor current when the converter according to one embodiment operates in a current discontinuous mode.

[0033] Figures 5 to 8 are diagrams showing each switch state and current path at each step in the example of Figure 4.

[0034] FIG. 9 is a waveform diagram of clocks, switches, and inductor current when the converter operates in a continuous current mode according to one embodiment.

[0035] Fig. 10 is a configuration diagram of a power device according to another embodiment.

[0036] Fig. 11 is a configuration diagram of a controller according to another embodiment.

[0037] FIG. 12 is a waveform diagram of clocks, switches, and inductor current when a converter according to another embodiment operates.

[0038] Figures 13 and 14 are diagrams showing each switch state and current path at each step in the example of Figure 12.

[0039] Fig. 15 is a flowchart of a control method of a converter according to one embodiment.

[0040] Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. When designating components in each drawing, it should be noted that, where possible, identical components will be given the same reference numbers, even if they appear in different drawings. Furthermore, when describing the present invention, detailed descriptions of known related structures or functions will be omitted if they are deemed to obscure the gist of the present invention.

[0041] Additionally, terms such as first, second, A, B, (a), (b), etc. may be used to describe components of the present invention. These terms are only intended to distinguish the components from other components, and the nature, order, or sequence of the components are not limited by the terms. When it is described that a component is "connected," "coupled," or "connected" to another component, it should be understood that the component may be directly connected or connected to the other component, but another component may also be "connected," "coupled," or "connected" between each component.

[0042] Figure 1 is a configuration diagram of a power device according to one embodiment.

[0043] Referring to FIG. 1, a power device (100) may include a converter (110), peripheral components, and a load.

[0044] The converter (110) can convert the input voltage (VIN) supplied to the input terminal (TI) into a first output voltage (VOUTP) and supply it to the first output terminal (TO1), and can convert the input voltage (VIN) into a second output voltage (VOUTN) and supply it to the second output terminal (TO2).

[0045] Capacitors (CI, CO1, CO2) may be connected to each terminal (TI, TO1, TO2). For example, an input capacitor (CI) may be connected to the input terminal (TI), a first output capacitor (CO1) may be connected to the first output terminal (TO1), and a second output capacitor (CO2) may be connected to the second output terminal (TO2). One side of the input capacitor (CI) may be connected to the input terminal (TI) and the other side may be connected to a reference potential node (NG). In addition, one side of the first output capacitor (CO1) may be connected to the first output terminal (TO1) and the other side may be connected to a reference potential node (NG). In addition, one side of the second output capacitor (CO2) may be connected to the second output terminal (TO2) and the other side may be connected to a reference potential node (NG).

[0046] The converter (110) may include a power stage (111) and a controller (112).

[0047] A power stage (111) may have multiple switches - for example, four switches - arranged thereon. And, one inductor (L) may be arranged in the power stage (111). Here, one switch may be composed of one switching element and may be formed in a series-parallel structure of multiple switching elements. A device that controls the connection and disconnection of one power path may be viewed as one switch. One inductor may be physically composed of one passive element and may be formed in a series-parallel structure of multiple sub-inductors. For the convenience of explanation, in the following description, one switch is composed of one switching element - for example, one MOSFET element - and one inductor is physically composed of one passive element, but the present embodiment is not limited thereto.

[0048] The switch can be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), a BJT (Bipolar Junction Transistor), a JFET (Junction Field-Effect Transistor), etc.

[0049] A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a device that controls the current between the drain and source by applying a voltage between the gate and source. MOSFETs are voltage-controlled devices, meaning that the channel's conduction state can be adjusted depending on the voltage applied to the gate. The drain-source current is determined by the gate voltage, and its excellent switching characteristics make it widely used in switching applications.

[0050] The Insulated Gate Bipolar Transistor (IGBT) combines the characteristics of both MOSFETs and BJTs. By applying a voltage between the gate and emitter, the collector-emitter current can be controlled. IGBTs can handle high voltages and can be configured to combine the input characteristics of a MOSFET with the output characteristics of a BJT. These characteristics make them ideal for applications requiring high power density.

[0051] A BJT (Bipolar Junction Transistor) consists of three terminals: a base, a collector, and an emitter. This device controls the current flowing between the collector and emitter by applying a base current. As a current-controlled device, the collector current can be amplified by the base current. This amplification characteristic allows its use in current amplifiers and other devices, and it has the advantage of handling high currents in certain applications.

[0052] Additionally, a JFET (Junction Field-Effect Transistor) is a device that can control the current between the drain and source by applying a voltage between the gate and source. The JFET regulates the current flow in the channel using a PN junction, and the current can be controlled depending on the gate voltage applied to the channel. This device can be classified as a voltage-controlled device, and because it has low-noise characteristics, it can be applied to certain analog circuits.

[0053] For convenience of explanation, the switch is described below as being composed of a MOSFET element, but the present embodiment is not limited thereto.

[0054] The controller can control the on / off of each switch by transmitting gate control signals (SGs) to the power stage (111). For example, the controller (112) can control the on / off of the first switch by transmitting the first gate signal to the first switch, and can control the on / off of the fourth switch by transmitting the fourth gate signal to the fourth switch.

[0055] The controller (112) can sense the input voltage (VIN), the first output voltage (VOUTP), the second output voltage (VOUTN), or the current of the inductor and use them to generate gate control signals (SGs). For this control, control blocks of a voltage control loop and / or a current control loop commonly used in converters can be used.

[0056] A load can be connected to each of the first output terminal (TO1) and the second output terminal (TO2). Independent loads can be connected to each of the first output terminal (TO1) and the second output terminal (TO2), and as illustrated in Fig. 1, one load (10) can be connected between the first output terminal (TO1) and the second output terminal (TO2).

[0057] In this case, one side of the load (10) can be connected to the first output terminal (TO1) and the other side can be connected to the second output terminal (TO2). Then, a first output voltage (VOUTP) can be formed on one side of the load (10) and a second output voltage (VOUTN) can be formed on the other side.

[0058] The potential of the first output voltage (VOUTP) may be higher than the potential of the second output voltage (VOUTN). The first output voltage (VOUTP) may be a positive voltage, and the second output voltage (VOUTN) may be a negative voltage. At this time, the potential of the first output voltage (VOUTP) may be higher than the potential of the reference potential node (NG), and the potential of the second output voltage (VOUTN) may be lower than the potential of the reference potential node (NG). Here, the potential of the reference potential node (NG) may be 0 V, which is the same as the ground potential, but may have a slightly different potential depending on the embodiment.

[0059] Figure 2 is a circuit diagram of a power stage according to one embodiment.

[0060] Referring to Fig. 2, an inductor (L) may be placed between a first node (N1) and a second node (N2). A current flowing from the first node (N1) to the second node (N2) may flow through the inductor. In addition, a voltage formed at the first node (N1) may become a voltage at one side of the inductor (L), and a voltage formed at the second node (N2) may become a voltage at the other side of the inductor (L). The energy stored in the inductor (L) may be determined by the difference between the voltage at one side and the voltage at the other side of the inductor (L).

[0061] A first switch (Q1) may be placed between a node where an input voltage (VIN) is formed—here, an input terminal (TI)—and a first node (N1). The first switch (Q1) may control the connection between the input terminal (TI) and the first node (N1). When the first switch (Q1) is turned on, the input terminal (TI) and the first node (N1) are connected, and the input voltage (VIN) formed at the input terminal (TI) may be supplied to the first node (N1).

[0062] A second switch (Q2) may be placed between a node where a first output voltage (VOUTP) is formed—here, the first output terminal (TO1)—and a second node (N2). The second switch (Q2) can control the connection between the first output terminal (TO1) and the second node (N2). When the second switch (Q2) is turned on, the first output terminal (TO1) and the second node (N2) are connected, and the first output voltage (VOUTP) formed at the first output terminal (TO1) can be supplied to the second node (N2).

[0063] A third switch (Q3) may be placed between a node where a second output voltage (VOUTN) is formed—here, the second output terminal (TO2)—and the first node (N1). The third switch (Q3) can control the connection between the second output terminal (TO2) and the first node (N1). When the third switch (Q3) is turned on, the second output terminal (TO2) and the first node (N1) are connected, and the second output voltage (VOUTN) formed at the second output terminal (TO2) can be supplied to the first node (N1).

[0064] A fourth switch (Q4) may be placed between the second node (N2) and the reference potential node (NG). The fourth switch (Q4) may control the connection between the second node (N2) and the reference potential node (NG). When the fourth switch (Q4) is turned on, a voltage of the reference potential may be formed at the second node (N2).

[0065] In a typical converter, the fifth switch (Q5) that controls the connection between the first node (N1) and the reference potential node is not included in the power stage (111) according to one embodiment. In the power stage (111) according to one embodiment, only one inductor (L) and four switches (Q1, Q2, Q3, Q4) can be arranged.

[0066] A gate driver can be connected to each switch (Q1, Q2, Q3, Q4). In addition, a gate control signal (SG1, SG2, SG3, SG4) can be supplied to each gate driver. An on / off operation of a first switch (Q1) can be performed according to a first gate control signal (SG1), an on / off operation of a second switch (Q2) can be performed according to a second gate control signal (SG2), an on / off operation of a third switch (Q3) can be performed according to a third gate control signal (SG3), and an on / off operation of a fourth switch (Q4) can be performed according to a fourth gate control signal (SG4).

[0067] Gate control signals (SG1, SG2, SG3, SG4) can be generated by the controller.

[0068] Figure 3 is a configuration diagram of a controller according to one embodiment.

[0069] Referring to FIG. 3, the controller (112) may include a control circuit (310). In addition, the control circuit (310) may output gate control signals (SG1, SG2, SG3, SG4).

[0070] The control circuit (310) can determine the on-time of the first switch according to the second output voltage (VOUTN). In addition, the control circuit (310) can determine the on-time of the second switch according to the current (IL) of the inductor. In addition, the control circuit (310) can determine the on-time of the third switch according to the first output voltage (VOUTP). In addition, the control circuit (310) can control the on-off of the switches so that the on-periods of the first switch and the third switch do not overlap, and so that the on-periods of the second switch and the fourth switch do not overlap.

[0071] A first clock (CLK1), a second clock (CLK2), a third clock (CLK3), and a ZCD signal (ZCD: zero current detection) can be supplied to the control circuit (310). In addition, the control circuit (310) can turn on the first switch according to an edge signal of the first clock (CLK1)—for example, a rising edge signal—and can turn on the second switch according to an edge signal of the second clock (CLK2), and can turn on the third switch according to an edge signal of the third clock (CLK3).

[0072] The controller (112) includes a first error amplifier (EA1) and a first comparator (CMP1), and can generate an error signal corresponding to the difference between the second output voltage (VOUTN) and the second output reference voltage (VOUTN_REF) using the first error amplifier (EA1). In addition, the controller (112) can compare this error signal with a triangle wave (VRAMP1) using the first comparator (CMP1) to form a first clock (CLK1), and transmit the first clock (CLK1) to the control circuit (310).

[0073] The controller (112) includes a second error amplifier (EA2) and a second comparator (CMP2), and can generate an error signal corresponding to the difference between the first output voltage (VOUTP) and the first output reference voltage (VOUTP_REF) using the second error amplifier (EA2). In addition, the controller (112) can compare this error signal with a triangle wave (VRAMP2) using the second comparator (CMP1) to form a third clock (CLK3), and transmit the third clock (CLK3) to the control circuit (310).

[0074] The controller (112) can form a third clock (CLK3) by further considering the level of the inductor current (IL). The first signal can be formed by comparing an error signal generated by the difference between the first output voltage (VOUTP) and the first output reference voltage (VOUTP_REF) with a triangle wave (VRAMP2), and the second signal can be formed when the level of the inductor current (IL) reaches a first constant value using the second on-time controller (OTC2). In addition, the controller (112) can form the third clock (CLK3) by performing an OR operation on the first signal and the second signal.

[0075] The controller (112) can generate a second clock (CLK2) using the first on-time controller (OTC1). The first on-time controller (OTC1) can generate the second clock (CLK2) when the level of the inductor current (IL) reaches a second constant value, and the control circuit (310) can turn on the second switch according to an edge signal of the second clock (CLK2)—for example, a rising edge signal.

[0076] The controller (112) includes a ZCD circuit and can detect the zero current point of the inductor current (IL) using the ZCD circuit. In addition, the controller (112) can generate a ZCD signal (ZCD) in response to the zero current point.

[0077] In addition, the control circuit (310) can determine the off-time of the third switch and the off-time of the fourth switch according to the ZCD signal (ZCD) for the inductor current (IL).

[0078] Fig. 4 is a waveform diagram of clocks, switches, and inductor current when a converter according to one embodiment operates in a current discontinuous mode. In addition, Figs. 5 to 8 are diagrams showing the states of each switch and current path at each step in the example of Fig. 4.

[0079] Referring to FIGS. 4 to 8, a switching cycle (TS) in a current discontinuous mode may be composed of four stages. In the first stage (D1), the inductor current (IL) builds up, and in the second stage (D2), the inductor current (IL) may decrease, be maintained, or increase. In the third stage (D3), the inductor current (IL) decreases to a zero level, and in the fourth stage (D4), no current may flow into the inductor.

[0080] In one switching cycle (TS), the first switch (Q1), the second switch (Q2), and the third switch (Q3) can be turned on in that order. If the start of one switching cycle (TS) is defined as from the second stage (D2), the second switch (Q2), the third switch (Q3), and the first switch (Q1) can be turned on in that order.

[0081] In the first stage (D1), the first switch (Q1) can be turned on according to the rising edge signal of the first clock (CLK1). At this time, the fourth switch (Q4) can also be turned on. In addition, the third switch (Q3), which is controlled so that the ON section of the first switch (Q1) does not overlap, can maintain the OFF state, and the second switch (Q2), which is controlled so that the ON section of the fourth switch (Q4) does not overlap, can maintain the OFF state.

[0082] In the first stage (D1), an input voltage (VIN) may be formed at the first node (N1), and a reference voltage may be formed at the second node (N2). Accordingly, energy may be accumulated in the inductor (L) from the first node (N1) to the second node (N2), and the inductor current (IL) may also flow from the first node (N1) to the second node (N2).

[0083] In the second stage (D2), the second switch (Q2) can be turned on according to the rising edge signal of the second clock (CLK2). In addition, the fourth switch (Q4), which is controlled so that the ON period of the second switch (Q2) does not overlap, can be turned off. In addition, the first switch (Q1) can maintain the ON state, and the third switch (Q3) can maintain the OFF state.

[0084] In the second step (D2), an input voltage (VIN) may be formed at the first node (N1), and a first output voltage (VOUTP) may be formed at the second node (N2). At this time, if the input voltage (VIN) is higher than the first output voltage (VOUTP), the inductor current (IL) may increase, if the input voltage (VIN) is equal to the first output voltage (VOUTP), the inductor current (IL) may be maintained, and if the input voltage (VIN) is lower than the first output voltage (VOUTP), the inductor current (IL) may decrease.

[0085] In the third step (D3), the third switch (Q3) can be turned on according to the rising edge signal of the third clock (CLK3). At this time, the fourth switch (Q4) can also be turned on. In addition, the first switch (Q1), which is controlled so that the ON section of the third switch (Q3) does not overlap, can be turned off, and the second switch (Q2), which is controlled so that the ON section of the fourth switch (Q4) does not overlap, can be turned off.

[0086] In the third step (D3), a second output voltage (VOUTN) may be formed at the first node (N1), and a reference voltage may be formed at the second node (N2). Accordingly, the inductor current (IL) may decrease.

[0087] In the fourth step (D4), the third switch (Q3) may be turned off and the fourth switch (Q4) may be turned off according to the ZCD signal (ZCD). In addition, the first switch (Q1) may be maintained in the off state and the second switch (Q2) may be maintained in the off state. At this time, no current may flow through the inductor (L).

[0088] FIG. 9 is a waveform diagram of clocks, switches, and inductor current when the converter operates in a continuous current mode according to one embodiment.

[0089] Referring to Fig. 9, the ZCD signal (ZCD) may not be generated because the inductor current (IL) does not go below the zero level in one switching cycle (TS).

[0090] In the first stage (D1), the first switch (Q1) can be turned on according to the rising edge signal of the first clock (CLK1). In addition, the third switch (Q3), which is controlled so that the ON period of the first switch (Q1) does not overlap, can be turned off. In addition, the second switch (Q2) can maintain the OFF state, and the fourth switch (Q4) can maintain the ON state.

[0091] In the first stage (D1), an input voltage (VIN) may be formed at the first node (N1), and a reference voltage may be formed at the second node (N2). Accordingly, energy may be accumulated in the inductor (L) from the first node (N1) to the second node (N2), and the inductor current (IL) may also flow from the first node (N1) to the second node (N2).

[0092] In the second stage (D2), the second switch (Q2) can be turned on according to the rising edge signal of the second clock (CLK2). In addition, the fourth switch (Q4), which is controlled so that the ON period of the second switch (Q2) does not overlap, can be turned off. In addition, the first switch (Q1) can maintain the ON state, and the third switch (Q3) can maintain the OFF state.

[0093] In the second step (D2), an input voltage (VIN) may be formed at the first node (N1), and a first output voltage (VOUTP) may be formed at the second node (N2). At this time, if the input voltage (VIN) is higher than the first output voltage (VOUTP), the inductor current (IL) may increase, if the input voltage (VIN) is equal to the first output voltage (VOUTP), the inductor current (IL) may be maintained, and if the input voltage (VIN) is lower than the first output voltage (VOUTP), the inductor current (IL) may decrease.

[0094] In the third step (D3), the third switch (Q3) can be turned on according to the rising edge signal of the third clock (CLK3). At this time, the fourth switch (Q4) can also be turned on. In addition, the first switch (Q1), which is controlled so that the ON section of the third switch (Q3) does not overlap, can be turned off, and the second switch (Q2), which is controlled so that the ON section of the fourth switch (Q4) does not overlap, can be turned off.

[0095] In the third step (D3), a second output voltage (VOUTN) may be formed at the first node (N1), and a reference voltage may be formed at the second node (N2). Accordingly, the inductor current (IL) may decrease.

[0096] A switching cycle (TS) may consist of a first stage (D1), a second stage (D2), and a third stage (D3).

[0097] Fig. 10 is a configuration diagram of a power device according to another embodiment.

[0098] Referring to FIG. 10, a power device (1000) may include a converter (110), peripheral components, and a load.

[0099] The converter (1110) can convert the input voltage (VIN) supplied to the input terminal (TI) into a first output terminal voltage (VTO1) and supply it to the first output terminal (TO1), and can convert the input voltage (VIN) into a second output terminal voltage (VTO2) and supply it to the second output terminal (TO2).

[0100] Capacitors (CI, CO1, CO2) may be connected to each terminal (TI, TO1, TO2). For example, an input capacitor (CI) may be connected to the input terminal (TI), a first output capacitor (CO1) may be connected to the first output terminal (TO1), and a second output capacitor (CO2) may be connected to the second output terminal (TO2). One side of the input capacitor (CI) may be connected to the input terminal (TI) and the other side may be connected to a reference potential node (NG). In addition, one side of the first output capacitor (CO1) may be connected to the first output terminal (TO1) and the other side may be connected to a reference potential node (NG). In addition, one side of the second output capacitor (CO2) may be connected to the second output terminal (TO2) and the other side may be connected to a reference potential node (NG).

[0101] The converter (1110) may include a power stage (111) and a controller (1112).

[0102] The configuration of the power stage (111) may be the same as the power stage according to an embodiment described with reference to FIGS. 1 to 9. Here, some descriptions of the power stage (111) are omitted.

[0103] A first load (10) may be placed between the first output terminal (TO1) and the second output terminal (TO2) of the power stage (111). In addition, a second load (20) may be placed between the first output terminal (TO1) and the reference potential node (NG).

[0104] The second load (20) may be supplied with a driving voltage known as AVDD, for example. AVDD may be supplied to an analog-to-digital converter (ADC) or another analog circuit component. For ease of understanding, the AVDD voltage is described as being supplied to the second load (20), but the present embodiment is not limited thereto.

[0105] The controller (1112) can sense the input voltage (VIN), the voltage (AVDD) supplied to the second load (20), the voltage (VOUTP) supplied to the first load (10), or the current of the inductor and use them to generate gate control signals (SGs). For this control, control blocks of a voltage control loop and / or a current control loop commonly used in converters can be used.

[0106] The potential of the first output terminal (TO1) may be higher than the potential of the reference potential node (NG), and the potential of the second output terminal (TO2) may be lower than the potential of the reference potential node (NG). For example, the first output terminal voltage (VTO1) may be a positive voltage, and the second output terminal voltage (VTO2) may be a negative voltage.

[0107] The controller (1112) can operate in two operation modes. And, the controller (1112) can determine the switching between the first mode and the second mode according to the difference in the current consumption (IOUT, IAVDD) of the first load (10) and the second load (20) or the difference in the power consumption. The controller (1112) can operate in the first mode when the current (IAVDD) of the second load (20) is N (where N is a natural number greater than or equal to 2) times greater than the current (IOUT) of the first load (10), and can operate in the second mode otherwise. For example, the controller (1112) can operate in the first mode when the current (IAVDD) of the second load (20) is three times greater than the current (IOUT) of the first load (10), and can operate in the second mode when it is less than three times greater.

[0108] The operation of the second mode may be identical to the operation described with reference to FIGS. 1 to 9. Some descriptions of the operation of the second mode are omitted here.

[0109] Fig. 11 is a configuration diagram of a controller according to another embodiment.

[0110] Referring to FIG. 11, the controller (1112) may include a control circuit (1310). In addition, the control circuit (1310) may output gate control signals (SG1, SG2, SG3, SG4).

[0111] The control circuit (1310) determines the on-times of the first switch and the second switch according to the voltage (AVDD) of the second load in the first mode, and determines the on-times of the third switch and the fourth switch according to the voltage of the first load—for example, VOUTP—or the current (IL) of the inductor, and can control the on-off of the switches so that the on-periods of the first switch and the third switch do not overlap and the on-periods of the second switch and the fourth switch do not overlap.

[0112] And, the control circuit (1310) determines the on-time of the first switch according to the voltage of the second output terminal - for example, VOUTN - in the second mode, determines the on-time of the second switch according to the current (IL) of the inductor, determines the on-time of the third switch according to the voltage of the first output terminal - for example, VOUTP -, and can control the on-off of the switches so that the on-periods of the first switch and the third switch do not overlap and the on-periods of the second switch and the fourth switch do not overlap.

[0113] In the first mode, the control circuit (1310) can control the on / off of switches according to the third clock (CLK3), the fourth clock (CLK3), and the ZCD signal (ZCD).

[0114] The controller (1112) can form a first signal by comparing an error signal generated by a difference between a voltage of a first load - for example, VOUTP - and a first load reference voltage - for example, VOUTP_REF - with a triangle wave, form a second signal when the level of an inductor current (IL) reaches a certain value, and form a third clock (CLK3) by performing an OR operation on the first signal and the second signal. In addition, the controller (1112) can turn on the third switch and the fourth switch according to an edge signal of the third clock (CLK3).

[0115] The controller (1112) can compare an error signal generated by the difference between the voltage of the second load (AVDD) and the second load reference voltage (AVDD_REF) with a triangle wave to form a fourth clock (CLK4). In addition, the controller (1112) can turn on the first switch and the second switch according to the edge signal of the fourth clock (CLK4).

[0116] And, the controller (1112) can operate the first switch and the second switch to be synchronized in the first mode, and can operate the third switch and the fourth switch to be synchronized.

[0117] The controller (1112) can switch modes according to the difference in current consumption or power consumption between the first load and the second load, and this mode switching signal can be received externally or generated in an internal circuit (AVDDEN).

[0118] Fig. 12 is a waveform diagram of clocks, switches, and inductor current when a converter according to another embodiment is operating. In addition, Figs. 13 and 14 are diagrams showing the states of each switch and current path at each step in the example of Fig. 12.

[0119] Referring to FIGS. 12 to 14, when the signal level of the mode switching signal (AVDDEN) changes at the day switching point (TR), the controller can change the operating mode. In FIG. 12, before the day switching point (TR), the controller operates in the second mode, and after the day switching point (TR), the controller operates in the first mode.

[0120] In the first mode, a single switching cycle (TS) can be composed of three stages: stage 5 (D5), stage 6 (D6), and stage 7 (D7).

[0121] In the fifth step (D5), the first switch (Q1) and the second switch (Q2) can be turned on according to the rising edge signal of the fourth clock (CLK4). In addition, the third switch (Q3), which is controlled so that the ON section of the first switch (Q1) does not overlap, can be maintained in the OFF state, and the fourth switch (Q4), which is controlled so that the ON section of the second switch (Q2) does not overlap, can be maintained in the OFF state.

[0122] In the fifth step (D5), an input voltage (VIN) may be formed at the first node (N1), and a first output terminal voltage (VTO1) may be formed at the second node (N2). At this time, an inductor current (IL) may build up.

[0123] In the sixth step (D6), the third switch (Q3) and the fourth switch (Q4) can be turned on according to the rising edge signal of the third clock (CLK3). In addition, the first switch (Q1) controlled so that the ON section of the third switch (Q3) does not overlap can be turned off, and the second switch (Q2) controlled so that the ON section of the fourth switch (Q4) does not overlap can be turned off.

[0124] In the sixth step (D6), a second output terminal voltage (VTO2) may be formed at the first node (N1), and a reference voltage may be formed at the second node (N2). Accordingly, the inductor current (IL) may decrease.

[0125] In the seventh step (D7), the third switch (Q3) may be turned off and the fourth switch (Q4) may be turned off according to the ZCD signal (ZCD). In addition, the first switch (Q1) may be maintained in the off state and the second switch (Q2) may be maintained in the off state. At this time, no current may flow through the inductor (L).

[0126] Fig. 15 is a flowchart of a control method of a converter according to one embodiment.

[0127] The power stage of the converter may include four switches and one inductor. Furthermore, the converter may convert an input voltage to generate a first output voltage and a second output voltage. The internal configuration of the power stage may be identical to that of the aforementioned power stage.

[0128] At this time, in the control of the converter, determining the on-time and off-time of each switch may be important. According to one embodiment, the converter can determine the on-time of the first switch based on the second output voltage (S1500).

[0129] And, the converter can determine the ON time of the second switch according to the current of the inductor (S1502).

[0130] And, the converter can determine the ON time of the third switch according to the first output voltage (S1504).

[0131] And, the converter can control the on / off of the switches so that the on periods of the first switch and the third switch do not overlap and the on periods of the second switch and the fourth switch do not overlap (S1506).

[0132] As described above, according to this embodiment, a converter that generates multiple output voltages using a single inductor can be configured. Furthermore, according to this embodiment, the size of a solution including the converter can be reduced, and its price competitiveness can be improved.

[0133] The terms "include," "comprise," or "have" described above, unless otherwise specifically stated, imply that the corresponding component may be included, and therefore should be interpreted to include other components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as terms defined in dictionaries, should be interpreted to be consistent with their meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense, unless explicitly defined herein.

[0134] The above description is merely an illustrative illustration of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

Claims

1. A power stage including an inductor arranged between a first node and a second node, a first switch controlling a connection between the first node and a node where an input voltage is formed, a second switch controlling a connection between the second node and a node where a first output voltage is formed, a third switch controlling a connection between the first node and a node where a second output voltage is formed, and a fourth switch controlling a connection between the second node and a reference potential node; and A controller that determines the on-time of the first switch according to the second output voltage, determines the on-time of the second switch according to the current of the inductor, determines the on-time of the third switch according to the first output voltage, and controls the on-off of the switches so that the on-periods of the first switch and the third switch do not overlap and the on-periods of the second switch and the fourth switch do not overlap. A buck-boost converter including:

2. In paragraph 1, The above controller, A buck-boost converter that determines the off-time of the third switch and the off-time of the fourth switch according to the ZCD (zero current detection) signal for the current of the inductor.

3. In paragraph 1, A buck-boost converter, wherein the potential of the first output voltage is higher than the potential of the second output voltage.

4. In paragraph 1, A buck-boost converter, wherein the potential of the first output voltage is higher than the potential of the reference potential node, and the potential of the second output voltage is lower than the potential of the reference potential node.

5. In paragraph 1, A buck-boost converter in which only one inductor and four switches are placed in the above power stage.

6. In paragraph 1, The above controller, A buck-boost converter that compares an error signal generated by the difference between the second output voltage and the second output reference voltage with a triangle wave to form a first clock, and turns on the first switch according to an edge signal of the first clock.

7. In paragraph 1, The above controller, A buck-boost converter that turns on the second switch when the current level of the inductor reaches a certain value.

8. In paragraph 1, The above controller, A buck-boost converter that compares an error signal generated by the difference between the first output voltage and the first output reference voltage with a triangle wave to form a third clock, and turns on the third switch according to an edge signal of the third clock.

9. In paragraph 1, The above controller, A buck-boost converter that forms a first signal by comparing an error signal generated by a difference between the first output voltage and the first output reference voltage with a triangle wave, forms a second signal when the current level of the inductor reaches a certain value, forms a third clock by performing an OR operation on the first signal and the second signal, and turns on the third switch according to an edge signal of the third clock.

10. In paragraph 1, A buck-boost converter in which the first switch, the second switch, and the third switch are turned on in sequence in one switching cycle.

11. A power stage including an inductor arranged between a first node and a second node, a first switch controlling a connection between the first node and an input terminal, a second switch controlling a connection between the second node and a first output terminal, a third switch controlling a connection between the first node and the second output terminal, and a fourth switch controlling a connection between the second node and a reference potential node, wherein a first load is arranged between the first output terminal and the second output terminal, and a second load is arranged between the first output terminal and the reference potential node; and In one mode, a controller that determines the on-time of the first switch and the second switch according to the voltage of the second load, determines the on-time of the third switch and the fourth switch according to the voltage of the first load or the current of the inductor, and controls the on-off of the switches so that the on-periods of the first switch and the third switch do not overlap and the on-periods of the second switch and the fourth switch do not overlap. A buck-boost converter including:

12. In paragraph 11, The above controller, A buck-boost converter that determines the off-time of the third switch and the off-time of the fourth switch according to the ZCD (zero current detection) signal for the current of the inductor.

13. In paragraph 11, The above controller, A buck-boost converter that operates in the first mode when the current of the second load is N (where N is a natural number greater than or equal to 2) times greater than the current of the first load.

14. In paragraph 11, A buck-boost converter, wherein the potential of the first output terminal is higher than the potential of the reference potential node, and the potential of the second output terminal is lower than the potential of the reference potential node.

15. In paragraph 11, The above controller, A buck-boost converter that compares an error signal generated by a difference between the voltage of the second load and the second load reference voltage with a triangle wave to form a fourth clock, and turns on the first switch and the second switch according to an edge signal of the fourth clock.

16. In paragraph 11, The above controller, A buck-boost converter that compares an error signal generated by a difference between the voltage of the first load and the first load reference voltage with a triangle wave to form a first signal, forms a second signal when the current level of the inductor reaches a certain value, forms a third clock by performing an OR operation on the first signal and the second signal, and turns on the third switch and the fourth switch according to an edge signal of the third clock.

17. In paragraph 11, The above controller, A buck-boost converter, wherein in another mode, the on-time of the first switch is determined according to the voltage of the second output terminal, the on-time of the second switch is determined according to the current of the inductor, and the on-time of the third switch is determined according to the voltage of the first output terminal, and the on-off of the switches is controlled such that the on-periods of the first switch and the third switch do not overlap and the on-periods of the second switch and the fourth switch do not overlap.

18. In paragraph 17, The above controller, A buck-boost converter that determines switching between the first mode and the other mode based on the difference in current consumption or power consumption between the first load and the second load.

19. In paragraph 11, A buck-boost converter, wherein in the above-described mode, the first switch and the second switch operate synchronously, and the third switch and the fourth switch operate synchronously.

20. A method for controlling a converter comprising an inductor arranged between a first node and a second node, a first switch controlling a connection between the first node and a node where an input voltage is formed, a second switch controlling a connection between the second node and a node where a first output voltage is formed, a third switch controlling a connection between the first node and a node where a second output voltage is formed, and a fourth switch controlling a connection between the second node and a reference potential node, A step of determining the on-time of the first switch according to the second output voltage; A step of determining the on-time of the second switch according to the current of the inductor; A step of determining the on-time of the third switch according to the first output voltage; and A step for controlling the on / off of the switches so that the on periods of the first switch and the third switch do not overlap, and so that the on periods of the second switch and the fourth switch do not overlap. A converter control method comprising:

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